1 /* 2 * Xilinx Versal Virtual board. 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/error-report.h" 14 #include "qapi/error.h" 15 #include "sysemu/device_tree.h" 16 #include "exec/address-spaces.h" 17 #include "hw/boards.h" 18 #include "hw/sysbus.h" 19 #include "hw/arm/sysbus-fdt.h" 20 #include "hw/arm/fdt.h" 21 #include "cpu.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/arm/xlnx-versal.h" 24 #include "qom/object.h" 25 26 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") 27 OBJECT_DECLARE_SIMPLE_TYPE(VersalVirt, XLNX_VERSAL_VIRT_MACHINE) 28 29 struct VersalVirt { 30 MachineState parent_obj; 31 32 Versal soc; 33 34 void *fdt; 35 int fdt_size; 36 struct { 37 uint32_t gic; 38 uint32_t ethernet_phy[2]; 39 uint32_t clk_125Mhz; 40 uint32_t clk_25Mhz; 41 uint32_t usb; 42 uint32_t dwc; 43 } phandle; 44 struct arm_boot_info binfo; 45 46 struct { 47 bool secure; 48 } cfg; 49 }; 50 51 static void fdt_create(VersalVirt *s) 52 { 53 MachineClass *mc = MACHINE_GET_CLASS(s); 54 int i; 55 56 s->fdt = create_device_tree(&s->fdt_size); 57 if (!s->fdt) { 58 error_report("create_device_tree() failed"); 59 exit(1); 60 } 61 62 /* Allocate all phandles. */ 63 s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt); 64 for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) { 65 s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt); 66 } 67 s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt); 68 s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt); 69 70 s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt); 71 s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt); 72 /* Create /chosen node for load_dtb. */ 73 qemu_fdt_add_subnode(s->fdt, "/chosen"); 74 75 /* Header */ 76 qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic); 77 qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2); 78 qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2); 79 qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc); 80 qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt"); 81 } 82 83 static void fdt_add_clk_node(VersalVirt *s, const char *name, 84 unsigned int freq_hz, uint32_t phandle) 85 { 86 qemu_fdt_add_subnode(s->fdt, name); 87 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 88 qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz); 89 qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0); 90 qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock"); 91 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 92 } 93 94 static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit) 95 { 96 int i; 97 98 qemu_fdt_add_subnode(s->fdt, "/cpus"); 99 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0); 100 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1); 101 102 for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) { 103 char *name = g_strdup_printf("/cpus/cpu@%d", i); 104 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 105 106 qemu_fdt_add_subnode(s->fdt, name); 107 qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity); 108 if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 109 qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci"); 110 } 111 qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu"); 112 qemu_fdt_setprop_string(s->fdt, name, "compatible", 113 armcpu->dtb_compatible); 114 g_free(name); 115 } 116 } 117 118 static void fdt_add_gic_nodes(VersalVirt *s) 119 { 120 char *nodename; 121 122 nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN); 123 qemu_fdt_add_subnode(s->fdt, nodename); 124 qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic); 125 qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts", 126 GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, 127 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 128 qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0); 129 qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", 130 2, MM_GIC_APU_DIST_MAIN, 131 2, MM_GIC_APU_DIST_MAIN_SIZE, 132 2, MM_GIC_APU_REDIST_0, 133 2, MM_GIC_APU_REDIST_0_SIZE); 134 qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); 135 qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); 136 g_free(nodename); 137 } 138 139 static void fdt_add_timer_nodes(VersalVirt *s) 140 { 141 const char compat[] = "arm,armv8-timer"; 142 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 143 144 qemu_fdt_add_subnode(s->fdt, "/timer"); 145 qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts", 146 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags, 147 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags, 148 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags, 149 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags); 150 qemu_fdt_setprop(s->fdt, "/timer", "compatible", 151 compat, sizeof(compat)); 152 } 153 154 static void fdt_add_usb_xhci_nodes(VersalVirt *s) 155 { 156 const char clocknames[] = "bus_clk\0ref_clk"; 157 const char irq_name[] = "dwc_usb3"; 158 const char compatVersalDWC3[] = "xlnx,versal-dwc3"; 159 const char compatDWC3[] = "snps,dwc3"; 160 char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS); 161 162 qemu_fdt_add_subnode(s->fdt, name); 163 qemu_fdt_setprop(s->fdt, name, "compatible", 164 compatVersalDWC3, sizeof(compatVersalDWC3)); 165 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 166 2, MM_USB2_CTRL_REGS, 167 2, MM_USB2_CTRL_REGS_SIZE); 168 qemu_fdt_setprop(s->fdt, name, "clock-names", 169 clocknames, sizeof(clocknames)); 170 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 171 s->phandle.clk_25Mhz, s->phandle.clk_125Mhz); 172 qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); 173 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); 174 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); 175 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); 176 g_free(name); 177 178 name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32, 179 MM_USB2_CTRL_REGS, MM_USB_0); 180 qemu_fdt_add_subnode(s->fdt, name); 181 qemu_fdt_setprop(s->fdt, name, "compatible", 182 compatDWC3, sizeof(compatDWC3)); 183 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 184 2, MM_USB_0, 2, MM_USB_0_SIZE); 185 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 186 irq_name, sizeof(irq_name)); 187 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 188 GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0, 189 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 190 qemu_fdt_setprop_cell(s->fdt, name, 191 "snps,quirk-frame-length-adjustment", 0x20); 192 qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1); 193 qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host"); 194 qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy"); 195 qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0); 196 qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0); 197 qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0); 198 qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0); 199 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); 200 qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed"); 201 g_free(name); 202 } 203 204 static void fdt_add_uart_nodes(VersalVirt *s) 205 { 206 uint64_t addrs[] = { MM_UART1, MM_UART0 }; 207 unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 }; 208 const char compat[] = "arm,pl011\0arm,sbsa-uart"; 209 const char clocknames[] = "uartclk\0apb_pclk"; 210 int i; 211 212 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 213 char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]); 214 qemu_fdt_add_subnode(s->fdt, name); 215 qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200); 216 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 217 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 218 qemu_fdt_setprop(s->fdt, name, "clock-names", 219 clocknames, sizeof(clocknames)); 220 221 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 222 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 223 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 224 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 225 2, addrs[i], 2, 0x1000); 226 qemu_fdt_setprop(s->fdt, name, "compatible", 227 compat, sizeof(compat)); 228 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 229 230 if (addrs[i] == MM_UART0) { 231 /* Select UART0. */ 232 qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name); 233 } 234 g_free(name); 235 } 236 } 237 238 static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname, 239 uint32_t phandle) 240 { 241 char *name = g_strdup_printf("%s/fixed-link", gemname); 242 243 qemu_fdt_add_subnode(s->fdt, name); 244 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 245 qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0); 246 qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000); 247 g_free(name); 248 } 249 250 static void fdt_add_gem_nodes(VersalVirt *s) 251 { 252 uint64_t addrs[] = { MM_GEM1, MM_GEM0 }; 253 unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 }; 254 const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk"; 255 const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem"; 256 int i; 257 258 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 259 char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]); 260 qemu_fdt_add_subnode(s->fdt, name); 261 262 fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]); 263 qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id"); 264 qemu_fdt_setprop_cell(s->fdt, name, "phy-handle", 265 s->phandle.ethernet_phy[i]); 266 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 267 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz, 268 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 269 qemu_fdt_setprop(s->fdt, name, "clock-names", 270 clocknames, sizeof(clocknames)); 271 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 272 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 273 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 274 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 275 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 276 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 277 2, addrs[i], 2, 0x1000); 278 qemu_fdt_setprop(s->fdt, name, "compatible", 279 compat_gem, sizeof(compat_gem)); 280 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1); 281 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0); 282 g_free(name); 283 } 284 } 285 286 static void fdt_add_zdma_nodes(VersalVirt *s) 287 { 288 const char clocknames[] = "clk_main\0clk_apb"; 289 const char compat[] = "xlnx,zynqmp-dma-1.0"; 290 int i; 291 292 for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) { 293 uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i; 294 char *name = g_strdup_printf("/dma@%" PRIx64, addr); 295 296 qemu_fdt_add_subnode(s->fdt, name); 297 298 qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64); 299 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 300 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 301 qemu_fdt_setprop(s->fdt, name, "clock-names", 302 clocknames, sizeof(clocknames)); 303 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 304 GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i, 305 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 306 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 307 2, addr, 2, 0x1000); 308 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 309 g_free(name); 310 } 311 } 312 313 static void fdt_add_sd_nodes(VersalVirt *s) 314 { 315 const char clocknames[] = "clk_xin\0clk_ahb"; 316 const char compat[] = "arasan,sdhci-8.9a"; 317 int i; 318 319 for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) { 320 uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i; 321 char *name = g_strdup_printf("/sdhci@%" PRIx64, addr); 322 323 qemu_fdt_add_subnode(s->fdt, name); 324 325 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 326 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 327 qemu_fdt_setprop(s->fdt, name, "clock-names", 328 clocknames, sizeof(clocknames)); 329 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 330 GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2, 331 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 332 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 333 2, addr, 2, MM_PMC_SD0_SIZE); 334 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 335 g_free(name); 336 } 337 } 338 339 static void fdt_add_rtc_node(VersalVirt *s) 340 { 341 const char compat[] = "xlnx,zynqmp-rtc"; 342 const char interrupt_names[] = "alarm\0sec"; 343 char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC); 344 345 qemu_fdt_add_subnode(s->fdt, name); 346 347 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 348 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ, 349 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 350 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ, 351 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 352 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 353 interrupt_names, sizeof(interrupt_names)); 354 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 355 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE); 356 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 357 g_free(name); 358 } 359 360 static void fdt_nop_memory_nodes(void *fdt, Error **errp) 361 { 362 Error *err = NULL; 363 char **node_path; 364 int n = 0; 365 366 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 367 if (err) { 368 error_propagate(errp, err); 369 return; 370 } 371 while (node_path[n]) { 372 if (g_str_has_prefix(node_path[n], "/memory")) { 373 qemu_fdt_nop_node(fdt, node_path[n]); 374 } 375 n++; 376 } 377 g_strfreev(node_path); 378 } 379 380 static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size) 381 { 382 /* Describes the various split DDR access regions. */ 383 static const struct { 384 uint64_t base; 385 uint64_t size; 386 } addr_ranges[] = { 387 { MM_TOP_DDR, MM_TOP_DDR_SIZE }, 388 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, 389 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, 390 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } 391 }; 392 uint64_t mem_reg_prop[8] = {0}; 393 uint64_t size = ram_size; 394 Error *err = NULL; 395 char *name; 396 int i; 397 398 fdt_nop_memory_nodes(fdt, &err); 399 if (err) { 400 error_report_err(err); 401 return; 402 } 403 404 name = g_strdup_printf("/memory@%x", MM_TOP_DDR); 405 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { 406 uint64_t mapsize; 407 408 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; 409 410 mem_reg_prop[i * 2] = addr_ranges[i].base; 411 mem_reg_prop[i * 2 + 1] = mapsize; 412 size -= mapsize; 413 } 414 qemu_fdt_add_subnode(fdt, name); 415 qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); 416 417 switch (i) { 418 case 1: 419 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 420 2, mem_reg_prop[0], 421 2, mem_reg_prop[1]); 422 break; 423 case 2: 424 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 425 2, mem_reg_prop[0], 426 2, mem_reg_prop[1], 427 2, mem_reg_prop[2], 428 2, mem_reg_prop[3]); 429 break; 430 case 3: 431 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 432 2, mem_reg_prop[0], 433 2, mem_reg_prop[1], 434 2, mem_reg_prop[2], 435 2, mem_reg_prop[3], 436 2, mem_reg_prop[4], 437 2, mem_reg_prop[5]); 438 break; 439 case 4: 440 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 441 2, mem_reg_prop[0], 442 2, mem_reg_prop[1], 443 2, mem_reg_prop[2], 444 2, mem_reg_prop[3], 445 2, mem_reg_prop[4], 446 2, mem_reg_prop[5], 447 2, mem_reg_prop[6], 448 2, mem_reg_prop[7]); 449 break; 450 default: 451 g_assert_not_reached(); 452 } 453 g_free(name); 454 } 455 456 static void versal_virt_modify_dtb(const struct arm_boot_info *binfo, 457 void *fdt) 458 { 459 VersalVirt *s = container_of(binfo, VersalVirt, binfo); 460 461 fdt_add_memory_nodes(s, fdt, binfo->ram_size); 462 } 463 464 static void *versal_virt_get_dtb(const struct arm_boot_info *binfo, 465 int *fdt_size) 466 { 467 const VersalVirt *board = container_of(binfo, VersalVirt, binfo); 468 469 *fdt_size = board->fdt_size; 470 return board->fdt; 471 } 472 473 #define NUM_VIRTIO_TRANSPORT 8 474 static void create_virtio_regions(VersalVirt *s) 475 { 476 int virtio_mmio_size = 0x200; 477 int i; 478 479 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 480 char *name = g_strdup_printf("virtio%d", i); 481 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 482 int irq = VERSAL_RSVD_IRQ_FIRST + i; 483 MemoryRegion *mr; 484 DeviceState *dev; 485 qemu_irq pic_irq; 486 487 pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq); 488 dev = qdev_new("virtio-mmio"); 489 object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev)); 490 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 491 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); 492 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 493 memory_region_add_subregion(&s->soc.mr_ps, base, mr); 494 g_free(name); 495 } 496 497 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 498 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 499 int irq = VERSAL_RSVD_IRQ_FIRST + i; 500 char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 501 502 qemu_fdt_add_subnode(s->fdt, name); 503 qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0); 504 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 505 GIC_FDT_IRQ_TYPE_SPI, irq, 506 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 507 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 508 2, base, 2, virtio_mmio_size); 509 qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio"); 510 g_free(name); 511 } 512 } 513 514 static void sd_plugin_card(SDHCIState *sd, DriveInfo *di) 515 { 516 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; 517 DeviceState *card; 518 519 card = qdev_new(TYPE_SD_CARD); 520 object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card)); 521 qdev_prop_set_drive_err(card, "drive", blk, &error_fatal); 522 qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"), 523 &error_fatal); 524 } 525 526 static void versal_virt_init(MachineState *machine) 527 { 528 VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine); 529 int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 530 int i; 531 532 /* 533 * If the user provides an Operating System to be loaded, we expect them 534 * to use the -kernel command line option. 535 * 536 * Users can load firmware or boot-loaders with the -device loader options. 537 * 538 * When loading an OS, we generate a dtb and let arm_load_kernel() select 539 * where it gets loaded. This dtb will be passed to the kernel in x0. 540 * 541 * If there's no -kernel option, we generate a DTB and place it at 0x1000 542 * for the bootloaders or firmware to pick up. 543 * 544 * If users want to provide their own DTB, they can use the -dtb option. 545 * These dtb's will have their memory nodes modified to match QEMU's 546 * selected ram_size option before they get passed to the kernel or fw. 547 * 548 * When loading an OS, we turn on QEMU's PSCI implementation with SMC 549 * as the PSCI conduit. When there's no -kernel, we assume the user 550 * provides EL3 firmware to handle PSCI. 551 */ 552 if (machine->kernel_filename) { 553 psci_conduit = QEMU_PSCI_CONDUIT_SMC; 554 } 555 556 object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc, 557 TYPE_XLNX_VERSAL); 558 object_property_set_link(OBJECT(&s->soc), "ddr", OBJECT(machine->ram), 559 &error_abort); 560 object_property_set_int(OBJECT(&s->soc), "psci-conduit", psci_conduit, 561 &error_abort); 562 sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); 563 564 fdt_create(s); 565 create_virtio_regions(s); 566 fdt_add_gem_nodes(s); 567 fdt_add_uart_nodes(s); 568 fdt_add_gic_nodes(s); 569 fdt_add_timer_nodes(s); 570 fdt_add_zdma_nodes(s); 571 fdt_add_usb_xhci_nodes(s); 572 fdt_add_sd_nodes(s); 573 fdt_add_rtc_node(s); 574 fdt_add_cpu_nodes(s, psci_conduit); 575 fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); 576 fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); 577 578 /* Make the APU cpu address space visible to virtio and other 579 * modules unaware of muliple address-spaces. */ 580 memory_region_add_subregion_overlap(get_system_memory(), 581 0, &s->soc.fpd.apu.mr, 0); 582 583 /* Plugin SD cards. */ 584 for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { 585 sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD)); 586 } 587 588 s->binfo.ram_size = machine->ram_size; 589 s->binfo.loader_start = 0x0; 590 s->binfo.get_dtb = versal_virt_get_dtb; 591 s->binfo.modify_dtb = versal_virt_modify_dtb; 592 if (machine->kernel_filename) { 593 arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo); 594 } else { 595 AddressSpace *as = arm_boot_address_space(&s->soc.fpd.apu.cpu[0], 596 &s->binfo); 597 /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL). 598 * Offset things by 4K. */ 599 s->binfo.loader_start = 0x1000; 600 s->binfo.dtb_limit = 0x1000000; 601 if (arm_load_dtb(s->binfo.loader_start, 602 &s->binfo, s->binfo.dtb_limit, as, machine) < 0) { 603 exit(EXIT_FAILURE); 604 } 605 } 606 } 607 608 static void versal_virt_machine_instance_init(Object *obj) 609 { 610 } 611 612 static void versal_virt_machine_class_init(ObjectClass *oc, void *data) 613 { 614 MachineClass *mc = MACHINE_CLASS(oc); 615 616 mc->desc = "Xilinx Versal Virtual development board"; 617 mc->init = versal_virt_init; 618 mc->min_cpus = XLNX_VERSAL_NR_ACPUS; 619 mc->max_cpus = XLNX_VERSAL_NR_ACPUS; 620 mc->default_cpus = XLNX_VERSAL_NR_ACPUS; 621 mc->no_cdrom = true; 622 mc->default_ram_id = "ddr"; 623 } 624 625 static const TypeInfo versal_virt_machine_init_typeinfo = { 626 .name = TYPE_XLNX_VERSAL_VIRT_MACHINE, 627 .parent = TYPE_MACHINE, 628 .class_init = versal_virt_machine_class_init, 629 .instance_init = versal_virt_machine_instance_init, 630 .instance_size = sizeof(VersalVirt), 631 }; 632 633 static void versal_virt_machine_init_register_types(void) 634 { 635 type_register_static(&versal_virt_machine_init_typeinfo); 636 } 637 638 type_init(versal_virt_machine_init_register_types) 639 640