1 /* 2 * STM32L4x5 SoC family 3 * 4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> 5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This work is heavily inspired by the stm32f405_soc by Alistair Francis. 13 * Original code is licensed under the MIT License: 14 * 15 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 16 */ 17 18 /* 19 * The reference used is the STMicroElectronics RM0351 Reference manual 20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. 21 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "qapi/error.h" 27 #include "exec/address-spaces.h" 28 #include "sysemu/sysemu.h" 29 #include "hw/or-irq.h" 30 #include "hw/arm/stm32l4x5_soc.h" 31 #include "hw/qdev-clock.h" 32 #include "hw/misc/unimp.h" 33 34 #define FLASH_BASE_ADDRESS 0x08000000 35 #define SRAM1_BASE_ADDRESS 0x20000000 36 #define SRAM1_SIZE (96 * KiB) 37 #define SRAM2_BASE_ADDRESS 0x10000000 38 #define SRAM2_SIZE (32 * KiB) 39 40 #define EXTI_ADDR 0x40010400 41 #define SYSCFG_ADDR 0x40010000 42 43 #define NUM_EXTI_IRQ 40 44 /* Match exti line connections with their CPU IRQ number */ 45 /* See Vector Table (Reference Manual p.396) */ 46 /* 47 * Some IRQs are connected to the same CPU IRQ (denoted by -1) 48 * and require an intermediary OR gate to function correctly. 49 */ 50 static const int exti_irq[NUM_EXTI_IRQ] = { 51 6, /* GPIO[0] */ 52 7, /* GPIO[1] */ 53 8, /* GPIO[2] */ 54 9, /* GPIO[3] */ 55 10, /* GPIO[4] */ 56 -1, -1, -1, -1, -1, /* GPIO[5..9] OR gate 23 */ 57 -1, -1, -1, -1, -1, -1, /* GPIO[10..15] OR gate 40 */ 58 -1, /* PVD OR gate 1 */ 59 67, /* OTG_FS_WKUP, Direct */ 60 41, /* RTC_ALARM */ 61 2, /* RTC_TAMP_STAMP2/CSS_LSE */ 62 3, /* RTC wakeup timer */ 63 -1, -1, /* COMP[1..2] OR gate 63 */ 64 31, /* I2C1 wakeup, Direct */ 65 33, /* I2C2 wakeup, Direct */ 66 72, /* I2C3 wakeup, Direct */ 67 37, /* USART1 wakeup, Direct */ 68 38, /* USART2 wakeup, Direct */ 69 39, /* USART3 wakeup, Direct */ 70 52, /* UART4 wakeup, Direct */ 71 53, /* UART4 wakeup, Direct */ 72 70, /* LPUART1 wakeup, Direct */ 73 65, /* LPTIM1, Direct */ 74 66, /* LPTIM2, Direct */ 75 76, /* SWPMI1 wakeup, Direct */ 76 -1, -1, -1, -1, /* PVM[1..4] OR gate 1 */ 77 78 /* LCD wakeup, Direct */ 78 }; 79 80 static const int exti_or_gates_out[NUM_EXTI_OR_GATES] = { 81 23, 40, 63, 1, 82 }; 83 84 static const int exti_or_gates_num_lines_in[NUM_EXTI_OR_GATES] = { 85 5, 6, 2, 5, 86 }; 87 88 /* 3 OR gates with consecutive inputs */ 89 #define NUM_EXTI_SIMPLE_OR_GATES 3 90 static const int exti_or_gates_first_line_in[NUM_EXTI_SIMPLE_OR_GATES] = { 91 5, 10, 21, 92 }; 93 94 /* 1 OR gate with non-consecutive inputs */ 95 #define EXTI_OR_GATE1_NUM_LINES_IN 5 96 static const int exti_or_gate1_lines_in[EXTI_OR_GATE1_NUM_LINES_IN] = { 97 16, 35, 36, 37, 38, 98 }; 99 100 static void stm32l4x5_soc_initfn(Object *obj) 101 { 102 Stm32l4x5SocState *s = STM32L4X5_SOC(obj); 103 104 object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI); 105 for (unsigned i = 0; i < NUM_EXTI_OR_GATES; i++) { 106 object_initialize_child(obj, "exti_or_gates[*]", &s->exti_or_gates[i], 107 TYPE_OR_IRQ); 108 } 109 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG); 110 111 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 112 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); 113 } 114 115 static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) 116 { 117 ERRP_GUARD(); 118 Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc); 119 const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc); 120 MemoryRegion *system_memory = get_system_memory(); 121 DeviceState *armv7m; 122 SysBusDevice *busdev; 123 124 /* 125 * We use s->refclk internally and only define it with qdev_init_clock_in() 126 * so it is correctly parented and not leaked on an init/deinit; it is not 127 * intended as an externally exposed clock. 128 */ 129 if (clock_has_source(s->refclk)) { 130 error_setg(errp, "refclk clock must not be wired up by the board code"); 131 return; 132 } 133 134 if (!clock_has_source(s->sysclk)) { 135 error_setg(errp, "sysclk clock must be wired up by the board code"); 136 return; 137 } 138 139 /* 140 * TODO: ideally we should model the SoC RCC and its ability to 141 * change the sysclk frequency and define different sysclk sources. 142 */ 143 144 /* The refclk always runs at frequency HCLK / 8 */ 145 clock_set_mul_div(s->refclk, 8, 1); 146 clock_set_source(s->refclk, s->sysclk); 147 148 if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash", 149 sc->flash_size, errp)) { 150 return; 151 } 152 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), 153 "flash_boot_alias", &s->flash, 0, 154 sc->flash_size); 155 156 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); 157 memory_region_add_subregion(system_memory, 0, &s->flash_alias); 158 159 if (!memory_region_init_ram(&s->sram1, OBJECT(dev_soc), "SRAM1", SRAM1_SIZE, 160 errp)) { 161 return; 162 } 163 memory_region_add_subregion(system_memory, SRAM1_BASE_ADDRESS, &s->sram1); 164 165 if (!memory_region_init_ram(&s->sram2, OBJECT(dev_soc), "SRAM2", SRAM2_SIZE, 166 errp)) { 167 return; 168 } 169 memory_region_add_subregion(system_memory, SRAM2_BASE_ADDRESS, &s->sram2); 170 171 object_initialize_child(OBJECT(dev_soc), "armv7m", &s->armv7m, TYPE_ARMV7M); 172 armv7m = DEVICE(&s->armv7m); 173 qdev_prop_set_uint32(armv7m, "num-irq", 96); 174 qdev_prop_set_uint32(armv7m, "num-prio-bits", 4); 175 qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); 176 qdev_prop_set_bit(armv7m, "enable-bitband", true); 177 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); 178 qdev_connect_clock_in(armv7m, "refclk", s->refclk); 179 object_property_set_link(OBJECT(&s->armv7m), "memory", 180 OBJECT(system_memory), &error_abort); 181 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { 182 return; 183 } 184 185 /* System configuration controller */ 186 busdev = SYS_BUS_DEVICE(&s->syscfg); 187 if (!sysbus_realize(busdev, errp)) { 188 return; 189 } 190 sysbus_mmio_map(busdev, 0, SYSCFG_ADDR); 191 /* 192 * TODO: when the GPIO device is implemented, connect it 193 * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and 194 * GPIO_NUM_PINS. 195 */ 196 197 /* EXTI device */ 198 busdev = SYS_BUS_DEVICE(&s->exti); 199 if (!sysbus_realize(busdev, errp)) { 200 return; 201 } 202 sysbus_mmio_map(busdev, 0, EXTI_ADDR); 203 204 /* IRQs with fan-in that require an OR gate */ 205 for (unsigned i = 0; i < NUM_EXTI_OR_GATES; i++) { 206 if (!object_property_set_int(OBJECT(&s->exti_or_gates[i]), "num-lines", 207 exti_or_gates_num_lines_in[i], errp)) { 208 return; 209 } 210 if (!qdev_realize(DEVICE(&s->exti_or_gates[i]), NULL, errp)) { 211 return; 212 } 213 214 qdev_connect_gpio_out(DEVICE(&s->exti_or_gates[i]), 0, 215 qdev_get_gpio_in(armv7m, exti_or_gates_out[i])); 216 217 if (i < NUM_EXTI_SIMPLE_OR_GATES) { 218 /* consecutive inputs for OR gates 23, 40, 63 */ 219 for (unsigned j = 0; j < exti_or_gates_num_lines_in[i]; j++) { 220 sysbus_connect_irq(SYS_BUS_DEVICE(&s->exti), 221 exti_or_gates_first_line_in[i] + j, 222 qdev_get_gpio_in(DEVICE(&s->exti_or_gates[i]), j)); 223 } 224 } else { 225 /* non-consecutive inputs for OR gate 1 */ 226 for (unsigned j = 0; j < EXTI_OR_GATE1_NUM_LINES_IN; j++) { 227 sysbus_connect_irq(SYS_BUS_DEVICE(&s->exti), 228 exti_or_gate1_lines_in[j], 229 qdev_get_gpio_in(DEVICE(&s->exti_or_gates[i]), j)); 230 } 231 } 232 } 233 234 /* IRQs that don't require fan-in */ 235 for (unsigned i = 0; i < NUM_EXTI_IRQ; i++) { 236 if (exti_irq[i] != -1) { 237 sysbus_connect_irq(busdev, i, 238 qdev_get_gpio_in(armv7m, exti_irq[i])); 239 } 240 } 241 242 for (unsigned i = 0; i < 16; i++) { 243 qdev_connect_gpio_out(DEVICE(&s->syscfg), i, 244 qdev_get_gpio_in(DEVICE(&s->exti), i)); 245 } 246 247 /* APB1 BUS */ 248 create_unimplemented_device("TIM2", 0x40000000, 0x400); 249 create_unimplemented_device("TIM3", 0x40000400, 0x400); 250 create_unimplemented_device("TIM4", 0x40000800, 0x400); 251 create_unimplemented_device("TIM5", 0x40000C00, 0x400); 252 create_unimplemented_device("TIM6", 0x40001000, 0x400); 253 create_unimplemented_device("TIM7", 0x40001400, 0x400); 254 /* RESERVED: 0x40001800, 0x1000 */ 255 create_unimplemented_device("RTC", 0x40002800, 0x400); 256 create_unimplemented_device("WWDG", 0x40002C00, 0x400); 257 create_unimplemented_device("IWDG", 0x40003000, 0x400); 258 /* RESERVED: 0x40001800, 0x400 */ 259 create_unimplemented_device("SPI2", 0x40003800, 0x400); 260 create_unimplemented_device("SPI3", 0x40003C00, 0x400); 261 /* RESERVED: 0x40004000, 0x400 */ 262 create_unimplemented_device("USART2", 0x40004400, 0x400); 263 create_unimplemented_device("USART3", 0x40004800, 0x400); 264 create_unimplemented_device("UART4", 0x40004C00, 0x400); 265 create_unimplemented_device("UART5", 0x40005000, 0x400); 266 create_unimplemented_device("I2C1", 0x40005400, 0x400); 267 create_unimplemented_device("I2C2", 0x40005800, 0x400); 268 create_unimplemented_device("I2C3", 0x40005C00, 0x400); 269 /* RESERVED: 0x40006000, 0x400 */ 270 create_unimplemented_device("CAN1", 0x40006400, 0x400); 271 /* RESERVED: 0x40006800, 0x400 */ 272 create_unimplemented_device("PWR", 0x40007000, 0x400); 273 create_unimplemented_device("DAC1", 0x40007400, 0x400); 274 create_unimplemented_device("OPAMP", 0x40007800, 0x400); 275 create_unimplemented_device("LPTIM1", 0x40007C00, 0x400); 276 create_unimplemented_device("LPUART1", 0x40008000, 0x400); 277 /* RESERVED: 0x40008400, 0x400 */ 278 create_unimplemented_device("SWPMI1", 0x40008800, 0x400); 279 /* RESERVED: 0x40008C00, 0x800 */ 280 create_unimplemented_device("LPTIM2", 0x40009400, 0x400); 281 /* RESERVED: 0x40009800, 0x6800 */ 282 283 /* APB2 BUS */ 284 create_unimplemented_device("VREFBUF", 0x40010030, 0x1D0); 285 create_unimplemented_device("COMP", 0x40010200, 0x200); 286 /* RESERVED: 0x40010800, 0x1400 */ 287 create_unimplemented_device("FIREWALL", 0x40011C00, 0x400); 288 /* RESERVED: 0x40012000, 0x800 */ 289 create_unimplemented_device("SDMMC1", 0x40012800, 0x400); 290 create_unimplemented_device("TIM1", 0x40012C00, 0x400); 291 create_unimplemented_device("SPI1", 0x40013000, 0x400); 292 create_unimplemented_device("TIM8", 0x40013400, 0x400); 293 create_unimplemented_device("USART1", 0x40013800, 0x400); 294 /* RESERVED: 0x40013C00, 0x400 */ 295 create_unimplemented_device("TIM15", 0x40014000, 0x400); 296 create_unimplemented_device("TIM16", 0x40014400, 0x400); 297 create_unimplemented_device("TIM17", 0x40014800, 0x400); 298 /* RESERVED: 0x40014C00, 0x800 */ 299 create_unimplemented_device("SAI1", 0x40015400, 0x400); 300 create_unimplemented_device("SAI2", 0x40015800, 0x400); 301 /* RESERVED: 0x40015C00, 0x400 */ 302 create_unimplemented_device("DFSDM1", 0x40016000, 0x400); 303 /* RESERVED: 0x40016400, 0x9C00 */ 304 305 /* AHB1 BUS */ 306 create_unimplemented_device("DMA1", 0x40020000, 0x400); 307 create_unimplemented_device("DMA2", 0x40020400, 0x400); 308 /* RESERVED: 0x40020800, 0x800 */ 309 create_unimplemented_device("RCC", 0x40021000, 0x400); 310 /* RESERVED: 0x40021400, 0xC00 */ 311 create_unimplemented_device("FLASH", 0x40022000, 0x400); 312 /* RESERVED: 0x40022400, 0xC00 */ 313 create_unimplemented_device("CRC", 0x40023000, 0x400); 314 /* RESERVED: 0x40023400, 0x400 */ 315 create_unimplemented_device("TSC", 0x40024000, 0x400); 316 317 /* RESERVED: 0x40024400, 0x7FDBC00 */ 318 319 /* AHB2 BUS */ 320 create_unimplemented_device("GPIOA", 0x48000000, 0x400); 321 create_unimplemented_device("GPIOB", 0x48000400, 0x400); 322 create_unimplemented_device("GPIOC", 0x48000800, 0x400); 323 create_unimplemented_device("GPIOD", 0x48000C00, 0x400); 324 create_unimplemented_device("GPIOE", 0x48001000, 0x400); 325 create_unimplemented_device("GPIOF", 0x48001400, 0x400); 326 create_unimplemented_device("GPIOG", 0x48001800, 0x400); 327 create_unimplemented_device("GPIOH", 0x48001C00, 0x400); 328 /* RESERVED: 0x48002000, 0x7FDBC00 */ 329 create_unimplemented_device("OTG_FS", 0x50000000, 0x40000); 330 create_unimplemented_device("ADC", 0x50040000, 0x400); 331 /* RESERVED: 0x50040400, 0x20400 */ 332 create_unimplemented_device("RNG", 0x50060800, 0x400); 333 334 /* AHB3 BUS */ 335 create_unimplemented_device("FMC", 0xA0000000, 0x1000); 336 create_unimplemented_device("QUADSPI", 0xA0001000, 0x400); 337 } 338 339 static void stm32l4x5_soc_class_init(ObjectClass *klass, void *data) 340 { 341 342 DeviceClass *dc = DEVICE_CLASS(klass); 343 344 dc->realize = stm32l4x5_soc_realize; 345 /* Reason: Mapped at fixed location on the system bus */ 346 dc->user_creatable = false; 347 /* No vmstate or reset required: device has no internal state */ 348 } 349 350 static void stm32l4x5xc_soc_class_init(ObjectClass *oc, void *data) 351 { 352 Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc); 353 354 ssc->flash_size = 256 * KiB; 355 } 356 357 static void stm32l4x5xe_soc_class_init(ObjectClass *oc, void *data) 358 { 359 Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc); 360 361 ssc->flash_size = 512 * KiB; 362 } 363 364 static void stm32l4x5xg_soc_class_init(ObjectClass *oc, void *data) 365 { 366 Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc); 367 368 ssc->flash_size = 1 * MiB; 369 } 370 371 static const TypeInfo stm32l4x5_soc_types[] = { 372 { 373 .name = TYPE_STM32L4X5XC_SOC, 374 .parent = TYPE_STM32L4X5_SOC, 375 .class_init = stm32l4x5xc_soc_class_init, 376 }, { 377 .name = TYPE_STM32L4X5XE_SOC, 378 .parent = TYPE_STM32L4X5_SOC, 379 .class_init = stm32l4x5xe_soc_class_init, 380 }, { 381 .name = TYPE_STM32L4X5XG_SOC, 382 .parent = TYPE_STM32L4X5_SOC, 383 .class_init = stm32l4x5xg_soc_class_init, 384 }, { 385 .name = TYPE_STM32L4X5_SOC, 386 .parent = TYPE_SYS_BUS_DEVICE, 387 .instance_size = sizeof(Stm32l4x5SocState), 388 .instance_init = stm32l4x5_soc_initfn, 389 .class_size = sizeof(Stm32l4x5SocClass), 390 .class_init = stm32l4x5_soc_class_init, 391 .abstract = true, 392 } 393 }; 394 395 DEFINE_TYPES(stm32l4x5_soc_types) 396