1Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``) 2================================================================== 3 4The QEMU Aspeed machines model BMCs of various OpenPOWER systems and 5Aspeed evaluation boards. They are based on different releases of the 6Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the 7AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600 8with dual cores ARM Cortex-A7 CPUs (1.2GHz). 9 10The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C, 11etc. 12 13AST2400 SoC based machines : 14 15- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC 16- ``quanta-q71l-bmc`` OpenBMC Quanta BMC 17- ``supermicrox11-bmc`` Supermicro X11 BMC 18 19AST2500 SoC based machines : 20 21- ``ast2500-evb`` Aspeed AST2500 Evaluation board 22- ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC 23- ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC 24- ``sonorapass-bmc`` OCP SonoraPass BMC 25- ``fp5280g2-bmc`` Inspur FP5280G2 BMC 26- ``g220a-bmc`` Bytedance G220A BMC 27- ``yosemitev2-bmc`` Facebook YosemiteV2 BMC 28- ``tiogapass-bmc`` Facebook Tiogapass BMC 29 30AST2600 SoC based machines : 31 32- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7) 33- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC 34- ``rainier-bmc`` IBM Rainier POWER10 BMC 35- ``fuji-bmc`` Facebook Fuji BMC 36- ``montblanc-bmc`` Facebook Montblanc BMC 37- ``bletchley-bmc`` Facebook Bletchley BMC 38- ``fby35-bmc`` Facebook fby35 BMC 39- ``qcom-dc-scm-v1-bmc`` Qualcomm DC-SCM V1 BMC 40- ``qcom-firework-bmc`` Qualcomm Firework BMC 41 42Supported devices 43----------------- 44 45 * SMP (for the AST2600 Cortex-A7) 46 * Interrupt Controller (VIC) 47 * Timer Controller 48 * RTC Controller 49 * I2C Controller, including the new register interface of the AST2600 50 * System Control Unit (SCU) 51 * SRAM mapping 52 * X-DMA Controller (basic interface) 53 * Static Memory Controller (SMC or FMC) - Only SPI Flash support 54 * SPI Memory Controller 55 * USB 2.0 Controller 56 * SD/MMC storage controllers 57 * SDRAM controller (dummy interface for basic settings and training) 58 * Watchdog Controller 59 * GPIO Controller (Master only) 60 * UART 61 * Ethernet controllers 62 * Front LEDs (PCA9552 on I2C bus) 63 * LPC Peripheral Controller (a subset of subdevices are supported) 64 * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA 65 * ADC 66 * Secure Boot Controller (AST2600) 67 * eMMC Boot Controller (dummy) 68 * PECI Controller (minimal) 69 * I3C Controller 70 71 72Missing devices 73--------------- 74 75 * Coprocessor support 76 * PWM and Fan Controller 77 * Slave GPIO Controller 78 * Super I/O Controller 79 * PCI-Express 1 Controller 80 * Graphic Display Controller 81 * MCTP Controller 82 * Mailbox Controller 83 * Virtual UART 84 * eSPI Controller 85 86Boot options 87------------ 88 89The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options 90to load a Linux kernel or from a firmware. Images can be downloaded from the 91OpenBMC jenkins : 92 93 https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ 94 95or directly from the OpenBMC GitHub release repository : 96 97 https://github.com/openbmc/openbmc/releases 98 99To boot a kernel directly from a Linux build tree: 100 101.. code-block:: bash 102 103 $ qemu-system-arm -M ast2600-evb -nographic \ 104 -kernel arch/arm/boot/zImage \ 105 -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \ 106 -initrd rootfs.cpio 107 108The image should be attached as an MTD drive. Run : 109 110.. code-block:: bash 111 112 $ qemu-system-arm -M romulus-bmc -nic user \ 113 -drive file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd -nographic 114 115Options specific to Aspeed machines are : 116 117 * ``execute-in-place`` which emulates the boot from the CE0 flash 118 device by using the FMC controller to load the instructions, and 119 not simply from RAM. This takes a little longer. 120 121 * ``fmc-model`` to change the FMC Flash model. FW needs support for 122 the chip model to boot. 123 124 * ``spi-model`` to change the SPI Flash model. 125 126 * ``bmc-console`` to change the default console device. Most of the 127 machines use the ``UART5`` device for a boot console, which is 128 mapped on ``/dev/ttyS4`` under Linux, but it is not always the 129 case. 130 131For instance, to start the ``ast2500-evb`` machine with a different 132FMC chip and a bigger (64M) SPI chip, use : 133 134.. code-block:: bash 135 136 -M ast2500-evb,fmc-model=mx25l25635e,spi-model=mx66u51235f 137 138To change the boot console and use device ``UART3`` (``/dev/ttyS2`` 139under Linux), use : 140 141.. code-block:: bash 142 143 -M ast2500-evb,bmc-console=uart3 144 145Aspeed minibmc family boards (``ast1030-evb``) 146================================================================== 147 148The QEMU Aspeed machines model mini BMCs of various Aspeed evaluation 149boards. They are based on different releases of the 150Aspeed SoC : the AST1030 integrating an ARM Cortex M4F CPU (200MHz). 151 152The SoC comes with SRAM, SPI, I2C, etc. 153 154AST1030 SoC based machines : 155 156- ``ast1030-evb`` Aspeed AST1030 Evaluation board (Cortex-M4F) 157 158Supported devices 159----------------- 160 161 * SMP (for the AST1030 Cortex-M4F) 162 * Interrupt Controller (VIC) 163 * Timer Controller 164 * I2C Controller 165 * System Control Unit (SCU) 166 * SRAM mapping 167 * Static Memory Controller (SMC or FMC) - Only SPI Flash support 168 * SPI Memory Controller 169 * USB 2.0 Controller 170 * Watchdog Controller 171 * GPIO Controller (Master only) 172 * UART 173 * LPC Peripheral Controller (a subset of subdevices are supported) 174 * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA 175 * ADC 176 * Secure Boot Controller 177 * PECI Controller (minimal) 178 179 180Missing devices 181--------------- 182 183 * PWM and Fan Controller 184 * Slave GPIO Controller 185 * Mailbox Controller 186 * Virtual UART 187 * eSPI Controller 188 * I3C Controller 189 190Boot options 191------------ 192 193The Aspeed machines can be started using the ``-kernel`` to load a 194Zephyr OS or from a firmware. Images can be downloaded from the 195ASPEED GitHub release repository : 196 197 https://github.com/AspeedTech-BMC/zephyr/releases 198 199To boot a kernel directly from a Zephyr build tree: 200 201.. code-block:: bash 202 203 $ qemu-system-arm -M ast1030-evb -nographic \ 204 -kernel zephyr.elf 205 206Facebook Yosemite v3.5 Platform and CraterLake Server (``fby35``) 207================================================================== 208 209Facebook has a series of multi-node compute server designs named 210Yosemite. The most recent version released was 211`Yosemite v3 <https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf>`__. 212 213Yosemite v3.5 is an iteration on this design, and is very similar: there's a 214baseboard with a BMC, and 4 server slots. The new server board design termed 215"CraterLake" includes a Bridge IC (BIC), with room for expansion boards to 216include various compute accelerators (video, inferencing, etc). At the moment, 217only the first server slot's BIC is included. 218 219Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds 220can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__ 221for an example. 222 223In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC 224runs `OpenBMC <https://github.com/facebook/openbmc>`__, and the BIC runs 225`OpenBIC <https://github.com/facebook/openbic>`__. 226 227Firmware images can be retrieved from the Github releases or built from the 228source code, see the README's for instructions on that. This image uses the 229"fby35" machine recipe from OpenBMC, and the "yv35-cl" target from OpenBIC. 230Some reference images can also be found here: 231 232.. code-block:: bash 233 234 $ wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd 235 $ wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf 236 237Since this machine has multiple SoC's, each with their own serial console, the 238recommended way to run it is to allocate a pseudoterminal for each serial 239console and let the monitor use stdio. Also, starting in a paused state is 240useful because it allows you to attach to the pseudoterminals before the boot 241process starts. 242 243.. code-block:: bash 244 245 $ qemu-system-arm -machine fby35 \ 246 -drive file=fby35.mtd,format=raw,if=mtd \ 247 -device loader,file=Y35BCL.elf,addr=0,cpu-num=2 \ 248 -serial pty -serial pty -serial mon:stdio \ 249 -display none -S 250 $ screen /dev/tty0 # In a separate TMUX pane, terminal window, etc. 251 $ screen /dev/tty1 252 $ (qemu) c # Start the boot process once screen is setup. 253