1Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``) 2================================================================== 3 4The QEMU Aspeed machines model BMCs of various OpenPOWER systems and 5Aspeed evaluation boards. They are based on different releases of the 6Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the 7AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600 8with dual cores ARM Cortex-A7 CPUs (1.2GHz). 9 10The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C, 11etc. 12 13AST2400 SoC based machines : 14 15- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC 16- ``quanta-q71l-bmc`` OpenBMC Quanta BMC 17- ``supermicrox11-bmc`` Supermicro X11 BMC 18 19AST2500 SoC based machines : 20 21- ``ast2500-evb`` Aspeed AST2500 Evaluation board 22- ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC 23- ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC 24- ``sonorapass-bmc`` OCP SonoraPass BMC 25- ``fp5280g2-bmc`` Inspur FP5280G2 BMC 26- ``g220a-bmc`` Bytedance G220A BMC 27 28AST2600 SoC based machines : 29 30- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7) 31- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC 32- ``rainier-bmc`` IBM Rainier POWER10 BMC 33- ``fuji-bmc`` Facebook Fuji BMC 34- ``fby35-bmc`` Facebook fby35 BMC 35 36Supported devices 37----------------- 38 39 * SMP (for the AST2600 Cortex-A7) 40 * Interrupt Controller (VIC) 41 * Timer Controller 42 * RTC Controller 43 * I2C Controller 44 * System Control Unit (SCU) 45 * SRAM mapping 46 * X-DMA Controller (basic interface) 47 * Static Memory Controller (SMC or FMC) - Only SPI Flash support 48 * SPI Memory Controller 49 * USB 2.0 Controller 50 * SD/MMC storage controllers 51 * SDRAM controller (dummy interface for basic settings and training) 52 * Watchdog Controller 53 * GPIO Controller (Master only) 54 * UART 55 * Ethernet controllers 56 * Front LEDs (PCA9552 on I2C bus) 57 * LPC Peripheral Controller (a subset of subdevices are supported) 58 * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA 59 * ADC 60 61 62Missing devices 63--------------- 64 65 * Coprocessor support 66 * PWM and Fan Controller 67 * Slave GPIO Controller 68 * Super I/O Controller 69 * PCI-Express 1 Controller 70 * Graphic Display Controller 71 * PECI Controller 72 * MCTP Controller 73 * Mailbox Controller 74 * Virtual UART 75 * eSPI Controller 76 * I3C Controller 77 78Boot options 79------------ 80 81The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options 82to load a Linux kernel or from a firmware. Images can be downloaded from the 83OpenBMC jenkins : 84 85 https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ 86 87or directly from the OpenBMC GitHub release repository : 88 89 https://github.com/openbmc/openbmc/releases 90 91To boot a kernel directly from a Linux build tree: 92 93.. code-block:: bash 94 95 $ qemu-system-arm -M ast2600-evb -nographic \ 96 -kernel arch/arm/boot/zImage \ 97 -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \ 98 -initrd rootfs.cpio 99 100The image should be attached as an MTD drive. Run : 101 102.. code-block:: bash 103 104 $ qemu-system-arm -M romulus-bmc -nic user \ 105 -drive file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd -nographic 106 107Options specific to Aspeed machines are : 108 109 * ``execute-in-place`` which emulates the boot from the CE0 flash 110 device by using the FMC controller to load the instructions, and 111 not simply from RAM. This takes a little longer. 112 113 * ``fmc-model`` to change the FMC Flash model. FW needs support for 114 the chip model to boot. 115 116 * ``spi-model`` to change the SPI Flash model. 117 118For instance, to start the ``ast2500-evb`` machine with a different 119FMC chip and a bigger (64M) SPI chip, use : 120 121.. code-block:: bash 122 123 -M ast2500-evb,fmc-model=mx25l25635e,spi-model=mx66u51235f 124 125 126Aspeed minibmc family boards (``ast1030-evb``) 127================================================================== 128 129The QEMU Aspeed machines model mini BMCs of various Aspeed evaluation 130boards. They are based on different releases of the 131Aspeed SoC : the AST1030 integrating an ARM Cortex M4F CPU (200MHz). 132 133The SoC comes with SRAM, SPI, I2C, etc. 134 135AST1030 SoC based machines : 136 137- ``ast1030-evb`` Aspeed AST1030 Evaluation board (Cortex-M4F) 138 139Supported devices 140----------------- 141 142 * SMP (for the AST1030 Cortex-M4F) 143 * Interrupt Controller (VIC) 144 * Timer Controller 145 * I2C Controller 146 * System Control Unit (SCU) 147 * SRAM mapping 148 * Static Memory Controller (SMC or FMC) - Only SPI Flash support 149 * SPI Memory Controller 150 * USB 2.0 Controller 151 * Watchdog Controller 152 * GPIO Controller (Master only) 153 * UART 154 * LPC Peripheral Controller (a subset of subdevices are supported) 155 * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA 156 * ADC 157 158 159Missing devices 160--------------- 161 162 * PWM and Fan Controller 163 * Slave GPIO Controller 164 * PECI Controller 165 * Mailbox Controller 166 * Virtual UART 167 * eSPI Controller 168 * I3C Controller 169 170Boot options 171------------ 172 173The Aspeed machines can be started using the ``-kernel`` to load a 174Zephyr OS or from a firmware. Images can be downloaded from the 175ASPEED GitHub release repository : 176 177 https://github.com/AspeedTech-BMC/zephyr/releases 178 179To boot a kernel directly from a Zephyr build tree: 180 181.. code-block:: bash 182 183 $ qemu-system-arm -M ast1030-evb -nographic \ 184 -kernel zephyr.elf 185 186Facebook Yosemite v3.5 Platform and CraterLake Server (``fby35``) 187================================================================== 188 189Facebook has a series of multi-node compute server designs named 190Yosemite. The most recent version released was 191`Yosemite v3 <https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf>`__. 192 193Yosemite v3.5 is an iteration on this design, and is very similar: there's a 194baseboard with a BMC, and 4 server slots. The new server board design termed 195"CraterLake" includes a Bridge IC (BIC), with room for expansion boards to 196include various compute accelerators (video, inferencing, etc). At the moment, 197only the first server slot's BIC is included. 198 199Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds 200can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__ 201for an example. 202 203In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC 204runs `OpenBMC <https://github.com/facebook/openbmc>`__, and the BIC runs 205`OpenBIC <https://github.com/facebook/openbic>`__. 206 207Firmware images can be retrieved from the Github releases or built from the 208source code, see the README's for instructions on that. This image uses the 209"fby35" machine recipe from OpenBMC, and the "yv35-cl" target from OpenBIC. 210Some reference images can also be found here: 211 212.. code-block:: bash 213 214 $ wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd 215 $ wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf 216 217Since this machine has multiple SoC's, each with their own serial console, the 218recommended way to run it is to allocate a pseudoterminal for each serial 219console and let the monitor use stdio. Also, starting in a paused state is 220useful because it allows you to attach to the pseudoterminals before the boot 221process starts. 222 223.. code-block:: bash 224 225 $ qemu-system-arm -machine fby35 \ 226 -drive file=fby35.mtd,format=raw,if=mtd \ 227 -device loader,file=Y35BCL.elf,addr=0,cpu-num=2 \ 228 -serial pty -serial pty -serial mon:stdio \ 229 -display none -S 230 $ screen /dev/tty0 # In a separate TMUX pane, terminal window, etc. 231 $ screen /dev/tty1 232 $ (qemu) c # Start the boot process once screen is setup. 233