1*530bd660SShawn McCarney{
2*530bd660SShawn McCarney    "rails": [
3*530bd660SShawn McCarney        {
4*530bd660SShawn McCarney            "name": "12.0V",
5*530bd660SShawn McCarney            "page": 0,
6*530bd660SShawn McCarney            "is_power_supply_rail": true,
7*530bd660SShawn McCarney            "check_status_vout": true,
8*530bd660SShawn McCarney            "compare_voltage_to_limit": true
9*530bd660SShawn McCarney        },
10*530bd660SShawn McCarney        {
11*530bd660SShawn McCarney            "name": "3V3IO",
12*530bd660SShawn McCarney            "page": 1,
13*530bd660SShawn McCarney            "check_status_vout": true,
14*530bd660SShawn McCarney            "compare_voltage_to_limit": true
15*530bd660SShawn McCarney        },
16*530bd660SShawn McCarney        {
17*530bd660SShawn McCarney            "name": "CP03_AVDD",
18*530bd660SShawn McCarney            "page": 18,
19*530bd660SShawn McCarney            "check_status_vout": true,
20*530bd660SShawn McCarney            "compare_voltage_to_limit": true
21*530bd660SShawn McCarney        },
22*530bd660SShawn McCarney        {
23*530bd660SShawn McCarney            "name": "CP12_AVDD",
24*530bd660SShawn McCarney            "page": 19,
25*530bd660SShawn McCarney            "check_status_vout": true,
26*530bd660SShawn McCarney            "compare_voltage_to_limit": true
27*530bd660SShawn McCarney        },
28*530bd660SShawn McCarney        {
29*530bd660SShawn McCarney            "name": "CP0_VDN",
30*530bd660SShawn McCarney            "page": 20,
31*530bd660SShawn McCarney            "gpio": { "line": 72 }
32*530bd660SShawn McCarney        },
33*530bd660SShawn McCarney        {
34*530bd660SShawn McCarney            "name": "CP1_VDN",
35*530bd660SShawn McCarney            "page": 21,
36*530bd660SShawn McCarney            "gpio": { "line": 73 }
37*530bd660SShawn McCarney        },
38*530bd660SShawn McCarney        {
39*530bd660SShawn McCarney            "name": "CP2_VDN",
40*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm2/cpu0",
41*530bd660SShawn McCarney            "page": 22,
42*530bd660SShawn McCarney            "gpio": { "line": 74 }
43*530bd660SShawn McCarney        },
44*530bd660SShawn McCarney        {
45*530bd660SShawn McCarney            "name": "CP3_VDN",
46*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm3/cpu0",
47*530bd660SShawn McCarney            "page": 23,
48*530bd660SShawn McCarney            "gpio": { "line": 75 }
49*530bd660SShawn McCarney        },
50*530bd660SShawn McCarney        {
51*530bd660SShawn McCarney            "name": "CP0_VDD0",
52*530bd660SShawn McCarney            "page": 2,
53*530bd660SShawn McCarney            "check_status_vout": true,
54*530bd660SShawn McCarney            "compare_voltage_to_limit": true
55*530bd660SShawn McCarney        },
56*530bd660SShawn McCarney        {
57*530bd660SShawn McCarney            "name": "CP1_VDD0",
58*530bd660SShawn McCarney            "page": 4,
59*530bd660SShawn McCarney            "check_status_vout": true,
60*530bd660SShawn McCarney            "compare_voltage_to_limit": true
61*530bd660SShawn McCarney        },
62*530bd660SShawn McCarney        {
63*530bd660SShawn McCarney            "name": "CP2_VDD0",
64*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm2/cpu0",
65*530bd660SShawn McCarney            "page": 6,
66*530bd660SShawn McCarney            "check_status_vout": true,
67*530bd660SShawn McCarney            "compare_voltage_to_limit": true
68*530bd660SShawn McCarney        },
69*530bd660SShawn McCarney        {
70*530bd660SShawn McCarney            "name": "CP3_VDD0",
71*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm3/cpu0",
72*530bd660SShawn McCarney            "page": 8,
73*530bd660SShawn McCarney            "check_status_vout": true,
74*530bd660SShawn McCarney            "compare_voltage_to_limit": true
75*530bd660SShawn McCarney        },
76*530bd660SShawn McCarney        {
77*530bd660SShawn McCarney            "name": "CP0_VDD1",
78*530bd660SShawn McCarney            "page": 3,
79*530bd660SShawn McCarney            "check_status_vout": true,
80*530bd660SShawn McCarney            "compare_voltage_to_limit": true
81*530bd660SShawn McCarney        },
82*530bd660SShawn McCarney        {
83*530bd660SShawn McCarney            "name": "CP1_VDD1",
84*530bd660SShawn McCarney            "page": 5,
85*530bd660SShawn McCarney            "check_status_vout": true,
86*530bd660SShawn McCarney            "compare_voltage_to_limit": true
87*530bd660SShawn McCarney        },
88*530bd660SShawn McCarney        {
89*530bd660SShawn McCarney            "name": "CP2_VDD1",
90*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm2/cpu0",
91*530bd660SShawn McCarney            "page": 7,
92*530bd660SShawn McCarney            "check_status_vout": true,
93*530bd660SShawn McCarney            "compare_voltage_to_limit": true
94*530bd660SShawn McCarney        },
95*530bd660SShawn McCarney        {
96*530bd660SShawn McCarney            "name": "CP3_VDD1",
97*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm3/cpu0",
98*530bd660SShawn McCarney            "page": 9,
99*530bd660SShawn McCarney            "check_status_vout": true,
100*530bd660SShawn McCarney            "compare_voltage_to_limit": true
101*530bd660SShawn McCarney        },
102*530bd660SShawn McCarney        {
103*530bd660SShawn McCarney            "name": "CP0_VCS0",
104*530bd660SShawn McCarney            "page": 10,
105*530bd660SShawn McCarney            "check_status_vout": true,
106*530bd660SShawn McCarney            "compare_voltage_to_limit": true
107*530bd660SShawn McCarney        },
108*530bd660SShawn McCarney        {
109*530bd660SShawn McCarney            "name": "CP1_VCS0",
110*530bd660SShawn McCarney            "page": 12,
111*530bd660SShawn McCarney            "check_status_vout": true,
112*530bd660SShawn McCarney            "compare_voltage_to_limit": true
113*530bd660SShawn McCarney        },
114*530bd660SShawn McCarney        {
115*530bd660SShawn McCarney            "name": "CP2_VCS0",
116*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm2/cpu0",
117*530bd660SShawn McCarney            "page": 14,
118*530bd660SShawn McCarney            "check_status_vout": true,
119*530bd660SShawn McCarney            "compare_voltage_to_limit": true
120*530bd660SShawn McCarney        },
121*530bd660SShawn McCarney        {
122*530bd660SShawn McCarney            "name": "CP3_VCS0",
123*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm3/cpu0",
124*530bd660SShawn McCarney            "page": 16,
125*530bd660SShawn McCarney            "check_status_vout": true,
126*530bd660SShawn McCarney            "compare_voltage_to_limit": true
127*530bd660SShawn McCarney        },
128*530bd660SShawn McCarney        {
129*530bd660SShawn McCarney            "name": "CP0_VCS1",
130*530bd660SShawn McCarney            "page": 11,
131*530bd660SShawn McCarney            "check_status_vout": true,
132*530bd660SShawn McCarney            "compare_voltage_to_limit": true
133*530bd660SShawn McCarney        },
134*530bd660SShawn McCarney        {
135*530bd660SShawn McCarney            "name": "CP1_VCS1",
136*530bd660SShawn McCarney            "page": 13,
137*530bd660SShawn McCarney            "check_status_vout": true,
138*530bd660SShawn McCarney            "compare_voltage_to_limit": true
139*530bd660SShawn McCarney        },
140*530bd660SShawn McCarney        {
141*530bd660SShawn McCarney            "name": "CP2_VCS1",
142*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm2/cpu0",
143*530bd660SShawn McCarney            "page": 15,
144*530bd660SShawn McCarney            "check_status_vout": true,
145*530bd660SShawn McCarney            "compare_voltage_to_limit": true
146*530bd660SShawn McCarney        },
147*530bd660SShawn McCarney        {
148*530bd660SShawn McCarney            "name": "CP3_VCS1",
149*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm3/cpu0",
150*530bd660SShawn McCarney            "page": 17,
151*530bd660SShawn McCarney            "check_status_vout": true,
152*530bd660SShawn McCarney            "compare_voltage_to_limit": true
153*530bd660SShawn McCarney        },
154*530bd660SShawn McCarney        {
155*530bd660SShawn McCarney            "name": "CP0_VIO",
156*530bd660SShawn McCarney            "page": 24,
157*530bd660SShawn McCarney            "gpio": { "line": 76 }
158*530bd660SShawn McCarney        },
159*530bd660SShawn McCarney        {
160*530bd660SShawn McCarney            "name": "CP1_VIO",
161*530bd660SShawn McCarney            "page": 25,
162*530bd660SShawn McCarney            "gpio": { "line": 77 }
163*530bd660SShawn McCarney        },
164*530bd660SShawn McCarney        {
165*530bd660SShawn McCarney            "name": "CP2_VIO",
166*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm2/cpu0",
167*530bd660SShawn McCarney            "page": 26,
168*530bd660SShawn McCarney            "gpio": { "line": 78 }
169*530bd660SShawn McCarney        },
170*530bd660SShawn McCarney        {
171*530bd660SShawn McCarney            "name": "CP3_VIO",
172*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm3/cpu0",
173*530bd660SShawn McCarney            "page": 27,
174*530bd660SShawn McCarney            "gpio": { "line": 79 }
175*530bd660SShawn McCarney        },
176*530bd660SShawn McCarney        {
177*530bd660SShawn McCarney            "name": "CP0_VPCIE",
178*530bd660SShawn McCarney            "page": 28,
179*530bd660SShawn McCarney            "gpio": { "line": 59 }
180*530bd660SShawn McCarney        },
181*530bd660SShawn McCarney        {
182*530bd660SShawn McCarney            "name": "CP1_VPCIE",
183*530bd660SShawn McCarney            "page": 29,
184*530bd660SShawn McCarney            "gpio": { "line": 60 }
185*530bd660SShawn McCarney        },
186*530bd660SShawn McCarney        {
187*530bd660SShawn McCarney            "name": "CP2_VPCIE",
188*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm2/cpu0",
189*530bd660SShawn McCarney            "page": 30,
190*530bd660SShawn McCarney            "gpio": { "line": 61 }
191*530bd660SShawn McCarney        },
192*530bd660SShawn McCarney        {
193*530bd660SShawn McCarney            "name": "CP3_VPCIE",
194*530bd660SShawn McCarney            "presence": "/xyz/openbmc_project/inventory/system/chassis/motherboard/dcm3/cpu0",
195*530bd660SShawn McCarney            "page": 31,
196*530bd660SShawn McCarney            "gpio": { "line": 62 }
197*530bd660SShawn McCarney        }
198*530bd660SShawn McCarney    ]
199*530bd660SShawn McCarney}
200