1From b06a228a5fd1589fc9bed654b3288b321fc21aa1 Mon Sep 17 00:00:00 2001
2From: "Richard W.M. Jones" <rjones@redhat.com>
3Date: Sun, 20 Nov 2016 15:04:52 +0000
4Subject: [PATCH] Add support for RISC-V.
5
6The architecture is sufficiently similar to aarch64 that simply
7extending the existing aarch64 macro works.
8---
9 src/include/storage/s_lock.h | 5 +++--
10 1 file changed, 3 insertions(+), 2 deletions(-)
11
12--- a/src/include/storage/s_lock.h
13+++ b/src/include/storage/s_lock.h
14@@ -316,11 +316,12 @@ tas(volatile slock_t *lock)
15
16 /*
17  * On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available.
18+ * On RISC-V, the same.
19  *
20  * We use the int-width variant of the builtin because it works on more chips
21  * than other widths.
22  */
23-#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64)
24+#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64) || defined(__riscv)
25 #ifdef HAVE_GCC__SYNC_INT32_TAS
26 #define HAS_TEST_AND_SET
27
28@@ -337,7 +338,7 @@ tas(volatile slock_t *lock)
29 #define S_UNLOCK(lock) __sync_lock_release(lock)
30
31 #endif	 /* HAVE_GCC__SYNC_INT32_TAS */
32-#endif	 /* __arm__ || __arm || __aarch64__ || __aarch64 */
33+#endif	 /* __arm__ || __arm || __aarch64__ || __aarch64 || __riscv */
34
35
36 /* S/390 and S/390x Linux (32- and 64-bit zSeries) */
37