1From ba079b8d6a50796db41bb0ddf4c22bfe022ef898 Mon Sep 17 00:00:00 2001
2From: "Richard W.M. Jones" <rjones@redhat.com>
3Date: Sun, 20 Nov 2016 15:04:52 +0000
4Subject: [PATCH 1/5] Add support for RISC-V.
5
6The architecture is sufficiently similar to aarch64 that simply
7extending the existing aarch64 macro works.
8
9Upstream-Status: Pending
10---
11 src/include/storage/s_lock.h | 5 +++--
12 1 file changed, 3 insertions(+), 2 deletions(-)
13
14diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h
15index c9fa84c..9b491e8 100644
16--- a/src/include/storage/s_lock.h
17+++ b/src/include/storage/s_lock.h
18@@ -252,11 +252,12 @@ spin_delay(void)
19
20 /*
21  * On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available.
22+ * On RISC-V, the same.
23  *
24  * We use the int-width variant of the builtin because it works on more chips
25  * than other widths.
26  */
27-#if defined(__arm__) || defined(__arm) || defined(__aarch64__)
28+#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__riscv)
29 #ifdef HAVE_GCC__SYNC_INT32_TAS
30 #define HAS_TEST_AND_SET
31
32@@ -290,7 +291,7 @@ spin_delay(void)
33
34 #endif	 /* __aarch64__ */
35 #endif	 /* HAVE_GCC__SYNC_INT32_TAS */
36-#endif	 /* __arm__ || __arm || __aarch64__ */
37+#endif	 /* __arm__ || __arm || __aarch64__ || __riscv */
38
39
40 /* S/390 and S/390x Linux (32- and 64-bit zSeries) */
41--
422.25.1
43
44