1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * turbostat -- show CPU frequency and C-state residency 4 * on modern Intel and AMD processors. 5 * 6 * Copyright (c) 2023 Intel Corporation. 7 * Len Brown <len.brown@intel.com> 8 */ 9 10 #define _GNU_SOURCE 11 #include MSRHEADER 12 #include INTEL_FAMILY_HEADER 13 #include <stdarg.h> 14 #include <stdio.h> 15 #include <err.h> 16 #include <unistd.h> 17 #include <sys/types.h> 18 #include <sys/wait.h> 19 #include <sys/stat.h> 20 #include <sys/select.h> 21 #include <sys/resource.h> 22 #include <fcntl.h> 23 #include <signal.h> 24 #include <sys/time.h> 25 #include <stdlib.h> 26 #include <getopt.h> 27 #include <dirent.h> 28 #include <string.h> 29 #include <ctype.h> 30 #include <sched.h> 31 #include <time.h> 32 #include <cpuid.h> 33 #include <sys/capability.h> 34 #include <errno.h> 35 #include <math.h> 36 #include <linux/perf_event.h> 37 #include <asm/unistd.h> 38 #include <stdbool.h> 39 40 #define UNUSED(x) (void)(x) 41 42 /* 43 * This list matches the column headers, except 44 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 45 * 2. Core and CPU are moved to the end, we can't have strings that contain them 46 * matching on them for --show and --hide. 47 */ 48 49 /* 50 * buffer size used by sscanf() for added column names 51 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 52 */ 53 #define NAME_BYTES 20 54 #define PATH_BYTES 128 55 56 enum counter_scope { SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE }; 57 enum counter_type { COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC }; 58 enum counter_format { FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT }; 59 60 struct msr_counter { 61 unsigned int msr_num; 62 char name[NAME_BYTES]; 63 char path[PATH_BYTES]; 64 unsigned int width; 65 enum counter_type type; 66 enum counter_format format; 67 struct msr_counter *next; 68 unsigned int flags; 69 #define FLAGS_HIDE (1 << 0) 70 #define FLAGS_SHOW (1 << 1) 71 #define SYSFS_PERCPU (1 << 1) 72 }; 73 74 struct msr_counter bic[] = { 75 { 0x0, "usec", "", 0, 0, 0, NULL, 0 }, 76 { 0x0, "Time_Of_Day_Seconds", "", 0, 0, 0, NULL, 0 }, 77 { 0x0, "Package", "", 0, 0, 0, NULL, 0 }, 78 { 0x0, "Node", "", 0, 0, 0, NULL, 0 }, 79 { 0x0, "Avg_MHz", "", 0, 0, 0, NULL, 0 }, 80 { 0x0, "Busy%", "", 0, 0, 0, NULL, 0 }, 81 { 0x0, "Bzy_MHz", "", 0, 0, 0, NULL, 0 }, 82 { 0x0, "TSC_MHz", "", 0, 0, 0, NULL, 0 }, 83 { 0x0, "IRQ", "", 0, 0, 0, NULL, 0 }, 84 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL, 0 }, 85 { 0x0, "sysfs", "", 0, 0, 0, NULL, 0 }, 86 { 0x0, "CPU%c1", "", 0, 0, 0, NULL, 0 }, 87 { 0x0, "CPU%c3", "", 0, 0, 0, NULL, 0 }, 88 { 0x0, "CPU%c6", "", 0, 0, 0, NULL, 0 }, 89 { 0x0, "CPU%c7", "", 0, 0, 0, NULL, 0 }, 90 { 0x0, "ThreadC", "", 0, 0, 0, NULL, 0 }, 91 { 0x0, "CoreTmp", "", 0, 0, 0, NULL, 0 }, 92 { 0x0, "CoreCnt", "", 0, 0, 0, NULL, 0 }, 93 { 0x0, "PkgTmp", "", 0, 0, 0, NULL, 0 }, 94 { 0x0, "GFX%rc6", "", 0, 0, 0, NULL, 0 }, 95 { 0x0, "GFXMHz", "", 0, 0, 0, NULL, 0 }, 96 { 0x0, "Pkg%pc2", "", 0, 0, 0, NULL, 0 }, 97 { 0x0, "Pkg%pc3", "", 0, 0, 0, NULL, 0 }, 98 { 0x0, "Pkg%pc6", "", 0, 0, 0, NULL, 0 }, 99 { 0x0, "Pkg%pc7", "", 0, 0, 0, NULL, 0 }, 100 { 0x0, "Pkg%pc8", "", 0, 0, 0, NULL, 0 }, 101 { 0x0, "Pkg%pc9", "", 0, 0, 0, NULL, 0 }, 102 { 0x0, "Pk%pc10", "", 0, 0, 0, NULL, 0 }, 103 { 0x0, "CPU%LPI", "", 0, 0, 0, NULL, 0 }, 104 { 0x0, "SYS%LPI", "", 0, 0, 0, NULL, 0 }, 105 { 0x0, "PkgWatt", "", 0, 0, 0, NULL, 0 }, 106 { 0x0, "CorWatt", "", 0, 0, 0, NULL, 0 }, 107 { 0x0, "GFXWatt", "", 0, 0, 0, NULL, 0 }, 108 { 0x0, "PkgCnt", "", 0, 0, 0, NULL, 0 }, 109 { 0x0, "RAMWatt", "", 0, 0, 0, NULL, 0 }, 110 { 0x0, "PKG_%", "", 0, 0, 0, NULL, 0 }, 111 { 0x0, "RAM_%", "", 0, 0, 0, NULL, 0 }, 112 { 0x0, "Pkg_J", "", 0, 0, 0, NULL, 0 }, 113 { 0x0, "Cor_J", "", 0, 0, 0, NULL, 0 }, 114 { 0x0, "GFX_J", "", 0, 0, 0, NULL, 0 }, 115 { 0x0, "RAM_J", "", 0, 0, 0, NULL, 0 }, 116 { 0x0, "Mod%c6", "", 0, 0, 0, NULL, 0 }, 117 { 0x0, "Totl%C0", "", 0, 0, 0, NULL, 0 }, 118 { 0x0, "Any%C0", "", 0, 0, 0, NULL, 0 }, 119 { 0x0, "GFX%C0", "", 0, 0, 0, NULL, 0 }, 120 { 0x0, "CPUGFX%", "", 0, 0, 0, NULL, 0 }, 121 { 0x0, "Core", "", 0, 0, 0, NULL, 0 }, 122 { 0x0, "CPU", "", 0, 0, 0, NULL, 0 }, 123 { 0x0, "APIC", "", 0, 0, 0, NULL, 0 }, 124 { 0x0, "X2APIC", "", 0, 0, 0, NULL, 0 }, 125 { 0x0, "Die", "", 0, 0, 0, NULL, 0 }, 126 { 0x0, "GFXAMHz", "", 0, 0, 0, NULL, 0 }, 127 { 0x0, "IPC", "", 0, 0, 0, NULL, 0 }, 128 { 0x0, "CoreThr", "", 0, 0, 0, NULL, 0 }, 129 { 0x0, "UncMHz", "", 0, 0, 0, NULL, 0 }, 130 }; 131 132 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 133 #define BIC_USEC (1ULL << 0) 134 #define BIC_TOD (1ULL << 1) 135 #define BIC_Package (1ULL << 2) 136 #define BIC_Node (1ULL << 3) 137 #define BIC_Avg_MHz (1ULL << 4) 138 #define BIC_Busy (1ULL << 5) 139 #define BIC_Bzy_MHz (1ULL << 6) 140 #define BIC_TSC_MHz (1ULL << 7) 141 #define BIC_IRQ (1ULL << 8) 142 #define BIC_SMI (1ULL << 9) 143 #define BIC_sysfs (1ULL << 10) 144 #define BIC_CPU_c1 (1ULL << 11) 145 #define BIC_CPU_c3 (1ULL << 12) 146 #define BIC_CPU_c6 (1ULL << 13) 147 #define BIC_CPU_c7 (1ULL << 14) 148 #define BIC_ThreadC (1ULL << 15) 149 #define BIC_CoreTmp (1ULL << 16) 150 #define BIC_CoreCnt (1ULL << 17) 151 #define BIC_PkgTmp (1ULL << 18) 152 #define BIC_GFX_rc6 (1ULL << 19) 153 #define BIC_GFXMHz (1ULL << 20) 154 #define BIC_Pkgpc2 (1ULL << 21) 155 #define BIC_Pkgpc3 (1ULL << 22) 156 #define BIC_Pkgpc6 (1ULL << 23) 157 #define BIC_Pkgpc7 (1ULL << 24) 158 #define BIC_Pkgpc8 (1ULL << 25) 159 #define BIC_Pkgpc9 (1ULL << 26) 160 #define BIC_Pkgpc10 (1ULL << 27) 161 #define BIC_CPU_LPI (1ULL << 28) 162 #define BIC_SYS_LPI (1ULL << 29) 163 #define BIC_PkgWatt (1ULL << 30) 164 #define BIC_CorWatt (1ULL << 31) 165 #define BIC_GFXWatt (1ULL << 32) 166 #define BIC_PkgCnt (1ULL << 33) 167 #define BIC_RAMWatt (1ULL << 34) 168 #define BIC_PKG__ (1ULL << 35) 169 #define BIC_RAM__ (1ULL << 36) 170 #define BIC_Pkg_J (1ULL << 37) 171 #define BIC_Cor_J (1ULL << 38) 172 #define BIC_GFX_J (1ULL << 39) 173 #define BIC_RAM_J (1ULL << 40) 174 #define BIC_Mod_c6 (1ULL << 41) 175 #define BIC_Totl_c0 (1ULL << 42) 176 #define BIC_Any_c0 (1ULL << 43) 177 #define BIC_GFX_c0 (1ULL << 44) 178 #define BIC_CPUGFX (1ULL << 45) 179 #define BIC_Core (1ULL << 46) 180 #define BIC_CPU (1ULL << 47) 181 #define BIC_APIC (1ULL << 48) 182 #define BIC_X2APIC (1ULL << 49) 183 #define BIC_Die (1ULL << 50) 184 #define BIC_GFXACTMHz (1ULL << 51) 185 #define BIC_IPC (1ULL << 52) 186 #define BIC_CORE_THROT_CNT (1ULL << 53) 187 #define BIC_UNCORE_MHZ (1ULL << 54) 188 189 #define BIC_TOPOLOGY (BIC_Package | BIC_Node | BIC_CoreCnt | BIC_PkgCnt | BIC_Core | BIC_CPU | BIC_Die ) 190 #define BIC_THERMAL_PWR ( BIC_CoreTmp | BIC_PkgTmp | BIC_PkgWatt | BIC_CorWatt | BIC_GFXWatt | BIC_RAMWatt | BIC_PKG__ | BIC_RAM__) 191 #define BIC_FREQUENCY ( BIC_Avg_MHz | BIC_Busy | BIC_Bzy_MHz | BIC_TSC_MHz | BIC_GFXMHz | BIC_GFXACTMHz | BIC_UNCORE_MHZ) 192 #define BIC_IDLE ( BIC_sysfs | BIC_CPU_c1 | BIC_CPU_c3 | BIC_CPU_c6 | BIC_CPU_c7 | BIC_GFX_rc6 | BIC_Pkgpc2 | BIC_Pkgpc3 | BIC_Pkgpc6 | BIC_Pkgpc7 | BIC_Pkgpc8 | BIC_Pkgpc9 | BIC_Pkgpc10 | BIC_CPU_LPI | BIC_SYS_LPI | BIC_Mod_c6 | BIC_Totl_c0 | BIC_Any_c0 | BIC_GFX_c0 | BIC_CPUGFX) 193 #define BIC_OTHER ( BIC_IRQ | BIC_SMI | BIC_ThreadC | BIC_CoreTmp | BIC_IPC) 194 195 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 196 197 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 198 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 199 200 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 201 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME) 202 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 203 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 204 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 205 #define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT) 206 207 char *proc_stat = "/proc/stat"; 208 FILE *outf; 209 int *fd_percpu; 210 int *fd_instr_count_percpu; 211 struct timeval interval_tv = { 5, 0 }; 212 struct timespec interval_ts = { 5, 0 }; 213 214 /* Save original CPU model */ 215 unsigned int model_orig; 216 217 unsigned int num_iterations; 218 unsigned int header_iterations; 219 unsigned int debug; 220 unsigned int quiet; 221 unsigned int shown; 222 unsigned int sums_need_wide_columns; 223 unsigned int rapl_joules; 224 unsigned int summary_only; 225 unsigned int list_header_only; 226 unsigned int dump_only; 227 unsigned int do_snb_cstates; 228 unsigned int do_knl_cstates; 229 unsigned int do_slm_cstates; 230 unsigned int use_c1_residency_msr; 231 unsigned int has_aperf; 232 unsigned int has_epb; 233 unsigned int has_turbo; 234 unsigned int is_hybrid; 235 unsigned int do_irtl_snb; 236 unsigned int do_irtl_hsw; 237 unsigned int units = 1000000; /* MHz etc */ 238 unsigned int genuine_intel; 239 unsigned int authentic_amd; 240 unsigned int hygon_genuine; 241 unsigned int max_level, max_extended_level; 242 unsigned int has_invariant_tsc; 243 unsigned int do_nhm_platform_info; 244 unsigned int no_MSR_MISC_PWR_MGMT; 245 unsigned int aperf_mperf_multiplier = 1; 246 double bclk; 247 double base_hz; 248 unsigned int has_base_hz; 249 double tsc_tweak = 1.0; 250 unsigned int show_pkg_only; 251 unsigned int show_core_only; 252 char *output_buffer, *outp; 253 unsigned int do_rapl; 254 unsigned int do_dts; 255 unsigned int do_ptm; 256 unsigned int do_ipc; 257 unsigned long long gfx_cur_rc6_ms; 258 unsigned long long cpuidle_cur_cpu_lpi_us; 259 unsigned long long cpuidle_cur_sys_lpi_us; 260 unsigned int gfx_cur_mhz; 261 unsigned int gfx_act_mhz; 262 unsigned int tj_max; 263 unsigned int tj_max_override; 264 int tcc_offset_bits; 265 double rapl_power_units, rapl_time_units; 266 double rapl_dram_energy_units, rapl_energy_units; 267 double rapl_joule_counter_range; 268 unsigned int do_core_perf_limit_reasons; 269 unsigned int has_automatic_cstate_conversion; 270 unsigned int dis_cstate_prewake; 271 unsigned int do_gfx_perf_limit_reasons; 272 unsigned int do_ring_perf_limit_reasons; 273 unsigned int crystal_hz; 274 unsigned long long tsc_hz; 275 int base_cpu; 276 double discover_bclk(unsigned int family, unsigned int model); 277 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 278 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 279 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 280 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 281 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 282 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 283 unsigned int has_misc_feature_control; 284 unsigned int first_counter_read = 1; 285 int ignore_stdin; 286 287 #define RAPL_PKG (1 << 0) 288 /* 0x610 MSR_PKG_POWER_LIMIT */ 289 /* 0x611 MSR_PKG_ENERGY_STATUS */ 290 #define RAPL_PKG_PERF_STATUS (1 << 1) 291 /* 0x613 MSR_PKG_PERF_STATUS */ 292 #define RAPL_PKG_POWER_INFO (1 << 2) 293 /* 0x614 MSR_PKG_POWER_INFO */ 294 295 #define RAPL_DRAM (1 << 3) 296 /* 0x618 MSR_DRAM_POWER_LIMIT */ 297 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 298 #define RAPL_DRAM_PERF_STATUS (1 << 4) 299 /* 0x61b MSR_DRAM_PERF_STATUS */ 300 #define RAPL_DRAM_POWER_INFO (1 << 5) 301 /* 0x61c MSR_DRAM_POWER_INFO */ 302 303 #define RAPL_CORES_POWER_LIMIT (1 << 6) 304 /* 0x638 MSR_PP0_POWER_LIMIT */ 305 #define RAPL_CORE_POLICY (1 << 7) 306 /* 0x63a MSR_PP0_POLICY */ 307 308 #define RAPL_GFX (1 << 8) 309 /* 0x640 MSR_PP1_POWER_LIMIT */ 310 /* 0x641 MSR_PP1_ENERGY_STATUS */ 311 /* 0x642 MSR_PP1_POLICY */ 312 313 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 314 /* 0x639 MSR_PP0_ENERGY_STATUS */ 315 #define RAPL_PER_CORE_ENERGY (1 << 10) 316 /* Indicates cores energy collection is per-core, 317 * not per-package. */ 318 #define RAPL_AMD_F17H (1 << 11) 319 /* 0xc0010299 MSR_RAPL_PWR_UNIT */ 320 /* 0xc001029a MSR_CORE_ENERGY_STAT */ 321 /* 0xc001029b MSR_PKG_ENERGY_STAT */ 322 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 323 #define TJMAX_DEFAULT 100 324 325 /* MSRs that are not yet in the kernel-provided header. */ 326 #define MSR_RAPL_PWR_UNIT 0xc0010299 327 #define MSR_CORE_ENERGY_STAT 0xc001029a 328 #define MSR_PKG_ENERGY_STAT 0xc001029b 329 330 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 331 332 int backwards_count; 333 char *progname; 334 335 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 336 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset; 337 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size; 338 #define MAX_ADDED_COUNTERS 8 339 #define MAX_ADDED_THREAD_COUNTERS 24 340 #define BITMASK_SIZE 32 341 342 struct thread_data { 343 struct timeval tv_begin; 344 struct timeval tv_end; 345 struct timeval tv_delta; 346 unsigned long long tsc; 347 unsigned long long aperf; 348 unsigned long long mperf; 349 unsigned long long c1; 350 unsigned long long instr_count; 351 unsigned long long irq_count; 352 unsigned int smi_count; 353 unsigned int cpu_id; 354 unsigned int apic_id; 355 unsigned int x2apic_id; 356 unsigned int flags; 357 bool is_atom; 358 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 359 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 360 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 361 } *thread_even, *thread_odd; 362 363 struct core_data { 364 unsigned long long c3; 365 unsigned long long c6; 366 unsigned long long c7; 367 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 368 unsigned int core_temp_c; 369 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */ 370 unsigned int core_id; 371 unsigned long long core_throt_cnt; 372 unsigned long long counter[MAX_ADDED_COUNTERS]; 373 } *core_even, *core_odd; 374 375 struct pkg_data { 376 unsigned long long pc2; 377 unsigned long long pc3; 378 unsigned long long pc6; 379 unsigned long long pc7; 380 unsigned long long pc8; 381 unsigned long long pc9; 382 unsigned long long pc10; 383 unsigned long long cpu_lpi; 384 unsigned long long sys_lpi; 385 unsigned long long pkg_wtd_core_c0; 386 unsigned long long pkg_any_core_c0; 387 unsigned long long pkg_any_gfxe_c0; 388 unsigned long long pkg_both_core_gfxe_c0; 389 long long gfx_rc6_ms; 390 unsigned int gfx_mhz; 391 unsigned int gfx_act_mhz; 392 unsigned int package_id; 393 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 394 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 395 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */ 396 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 397 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 398 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 399 unsigned int pkg_temp_c; 400 unsigned int uncore_mhz; 401 unsigned long long counter[MAX_ADDED_COUNTERS]; 402 } *package_even, *package_odd; 403 404 #define ODD_COUNTERS thread_odd, core_odd, package_odd 405 #define EVEN_COUNTERS thread_even, core_even, package_even 406 407 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 408 ((thread_base) + \ 409 ((pkg_no) * \ 410 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 411 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 412 ((core_no) * topo.threads_per_core) + \ 413 (thread_no)) 414 415 #define GET_CORE(core_base, core_no, node_no, pkg_no) \ 416 ((core_base) + \ 417 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 418 ((node_no) * topo.cores_per_node) + \ 419 (core_no)) 420 421 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 422 423 /* 424 * The accumulated sum of MSR is defined as a monotonic 425 * increasing MSR, it will be accumulated periodically, 426 * despite its register's bit width. 427 */ 428 enum { 429 IDX_PKG_ENERGY, 430 IDX_DRAM_ENERGY, 431 IDX_PP0_ENERGY, 432 IDX_PP1_ENERGY, 433 IDX_PKG_PERF, 434 IDX_DRAM_PERF, 435 IDX_COUNT, 436 }; 437 438 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr); 439 440 struct msr_sum_array { 441 /* get_msr_sum() = sum + (get_msr() - last) */ 442 struct { 443 /*The accumulated MSR value is updated by the timer */ 444 unsigned long long sum; 445 /*The MSR footprint recorded in last timer */ 446 unsigned long long last; 447 } entries[IDX_COUNT]; 448 }; 449 450 /* The percpu MSR sum array.*/ 451 struct msr_sum_array *per_cpu_msr_sum; 452 453 off_t idx_to_offset(int idx) 454 { 455 off_t offset; 456 457 switch (idx) { 458 case IDX_PKG_ENERGY: 459 if (do_rapl & RAPL_AMD_F17H) 460 offset = MSR_PKG_ENERGY_STAT; 461 else 462 offset = MSR_PKG_ENERGY_STATUS; 463 break; 464 case IDX_DRAM_ENERGY: 465 offset = MSR_DRAM_ENERGY_STATUS; 466 break; 467 case IDX_PP0_ENERGY: 468 offset = MSR_PP0_ENERGY_STATUS; 469 break; 470 case IDX_PP1_ENERGY: 471 offset = MSR_PP1_ENERGY_STATUS; 472 break; 473 case IDX_PKG_PERF: 474 offset = MSR_PKG_PERF_STATUS; 475 break; 476 case IDX_DRAM_PERF: 477 offset = MSR_DRAM_PERF_STATUS; 478 break; 479 default: 480 offset = -1; 481 } 482 return offset; 483 } 484 485 int offset_to_idx(off_t offset) 486 { 487 int idx; 488 489 switch (offset) { 490 case MSR_PKG_ENERGY_STATUS: 491 case MSR_PKG_ENERGY_STAT: 492 idx = IDX_PKG_ENERGY; 493 break; 494 case MSR_DRAM_ENERGY_STATUS: 495 idx = IDX_DRAM_ENERGY; 496 break; 497 case MSR_PP0_ENERGY_STATUS: 498 idx = IDX_PP0_ENERGY; 499 break; 500 case MSR_PP1_ENERGY_STATUS: 501 idx = IDX_PP1_ENERGY; 502 break; 503 case MSR_PKG_PERF_STATUS: 504 idx = IDX_PKG_PERF; 505 break; 506 case MSR_DRAM_PERF_STATUS: 507 idx = IDX_DRAM_PERF; 508 break; 509 default: 510 idx = -1; 511 } 512 return idx; 513 } 514 515 int idx_valid(int idx) 516 { 517 switch (idx) { 518 case IDX_PKG_ENERGY: 519 return do_rapl & (RAPL_PKG | RAPL_AMD_F17H); 520 case IDX_DRAM_ENERGY: 521 return do_rapl & RAPL_DRAM; 522 case IDX_PP0_ENERGY: 523 return do_rapl & RAPL_CORES_ENERGY_STATUS; 524 case IDX_PP1_ENERGY: 525 return do_rapl & RAPL_GFX; 526 case IDX_PKG_PERF: 527 return do_rapl & RAPL_PKG_PERF_STATUS; 528 case IDX_DRAM_PERF: 529 return do_rapl & RAPL_DRAM_PERF_STATUS; 530 default: 531 return 0; 532 } 533 } 534 535 struct sys_counters { 536 unsigned int added_thread_counters; 537 unsigned int added_core_counters; 538 unsigned int added_package_counters; 539 struct msr_counter *tp; 540 struct msr_counter *cp; 541 struct msr_counter *pp; 542 } sys; 543 544 struct system_summary { 545 struct thread_data threads; 546 struct core_data cores; 547 struct pkg_data packages; 548 } average; 549 550 struct cpu_topology { 551 int physical_package_id; 552 int die_id; 553 int logical_cpu_id; 554 int physical_node_id; 555 int logical_node_id; /* 0-based count within the package */ 556 int physical_core_id; 557 int thread_id; 558 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 559 } *cpus; 560 561 struct topo_params { 562 int num_packages; 563 int num_die; 564 int num_cpus; 565 int num_cores; 566 int max_cpu_num; 567 int max_node_num; 568 int nodes_per_pkg; 569 int cores_per_node; 570 int threads_per_core; 571 } topo; 572 573 struct timeval tv_even, tv_odd, tv_delta; 574 575 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 576 int *irqs_per_cpu; /* indexed by cpu_num */ 577 578 void setup_all_buffers(void); 579 580 char *sys_lpi_file; 581 char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us"; 582 char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec"; 583 584 int cpu_is_not_present(int cpu) 585 { 586 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 587 } 588 589 /* 590 * run func(thread, core, package) in topology order 591 * skip non-present cpus 592 */ 593 594 int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *), 595 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 596 { 597 int retval, pkg_no, core_no, thread_no, node_no; 598 599 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 600 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) { 601 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 602 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) { 603 struct thread_data *t; 604 struct core_data *c; 605 struct pkg_data *p; 606 607 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no); 608 609 if (cpu_is_not_present(t->cpu_id)) 610 continue; 611 612 c = GET_CORE(core_base, core_no, node_no, pkg_no); 613 p = GET_PKG(pkg_base, pkg_no); 614 615 retval = func(t, c, p); 616 if (retval) 617 return retval; 618 } 619 } 620 } 621 } 622 return 0; 623 } 624 625 int cpu_migrate(int cpu) 626 { 627 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 628 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 629 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 630 return -1; 631 else 632 return 0; 633 } 634 635 int get_msr_fd(int cpu) 636 { 637 char pathname[32]; 638 int fd; 639 640 fd = fd_percpu[cpu]; 641 642 if (fd) 643 return fd; 644 645 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 646 fd = open(pathname, O_RDONLY); 647 if (fd < 0) 648 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 649 650 fd_percpu[cpu] = fd; 651 652 return fd; 653 } 654 655 static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags) 656 { 657 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags); 658 } 659 660 static int perf_instr_count_open(int cpu_num) 661 { 662 struct perf_event_attr pea; 663 int fd; 664 665 memset(&pea, 0, sizeof(struct perf_event_attr)); 666 pea.type = PERF_TYPE_HARDWARE; 667 pea.size = sizeof(struct perf_event_attr); 668 pea.config = PERF_COUNT_HW_INSTRUCTIONS; 669 670 /* counter for cpu_num, including user + kernel and all processes */ 671 fd = perf_event_open(&pea, -1, cpu_num, -1, 0); 672 if (fd == -1) { 673 warnx("capget(CAP_PERFMON) failed, try \"# setcap cap_sys_admin=ep %s\"", progname); 674 BIC_NOT_PRESENT(BIC_IPC); 675 } 676 677 return fd; 678 } 679 680 int get_instr_count_fd(int cpu) 681 { 682 if (fd_instr_count_percpu[cpu]) 683 return fd_instr_count_percpu[cpu]; 684 685 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu); 686 687 return fd_instr_count_percpu[cpu]; 688 } 689 690 int get_msr(int cpu, off_t offset, unsigned long long *msr) 691 { 692 ssize_t retval; 693 694 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 695 696 if (retval != sizeof *msr) 697 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 698 699 return 0; 700 } 701 702 #define MAX_DEFERRED 16 703 char *deferred_add_names[MAX_DEFERRED]; 704 char *deferred_skip_names[MAX_DEFERRED]; 705 int deferred_add_index; 706 int deferred_skip_index; 707 708 /* 709 * HIDE_LIST - hide this list of counters, show the rest [default] 710 * SHOW_LIST - show this list of counters, hide the rest 711 */ 712 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 713 714 void help(void) 715 { 716 fprintf(outf, 717 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 718 "\n" 719 "Turbostat forks the specified COMMAND and prints statistics\n" 720 "when COMMAND completes.\n" 721 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 722 "to print statistics, until interrupted.\n" 723 " -a, --add add a counter\n" 724 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 725 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n" 726 " {core | package | j,k,l..m,n-p }\n" 727 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n" 728 " -D, --Dump displays the raw counter values\n" 729 " -e, --enable [all | column]\n" 730 " shows all or the specified disabled column\n" 731 " -H, --hide [column|column,column,...]\n" 732 " hide the specified column(s)\n" 733 " -i, --interval sec.subsec\n" 734 " Override default 5-second measurement interval\n" 735 " -J, --Joules displays energy in Joules instead of Watts\n" 736 " -l, --list list column headers only\n" 737 " -n, --num_iterations num\n" 738 " number of the measurement iterations\n" 739 " -N, --header_iterations num\n" 740 " print header every num iterations\n" 741 " -o, --out file\n" 742 " create or truncate \"file\" for all output\n" 743 " -q, --quiet skip decoding system configuration header\n" 744 " -s, --show [column|column,column,...]\n" 745 " show only the specified column(s)\n" 746 " -S, --Summary\n" 747 " limits output to 1-line system summary per interval\n" 748 " -T, --TCC temperature\n" 749 " sets the Thermal Control Circuit temperature in\n" 750 " degrees Celsius\n" 751 " -h, --help print this help message\n" 752 " -v, --version print version information\n" "\n" "For more help, run \"man turbostat\"\n"); 753 } 754 755 /* 756 * bic_lookup 757 * for all the strings in comma separate name_list, 758 * set the approprate bit in return value. 759 */ 760 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 761 { 762 unsigned int i; 763 unsigned long long retval = 0; 764 765 while (name_list) { 766 char *comma; 767 768 comma = strchr(name_list, ','); 769 770 if (comma) 771 *comma = '\0'; 772 773 for (i = 0; i < MAX_BIC; ++i) { 774 if (!strcmp(name_list, bic[i].name)) { 775 retval |= (1ULL << i); 776 break; 777 } 778 if (!strcmp(name_list, "all")) { 779 retval |= ~0; 780 break; 781 } else if (!strcmp(name_list, "topology")) { 782 retval |= BIC_TOPOLOGY; 783 break; 784 } else if (!strcmp(name_list, "power")) { 785 retval |= BIC_THERMAL_PWR; 786 break; 787 } else if (!strcmp(name_list, "idle")) { 788 retval |= BIC_IDLE; 789 break; 790 } else if (!strcmp(name_list, "frequency")) { 791 retval |= BIC_FREQUENCY; 792 break; 793 } else if (!strcmp(name_list, "other")) { 794 retval |= BIC_OTHER; 795 break; 796 } 797 798 } 799 if (i == MAX_BIC) { 800 if (mode == SHOW_LIST) { 801 deferred_add_names[deferred_add_index++] = name_list; 802 if (deferred_add_index >= MAX_DEFERRED) { 803 fprintf(stderr, "More than max %d un-recognized --add options '%s'\n", 804 MAX_DEFERRED, name_list); 805 help(); 806 exit(1); 807 } 808 } else { 809 deferred_skip_names[deferred_skip_index++] = name_list; 810 if (debug) 811 fprintf(stderr, "deferred \"%s\"\n", name_list); 812 if (deferred_skip_index >= MAX_DEFERRED) { 813 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 814 MAX_DEFERRED, name_list); 815 help(); 816 exit(1); 817 } 818 } 819 } 820 821 name_list = comma; 822 if (name_list) 823 name_list++; 824 825 } 826 return retval; 827 } 828 829 void print_header(char *delim) 830 { 831 struct msr_counter *mp; 832 int printed = 0; 833 834 if (DO_BIC(BIC_USEC)) 835 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 836 if (DO_BIC(BIC_TOD)) 837 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 838 if (DO_BIC(BIC_Package)) 839 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 840 if (DO_BIC(BIC_Die)) 841 outp += sprintf(outp, "%sDie", (printed++ ? delim : "")); 842 if (DO_BIC(BIC_Node)) 843 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 844 if (DO_BIC(BIC_Core)) 845 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 846 if (DO_BIC(BIC_CPU)) 847 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 848 if (DO_BIC(BIC_APIC)) 849 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 850 if (DO_BIC(BIC_X2APIC)) 851 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 852 if (DO_BIC(BIC_Avg_MHz)) 853 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 854 if (DO_BIC(BIC_Busy)) 855 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 856 if (DO_BIC(BIC_Bzy_MHz)) 857 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 858 if (DO_BIC(BIC_TSC_MHz)) 859 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 860 861 if (DO_BIC(BIC_IPC)) 862 outp += sprintf(outp, "%sIPC", (printed++ ? delim : "")); 863 864 if (DO_BIC(BIC_IRQ)) { 865 if (sums_need_wide_columns) 866 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 867 else 868 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 869 } 870 871 if (DO_BIC(BIC_SMI)) 872 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 873 874 for (mp = sys.tp; mp; mp = mp->next) { 875 876 if (mp->format == FORMAT_RAW) { 877 if (mp->width == 64) 878 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 879 else 880 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 881 } else { 882 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 883 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 884 else 885 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 886 } 887 } 888 889 if (DO_BIC(BIC_CPU_c1)) 890 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 891 if (DO_BIC(BIC_CPU_c3)) 892 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 893 if (DO_BIC(BIC_CPU_c6)) 894 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 895 if (DO_BIC(BIC_CPU_c7)) 896 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 897 898 if (DO_BIC(BIC_Mod_c6)) 899 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 900 901 if (DO_BIC(BIC_CoreTmp)) 902 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 903 904 if (DO_BIC(BIC_CORE_THROT_CNT)) 905 outp += sprintf(outp, "%sCoreThr", (printed++ ? delim : "")); 906 907 if (do_rapl && !rapl_joules) { 908 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 909 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 910 } else if (do_rapl && rapl_joules) { 911 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 912 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 913 } 914 915 for (mp = sys.cp; mp; mp = mp->next) { 916 if (mp->format == FORMAT_RAW) { 917 if (mp->width == 64) 918 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 919 else 920 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 921 } else { 922 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 923 outp += sprintf(outp, "%s%8s", delim, mp->name); 924 else 925 outp += sprintf(outp, "%s%s", delim, mp->name); 926 } 927 } 928 929 if (DO_BIC(BIC_PkgTmp)) 930 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 931 932 if (DO_BIC(BIC_GFX_rc6)) 933 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 934 935 if (DO_BIC(BIC_GFXMHz)) 936 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 937 938 if (DO_BIC(BIC_GFXACTMHz)) 939 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : "")); 940 941 if (DO_BIC(BIC_Totl_c0)) 942 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 943 if (DO_BIC(BIC_Any_c0)) 944 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 945 if (DO_BIC(BIC_GFX_c0)) 946 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 947 if (DO_BIC(BIC_CPUGFX)) 948 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 949 950 if (DO_BIC(BIC_Pkgpc2)) 951 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 952 if (DO_BIC(BIC_Pkgpc3)) 953 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 954 if (DO_BIC(BIC_Pkgpc6)) 955 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 956 if (DO_BIC(BIC_Pkgpc7)) 957 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 958 if (DO_BIC(BIC_Pkgpc8)) 959 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 960 if (DO_BIC(BIC_Pkgpc9)) 961 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 962 if (DO_BIC(BIC_Pkgpc10)) 963 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 964 if (DO_BIC(BIC_CPU_LPI)) 965 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 966 if (DO_BIC(BIC_SYS_LPI)) 967 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 968 969 if (do_rapl && !rapl_joules) { 970 if (DO_BIC(BIC_PkgWatt)) 971 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 972 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 973 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 974 if (DO_BIC(BIC_GFXWatt)) 975 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 976 if (DO_BIC(BIC_RAMWatt)) 977 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 978 if (DO_BIC(BIC_PKG__)) 979 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 980 if (DO_BIC(BIC_RAM__)) 981 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 982 } else if (do_rapl && rapl_joules) { 983 if (DO_BIC(BIC_Pkg_J)) 984 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 985 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 986 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 987 if (DO_BIC(BIC_GFX_J)) 988 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 989 if (DO_BIC(BIC_RAM_J)) 990 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 991 if (DO_BIC(BIC_PKG__)) 992 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 993 if (DO_BIC(BIC_RAM__)) 994 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 995 } 996 if (DO_BIC(BIC_UNCORE_MHZ)) 997 outp += sprintf(outp, "%sUncMHz", (printed++ ? delim : "")); 998 999 for (mp = sys.pp; mp; mp = mp->next) { 1000 if (mp->format == FORMAT_RAW) { 1001 if (mp->width == 64) 1002 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 1003 else 1004 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 1005 } else { 1006 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1007 outp += sprintf(outp, "%s%8s", delim, mp->name); 1008 else 1009 outp += sprintf(outp, "%s%s", delim, mp->name); 1010 } 1011 } 1012 1013 outp += sprintf(outp, "\n"); 1014 } 1015 1016 int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1017 { 1018 int i; 1019 struct msr_counter *mp; 1020 1021 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 1022 1023 if (t) { 1024 outp += sprintf(outp, "CPU: %d flags 0x%x\n", t->cpu_id, t->flags); 1025 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 1026 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 1027 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 1028 outp += sprintf(outp, "c1: %016llX\n", t->c1); 1029 1030 if (DO_BIC(BIC_IPC)) 1031 outp += sprintf(outp, "IPC: %lld\n", t->instr_count); 1032 1033 if (DO_BIC(BIC_IRQ)) 1034 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 1035 if (DO_BIC(BIC_SMI)) 1036 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 1037 1038 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1039 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, t->counter[i]); 1040 } 1041 } 1042 1043 if (c) { 1044 outp += sprintf(outp, "core: %d\n", c->core_id); 1045 outp += sprintf(outp, "c3: %016llX\n", c->c3); 1046 outp += sprintf(outp, "c6: %016llX\n", c->c6); 1047 outp += sprintf(outp, "c7: %016llX\n", c->c7); 1048 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 1049 outp += sprintf(outp, "cpu_throt_count: %016llX\n", c->core_throt_cnt); 1050 outp += sprintf(outp, "Joules: %0X\n", c->core_energy); 1051 1052 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1053 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, c->counter[i]); 1054 } 1055 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 1056 } 1057 1058 if (p) { 1059 outp += sprintf(outp, "package: %d\n", p->package_id); 1060 1061 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 1062 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 1063 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 1064 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 1065 1066 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 1067 if (DO_BIC(BIC_Pkgpc3)) 1068 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 1069 if (DO_BIC(BIC_Pkgpc6)) 1070 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 1071 if (DO_BIC(BIC_Pkgpc7)) 1072 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 1073 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 1074 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 1075 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 1076 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 1077 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 1078 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg); 1079 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores); 1080 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx); 1081 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram); 1082 outp += sprintf(outp, "Throttle PKG: %0llX\n", p->rapl_pkg_perf_status); 1083 outp += sprintf(outp, "Throttle RAM: %0llX\n", p->rapl_dram_perf_status); 1084 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 1085 1086 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1087 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, p->counter[i]); 1088 } 1089 } 1090 1091 outp += sprintf(outp, "\n"); 1092 1093 return 0; 1094 } 1095 1096 /* 1097 * column formatting convention & formats 1098 */ 1099 int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1100 { 1101 double interval_float, tsc; 1102 char *fmt8; 1103 int i; 1104 struct msr_counter *mp; 1105 char *delim = "\t"; 1106 int printed = 0; 1107 1108 /* if showing only 1st thread in core and this isn't one, bail out */ 1109 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1110 return 0; 1111 1112 /* if showing only 1st thread in pkg and this isn't one, bail out */ 1113 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1114 return 0; 1115 1116 /*if not summary line and --cpu is used */ 1117 if ((t != &average.threads) && (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 1118 return 0; 1119 1120 if (DO_BIC(BIC_USEC)) { 1121 /* on each row, print how many usec each timestamp took to gather */ 1122 struct timeval tv; 1123 1124 timersub(&t->tv_end, &t->tv_begin, &tv); 1125 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 1126 } 1127 1128 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 1129 if (DO_BIC(BIC_TOD)) 1130 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 1131 1132 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec / 1000000.0; 1133 1134 tsc = t->tsc * tsc_tweak; 1135 1136 /* topo columns, print blanks on 1st (average) line */ 1137 if (t == &average.threads) { 1138 if (DO_BIC(BIC_Package)) 1139 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1140 if (DO_BIC(BIC_Die)) 1141 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1142 if (DO_BIC(BIC_Node)) 1143 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1144 if (DO_BIC(BIC_Core)) 1145 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1146 if (DO_BIC(BIC_CPU)) 1147 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1148 if (DO_BIC(BIC_APIC)) 1149 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1150 if (DO_BIC(BIC_X2APIC)) 1151 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1152 } else { 1153 if (DO_BIC(BIC_Package)) { 1154 if (p) 1155 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 1156 else 1157 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1158 } 1159 if (DO_BIC(BIC_Die)) { 1160 if (c) 1161 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id); 1162 else 1163 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1164 } 1165 if (DO_BIC(BIC_Node)) { 1166 if (t) 1167 outp += sprintf(outp, "%s%d", 1168 (printed++ ? delim : ""), cpus[t->cpu_id].physical_node_id); 1169 else 1170 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1171 } 1172 if (DO_BIC(BIC_Core)) { 1173 if (c) 1174 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 1175 else 1176 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1177 } 1178 if (DO_BIC(BIC_CPU)) 1179 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 1180 if (DO_BIC(BIC_APIC)) 1181 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 1182 if (DO_BIC(BIC_X2APIC)) 1183 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 1184 } 1185 1186 if (DO_BIC(BIC_Avg_MHz)) 1187 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 / units * t->aperf / interval_float); 1188 1189 if (DO_BIC(BIC_Busy)) 1190 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf / tsc); 1191 1192 if (DO_BIC(BIC_Bzy_MHz)) { 1193 if (has_base_hz) 1194 outp += 1195 sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 1196 else 1197 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1198 tsc / units * t->aperf / t->mperf / interval_float); 1199 } 1200 1201 if (DO_BIC(BIC_TSC_MHz)) 1202 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc / units / interval_float); 1203 1204 if (DO_BIC(BIC_IPC)) 1205 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf); 1206 1207 /* IRQ */ 1208 if (DO_BIC(BIC_IRQ)) { 1209 if (sums_need_wide_columns) 1210 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 1211 else 1212 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 1213 } 1214 1215 /* SMI */ 1216 if (DO_BIC(BIC_SMI)) 1217 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 1218 1219 /* Added counters */ 1220 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1221 if (mp->format == FORMAT_RAW) { 1222 if (mp->width == 32) 1223 outp += 1224 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]); 1225 else 1226 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 1227 } else if (mp->format == FORMAT_DELTA) { 1228 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1229 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 1230 else 1231 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 1232 } else if (mp->format == FORMAT_PERCENT) { 1233 if (mp->type == COUNTER_USEC) 1234 outp += 1235 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1236 t->counter[i] / interval_float / 10000); 1237 else 1238 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i] / tsc); 1239 } 1240 } 1241 1242 /* C1 */ 1243 if (DO_BIC(BIC_CPU_c1)) 1244 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1 / tsc); 1245 1246 /* print per-core data only for 1st thread in core */ 1247 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1248 goto done; 1249 1250 if (DO_BIC(BIC_CPU_c3)) 1251 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3 / tsc); 1252 if (DO_BIC(BIC_CPU_c6)) 1253 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6 / tsc); 1254 if (DO_BIC(BIC_CPU_c7)) 1255 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7 / tsc); 1256 1257 /* Mod%c6 */ 1258 if (DO_BIC(BIC_Mod_c6)) 1259 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 1260 1261 if (DO_BIC(BIC_CoreTmp)) 1262 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1263 1264 /* Core throttle count */ 1265 if (DO_BIC(BIC_CORE_THROT_CNT)) 1266 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->core_throt_cnt); 1267 1268 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1269 if (mp->format == FORMAT_RAW) { 1270 if (mp->width == 32) 1271 outp += 1272 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]); 1273 else 1274 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1275 } else if (mp->format == FORMAT_DELTA) { 1276 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1277 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1278 else 1279 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1280 } else if (mp->format == FORMAT_PERCENT) { 1281 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i] / tsc); 1282 } 1283 } 1284 1285 fmt8 = "%s%.2f"; 1286 1287 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1288 outp += 1289 sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float); 1290 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1291 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units); 1292 1293 /* print per-package data only for 1st core in package */ 1294 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1295 goto done; 1296 1297 /* PkgTmp */ 1298 if (DO_BIC(BIC_PkgTmp)) 1299 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1300 1301 /* GFXrc6 */ 1302 if (DO_BIC(BIC_GFX_rc6)) { 1303 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1304 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1305 } else { 1306 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1307 p->gfx_rc6_ms / 10.0 / interval_float); 1308 } 1309 } 1310 1311 /* GFXMHz */ 1312 if (DO_BIC(BIC_GFXMHz)) 1313 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1314 1315 /* GFXACTMHz */ 1316 if (DO_BIC(BIC_GFXACTMHz)) 1317 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz); 1318 1319 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1320 if (DO_BIC(BIC_Totl_c0)) 1321 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0 / tsc); 1322 if (DO_BIC(BIC_Any_c0)) 1323 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0 / tsc); 1324 if (DO_BIC(BIC_GFX_c0)) 1325 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0 / tsc); 1326 if (DO_BIC(BIC_CPUGFX)) 1327 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0 / tsc); 1328 1329 if (DO_BIC(BIC_Pkgpc2)) 1330 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2 / tsc); 1331 if (DO_BIC(BIC_Pkgpc3)) 1332 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3 / tsc); 1333 if (DO_BIC(BIC_Pkgpc6)) 1334 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6 / tsc); 1335 if (DO_BIC(BIC_Pkgpc7)) 1336 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7 / tsc); 1337 if (DO_BIC(BIC_Pkgpc8)) 1338 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8 / tsc); 1339 if (DO_BIC(BIC_Pkgpc9)) 1340 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9 / tsc); 1341 if (DO_BIC(BIC_Pkgpc10)) 1342 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10 / tsc); 1343 1344 if (DO_BIC(BIC_CPU_LPI)) 1345 outp += 1346 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1347 if (DO_BIC(BIC_SYS_LPI)) 1348 outp += 1349 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1350 1351 if (DO_BIC(BIC_PkgWatt)) 1352 outp += 1353 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1354 1355 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1356 outp += 1357 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1358 if (DO_BIC(BIC_GFXWatt)) 1359 outp += 1360 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1361 if (DO_BIC(BIC_RAMWatt)) 1362 outp += 1363 sprintf(outp, fmt8, (printed++ ? delim : ""), 1364 p->energy_dram * rapl_dram_energy_units / interval_float); 1365 if (DO_BIC(BIC_Pkg_J)) 1366 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 1367 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1368 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 1369 if (DO_BIC(BIC_GFX_J)) 1370 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 1371 if (DO_BIC(BIC_RAM_J)) 1372 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 1373 if (DO_BIC(BIC_PKG__)) 1374 outp += 1375 sprintf(outp, fmt8, (printed++ ? delim : ""), 1376 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 1377 if (DO_BIC(BIC_RAM__)) 1378 outp += 1379 sprintf(outp, fmt8, (printed++ ? delim : ""), 1380 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 1381 /* UncMHz */ 1382 if (DO_BIC(BIC_UNCORE_MHZ)) 1383 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->uncore_mhz); 1384 1385 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1386 if (mp->format == FORMAT_RAW) { 1387 if (mp->width == 32) 1388 outp += 1389 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]); 1390 else 1391 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 1392 } else if (mp->format == FORMAT_DELTA) { 1393 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1394 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 1395 else 1396 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 1397 } else if (mp->format == FORMAT_PERCENT) { 1398 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i] / tsc); 1399 } 1400 } 1401 1402 done: 1403 if (*(outp - 1) != '\n') 1404 outp += sprintf(outp, "\n"); 1405 1406 return 0; 1407 } 1408 1409 void flush_output_stdout(void) 1410 { 1411 FILE *filep; 1412 1413 if (outf == stderr) 1414 filep = stdout; 1415 else 1416 filep = outf; 1417 1418 fputs(output_buffer, filep); 1419 fflush(filep); 1420 1421 outp = output_buffer; 1422 } 1423 1424 void flush_output_stderr(void) 1425 { 1426 fputs(output_buffer, outf); 1427 fflush(outf); 1428 outp = output_buffer; 1429 } 1430 1431 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1432 { 1433 static int count; 1434 1435 if ((!count || (header_iterations && !(count % header_iterations))) || !summary_only) 1436 print_header("\t"); 1437 1438 format_counters(&average.threads, &average.cores, &average.packages); 1439 1440 count++; 1441 1442 if (summary_only) 1443 return; 1444 1445 for_all_cpus(format_counters, t, c, p); 1446 } 1447 1448 #define DELTA_WRAP32(new, old) \ 1449 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32); 1450 1451 int delta_package(struct pkg_data *new, struct pkg_data *old) 1452 { 1453 int i; 1454 struct msr_counter *mp; 1455 1456 if (DO_BIC(BIC_Totl_c0)) 1457 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 1458 if (DO_BIC(BIC_Any_c0)) 1459 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 1460 if (DO_BIC(BIC_GFX_c0)) 1461 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 1462 if (DO_BIC(BIC_CPUGFX)) 1463 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 1464 1465 old->pc2 = new->pc2 - old->pc2; 1466 if (DO_BIC(BIC_Pkgpc3)) 1467 old->pc3 = new->pc3 - old->pc3; 1468 if (DO_BIC(BIC_Pkgpc6)) 1469 old->pc6 = new->pc6 - old->pc6; 1470 if (DO_BIC(BIC_Pkgpc7)) 1471 old->pc7 = new->pc7 - old->pc7; 1472 old->pc8 = new->pc8 - old->pc8; 1473 old->pc9 = new->pc9 - old->pc9; 1474 old->pc10 = new->pc10 - old->pc10; 1475 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 1476 old->sys_lpi = new->sys_lpi - old->sys_lpi; 1477 old->pkg_temp_c = new->pkg_temp_c; 1478 1479 /* flag an error when rc6 counter resets/wraps */ 1480 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 1481 old->gfx_rc6_ms = -1; 1482 else 1483 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 1484 1485 old->uncore_mhz = new->uncore_mhz; 1486 old->gfx_mhz = new->gfx_mhz; 1487 old->gfx_act_mhz = new->gfx_act_mhz; 1488 1489 old->energy_pkg = new->energy_pkg - old->energy_pkg; 1490 old->energy_cores = new->energy_cores - old->energy_cores; 1491 old->energy_gfx = new->energy_gfx - old->energy_gfx; 1492 old->energy_dram = new->energy_dram - old->energy_dram; 1493 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status; 1494 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status; 1495 1496 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1497 if (mp->format == FORMAT_RAW) 1498 old->counter[i] = new->counter[i]; 1499 else 1500 old->counter[i] = new->counter[i] - old->counter[i]; 1501 } 1502 1503 return 0; 1504 } 1505 1506 void delta_core(struct core_data *new, struct core_data *old) 1507 { 1508 int i; 1509 struct msr_counter *mp; 1510 1511 old->c3 = new->c3 - old->c3; 1512 old->c6 = new->c6 - old->c6; 1513 old->c7 = new->c7 - old->c7; 1514 old->core_temp_c = new->core_temp_c; 1515 old->core_throt_cnt = new->core_throt_cnt; 1516 old->mc6_us = new->mc6_us - old->mc6_us; 1517 1518 DELTA_WRAP32(new->core_energy, old->core_energy); 1519 1520 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1521 if (mp->format == FORMAT_RAW) 1522 old->counter[i] = new->counter[i]; 1523 else 1524 old->counter[i] = new->counter[i] - old->counter[i]; 1525 } 1526 } 1527 1528 int soft_c1_residency_display(int bic) 1529 { 1530 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr) 1531 return 0; 1532 1533 return DO_BIC_READ(bic); 1534 } 1535 1536 /* 1537 * old = new - old 1538 */ 1539 int delta_thread(struct thread_data *new, struct thread_data *old, struct core_data *core_delta) 1540 { 1541 int i; 1542 struct msr_counter *mp; 1543 1544 /* we run cpuid just the 1st time, copy the results */ 1545 if (DO_BIC(BIC_APIC)) 1546 new->apic_id = old->apic_id; 1547 if (DO_BIC(BIC_X2APIC)) 1548 new->x2apic_id = old->x2apic_id; 1549 1550 /* 1551 * the timestamps from start of measurement interval are in "old" 1552 * the timestamp from end of measurement interval are in "new" 1553 * over-write old w/ new so we can print end of interval values 1554 */ 1555 1556 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta); 1557 old->tv_begin = new->tv_begin; 1558 old->tv_end = new->tv_end; 1559 1560 old->tsc = new->tsc - old->tsc; 1561 1562 /* check for TSC < 1 Mcycles over interval */ 1563 if (old->tsc < (1000 * 1000)) 1564 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1565 "You can disable all c-states by booting with \"idle=poll\"\n" 1566 "or just the deep ones with \"processor.max_cstate=1\""); 1567 1568 old->c1 = new->c1 - old->c1; 1569 1570 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) { 1571 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1572 old->aperf = new->aperf - old->aperf; 1573 old->mperf = new->mperf - old->mperf; 1574 } else { 1575 return -1; 1576 } 1577 } 1578 1579 if (use_c1_residency_msr) { 1580 /* 1581 * Some models have a dedicated C1 residency MSR, 1582 * which should be more accurate than the derivation below. 1583 */ 1584 } else { 1585 /* 1586 * As counter collection is not atomic, 1587 * it is possible for mperf's non-halted cycles + idle states 1588 * to exceed TSC's all cycles: show c1 = 0% in that case. 1589 */ 1590 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 1591 old->c1 = 0; 1592 else { 1593 /* normal case, derive c1 */ 1594 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1595 - core_delta->c6 - core_delta->c7; 1596 } 1597 } 1598 1599 if (old->mperf == 0) { 1600 if (debug > 1) 1601 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1602 old->mperf = 1; /* divide by 0 protection */ 1603 } 1604 1605 if (DO_BIC(BIC_IPC)) 1606 old->instr_count = new->instr_count - old->instr_count; 1607 1608 if (DO_BIC(BIC_IRQ)) 1609 old->irq_count = new->irq_count - old->irq_count; 1610 1611 if (DO_BIC(BIC_SMI)) 1612 old->smi_count = new->smi_count - old->smi_count; 1613 1614 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1615 if (mp->format == FORMAT_RAW) 1616 old->counter[i] = new->counter[i]; 1617 else 1618 old->counter[i] = new->counter[i] - old->counter[i]; 1619 } 1620 return 0; 1621 } 1622 1623 int delta_cpu(struct thread_data *t, struct core_data *c, 1624 struct pkg_data *p, struct thread_data *t2, struct core_data *c2, struct pkg_data *p2) 1625 { 1626 int retval = 0; 1627 1628 /* calculate core delta only for 1st thread in core */ 1629 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1630 delta_core(c, c2); 1631 1632 /* always calculate thread delta */ 1633 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1634 if (retval) 1635 return retval; 1636 1637 /* calculate package delta only for 1st core in package */ 1638 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1639 retval = delta_package(p, p2); 1640 1641 return retval; 1642 } 1643 1644 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1645 { 1646 int i; 1647 struct msr_counter *mp; 1648 1649 t->tv_begin.tv_sec = 0; 1650 t->tv_begin.tv_usec = 0; 1651 t->tv_end.tv_sec = 0; 1652 t->tv_end.tv_usec = 0; 1653 t->tv_delta.tv_sec = 0; 1654 t->tv_delta.tv_usec = 0; 1655 1656 t->tsc = 0; 1657 t->aperf = 0; 1658 t->mperf = 0; 1659 t->c1 = 0; 1660 1661 t->instr_count = 0; 1662 1663 t->irq_count = 0; 1664 t->smi_count = 0; 1665 1666 /* tells format_counters to dump all fields from this set */ 1667 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1668 1669 c->c3 = 0; 1670 c->c6 = 0; 1671 c->c7 = 0; 1672 c->mc6_us = 0; 1673 c->core_temp_c = 0; 1674 c->core_energy = 0; 1675 c->core_throt_cnt = 0; 1676 1677 p->pkg_wtd_core_c0 = 0; 1678 p->pkg_any_core_c0 = 0; 1679 p->pkg_any_gfxe_c0 = 0; 1680 p->pkg_both_core_gfxe_c0 = 0; 1681 1682 p->pc2 = 0; 1683 if (DO_BIC(BIC_Pkgpc3)) 1684 p->pc3 = 0; 1685 if (DO_BIC(BIC_Pkgpc6)) 1686 p->pc6 = 0; 1687 if (DO_BIC(BIC_Pkgpc7)) 1688 p->pc7 = 0; 1689 p->pc8 = 0; 1690 p->pc9 = 0; 1691 p->pc10 = 0; 1692 p->cpu_lpi = 0; 1693 p->sys_lpi = 0; 1694 1695 p->energy_pkg = 0; 1696 p->energy_dram = 0; 1697 p->energy_cores = 0; 1698 p->energy_gfx = 0; 1699 p->rapl_pkg_perf_status = 0; 1700 p->rapl_dram_perf_status = 0; 1701 p->pkg_temp_c = 0; 1702 1703 p->gfx_rc6_ms = 0; 1704 p->uncore_mhz = 0; 1705 p->gfx_mhz = 0; 1706 p->gfx_act_mhz = 0; 1707 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1708 t->counter[i] = 0; 1709 1710 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1711 c->counter[i] = 0; 1712 1713 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1714 p->counter[i] = 0; 1715 } 1716 1717 int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1718 { 1719 int i; 1720 struct msr_counter *mp; 1721 1722 /* copy un-changing apic_id's */ 1723 if (DO_BIC(BIC_APIC)) 1724 average.threads.apic_id = t->apic_id; 1725 if (DO_BIC(BIC_X2APIC)) 1726 average.threads.x2apic_id = t->x2apic_id; 1727 1728 /* remember first tv_begin */ 1729 if (average.threads.tv_begin.tv_sec == 0) 1730 average.threads.tv_begin = t->tv_begin; 1731 1732 /* remember last tv_end */ 1733 average.threads.tv_end = t->tv_end; 1734 1735 average.threads.tsc += t->tsc; 1736 average.threads.aperf += t->aperf; 1737 average.threads.mperf += t->mperf; 1738 average.threads.c1 += t->c1; 1739 1740 average.threads.instr_count += t->instr_count; 1741 1742 average.threads.irq_count += t->irq_count; 1743 average.threads.smi_count += t->smi_count; 1744 1745 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1746 if (mp->format == FORMAT_RAW) 1747 continue; 1748 average.threads.counter[i] += t->counter[i]; 1749 } 1750 1751 /* sum per-core values only for 1st thread in core */ 1752 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1753 return 0; 1754 1755 average.cores.c3 += c->c3; 1756 average.cores.c6 += c->c6; 1757 average.cores.c7 += c->c7; 1758 average.cores.mc6_us += c->mc6_us; 1759 1760 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1761 average.cores.core_throt_cnt = MAX(average.cores.core_throt_cnt, c->core_throt_cnt); 1762 1763 average.cores.core_energy += c->core_energy; 1764 1765 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1766 if (mp->format == FORMAT_RAW) 1767 continue; 1768 average.cores.counter[i] += c->counter[i]; 1769 } 1770 1771 /* sum per-pkg values only for 1st core in pkg */ 1772 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1773 return 0; 1774 1775 if (DO_BIC(BIC_Totl_c0)) 1776 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1777 if (DO_BIC(BIC_Any_c0)) 1778 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1779 if (DO_BIC(BIC_GFX_c0)) 1780 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1781 if (DO_BIC(BIC_CPUGFX)) 1782 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1783 1784 average.packages.pc2 += p->pc2; 1785 if (DO_BIC(BIC_Pkgpc3)) 1786 average.packages.pc3 += p->pc3; 1787 if (DO_BIC(BIC_Pkgpc6)) 1788 average.packages.pc6 += p->pc6; 1789 if (DO_BIC(BIC_Pkgpc7)) 1790 average.packages.pc7 += p->pc7; 1791 average.packages.pc8 += p->pc8; 1792 average.packages.pc9 += p->pc9; 1793 average.packages.pc10 += p->pc10; 1794 1795 average.packages.cpu_lpi = p->cpu_lpi; 1796 average.packages.sys_lpi = p->sys_lpi; 1797 1798 average.packages.energy_pkg += p->energy_pkg; 1799 average.packages.energy_dram += p->energy_dram; 1800 average.packages.energy_cores += p->energy_cores; 1801 average.packages.energy_gfx += p->energy_gfx; 1802 1803 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1804 average.packages.uncore_mhz = p->uncore_mhz; 1805 average.packages.gfx_mhz = p->gfx_mhz; 1806 average.packages.gfx_act_mhz = p->gfx_act_mhz; 1807 1808 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1809 1810 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1811 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1812 1813 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1814 if ((mp->format == FORMAT_RAW) && (topo.num_packages == 0)) 1815 average.packages.counter[i] = p->counter[i]; 1816 else 1817 average.packages.counter[i] += p->counter[i]; 1818 } 1819 return 0; 1820 } 1821 1822 /* 1823 * sum the counters for all cpus in the system 1824 * compute the weighted average 1825 */ 1826 void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1827 { 1828 int i; 1829 struct msr_counter *mp; 1830 1831 clear_counters(&average.threads, &average.cores, &average.packages); 1832 1833 for_all_cpus(sum_counters, t, c, p); 1834 1835 /* Use the global time delta for the average. */ 1836 average.threads.tv_delta = tv_delta; 1837 1838 average.threads.tsc /= topo.num_cpus; 1839 average.threads.aperf /= topo.num_cpus; 1840 average.threads.mperf /= topo.num_cpus; 1841 average.threads.instr_count /= topo.num_cpus; 1842 average.threads.c1 /= topo.num_cpus; 1843 1844 if (average.threads.irq_count > 9999999) 1845 sums_need_wide_columns = 1; 1846 1847 average.cores.c3 /= topo.num_cores; 1848 average.cores.c6 /= topo.num_cores; 1849 average.cores.c7 /= topo.num_cores; 1850 average.cores.mc6_us /= topo.num_cores; 1851 1852 if (DO_BIC(BIC_Totl_c0)) 1853 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1854 if (DO_BIC(BIC_Any_c0)) 1855 average.packages.pkg_any_core_c0 /= topo.num_packages; 1856 if (DO_BIC(BIC_GFX_c0)) 1857 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1858 if (DO_BIC(BIC_CPUGFX)) 1859 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1860 1861 average.packages.pc2 /= topo.num_packages; 1862 if (DO_BIC(BIC_Pkgpc3)) 1863 average.packages.pc3 /= topo.num_packages; 1864 if (DO_BIC(BIC_Pkgpc6)) 1865 average.packages.pc6 /= topo.num_packages; 1866 if (DO_BIC(BIC_Pkgpc7)) 1867 average.packages.pc7 /= topo.num_packages; 1868 1869 average.packages.pc8 /= topo.num_packages; 1870 average.packages.pc9 /= topo.num_packages; 1871 average.packages.pc10 /= topo.num_packages; 1872 1873 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1874 if (mp->format == FORMAT_RAW) 1875 continue; 1876 if (mp->type == COUNTER_ITEMS) { 1877 if (average.threads.counter[i] > 9999999) 1878 sums_need_wide_columns = 1; 1879 continue; 1880 } 1881 average.threads.counter[i] /= topo.num_cpus; 1882 } 1883 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1884 if (mp->format == FORMAT_RAW) 1885 continue; 1886 if (mp->type == COUNTER_ITEMS) { 1887 if (average.cores.counter[i] > 9999999) 1888 sums_need_wide_columns = 1; 1889 } 1890 average.cores.counter[i] /= topo.num_cores; 1891 } 1892 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1893 if (mp->format == FORMAT_RAW) 1894 continue; 1895 if (mp->type == COUNTER_ITEMS) { 1896 if (average.packages.counter[i] > 9999999) 1897 sums_need_wide_columns = 1; 1898 } 1899 average.packages.counter[i] /= topo.num_packages; 1900 } 1901 } 1902 1903 static unsigned long long rdtsc(void) 1904 { 1905 unsigned int low, high; 1906 1907 asm volatile ("rdtsc":"=a" (low), "=d"(high)); 1908 1909 return low | ((unsigned long long)high) << 32; 1910 } 1911 1912 /* 1913 * Open a file, and exit on failure 1914 */ 1915 FILE *fopen_or_die(const char *path, const char *mode) 1916 { 1917 FILE *filep = fopen(path, mode); 1918 1919 if (!filep) 1920 err(1, "%s: open failed", path); 1921 return filep; 1922 } 1923 1924 /* 1925 * snapshot_sysfs_counter() 1926 * 1927 * return snapshot of given counter 1928 */ 1929 unsigned long long snapshot_sysfs_counter(char *path) 1930 { 1931 FILE *fp; 1932 int retval; 1933 unsigned long long counter; 1934 1935 fp = fopen_or_die(path, "r"); 1936 1937 retval = fscanf(fp, "%lld", &counter); 1938 if (retval != 1) 1939 err(1, "snapshot_sysfs_counter(%s)", path); 1940 1941 fclose(fp); 1942 1943 return counter; 1944 } 1945 1946 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 1947 { 1948 if (mp->msr_num != 0) { 1949 if (get_msr(cpu, mp->msr_num, counterp)) 1950 return -1; 1951 } else { 1952 char path[128 + PATH_BYTES]; 1953 1954 if (mp->flags & SYSFS_PERCPU) { 1955 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", cpu, mp->path); 1956 1957 *counterp = snapshot_sysfs_counter(path); 1958 } else { 1959 *counterp = snapshot_sysfs_counter(mp->path); 1960 } 1961 } 1962 1963 return 0; 1964 } 1965 1966 unsigned long long get_uncore_mhz(int package, int die) 1967 { 1968 char path[128]; 1969 1970 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/current_freq_khz", package, 1971 die); 1972 1973 return (snapshot_sysfs_counter(path) / 1000); 1974 } 1975 1976 int get_epb(int cpu) 1977 { 1978 char path[128 + PATH_BYTES]; 1979 unsigned long long msr; 1980 int ret, epb = -1; 1981 FILE *fp; 1982 1983 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu); 1984 1985 fp = fopen(path, "r"); 1986 if (!fp) 1987 goto msr_fallback; 1988 1989 ret = fscanf(fp, "%d", &epb); 1990 if (ret != 1) 1991 err(1, "%s(%s)", __func__, path); 1992 1993 fclose(fp); 1994 1995 return epb; 1996 1997 msr_fallback: 1998 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr); 1999 2000 return msr & 0xf; 2001 } 2002 2003 void get_apic_id(struct thread_data *t) 2004 { 2005 unsigned int eax, ebx, ecx, edx; 2006 2007 if (DO_BIC(BIC_APIC)) { 2008 eax = ebx = ecx = edx = 0; 2009 __cpuid(1, eax, ebx, ecx, edx); 2010 2011 t->apic_id = (ebx >> 24) & 0xff; 2012 } 2013 2014 if (!DO_BIC(BIC_X2APIC)) 2015 return; 2016 2017 if (authentic_amd || hygon_genuine) { 2018 unsigned int topology_extensions; 2019 2020 if (max_extended_level < 0x8000001e) 2021 return; 2022 2023 eax = ebx = ecx = edx = 0; 2024 __cpuid(0x80000001, eax, ebx, ecx, edx); 2025 topology_extensions = ecx & (1 << 22); 2026 2027 if (topology_extensions == 0) 2028 return; 2029 2030 eax = ebx = ecx = edx = 0; 2031 __cpuid(0x8000001e, eax, ebx, ecx, edx); 2032 2033 t->x2apic_id = eax; 2034 return; 2035 } 2036 2037 if (!genuine_intel) 2038 return; 2039 2040 if (max_level < 0xb) 2041 return; 2042 2043 ecx = 0; 2044 __cpuid(0xb, eax, ebx, ecx, edx); 2045 t->x2apic_id = edx; 2046 2047 if (debug && (t->apic_id != (t->x2apic_id & 0xff))) 2048 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id); 2049 } 2050 2051 int get_core_throt_cnt(int cpu, unsigned long long *cnt) 2052 { 2053 char path[128 + PATH_BYTES]; 2054 unsigned long long tmp; 2055 FILE *fp; 2056 int ret; 2057 2058 sprintf(path, "/sys/devices/system/cpu/cpu%d/thermal_throttle/core_throttle_count", cpu); 2059 fp = fopen(path, "r"); 2060 if (!fp) 2061 return -1; 2062 ret = fscanf(fp, "%lld", &tmp); 2063 fclose(fp); 2064 if (ret != 1) 2065 return -1; 2066 *cnt = tmp; 2067 2068 return 0; 2069 } 2070 2071 /* 2072 * get_counters(...) 2073 * migrate to cpu 2074 * acquire and record local counters for that cpu 2075 */ 2076 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2077 { 2078 int cpu = t->cpu_id; 2079 unsigned long long msr; 2080 int aperf_mperf_retry_count = 0; 2081 struct msr_counter *mp; 2082 int i; 2083 2084 if (cpu_migrate(cpu)) { 2085 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu); 2086 return -1; 2087 } 2088 2089 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 2090 2091 if (first_counter_read) 2092 get_apic_id(t); 2093 retry: 2094 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 2095 2096 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) { 2097 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 2098 2099 /* 2100 * The TSC, APERF and MPERF must be read together for 2101 * APERF/MPERF and MPERF/TSC to give accurate results. 2102 * 2103 * Unfortunately, APERF and MPERF are read by 2104 * individual system call, so delays may occur 2105 * between them. If the time to read them 2106 * varies by a large amount, we re-read them. 2107 */ 2108 2109 /* 2110 * This initial dummy APERF read has been seen to 2111 * reduce jitter in the subsequent reads. 2112 */ 2113 2114 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 2115 return -3; 2116 2117 t->tsc = rdtsc(); /* re-read close to APERF */ 2118 2119 tsc_before = t->tsc; 2120 2121 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 2122 return -3; 2123 2124 tsc_between = rdtsc(); 2125 2126 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 2127 return -4; 2128 2129 tsc_after = rdtsc(); 2130 2131 aperf_time = tsc_between - tsc_before; 2132 mperf_time = tsc_after - tsc_between; 2133 2134 /* 2135 * If the system call latency to read APERF and MPERF 2136 * differ by more than 2x, then try again. 2137 */ 2138 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 2139 aperf_mperf_retry_count++; 2140 if (aperf_mperf_retry_count < 5) 2141 goto retry; 2142 else 2143 warnx("cpu%d jitter %lld %lld", cpu, aperf_time, mperf_time); 2144 } 2145 aperf_mperf_retry_count = 0; 2146 2147 t->aperf = t->aperf * aperf_mperf_multiplier; 2148 t->mperf = t->mperf * aperf_mperf_multiplier; 2149 } 2150 2151 if (DO_BIC(BIC_IPC)) 2152 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long)) 2153 return -4; 2154 2155 if (DO_BIC(BIC_IRQ)) 2156 t->irq_count = irqs_per_cpu[cpu]; 2157 if (DO_BIC(BIC_SMI)) { 2158 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 2159 return -5; 2160 t->smi_count = msr & 0xFFFFFFFF; 2161 } 2162 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 2163 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 2164 return -6; 2165 } 2166 2167 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 2168 if (get_mp(cpu, mp, &t->counter[i])) 2169 return -10; 2170 } 2171 2172 /* collect core counters only for 1st thread in core */ 2173 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 2174 goto done; 2175 2176 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) { 2177 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 2178 return -6; 2179 } 2180 2181 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) { 2182 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 2183 return -7; 2184 } else if (do_knl_cstates && soft_c1_residency_display(BIC_CPU_c6)) { 2185 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 2186 return -7; 2187 } 2188 2189 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) { 2190 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 2191 return -8; 2192 else if (t->is_atom) { 2193 /* 2194 * For Atom CPUs that has core cstate deeper than c6, 2195 * MSR_CORE_C6_RESIDENCY returns residency of cc6 and deeper. 2196 * Minus CC7 (and deeper cstates) residency to get 2197 * accturate cc6 residency. 2198 */ 2199 c->c6 -= c->c7; 2200 } 2201 } 2202 2203 if (DO_BIC(BIC_Mod_c6)) 2204 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 2205 return -8; 2206 2207 if (DO_BIC(BIC_CoreTmp)) { 2208 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 2209 return -9; 2210 c->core_temp_c = tj_max - ((msr >> 16) & 0x7F); 2211 } 2212 2213 if (DO_BIC(BIC_CORE_THROT_CNT)) 2214 get_core_throt_cnt(cpu, &c->core_throt_cnt); 2215 2216 if (do_rapl & RAPL_AMD_F17H) { 2217 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr)) 2218 return -14; 2219 c->core_energy = msr & 0xFFFFFFFF; 2220 } 2221 2222 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 2223 if (get_mp(cpu, mp, &c->counter[i])) 2224 return -10; 2225 } 2226 2227 /* collect package counters only for 1st core in package */ 2228 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2229 goto done; 2230 2231 if (DO_BIC(BIC_Totl_c0)) { 2232 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 2233 return -10; 2234 } 2235 if (DO_BIC(BIC_Any_c0)) { 2236 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 2237 return -11; 2238 } 2239 if (DO_BIC(BIC_GFX_c0)) { 2240 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 2241 return -12; 2242 } 2243 if (DO_BIC(BIC_CPUGFX)) { 2244 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 2245 return -13; 2246 } 2247 if (DO_BIC(BIC_Pkgpc3)) 2248 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 2249 return -9; 2250 if (DO_BIC(BIC_Pkgpc6)) { 2251 if (do_slm_cstates) { 2252 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 2253 return -10; 2254 } else { 2255 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 2256 return -10; 2257 } 2258 } 2259 2260 if (DO_BIC(BIC_Pkgpc2)) 2261 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 2262 return -11; 2263 if (DO_BIC(BIC_Pkgpc7)) 2264 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 2265 return -12; 2266 if (DO_BIC(BIC_Pkgpc8)) 2267 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 2268 return -13; 2269 if (DO_BIC(BIC_Pkgpc9)) 2270 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 2271 return -13; 2272 if (DO_BIC(BIC_Pkgpc10)) 2273 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 2274 return -13; 2275 2276 if (DO_BIC(BIC_CPU_LPI)) 2277 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 2278 if (DO_BIC(BIC_SYS_LPI)) 2279 p->sys_lpi = cpuidle_cur_sys_lpi_us; 2280 2281 if (do_rapl & RAPL_PKG) { 2282 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 2283 return -13; 2284 p->energy_pkg = msr; 2285 } 2286 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 2287 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 2288 return -14; 2289 p->energy_cores = msr; 2290 } 2291 if (do_rapl & RAPL_DRAM) { 2292 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 2293 return -15; 2294 p->energy_dram = msr; 2295 } 2296 if (do_rapl & RAPL_GFX) { 2297 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 2298 return -16; 2299 p->energy_gfx = msr; 2300 } 2301 if (do_rapl & RAPL_PKG_PERF_STATUS) { 2302 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr)) 2303 return -16; 2304 p->rapl_pkg_perf_status = msr; 2305 } 2306 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 2307 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr)) 2308 return -16; 2309 p->rapl_dram_perf_status = msr; 2310 } 2311 if (do_rapl & RAPL_AMD_F17H) { 2312 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr)) 2313 return -13; 2314 p->energy_pkg = msr; 2315 } 2316 if (DO_BIC(BIC_PkgTmp)) { 2317 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 2318 return -17; 2319 p->pkg_temp_c = tj_max - ((msr >> 16) & 0x7F); 2320 } 2321 2322 if (DO_BIC(BIC_GFX_rc6)) 2323 p->gfx_rc6_ms = gfx_cur_rc6_ms; 2324 2325 /* n.b. assume die0 uncore frequency applies to whole package */ 2326 if (DO_BIC(BIC_UNCORE_MHZ)) 2327 p->uncore_mhz = get_uncore_mhz(p->package_id, 0); 2328 2329 if (DO_BIC(BIC_GFXMHz)) 2330 p->gfx_mhz = gfx_cur_mhz; 2331 2332 if (DO_BIC(BIC_GFXACTMHz)) 2333 p->gfx_act_mhz = gfx_act_mhz; 2334 2335 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2336 if (get_mp(cpu, mp, &p->counter[i])) 2337 return -10; 2338 } 2339 done: 2340 gettimeofday(&t->tv_end, (struct timezone *)NULL); 2341 2342 return 0; 2343 } 2344 2345 /* 2346 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 2347 * If you change the values, note they are used both in comparisons 2348 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 2349 */ 2350 2351 #define PCLUKN 0 /* Unknown */ 2352 #define PCLRSV 1 /* Reserved */ 2353 #define PCL__0 2 /* PC0 */ 2354 #define PCL__1 3 /* PC1 */ 2355 #define PCL__2 4 /* PC2 */ 2356 #define PCL__3 5 /* PC3 */ 2357 #define PCL__4 6 /* PC4 */ 2358 #define PCL__6 7 /* PC6 */ 2359 #define PCL_6N 8 /* PC6 No Retention */ 2360 #define PCL_6R 9 /* PC6 Retention */ 2361 #define PCL__7 10 /* PC7 */ 2362 #define PCL_7S 11 /* PC7 Shrink */ 2363 #define PCL__8 12 /* PC8 */ 2364 #define PCL__9 13 /* PC9 */ 2365 #define PCL_10 14 /* PC10 */ 2366 #define PCLUNL 15 /* Unlimited */ 2367 2368 int pkg_cstate_limit = PCLUKN; 2369 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 2370 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited" 2371 }; 2372 2373 int nhm_pkg_cstate_limits[16] = 2374 { PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2375 PCLRSV, PCLRSV 2376 }; 2377 2378 int snb_pkg_cstate_limits[16] = 2379 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2380 PCLRSV, PCLRSV 2381 }; 2382 2383 int hsw_pkg_cstate_limits[16] = 2384 { PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2385 PCLRSV, PCLRSV 2386 }; 2387 2388 int slv_pkg_cstate_limits[16] = 2389 { PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2390 PCL__6, PCL__7 2391 }; 2392 2393 int amt_pkg_cstate_limits[16] = 2394 { PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2395 PCLRSV, PCLRSV 2396 }; 2397 2398 int phi_pkg_cstate_limits[16] = 2399 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2400 PCLRSV, PCLRSV 2401 }; 2402 2403 int glm_pkg_cstate_limits[16] = 2404 { PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2405 PCLRSV, PCLRSV 2406 }; 2407 2408 int skx_pkg_cstate_limits[16] = 2409 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2410 PCLRSV, PCLRSV 2411 }; 2412 2413 int icx_pkg_cstate_limits[16] = 2414 { PCL__0, PCL__2, PCL__6, PCL__6, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2415 PCLRSV, PCLRSV 2416 }; 2417 2418 static void calculate_tsc_tweak() 2419 { 2420 tsc_tweak = base_hz / tsc_hz; 2421 } 2422 2423 void prewake_cstate_probe(unsigned int family, unsigned int model); 2424 2425 static void dump_nhm_platform_info(void) 2426 { 2427 unsigned long long msr; 2428 unsigned int ratio; 2429 2430 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2431 2432 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 2433 2434 ratio = (msr >> 40) & 0xFF; 2435 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk); 2436 2437 ratio = (msr >> 8) & 0xFF; 2438 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk); 2439 2440 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 2441 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 2442 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 2443 2444 /* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */ 2445 if (dis_cstate_prewake) 2446 fprintf(outf, "C-state Pre-wake: %sabled\n", msr & 0x40000000 ? "DIS" : "EN"); 2447 2448 return; 2449 } 2450 2451 static void dump_hsw_turbo_ratio_limits(void) 2452 { 2453 unsigned long long msr; 2454 unsigned int ratio; 2455 2456 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 2457 2458 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 2459 2460 ratio = (msr >> 8) & 0xFF; 2461 if (ratio) 2462 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk); 2463 2464 ratio = (msr >> 0) & 0xFF; 2465 if (ratio) 2466 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk); 2467 return; 2468 } 2469 2470 static void dump_ivt_turbo_ratio_limits(void) 2471 { 2472 unsigned long long msr; 2473 unsigned int ratio; 2474 2475 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 2476 2477 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 2478 2479 ratio = (msr >> 56) & 0xFF; 2480 if (ratio) 2481 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk); 2482 2483 ratio = (msr >> 48) & 0xFF; 2484 if (ratio) 2485 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk); 2486 2487 ratio = (msr >> 40) & 0xFF; 2488 if (ratio) 2489 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk); 2490 2491 ratio = (msr >> 32) & 0xFF; 2492 if (ratio) 2493 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk); 2494 2495 ratio = (msr >> 24) & 0xFF; 2496 if (ratio) 2497 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk); 2498 2499 ratio = (msr >> 16) & 0xFF; 2500 if (ratio) 2501 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk); 2502 2503 ratio = (msr >> 8) & 0xFF; 2504 if (ratio) 2505 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk); 2506 2507 ratio = (msr >> 0) & 0xFF; 2508 if (ratio) 2509 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk); 2510 return; 2511 } 2512 2513 int has_turbo_ratio_group_limits(int family, int model) 2514 { 2515 2516 if (!genuine_intel) 2517 return 0; 2518 2519 if (family != 6) 2520 return 0; 2521 2522 switch (model) { 2523 case INTEL_FAM6_ATOM_GOLDMONT: 2524 case INTEL_FAM6_SKYLAKE_X: 2525 case INTEL_FAM6_ICELAKE_X: 2526 case INTEL_FAM6_SAPPHIRERAPIDS_X: 2527 case INTEL_FAM6_ATOM_GOLDMONT_D: 2528 case INTEL_FAM6_ATOM_TREMONT_D: 2529 return 1; 2530 default: 2531 return 0; 2532 } 2533 } 2534 2535 static void dump_turbo_ratio_limits(int trl_msr_offset, int family, int model) 2536 { 2537 unsigned long long msr, core_counts; 2538 int shift; 2539 2540 get_msr(base_cpu, trl_msr_offset, &msr); 2541 fprintf(outf, "cpu%d: MSR_%sTURBO_RATIO_LIMIT: 0x%08llx\n", 2542 base_cpu, trl_msr_offset == MSR_SECONDARY_TURBO_RATIO_LIMIT ? "SECONDARY_" : "", msr); 2543 2544 if (has_turbo_ratio_group_limits(family, model)) { 2545 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 2546 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 2547 } else { 2548 core_counts = 0x0807060504030201; 2549 } 2550 2551 for (shift = 56; shift >= 0; shift -= 8) { 2552 unsigned int ratio, group_size; 2553 2554 ratio = (msr >> shift) & 0xFF; 2555 group_size = (core_counts >> shift) & 0xFF; 2556 if (ratio) 2557 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2558 ratio, bclk, ratio * bclk, group_size); 2559 } 2560 2561 return; 2562 } 2563 2564 static void dump_atom_turbo_ratio_limits(void) 2565 { 2566 unsigned long long msr; 2567 unsigned int ratio; 2568 2569 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 2570 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2571 2572 ratio = (msr >> 0) & 0x3F; 2573 if (ratio) 2574 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", ratio, bclk, ratio * bclk); 2575 2576 ratio = (msr >> 8) & 0x3F; 2577 if (ratio) 2578 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", ratio, bclk, ratio * bclk); 2579 2580 ratio = (msr >> 16) & 0x3F; 2581 if (ratio) 2582 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk); 2583 2584 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 2585 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2586 2587 ratio = (msr >> 24) & 0x3F; 2588 if (ratio) 2589 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk); 2590 2591 ratio = (msr >> 16) & 0x3F; 2592 if (ratio) 2593 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk); 2594 2595 ratio = (msr >> 8) & 0x3F; 2596 if (ratio) 2597 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk); 2598 2599 ratio = (msr >> 0) & 0x3F; 2600 if (ratio) 2601 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", ratio, bclk, ratio * bclk); 2602 } 2603 2604 static void dump_knl_turbo_ratio_limits(void) 2605 { 2606 const unsigned int buckets_no = 7; 2607 2608 unsigned long long msr; 2609 int delta_cores, delta_ratio; 2610 int i, b_nr; 2611 unsigned int cores[buckets_no]; 2612 unsigned int ratio[buckets_no]; 2613 2614 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2615 2616 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2617 2618 /* 2619 * Turbo encoding in KNL is as follows: 2620 * [0] -- Reserved 2621 * [7:1] -- Base value of number of active cores of bucket 1. 2622 * [15:8] -- Base value of freq ratio of bucket 1. 2623 * [20:16] -- +ve delta of number of active cores of bucket 2. 2624 * i.e. active cores of bucket 2 = 2625 * active cores of bucket 1 + delta 2626 * [23:21] -- Negative delta of freq ratio of bucket 2. 2627 * i.e. freq ratio of bucket 2 = 2628 * freq ratio of bucket 1 - delta 2629 * [28:24]-- +ve delta of number of active cores of bucket 3. 2630 * [31:29]-- -ve delta of freq ratio of bucket 3. 2631 * [36:32]-- +ve delta of number of active cores of bucket 4. 2632 * [39:37]-- -ve delta of freq ratio of bucket 4. 2633 * [44:40]-- +ve delta of number of active cores of bucket 5. 2634 * [47:45]-- -ve delta of freq ratio of bucket 5. 2635 * [52:48]-- +ve delta of number of active cores of bucket 6. 2636 * [55:53]-- -ve delta of freq ratio of bucket 6. 2637 * [60:56]-- +ve delta of number of active cores of bucket 7. 2638 * [63:61]-- -ve delta of freq ratio of bucket 7. 2639 */ 2640 2641 b_nr = 0; 2642 cores[b_nr] = (msr & 0xFF) >> 1; 2643 ratio[b_nr] = (msr >> 8) & 0xFF; 2644 2645 for (i = 16; i < 64; i += 8) { 2646 delta_cores = (msr >> i) & 0x1F; 2647 delta_ratio = (msr >> (i + 5)) & 0x7; 2648 2649 cores[b_nr + 1] = cores[b_nr] + delta_cores; 2650 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 2651 b_nr++; 2652 } 2653 2654 for (i = buckets_no - 1; i >= 0; i--) 2655 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 2656 fprintf(outf, 2657 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2658 ratio[i], bclk, ratio[i] * bclk, cores[i]); 2659 } 2660 2661 static void dump_nhm_cst_cfg(void) 2662 { 2663 unsigned long long msr; 2664 2665 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2666 2667 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 2668 2669 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 2670 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 2671 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 2672 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 2673 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 2674 (msr & (1 << 15)) ? "" : "UN", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]); 2675 2676 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 2677 if (has_automatic_cstate_conversion) { 2678 fprintf(outf, ", automatic c-state conversion=%s", (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 2679 } 2680 2681 fprintf(outf, ")\n"); 2682 2683 return; 2684 } 2685 2686 static void dump_config_tdp(void) 2687 { 2688 unsigned long long msr; 2689 2690 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 2691 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 2692 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 2693 2694 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 2695 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 2696 if (msr) { 2697 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2698 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2699 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2700 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 2701 } 2702 fprintf(outf, ")\n"); 2703 2704 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 2705 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 2706 if (msr) { 2707 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2708 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2709 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2710 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 2711 } 2712 fprintf(outf, ")\n"); 2713 2714 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 2715 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 2716 if ((msr) & 0x3) 2717 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 2718 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2719 fprintf(outf, ")\n"); 2720 2721 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 2722 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 2723 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 2724 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2725 fprintf(outf, ")\n"); 2726 } 2727 2728 unsigned int irtl_time_units[] = { 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 2729 2730 void print_irtl(void) 2731 { 2732 unsigned long long msr; 2733 2734 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 2735 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 2736 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2737 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2738 2739 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 2740 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 2741 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2742 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2743 2744 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 2745 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 2746 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2747 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2748 2749 if (!do_irtl_hsw) 2750 return; 2751 2752 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 2753 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 2754 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2755 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2756 2757 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 2758 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 2759 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2760 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2761 2762 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 2763 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 2764 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2765 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2766 2767 } 2768 2769 void free_fd_percpu(void) 2770 { 2771 int i; 2772 2773 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 2774 if (fd_percpu[i] != 0) 2775 close(fd_percpu[i]); 2776 } 2777 2778 free(fd_percpu); 2779 } 2780 2781 void free_all_buffers(void) 2782 { 2783 int i; 2784 2785 CPU_FREE(cpu_present_set); 2786 cpu_present_set = NULL; 2787 cpu_present_setsize = 0; 2788 2789 CPU_FREE(cpu_affinity_set); 2790 cpu_affinity_set = NULL; 2791 cpu_affinity_setsize = 0; 2792 2793 free(thread_even); 2794 free(core_even); 2795 free(package_even); 2796 2797 thread_even = NULL; 2798 core_even = NULL; 2799 package_even = NULL; 2800 2801 free(thread_odd); 2802 free(core_odd); 2803 free(package_odd); 2804 2805 thread_odd = NULL; 2806 core_odd = NULL; 2807 package_odd = NULL; 2808 2809 free(output_buffer); 2810 output_buffer = NULL; 2811 outp = NULL; 2812 2813 free_fd_percpu(); 2814 2815 free(irq_column_2_cpu); 2816 free(irqs_per_cpu); 2817 2818 for (i = 0; i <= topo.max_cpu_num; ++i) { 2819 if (cpus[i].put_ids) 2820 CPU_FREE(cpus[i].put_ids); 2821 } 2822 free(cpus); 2823 } 2824 2825 /* 2826 * Parse a file containing a single int. 2827 * Return 0 if file can not be opened 2828 * Exit if file can be opened, but can not be parsed 2829 */ 2830 int parse_int_file(const char *fmt, ...) 2831 { 2832 va_list args; 2833 char path[PATH_MAX]; 2834 FILE *filep; 2835 int value; 2836 2837 va_start(args, fmt); 2838 vsnprintf(path, sizeof(path), fmt, args); 2839 va_end(args); 2840 filep = fopen(path, "r"); 2841 if (!filep) 2842 return 0; 2843 if (fscanf(filep, "%d", &value) != 1) 2844 err(1, "%s: failed to parse number from file", path); 2845 fclose(filep); 2846 return value; 2847 } 2848 2849 /* 2850 * cpu_is_first_core_in_package(cpu) 2851 * return 1 if given CPU is 1st core in package 2852 */ 2853 int cpu_is_first_core_in_package(int cpu) 2854 { 2855 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2856 } 2857 2858 int get_physical_package_id(int cpu) 2859 { 2860 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2861 } 2862 2863 int get_die_id(int cpu) 2864 { 2865 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu); 2866 } 2867 2868 int get_core_id(int cpu) 2869 { 2870 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2871 } 2872 2873 void set_node_data(void) 2874 { 2875 int pkg, node, lnode, cpu, cpux; 2876 int cpu_count; 2877 2878 /* initialize logical_node_id */ 2879 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) 2880 cpus[cpu].logical_node_id = -1; 2881 2882 cpu_count = 0; 2883 for (pkg = 0; pkg < topo.num_packages; pkg++) { 2884 lnode = 0; 2885 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) { 2886 if (cpus[cpu].physical_package_id != pkg) 2887 continue; 2888 /* find a cpu with an unset logical_node_id */ 2889 if (cpus[cpu].logical_node_id != -1) 2890 continue; 2891 cpus[cpu].logical_node_id = lnode; 2892 node = cpus[cpu].physical_node_id; 2893 cpu_count++; 2894 /* 2895 * find all matching cpus on this pkg and set 2896 * the logical_node_id 2897 */ 2898 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) { 2899 if ((cpus[cpux].physical_package_id == pkg) && (cpus[cpux].physical_node_id == node)) { 2900 cpus[cpux].logical_node_id = lnode; 2901 cpu_count++; 2902 } 2903 } 2904 lnode++; 2905 if (lnode > topo.nodes_per_pkg) 2906 topo.nodes_per_pkg = lnode; 2907 } 2908 if (cpu_count >= topo.max_cpu_num) 2909 break; 2910 } 2911 } 2912 2913 int get_physical_node_id(struct cpu_topology *thiscpu) 2914 { 2915 char path[80]; 2916 FILE *filep; 2917 int i; 2918 int cpu = thiscpu->logical_cpu_id; 2919 2920 for (i = 0; i <= topo.max_cpu_num; i++) { 2921 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", cpu, i); 2922 filep = fopen(path, "r"); 2923 if (!filep) 2924 continue; 2925 fclose(filep); 2926 return i; 2927 } 2928 return -1; 2929 } 2930 2931 int get_thread_siblings(struct cpu_topology *thiscpu) 2932 { 2933 char path[80], character; 2934 FILE *filep; 2935 unsigned long map; 2936 int so, shift, sib_core; 2937 int cpu = thiscpu->logical_cpu_id; 2938 int offset = topo.max_cpu_num + 1; 2939 size_t size; 2940 int thread_id = 0; 2941 2942 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 2943 if (thiscpu->thread_id < 0) 2944 thiscpu->thread_id = thread_id++; 2945 if (!thiscpu->put_ids) 2946 return -1; 2947 2948 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 2949 CPU_ZERO_S(size, thiscpu->put_ids); 2950 2951 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 2952 filep = fopen(path, "r"); 2953 2954 if (!filep) { 2955 warnx("%s: open failed", path); 2956 return -1; 2957 } 2958 do { 2959 offset -= BITMASK_SIZE; 2960 if (fscanf(filep, "%lx%c", &map, &character) != 2) 2961 err(1, "%s: failed to parse file", path); 2962 for (shift = 0; shift < BITMASK_SIZE; shift++) { 2963 if ((map >> shift) & 0x1) { 2964 so = shift + offset; 2965 sib_core = get_core_id(so); 2966 if (sib_core == thiscpu->physical_core_id) { 2967 CPU_SET_S(so, size, thiscpu->put_ids); 2968 if ((so != cpu) && (cpus[so].thread_id < 0)) 2969 cpus[so].thread_id = thread_id++; 2970 } 2971 } 2972 } 2973 } while (character == ','); 2974 fclose(filep); 2975 2976 return CPU_COUNT_S(size, thiscpu->put_ids); 2977 } 2978 2979 /* 2980 * run func(thread, core, package) in topology order 2981 * skip non-present cpus 2982 */ 2983 2984 int for_all_cpus_2(int (func) (struct thread_data *, struct core_data *, 2985 struct pkg_data *, struct thread_data *, struct core_data *, 2986 struct pkg_data *), struct thread_data *thread_base, 2987 struct core_data *core_base, struct pkg_data *pkg_base, 2988 struct thread_data *thread_base2, struct core_data *core_base2, struct pkg_data *pkg_base2) 2989 { 2990 int retval, pkg_no, node_no, core_no, thread_no; 2991 2992 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2993 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 2994 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 2995 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) { 2996 struct thread_data *t, *t2; 2997 struct core_data *c, *c2; 2998 struct pkg_data *p, *p2; 2999 3000 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no); 3001 3002 if (cpu_is_not_present(t->cpu_id)) 3003 continue; 3004 3005 t2 = GET_THREAD(thread_base2, thread_no, core_no, node_no, pkg_no); 3006 3007 c = GET_CORE(core_base, core_no, node_no, pkg_no); 3008 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no); 3009 3010 p = GET_PKG(pkg_base, pkg_no); 3011 p2 = GET_PKG(pkg_base2, pkg_no); 3012 3013 retval = func(t, c, p, t2, c2, p2); 3014 if (retval) 3015 return retval; 3016 } 3017 } 3018 } 3019 } 3020 return 0; 3021 } 3022 3023 /* 3024 * run func(cpu) on every cpu in /proc/stat 3025 * return max_cpu number 3026 */ 3027 int for_all_proc_cpus(int (func) (int)) 3028 { 3029 FILE *fp; 3030 int cpu_num; 3031 int retval; 3032 3033 fp = fopen_or_die(proc_stat, "r"); 3034 3035 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 3036 if (retval != 0) 3037 err(1, "%s: failed to parse format", proc_stat); 3038 3039 while (1) { 3040 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 3041 if (retval != 1) 3042 break; 3043 3044 retval = func(cpu_num); 3045 if (retval) { 3046 fclose(fp); 3047 return (retval); 3048 } 3049 } 3050 fclose(fp); 3051 return 0; 3052 } 3053 3054 void re_initialize(void) 3055 { 3056 free_all_buffers(); 3057 setup_all_buffers(); 3058 fprintf(outf, "turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 3059 } 3060 3061 void set_max_cpu_num(void) 3062 { 3063 FILE *filep; 3064 int base_cpu; 3065 unsigned long dummy; 3066 char pathname[64]; 3067 3068 base_cpu = sched_getcpu(); 3069 if (base_cpu < 0) 3070 err(1, "cannot find calling cpu ID"); 3071 sprintf(pathname, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", base_cpu); 3072 3073 filep = fopen_or_die(pathname, "r"); 3074 topo.max_cpu_num = 0; 3075 while (fscanf(filep, "%lx,", &dummy) == 1) 3076 topo.max_cpu_num += BITMASK_SIZE; 3077 fclose(filep); 3078 topo.max_cpu_num--; /* 0 based */ 3079 } 3080 3081 /* 3082 * count_cpus() 3083 * remember the last one seen, it will be the max 3084 */ 3085 int count_cpus(int cpu) 3086 { 3087 UNUSED(cpu); 3088 3089 topo.num_cpus++; 3090 return 0; 3091 } 3092 3093 int mark_cpu_present(int cpu) 3094 { 3095 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 3096 return 0; 3097 } 3098 3099 int init_thread_id(int cpu) 3100 { 3101 cpus[cpu].thread_id = -1; 3102 return 0; 3103 } 3104 3105 /* 3106 * snapshot_proc_interrupts() 3107 * 3108 * read and record summary of /proc/interrupts 3109 * 3110 * return 1 if config change requires a restart, else return 0 3111 */ 3112 int snapshot_proc_interrupts(void) 3113 { 3114 static FILE *fp; 3115 int column, retval; 3116 3117 if (fp == NULL) 3118 fp = fopen_or_die("/proc/interrupts", "r"); 3119 else 3120 rewind(fp); 3121 3122 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 3123 for (column = 0; column < topo.num_cpus; ++column) { 3124 int cpu_number; 3125 3126 retval = fscanf(fp, " CPU%d", &cpu_number); 3127 if (retval != 1) 3128 break; 3129 3130 if (cpu_number > topo.max_cpu_num) { 3131 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 3132 return 1; 3133 } 3134 3135 irq_column_2_cpu[column] = cpu_number; 3136 irqs_per_cpu[cpu_number] = 0; 3137 } 3138 3139 /* read /proc/interrupt count lines and sum up irqs per cpu */ 3140 while (1) { 3141 int column; 3142 char buf[64]; 3143 3144 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 3145 if (retval != 1) 3146 break; 3147 3148 /* read the count per cpu */ 3149 for (column = 0; column < topo.num_cpus; ++column) { 3150 3151 int cpu_number, irq_count; 3152 3153 retval = fscanf(fp, " %d", &irq_count); 3154 if (retval != 1) 3155 break; 3156 3157 cpu_number = irq_column_2_cpu[column]; 3158 irqs_per_cpu[cpu_number] += irq_count; 3159 3160 } 3161 3162 while (getc(fp) != '\n') ; /* flush interrupt description */ 3163 3164 } 3165 return 0; 3166 } 3167 3168 /* 3169 * snapshot_gfx_rc6_ms() 3170 * 3171 * record snapshot of 3172 * /sys/class/drm/card0/power/rc6_residency_ms 3173 * 3174 * return 1 if config change requires a restart, else return 0 3175 */ 3176 int snapshot_gfx_rc6_ms(void) 3177 { 3178 FILE *fp; 3179 int retval; 3180 3181 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 3182 3183 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 3184 if (retval != 1) 3185 err(1, "GFX rc6"); 3186 3187 fclose(fp); 3188 3189 return 0; 3190 } 3191 3192 /* 3193 * snapshot_gfx_mhz() 3194 * 3195 * record snapshot of 3196 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 3197 * 3198 * return 1 if config change requires a restart, else return 0 3199 */ 3200 int snapshot_gfx_mhz(void) 3201 { 3202 static FILE *fp; 3203 int retval; 3204 3205 if (fp == NULL) 3206 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 3207 else { 3208 rewind(fp); 3209 fflush(fp); 3210 } 3211 3212 retval = fscanf(fp, "%d", &gfx_cur_mhz); 3213 if (retval != 1) 3214 err(1, "GFX MHz"); 3215 3216 return 0; 3217 } 3218 3219 /* 3220 * snapshot_gfx_cur_mhz() 3221 * 3222 * record snapshot of 3223 * /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz 3224 * 3225 * return 1 if config change requires a restart, else return 0 3226 */ 3227 int snapshot_gfx_act_mhz(void) 3228 { 3229 static FILE *fp; 3230 int retval; 3231 3232 if (fp == NULL) 3233 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r"); 3234 else { 3235 rewind(fp); 3236 fflush(fp); 3237 } 3238 3239 retval = fscanf(fp, "%d", &gfx_act_mhz); 3240 if (retval != 1) 3241 err(1, "GFX ACT MHz"); 3242 3243 return 0; 3244 } 3245 3246 /* 3247 * snapshot_cpu_lpi() 3248 * 3249 * record snapshot of 3250 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 3251 */ 3252 int snapshot_cpu_lpi_us(void) 3253 { 3254 FILE *fp; 3255 int retval; 3256 3257 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 3258 3259 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 3260 if (retval != 1) { 3261 fprintf(stderr, "Disabling Low Power Idle CPU output\n"); 3262 BIC_NOT_PRESENT(BIC_CPU_LPI); 3263 fclose(fp); 3264 return -1; 3265 } 3266 3267 fclose(fp); 3268 3269 return 0; 3270 } 3271 3272 /* 3273 * snapshot_sys_lpi() 3274 * 3275 * record snapshot of sys_lpi_file 3276 */ 3277 int snapshot_sys_lpi_us(void) 3278 { 3279 FILE *fp; 3280 int retval; 3281 3282 fp = fopen_or_die(sys_lpi_file, "r"); 3283 3284 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 3285 if (retval != 1) { 3286 fprintf(stderr, "Disabling Low Power Idle System output\n"); 3287 BIC_NOT_PRESENT(BIC_SYS_LPI); 3288 fclose(fp); 3289 return -1; 3290 } 3291 fclose(fp); 3292 3293 return 0; 3294 } 3295 3296 /* 3297 * snapshot /proc and /sys files 3298 * 3299 * return 1 if configuration restart needed, else return 0 3300 */ 3301 int snapshot_proc_sysfs_files(void) 3302 { 3303 if (DO_BIC(BIC_IRQ)) 3304 if (snapshot_proc_interrupts()) 3305 return 1; 3306 3307 if (DO_BIC(BIC_GFX_rc6)) 3308 snapshot_gfx_rc6_ms(); 3309 3310 if (DO_BIC(BIC_GFXMHz)) 3311 snapshot_gfx_mhz(); 3312 3313 if (DO_BIC(BIC_GFXACTMHz)) 3314 snapshot_gfx_act_mhz(); 3315 3316 if (DO_BIC(BIC_CPU_LPI)) 3317 snapshot_cpu_lpi_us(); 3318 3319 if (DO_BIC(BIC_SYS_LPI)) 3320 snapshot_sys_lpi_us(); 3321 3322 return 0; 3323 } 3324 3325 int exit_requested; 3326 3327 static void signal_handler(int signal) 3328 { 3329 switch (signal) { 3330 case SIGINT: 3331 exit_requested = 1; 3332 if (debug) 3333 fprintf(stderr, " SIGINT\n"); 3334 break; 3335 case SIGUSR1: 3336 if (debug > 1) 3337 fprintf(stderr, "SIGUSR1\n"); 3338 break; 3339 } 3340 } 3341 3342 void setup_signal_handler(void) 3343 { 3344 struct sigaction sa; 3345 3346 memset(&sa, 0, sizeof(sa)); 3347 3348 sa.sa_handler = &signal_handler; 3349 3350 if (sigaction(SIGINT, &sa, NULL) < 0) 3351 err(1, "sigaction SIGINT"); 3352 if (sigaction(SIGUSR1, &sa, NULL) < 0) 3353 err(1, "sigaction SIGUSR1"); 3354 } 3355 3356 void do_sleep(void) 3357 { 3358 struct timeval tout; 3359 struct timespec rest; 3360 fd_set readfds; 3361 int retval; 3362 3363 FD_ZERO(&readfds); 3364 FD_SET(0, &readfds); 3365 3366 if (ignore_stdin) { 3367 nanosleep(&interval_ts, NULL); 3368 return; 3369 } 3370 3371 tout = interval_tv; 3372 retval = select(1, &readfds, NULL, NULL, &tout); 3373 3374 if (retval == 1) { 3375 switch (getc(stdin)) { 3376 case 'q': 3377 exit_requested = 1; 3378 break; 3379 case EOF: 3380 /* 3381 * 'stdin' is a pipe closed on the other end. There 3382 * won't be any further input. 3383 */ 3384 ignore_stdin = 1; 3385 /* Sleep the rest of the time */ 3386 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000); 3387 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000; 3388 nanosleep(&rest, NULL); 3389 } 3390 } 3391 } 3392 3393 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr) 3394 { 3395 int ret, idx; 3396 unsigned long long msr_cur, msr_last; 3397 3398 if (!per_cpu_msr_sum) 3399 return 1; 3400 3401 idx = offset_to_idx(offset); 3402 if (idx < 0) 3403 return idx; 3404 /* get_msr_sum() = sum + (get_msr() - last) */ 3405 ret = get_msr(cpu, offset, &msr_cur); 3406 if (ret) 3407 return ret; 3408 msr_last = per_cpu_msr_sum[cpu].entries[idx].last; 3409 DELTA_WRAP32(msr_cur, msr_last); 3410 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum; 3411 3412 return 0; 3413 } 3414 3415 timer_t timerid; 3416 3417 /* Timer callback, update the sum of MSRs periodically. */ 3418 static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3419 { 3420 int i, ret; 3421 int cpu = t->cpu_id; 3422 3423 UNUSED(c); 3424 UNUSED(p); 3425 3426 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) { 3427 unsigned long long msr_cur, msr_last; 3428 off_t offset; 3429 3430 if (!idx_valid(i)) 3431 continue; 3432 offset = idx_to_offset(i); 3433 if (offset < 0) 3434 continue; 3435 ret = get_msr(cpu, offset, &msr_cur); 3436 if (ret) { 3437 fprintf(outf, "Can not update msr(0x%llx)\n", (unsigned long long)offset); 3438 continue; 3439 } 3440 3441 msr_last = per_cpu_msr_sum[cpu].entries[i].last; 3442 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff; 3443 3444 DELTA_WRAP32(msr_cur, msr_last); 3445 per_cpu_msr_sum[cpu].entries[i].sum += msr_last; 3446 } 3447 return 0; 3448 } 3449 3450 static void msr_record_handler(union sigval v) 3451 { 3452 UNUSED(v); 3453 3454 for_all_cpus(update_msr_sum, EVEN_COUNTERS); 3455 } 3456 3457 void msr_sum_record(void) 3458 { 3459 struct itimerspec its; 3460 struct sigevent sev; 3461 3462 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array)); 3463 if (!per_cpu_msr_sum) { 3464 fprintf(outf, "Can not allocate memory for long time MSR.\n"); 3465 return; 3466 } 3467 /* 3468 * Signal handler might be restricted, so use thread notifier instead. 3469 */ 3470 memset(&sev, 0, sizeof(struct sigevent)); 3471 sev.sigev_notify = SIGEV_THREAD; 3472 sev.sigev_notify_function = msr_record_handler; 3473 3474 sev.sigev_value.sival_ptr = &timerid; 3475 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) { 3476 fprintf(outf, "Can not create timer.\n"); 3477 goto release_msr; 3478 } 3479 3480 its.it_value.tv_sec = 0; 3481 its.it_value.tv_nsec = 1; 3482 /* 3483 * A wraparound time has been calculated early. 3484 * Some sources state that the peak power for a 3485 * microprocessor is usually 1.5 times the TDP rating, 3486 * use 2 * TDP for safety. 3487 */ 3488 its.it_interval.tv_sec = rapl_joule_counter_range / 2; 3489 its.it_interval.tv_nsec = 0; 3490 3491 if (timer_settime(timerid, 0, &its, NULL) == -1) { 3492 fprintf(outf, "Can not set timer.\n"); 3493 goto release_timer; 3494 } 3495 return; 3496 3497 release_timer: 3498 timer_delete(timerid); 3499 release_msr: 3500 free(per_cpu_msr_sum); 3501 } 3502 3503 /* 3504 * set_my_sched_priority(pri) 3505 * return previous 3506 */ 3507 int set_my_sched_priority(int priority) 3508 { 3509 int retval; 3510 int original_priority; 3511 3512 errno = 0; 3513 original_priority = getpriority(PRIO_PROCESS, 0); 3514 if (errno && (original_priority == -1)) 3515 err(errno, "getpriority"); 3516 3517 retval = setpriority(PRIO_PROCESS, 0, priority); 3518 if (retval) 3519 errx(retval, "capget(CAP_SYS_NICE) failed,try \"# setcap cap_sys_nice=ep %s\"", progname); 3520 3521 errno = 0; 3522 retval = getpriority(PRIO_PROCESS, 0); 3523 if (retval != priority) 3524 err(retval, "getpriority(%d) != setpriority(%d)", retval, priority); 3525 3526 return original_priority; 3527 } 3528 3529 void turbostat_loop() 3530 { 3531 int retval; 3532 int restarted = 0; 3533 unsigned int done_iters = 0; 3534 3535 setup_signal_handler(); 3536 3537 /* 3538 * elevate own priority for interval mode 3539 */ 3540 set_my_sched_priority(-20); 3541 3542 restart: 3543 restarted++; 3544 3545 snapshot_proc_sysfs_files(); 3546 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3547 first_counter_read = 0; 3548 if (retval < -1) { 3549 exit(retval); 3550 } else if (retval == -1) { 3551 if (restarted > 10) { 3552 exit(retval); 3553 } 3554 re_initialize(); 3555 goto restart; 3556 } 3557 restarted = 0; 3558 done_iters = 0; 3559 gettimeofday(&tv_even, (struct timezone *)NULL); 3560 3561 while (1) { 3562 if (for_all_proc_cpus(cpu_is_not_present)) { 3563 re_initialize(); 3564 goto restart; 3565 } 3566 do_sleep(); 3567 if (snapshot_proc_sysfs_files()) 3568 goto restart; 3569 retval = for_all_cpus(get_counters, ODD_COUNTERS); 3570 if (retval < -1) { 3571 exit(retval); 3572 } else if (retval == -1) { 3573 re_initialize(); 3574 goto restart; 3575 } 3576 gettimeofday(&tv_odd, (struct timezone *)NULL); 3577 timersub(&tv_odd, &tv_even, &tv_delta); 3578 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 3579 re_initialize(); 3580 goto restart; 3581 } 3582 compute_average(EVEN_COUNTERS); 3583 format_all_counters(EVEN_COUNTERS); 3584 flush_output_stdout(); 3585 if (exit_requested) 3586 break; 3587 if (num_iterations && ++done_iters >= num_iterations) 3588 break; 3589 do_sleep(); 3590 if (snapshot_proc_sysfs_files()) 3591 goto restart; 3592 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3593 if (retval < -1) { 3594 exit(retval); 3595 } else if (retval == -1) { 3596 re_initialize(); 3597 goto restart; 3598 } 3599 gettimeofday(&tv_even, (struct timezone *)NULL); 3600 timersub(&tv_even, &tv_odd, &tv_delta); 3601 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 3602 re_initialize(); 3603 goto restart; 3604 } 3605 compute_average(ODD_COUNTERS); 3606 format_all_counters(ODD_COUNTERS); 3607 flush_output_stdout(); 3608 if (exit_requested) 3609 break; 3610 if (num_iterations && ++done_iters >= num_iterations) 3611 break; 3612 } 3613 } 3614 3615 void check_dev_msr() 3616 { 3617 struct stat sb; 3618 char pathname[32]; 3619 3620 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3621 if (stat(pathname, &sb)) 3622 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 3623 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 3624 } 3625 3626 /* 3627 * check for CAP_SYS_RAWIO 3628 * return 0 on success 3629 * return 1 on fail 3630 */ 3631 int check_for_cap_sys_rawio(void) 3632 { 3633 cap_t caps; 3634 cap_flag_value_t cap_flag_value; 3635 3636 caps = cap_get_proc(); 3637 if (caps == NULL) 3638 err(-6, "cap_get_proc\n"); 3639 3640 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value)) 3641 err(-6, "cap_get\n"); 3642 3643 if (cap_flag_value != CAP_SET) { 3644 warnx("capget(CAP_SYS_RAWIO) failed," " try \"# setcap cap_sys_rawio=ep %s\"", progname); 3645 return 1; 3646 } 3647 3648 if (cap_free(caps) == -1) 3649 err(-6, "cap_free\n"); 3650 3651 return 0; 3652 } 3653 3654 void check_permissions(void) 3655 { 3656 int do_exit = 0; 3657 char pathname[32]; 3658 3659 /* check for CAP_SYS_RAWIO */ 3660 do_exit += check_for_cap_sys_rawio(); 3661 3662 /* test file permissions */ 3663 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3664 if (euidaccess(pathname, R_OK)) { 3665 do_exit++; 3666 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 3667 } 3668 3669 /* if all else fails, thell them to be root */ 3670 if (do_exit) 3671 if (getuid() != 0) 3672 warnx("... or simply run as root"); 3673 3674 if (do_exit) 3675 exit(-6); 3676 } 3677 3678 /* 3679 * NHM adds support for additional MSRs: 3680 * 3681 * MSR_SMI_COUNT 0x00000034 3682 * 3683 * MSR_PLATFORM_INFO 0x000000ce 3684 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 3685 * 3686 * MSR_MISC_PWR_MGMT 0x000001aa 3687 * 3688 * MSR_PKG_C3_RESIDENCY 0x000003f8 3689 * MSR_PKG_C6_RESIDENCY 0x000003f9 3690 * MSR_CORE_C3_RESIDENCY 0x000003fc 3691 * MSR_CORE_C6_RESIDENCY 0x000003fd 3692 * 3693 * Side effect: 3694 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 3695 * sets has_misc_feature_control 3696 */ 3697 int probe_nhm_msrs(unsigned int family, unsigned int model) 3698 { 3699 unsigned long long msr; 3700 unsigned int base_ratio; 3701 int *pkg_cstate_limits; 3702 3703 if (!genuine_intel) 3704 return 0; 3705 3706 if (family != 6) 3707 return 0; 3708 3709 bclk = discover_bclk(family, model); 3710 3711 switch (model) { 3712 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 3713 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3714 pkg_cstate_limits = nhm_pkg_cstate_limits; 3715 break; 3716 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 3717 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 3718 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3719 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3720 pkg_cstate_limits = snb_pkg_cstate_limits; 3721 has_misc_feature_control = 1; 3722 break; 3723 case INTEL_FAM6_HASWELL: /* HSW */ 3724 case INTEL_FAM6_HASWELL_G: /* HSW */ 3725 case INTEL_FAM6_HASWELL_X: /* HSX */ 3726 case INTEL_FAM6_HASWELL_L: /* HSW */ 3727 case INTEL_FAM6_BROADWELL: /* BDW */ 3728 case INTEL_FAM6_BROADWELL_G: /* BDW */ 3729 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3730 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 3731 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 3732 pkg_cstate_limits = hsw_pkg_cstate_limits; 3733 has_misc_feature_control = 1; 3734 break; 3735 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3736 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */ 3737 pkg_cstate_limits = skx_pkg_cstate_limits; 3738 has_misc_feature_control = 1; 3739 break; 3740 case INTEL_FAM6_ICELAKE_X: /* ICX */ 3741 pkg_cstate_limits = icx_pkg_cstate_limits; 3742 has_misc_feature_control = 1; 3743 break; 3744 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3745 no_MSR_MISC_PWR_MGMT = 1; 3746 /* FALLTHRU */ 3747 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 3748 pkg_cstate_limits = slv_pkg_cstate_limits; 3749 break; 3750 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 3751 pkg_cstate_limits = amt_pkg_cstate_limits; 3752 no_MSR_MISC_PWR_MGMT = 1; 3753 break; 3754 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 3755 pkg_cstate_limits = phi_pkg_cstate_limits; 3756 break; 3757 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3758 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3759 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 3760 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 3761 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 3762 pkg_cstate_limits = glm_pkg_cstate_limits; 3763 break; 3764 default: 3765 return 0; 3766 } 3767 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3768 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3769 3770 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3771 base_ratio = (msr >> 8) & 0xFF; 3772 3773 base_hz = base_ratio * bclk * 1000000; 3774 has_base_hz = 1; 3775 return 1; 3776 } 3777 3778 /* 3779 * SLV client has support for unique MSRs: 3780 * 3781 * MSR_CC6_DEMOTION_POLICY_CONFIG 3782 * MSR_MC6_DEMOTION_POLICY_CONFIG 3783 */ 3784 3785 int has_slv_msrs(unsigned int family, unsigned int model) 3786 { 3787 if (!genuine_intel) 3788 return 0; 3789 3790 if (family != 6) 3791 return 0; 3792 3793 switch (model) { 3794 case INTEL_FAM6_ATOM_SILVERMONT: 3795 case INTEL_FAM6_ATOM_SILVERMONT_MID: 3796 case INTEL_FAM6_ATOM_AIRMONT_MID: 3797 return 1; 3798 } 3799 return 0; 3800 } 3801 3802 int is_dnv(unsigned int family, unsigned int model) 3803 { 3804 3805 if (!genuine_intel) 3806 return 0; 3807 3808 if (family != 6) 3809 return 0; 3810 3811 switch (model) { 3812 case INTEL_FAM6_ATOM_GOLDMONT_D: 3813 return 1; 3814 } 3815 return 0; 3816 } 3817 3818 int is_bdx(unsigned int family, unsigned int model) 3819 { 3820 3821 if (!genuine_intel) 3822 return 0; 3823 3824 if (family != 6) 3825 return 0; 3826 3827 switch (model) { 3828 case INTEL_FAM6_BROADWELL_X: 3829 return 1; 3830 } 3831 return 0; 3832 } 3833 3834 int is_skx(unsigned int family, unsigned int model) 3835 { 3836 3837 if (!genuine_intel) 3838 return 0; 3839 3840 if (family != 6) 3841 return 0; 3842 3843 switch (model) { 3844 case INTEL_FAM6_SKYLAKE_X: 3845 return 1; 3846 } 3847 return 0; 3848 } 3849 3850 int is_icx(unsigned int family, unsigned int model) 3851 { 3852 3853 if (!genuine_intel) 3854 return 0; 3855 3856 if (family != 6) 3857 return 0; 3858 3859 switch (model) { 3860 case INTEL_FAM6_ICELAKE_X: 3861 return 1; 3862 } 3863 return 0; 3864 } 3865 3866 int is_spr(unsigned int family, unsigned int model) 3867 { 3868 3869 if (!genuine_intel) 3870 return 0; 3871 3872 if (family != 6) 3873 return 0; 3874 3875 switch (model) { 3876 case INTEL_FAM6_SAPPHIRERAPIDS_X: 3877 return 1; 3878 } 3879 return 0; 3880 } 3881 3882 int is_ehl(unsigned int family, unsigned int model) 3883 { 3884 if (!genuine_intel) 3885 return 0; 3886 3887 if (family != 6) 3888 return 0; 3889 3890 switch (model) { 3891 case INTEL_FAM6_ATOM_TREMONT: 3892 return 1; 3893 } 3894 return 0; 3895 } 3896 3897 int is_jvl(unsigned int family, unsigned int model) 3898 { 3899 if (!genuine_intel) 3900 return 0; 3901 3902 if (family != 6) 3903 return 0; 3904 3905 switch (model) { 3906 case INTEL_FAM6_ATOM_TREMONT_D: 3907 return 1; 3908 } 3909 return 0; 3910 } 3911 3912 int has_turbo_ratio_limit(unsigned int family, unsigned int model) 3913 { 3914 if (has_slv_msrs(family, model)) 3915 return 0; 3916 3917 if (family != 6) 3918 return 0; 3919 3920 switch (model) { 3921 /* Nehalem compatible, but do not include turbo-ratio limit support */ 3922 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3923 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 3924 return 0; 3925 default: 3926 return 1; 3927 } 3928 } 3929 3930 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 3931 { 3932 if (has_slv_msrs(family, model)) 3933 return 1; 3934 3935 return 0; 3936 } 3937 3938 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 3939 { 3940 if (!genuine_intel) 3941 return 0; 3942 3943 if (family != 6) 3944 return 0; 3945 3946 switch (model) { 3947 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3948 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3949 return 1; 3950 default: 3951 return 0; 3952 } 3953 } 3954 3955 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 3956 { 3957 if (!genuine_intel) 3958 return 0; 3959 3960 if (family != 6) 3961 return 0; 3962 3963 switch (model) { 3964 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3965 return 1; 3966 default: 3967 return 0; 3968 } 3969 } 3970 3971 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 3972 { 3973 if (!genuine_intel) 3974 return 0; 3975 3976 if (family != 6) 3977 return 0; 3978 3979 switch (model) { 3980 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3981 return 1; 3982 default: 3983 return 0; 3984 } 3985 } 3986 3987 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) 3988 { 3989 if (!genuine_intel) 3990 return 0; 3991 3992 if (family != 6) 3993 return 0; 3994 3995 switch (model) { 3996 case INTEL_FAM6_ATOM_GOLDMONT: 3997 case INTEL_FAM6_SKYLAKE_X: 3998 case INTEL_FAM6_ICELAKE_X: 3999 case INTEL_FAM6_SAPPHIRERAPIDS_X: 4000 return 1; 4001 default: 4002 return 0; 4003 } 4004 } 4005 4006 int has_config_tdp(unsigned int family, unsigned int model) 4007 { 4008 if (!genuine_intel) 4009 return 0; 4010 4011 if (family != 6) 4012 return 0; 4013 4014 switch (model) { 4015 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 4016 case INTEL_FAM6_HASWELL: /* HSW */ 4017 case INTEL_FAM6_HASWELL_X: /* HSX */ 4018 case INTEL_FAM6_HASWELL_L: /* HSW */ 4019 case INTEL_FAM6_HASWELL_G: /* HSW */ 4020 case INTEL_FAM6_BROADWELL: /* BDW */ 4021 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4022 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4023 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4024 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4025 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4026 case INTEL_FAM6_ICELAKE_X: /* ICX */ 4027 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */ 4028 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 4029 return 1; 4030 default: 4031 return 0; 4032 } 4033 } 4034 4035 /* 4036 * tcc_offset_bits: 4037 * 0: Tcc Offset not supported (Default) 4038 * 6: Bit 29:24 of MSR_PLATFORM_INFO 4039 * 4: Bit 27:24 of MSR_PLATFORM_INFO 4040 */ 4041 void check_tcc_offset(int model) 4042 { 4043 unsigned long long msr; 4044 4045 if (!genuine_intel) 4046 return; 4047 4048 switch (model) { 4049 case INTEL_FAM6_SKYLAKE_L: 4050 case INTEL_FAM6_SKYLAKE: 4051 case INTEL_FAM6_KABYLAKE_L: 4052 case INTEL_FAM6_KABYLAKE: 4053 case INTEL_FAM6_ICELAKE_L: 4054 case INTEL_FAM6_ICELAKE: 4055 case INTEL_FAM6_TIGERLAKE_L: 4056 case INTEL_FAM6_TIGERLAKE: 4057 case INTEL_FAM6_COMETLAKE: 4058 if (!get_msr(base_cpu, MSR_PLATFORM_INFO, &msr)) { 4059 msr = (msr >> 30) & 1; 4060 if (msr) 4061 tcc_offset_bits = 6; 4062 } 4063 return; 4064 default: 4065 return; 4066 } 4067 } 4068 4069 static void remove_underbar(char *s) 4070 { 4071 char *to = s; 4072 4073 while (*s) { 4074 if (*s != '_') 4075 *to++ = *s; 4076 s++; 4077 } 4078 4079 *to = 0; 4080 } 4081 4082 static void dump_turbo_ratio_info(unsigned int family, unsigned int model) 4083 { 4084 if (!has_turbo) 4085 return; 4086 4087 if (has_hsw_turbo_ratio_limit(family, model)) 4088 dump_hsw_turbo_ratio_limits(); 4089 4090 if (has_ivt_turbo_ratio_limit(family, model)) 4091 dump_ivt_turbo_ratio_limits(); 4092 4093 if (has_turbo_ratio_limit(family, model)) { 4094 dump_turbo_ratio_limits(MSR_TURBO_RATIO_LIMIT, family, model); 4095 4096 if (is_hybrid) 4097 dump_turbo_ratio_limits(MSR_SECONDARY_TURBO_RATIO_LIMIT, family, model); 4098 } 4099 4100 if (has_atom_turbo_ratio_limit(family, model)) 4101 dump_atom_turbo_ratio_limits(); 4102 4103 if (has_knl_turbo_ratio_limit(family, model)) 4104 dump_knl_turbo_ratio_limits(); 4105 4106 if (has_config_tdp(family, model)) 4107 dump_config_tdp(); 4108 } 4109 4110 static void dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 4111 { 4112 if (!do_nhm_platform_info) 4113 return; 4114 4115 dump_nhm_platform_info(); 4116 dump_turbo_ratio_info(family, model); 4117 dump_nhm_cst_cfg(); 4118 } 4119 4120 static int read_sysfs_int(char *path) 4121 { 4122 FILE *input; 4123 int retval = -1; 4124 4125 input = fopen(path, "r"); 4126 if (input == NULL) { 4127 if (debug) 4128 fprintf(outf, "NSFOD %s\n", path); 4129 return (-1); 4130 } 4131 if (fscanf(input, "%d", &retval) != 1) 4132 err(1, "%s: failed to read int from file", path); 4133 fclose(input); 4134 4135 return (retval); 4136 } 4137 4138 static void dump_sysfs_file(char *path) 4139 { 4140 FILE *input; 4141 char cpuidle_buf[64]; 4142 4143 input = fopen(path, "r"); 4144 if (input == NULL) { 4145 if (debug) 4146 fprintf(outf, "NSFOD %s\n", path); 4147 return; 4148 } 4149 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input)) 4150 err(1, "%s: failed to read file", path); 4151 fclose(input); 4152 4153 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf); 4154 } 4155 4156 static void intel_uncore_frequency_probe(void) 4157 { 4158 int i, j; 4159 char path[128]; 4160 4161 if (!genuine_intel) 4162 return; 4163 4164 if (access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00", R_OK)) 4165 return; 4166 4167 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/current_freq_khz", R_OK)) 4168 BIC_PRESENT(BIC_UNCORE_MHZ); 4169 4170 if (quiet) 4171 return; 4172 4173 for (i = 0; i < topo.num_packages; ++i) { 4174 for (j = 0; j < topo.num_die; ++j) { 4175 int k, l; 4176 4177 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/min_freq_khz", 4178 i, j); 4179 k = read_sysfs_int(path); 4180 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/max_freq_khz", 4181 i, j); 4182 l = read_sysfs_int(path); 4183 fprintf(outf, "Uncore Frequency pkg%d die%d: %d - %d MHz ", i, j, k / 1000, l / 1000); 4184 4185 sprintf(path, 4186 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_min_freq_khz", 4187 i, j); 4188 k = read_sysfs_int(path); 4189 sprintf(path, 4190 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_max_freq_khz", 4191 i, j); 4192 l = read_sysfs_int(path); 4193 fprintf(outf, "(%d - %d MHz)\n", k / 1000, l / 1000); 4194 } 4195 } 4196 } 4197 4198 static void dump_sysfs_cstate_config(void) 4199 { 4200 char path[64]; 4201 char name_buf[16]; 4202 char desc[64]; 4203 FILE *input; 4204 int state; 4205 char *sp; 4206 4207 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) { 4208 fprintf(outf, "cpuidle not loaded\n"); 4209 return; 4210 } 4211 4212 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver"); 4213 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor"); 4214 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro"); 4215 4216 for (state = 0; state < 10; ++state) { 4217 4218 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 4219 input = fopen(path, "r"); 4220 if (input == NULL) 4221 continue; 4222 if (!fgets(name_buf, sizeof(name_buf), input)) 4223 err(1, "%s: failed to read file", path); 4224 4225 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 4226 sp = strchr(name_buf, '-'); 4227 if (!sp) 4228 sp = strchrnul(name_buf, '\n'); 4229 *sp = '\0'; 4230 fclose(input); 4231 4232 remove_underbar(name_buf); 4233 4234 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", base_cpu, state); 4235 input = fopen(path, "r"); 4236 if (input == NULL) 4237 continue; 4238 if (!fgets(desc, sizeof(desc), input)) 4239 err(1, "%s: failed to read file", path); 4240 4241 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 4242 fclose(input); 4243 } 4244 } 4245 4246 static void dump_sysfs_pstate_config(void) 4247 { 4248 char path[64]; 4249 char driver_buf[64]; 4250 char governor_buf[64]; 4251 FILE *input; 4252 int turbo; 4253 4254 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", base_cpu); 4255 input = fopen(path, "r"); 4256 if (input == NULL) { 4257 fprintf(outf, "NSFOD %s\n", path); 4258 return; 4259 } 4260 if (!fgets(driver_buf, sizeof(driver_buf), input)) 4261 err(1, "%s: failed to read file", path); 4262 fclose(input); 4263 4264 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", base_cpu); 4265 input = fopen(path, "r"); 4266 if (input == NULL) { 4267 fprintf(outf, "NSFOD %s\n", path); 4268 return; 4269 } 4270 if (!fgets(governor_buf, sizeof(governor_buf), input)) 4271 err(1, "%s: failed to read file", path); 4272 fclose(input); 4273 4274 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 4275 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 4276 4277 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 4278 input = fopen(path, "r"); 4279 if (input != NULL) { 4280 if (fscanf(input, "%d", &turbo) != 1) 4281 err(1, "%s: failed to parse number from file", path); 4282 fprintf(outf, "cpufreq boost: %d\n", turbo); 4283 fclose(input); 4284 } 4285 4286 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 4287 input = fopen(path, "r"); 4288 if (input != NULL) { 4289 if (fscanf(input, "%d", &turbo) != 1) 4290 err(1, "%s: failed to parse number from file", path); 4291 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 4292 fclose(input); 4293 } 4294 } 4295 4296 /* 4297 * print_epb() 4298 * Decode the ENERGY_PERF_BIAS MSR 4299 */ 4300 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4301 { 4302 char *epb_string; 4303 int cpu, epb; 4304 4305 UNUSED(c); 4306 UNUSED(p); 4307 4308 if (!has_epb) 4309 return 0; 4310 4311 cpu = t->cpu_id; 4312 4313 /* EPB is per-package */ 4314 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4315 return 0; 4316 4317 if (cpu_migrate(cpu)) { 4318 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu); 4319 return -1; 4320 } 4321 4322 epb = get_epb(cpu); 4323 if (epb < 0) 4324 return 0; 4325 4326 switch (epb) { 4327 case ENERGY_PERF_BIAS_PERFORMANCE: 4328 epb_string = "performance"; 4329 break; 4330 case ENERGY_PERF_BIAS_NORMAL: 4331 epb_string = "balanced"; 4332 break; 4333 case ENERGY_PERF_BIAS_POWERSAVE: 4334 epb_string = "powersave"; 4335 break; 4336 default: 4337 epb_string = "custom"; 4338 break; 4339 } 4340 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string); 4341 4342 return 0; 4343 } 4344 4345 /* 4346 * print_hwp() 4347 * Decode the MSR_HWP_CAPABILITIES 4348 */ 4349 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4350 { 4351 unsigned long long msr; 4352 int cpu; 4353 4354 UNUSED(c); 4355 UNUSED(p); 4356 4357 if (!has_hwp) 4358 return 0; 4359 4360 cpu = t->cpu_id; 4361 4362 /* MSR_HWP_CAPABILITIES is per-package */ 4363 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4364 return 0; 4365 4366 if (cpu_migrate(cpu)) { 4367 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu); 4368 return -1; 4369 } 4370 4371 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 4372 return 0; 4373 4374 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 4375 4376 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 4377 if ((msr & (1 << 0)) == 0) 4378 return 0; 4379 4380 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 4381 return 0; 4382 4383 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 4384 "(high %d guar %d eff %d low %d)\n", 4385 cpu, msr, 4386 (unsigned int)HWP_HIGHEST_PERF(msr), 4387 (unsigned int)HWP_GUARANTEED_PERF(msr), 4388 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), (unsigned int)HWP_LOWEST_PERF(msr)); 4389 4390 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 4391 return 0; 4392 4393 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 4394 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 4395 cpu, msr, 4396 (unsigned int)(((msr) >> 0) & 0xff), 4397 (unsigned int)(((msr) >> 8) & 0xff), 4398 (unsigned int)(((msr) >> 16) & 0xff), 4399 (unsigned int)(((msr) >> 24) & 0xff), 4400 (unsigned int)(((msr) >> 32) & 0xff3), (unsigned int)(((msr) >> 42) & 0x1)); 4401 4402 if (has_hwp_pkg) { 4403 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 4404 return 0; 4405 4406 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 4407 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 4408 cpu, msr, 4409 (unsigned int)(((msr) >> 0) & 0xff), 4410 (unsigned int)(((msr) >> 8) & 0xff), 4411 (unsigned int)(((msr) >> 16) & 0xff), 4412 (unsigned int)(((msr) >> 24) & 0xff), (unsigned int)(((msr) >> 32) & 0xff3)); 4413 } 4414 if (has_hwp_notify) { 4415 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 4416 return 0; 4417 4418 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 4419 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 4420 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis"); 4421 } 4422 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 4423 return 0; 4424 4425 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 4426 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 4427 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x4) ? "" : "No-"); 4428 4429 return 0; 4430 } 4431 4432 /* 4433 * print_perf_limit() 4434 */ 4435 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4436 { 4437 unsigned long long msr; 4438 int cpu; 4439 4440 UNUSED(c); 4441 UNUSED(p); 4442 4443 cpu = t->cpu_id; 4444 4445 /* per-package */ 4446 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4447 return 0; 4448 4449 if (cpu_migrate(cpu)) { 4450 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu); 4451 return -1; 4452 } 4453 4454 if (do_core_perf_limit_reasons) { 4455 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 4456 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4457 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 4458 (msr & 1 << 15) ? "bit15, " : "", 4459 (msr & 1 << 14) ? "bit14, " : "", 4460 (msr & 1 << 13) ? "Transitions, " : "", 4461 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 4462 (msr & 1 << 11) ? "PkgPwrL2, " : "", 4463 (msr & 1 << 10) ? "PkgPwrL1, " : "", 4464 (msr & 1 << 9) ? "CorePwr, " : "", 4465 (msr & 1 << 8) ? "Amps, " : "", 4466 (msr & 1 << 6) ? "VR-Therm, " : "", 4467 (msr & 1 << 5) ? "Auto-HWP, " : "", 4468 (msr & 1 << 4) ? "Graphics, " : "", 4469 (msr & 1 << 2) ? "bit2, " : "", 4470 (msr & 1 << 1) ? "ThermStatus, " : "", (msr & 1 << 0) ? "PROCHOT, " : ""); 4471 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 4472 (msr & 1 << 31) ? "bit31, " : "", 4473 (msr & 1 << 30) ? "bit30, " : "", 4474 (msr & 1 << 29) ? "Transitions, " : "", 4475 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 4476 (msr & 1 << 27) ? "PkgPwrL2, " : "", 4477 (msr & 1 << 26) ? "PkgPwrL1, " : "", 4478 (msr & 1 << 25) ? "CorePwr, " : "", 4479 (msr & 1 << 24) ? "Amps, " : "", 4480 (msr & 1 << 22) ? "VR-Therm, " : "", 4481 (msr & 1 << 21) ? "Auto-HWP, " : "", 4482 (msr & 1 << 20) ? "Graphics, " : "", 4483 (msr & 1 << 18) ? "bit18, " : "", 4484 (msr & 1 << 17) ? "ThermStatus, " : "", (msr & 1 << 16) ? "PROCHOT, " : ""); 4485 4486 } 4487 if (do_gfx_perf_limit_reasons) { 4488 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 4489 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4490 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 4491 (msr & 1 << 0) ? "PROCHOT, " : "", 4492 (msr & 1 << 1) ? "ThermStatus, " : "", 4493 (msr & 1 << 4) ? "Graphics, " : "", 4494 (msr & 1 << 6) ? "VR-Therm, " : "", 4495 (msr & 1 << 8) ? "Amps, " : "", 4496 (msr & 1 << 9) ? "GFXPwr, " : "", 4497 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4498 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 4499 (msr & 1 << 16) ? "PROCHOT, " : "", 4500 (msr & 1 << 17) ? "ThermStatus, " : "", 4501 (msr & 1 << 20) ? "Graphics, " : "", 4502 (msr & 1 << 22) ? "VR-Therm, " : "", 4503 (msr & 1 << 24) ? "Amps, " : "", 4504 (msr & 1 << 25) ? "GFXPwr, " : "", 4505 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4506 } 4507 if (do_ring_perf_limit_reasons) { 4508 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 4509 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4510 fprintf(outf, " (Active: %s%s%s%s%s%s)", 4511 (msr & 1 << 0) ? "PROCHOT, " : "", 4512 (msr & 1 << 1) ? "ThermStatus, " : "", 4513 (msr & 1 << 6) ? "VR-Therm, " : "", 4514 (msr & 1 << 8) ? "Amps, " : "", 4515 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4516 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 4517 (msr & 1 << 16) ? "PROCHOT, " : "", 4518 (msr & 1 << 17) ? "ThermStatus, " : "", 4519 (msr & 1 << 22) ? "VR-Therm, " : "", 4520 (msr & 1 << 24) ? "Amps, " : "", 4521 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4522 } 4523 return 0; 4524 } 4525 4526 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 4527 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 4528 4529 double get_tdp_intel(unsigned int model) 4530 { 4531 unsigned long long msr; 4532 4533 if (do_rapl & RAPL_PKG_POWER_INFO) 4534 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 4535 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 4536 4537 switch (model) { 4538 case INTEL_FAM6_ATOM_SILVERMONT: 4539 case INTEL_FAM6_ATOM_SILVERMONT_D: 4540 return 30.0; 4541 default: 4542 return 135.0; 4543 } 4544 } 4545 4546 double get_tdp_amd(unsigned int family) 4547 { 4548 UNUSED(family); 4549 4550 /* This is the max stock TDP of HEDT/Server Fam17h+ chips */ 4551 return 280.0; 4552 } 4553 4554 /* 4555 * rapl_dram_energy_units_probe() 4556 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 4557 */ 4558 static double rapl_dram_energy_units_probe(int model, double rapl_energy_units) 4559 { 4560 /* only called for genuine_intel, family 6 */ 4561 4562 switch (model) { 4563 case INTEL_FAM6_HASWELL_X: /* HSX */ 4564 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4565 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4566 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4567 case INTEL_FAM6_ICELAKE_X: /* ICX */ 4568 return (rapl_dram_energy_units = 15.3 / 1000000); 4569 default: 4570 return (rapl_energy_units); 4571 } 4572 } 4573 4574 void rapl_probe_intel(unsigned int family, unsigned int model) 4575 { 4576 unsigned long long msr; 4577 unsigned int time_unit; 4578 double tdp; 4579 4580 if (family != 6) 4581 return; 4582 4583 switch (model) { 4584 case INTEL_FAM6_SANDYBRIDGE: 4585 case INTEL_FAM6_IVYBRIDGE: 4586 case INTEL_FAM6_HASWELL: /* HSW */ 4587 case INTEL_FAM6_HASWELL_L: /* HSW */ 4588 case INTEL_FAM6_HASWELL_G: /* HSW */ 4589 case INTEL_FAM6_BROADWELL: /* BDW */ 4590 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4591 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 4592 if (rapl_joules) { 4593 BIC_PRESENT(BIC_Pkg_J); 4594 BIC_PRESENT(BIC_Cor_J); 4595 BIC_PRESENT(BIC_GFX_J); 4596 } else { 4597 BIC_PRESENT(BIC_PkgWatt); 4598 BIC_PRESENT(BIC_CorWatt); 4599 BIC_PRESENT(BIC_GFXWatt); 4600 } 4601 break; 4602 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4603 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4604 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 4605 if (rapl_joules) 4606 BIC_PRESENT(BIC_Pkg_J); 4607 else 4608 BIC_PRESENT(BIC_PkgWatt); 4609 break; 4610 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4611 do_rapl = 4612 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS 4613 | RAPL_GFX | RAPL_PKG_POWER_INFO; 4614 if (rapl_joules) { 4615 BIC_PRESENT(BIC_Pkg_J); 4616 BIC_PRESENT(BIC_Cor_J); 4617 BIC_PRESENT(BIC_RAM_J); 4618 BIC_PRESENT(BIC_GFX_J); 4619 } else { 4620 BIC_PRESENT(BIC_PkgWatt); 4621 BIC_PRESENT(BIC_CorWatt); 4622 BIC_PRESENT(BIC_RAMWatt); 4623 BIC_PRESENT(BIC_GFXWatt); 4624 } 4625 break; 4626 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 4627 do_rapl = RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 4628 BIC_PRESENT(BIC_PKG__); 4629 if (rapl_joules) 4630 BIC_PRESENT(BIC_Pkg_J); 4631 else 4632 BIC_PRESENT(BIC_PkgWatt); 4633 break; 4634 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4635 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4636 do_rapl = 4637 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS 4638 | RAPL_GFX | RAPL_PKG_POWER_INFO; 4639 BIC_PRESENT(BIC_PKG__); 4640 BIC_PRESENT(BIC_RAM__); 4641 if (rapl_joules) { 4642 BIC_PRESENT(BIC_Pkg_J); 4643 BIC_PRESENT(BIC_Cor_J); 4644 BIC_PRESENT(BIC_RAM_J); 4645 BIC_PRESENT(BIC_GFX_J); 4646 } else { 4647 BIC_PRESENT(BIC_PkgWatt); 4648 BIC_PRESENT(BIC_CorWatt); 4649 BIC_PRESENT(BIC_RAMWatt); 4650 BIC_PRESENT(BIC_GFXWatt); 4651 } 4652 break; 4653 case INTEL_FAM6_HASWELL_X: /* HSX */ 4654 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4655 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4656 case INTEL_FAM6_ICELAKE_X: /* ICX */ 4657 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */ 4658 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4659 do_rapl = 4660 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | 4661 RAPL_PKG_POWER_INFO; 4662 BIC_PRESENT(BIC_PKG__); 4663 BIC_PRESENT(BIC_RAM__); 4664 if (rapl_joules) { 4665 BIC_PRESENT(BIC_Pkg_J); 4666 BIC_PRESENT(BIC_RAM_J); 4667 } else { 4668 BIC_PRESENT(BIC_PkgWatt); 4669 BIC_PRESENT(BIC_RAMWatt); 4670 } 4671 break; 4672 case INTEL_FAM6_SANDYBRIDGE_X: 4673 case INTEL_FAM6_IVYBRIDGE_X: 4674 do_rapl = 4675 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | 4676 RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 4677 BIC_PRESENT(BIC_PKG__); 4678 BIC_PRESENT(BIC_RAM__); 4679 if (rapl_joules) { 4680 BIC_PRESENT(BIC_Pkg_J); 4681 BIC_PRESENT(BIC_Cor_J); 4682 BIC_PRESENT(BIC_RAM_J); 4683 } else { 4684 BIC_PRESENT(BIC_PkgWatt); 4685 BIC_PRESENT(BIC_CorWatt); 4686 BIC_PRESENT(BIC_RAMWatt); 4687 } 4688 break; 4689 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4690 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 4691 do_rapl = RAPL_PKG | RAPL_CORES; 4692 if (rapl_joules) { 4693 BIC_PRESENT(BIC_Pkg_J); 4694 BIC_PRESENT(BIC_Cor_J); 4695 } else { 4696 BIC_PRESENT(BIC_PkgWatt); 4697 BIC_PRESENT(BIC_CorWatt); 4698 } 4699 break; 4700 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 4701 do_rapl = 4702 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | 4703 RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 4704 BIC_PRESENT(BIC_PKG__); 4705 BIC_PRESENT(BIC_RAM__); 4706 if (rapl_joules) { 4707 BIC_PRESENT(BIC_Pkg_J); 4708 BIC_PRESENT(BIC_Cor_J); 4709 BIC_PRESENT(BIC_RAM_J); 4710 } else { 4711 BIC_PRESENT(BIC_PkgWatt); 4712 BIC_PRESENT(BIC_CorWatt); 4713 BIC_PRESENT(BIC_RAMWatt); 4714 } 4715 break; 4716 default: 4717 return; 4718 } 4719 4720 /* units on package 0, verify later other packages match */ 4721 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 4722 return; 4723 4724 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 4725 if (model == INTEL_FAM6_ATOM_SILVERMONT) 4726 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 4727 else 4728 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 4729 4730 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 4731 4732 time_unit = msr >> 16 & 0xF; 4733 if (time_unit == 0) 4734 time_unit = 0xA; 4735 4736 rapl_time_units = 1.0 / (1 << (time_unit)); 4737 4738 tdp = get_tdp_intel(model); 4739 4740 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4741 if (!quiet) 4742 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4743 } 4744 4745 void rapl_probe_amd(unsigned int family, unsigned int model) 4746 { 4747 unsigned long long msr; 4748 unsigned int eax, ebx, ecx, edx; 4749 unsigned int has_rapl = 0; 4750 double tdp; 4751 4752 UNUSED(model); 4753 4754 if (max_extended_level >= 0x80000007) { 4755 __cpuid(0x80000007, eax, ebx, ecx, edx); 4756 /* RAPL (Fam 17h+) */ 4757 has_rapl = edx & (1 << 14); 4758 } 4759 4760 if (!has_rapl || family < 0x17) 4761 return; 4762 4763 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY; 4764 if (rapl_joules) { 4765 BIC_PRESENT(BIC_Pkg_J); 4766 BIC_PRESENT(BIC_Cor_J); 4767 } else { 4768 BIC_PRESENT(BIC_PkgWatt); 4769 BIC_PRESENT(BIC_CorWatt); 4770 } 4771 4772 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr)) 4773 return; 4774 4775 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf)); 4776 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f)); 4777 rapl_power_units = ldexp(1.0, -(msr & 0xf)); 4778 4779 tdp = get_tdp_amd(family); 4780 4781 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4782 if (!quiet) 4783 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4784 } 4785 4786 /* 4787 * rapl_probe() 4788 * 4789 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 4790 */ 4791 void rapl_probe(unsigned int family, unsigned int model) 4792 { 4793 if (genuine_intel) 4794 rapl_probe_intel(family, model); 4795 if (authentic_amd || hygon_genuine) 4796 rapl_probe_amd(family, model); 4797 } 4798 4799 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 4800 { 4801 if (!genuine_intel) 4802 return; 4803 4804 if (family != 6) 4805 return; 4806 4807 switch (model) { 4808 case INTEL_FAM6_HASWELL: /* HSW */ 4809 case INTEL_FAM6_HASWELL_L: /* HSW */ 4810 case INTEL_FAM6_HASWELL_G: /* HSW */ 4811 do_gfx_perf_limit_reasons = 1; 4812 /* FALLTHRU */ 4813 case INTEL_FAM6_HASWELL_X: /* HSX */ 4814 do_core_perf_limit_reasons = 1; 4815 do_ring_perf_limit_reasons = 1; 4816 default: 4817 return; 4818 } 4819 } 4820 4821 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model) 4822 { 4823 if (family != 6) 4824 return; 4825 4826 switch (model) { 4827 case INTEL_FAM6_BROADWELL_X: 4828 case INTEL_FAM6_SKYLAKE_X: 4829 has_automatic_cstate_conversion = 1; 4830 } 4831 } 4832 4833 void prewake_cstate_probe(unsigned int family, unsigned int model) 4834 { 4835 if (is_icx(family, model) || is_spr(family, model)) 4836 dis_cstate_prewake = 1; 4837 } 4838 4839 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4840 { 4841 unsigned long long msr; 4842 unsigned int dts, dts2; 4843 int cpu; 4844 4845 UNUSED(c); 4846 UNUSED(p); 4847 4848 if (!(do_dts || do_ptm)) 4849 return 0; 4850 4851 cpu = t->cpu_id; 4852 4853 /* DTS is per-core, no need to print for each thread */ 4854 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 4855 return 0; 4856 4857 if (cpu_migrate(cpu)) { 4858 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu); 4859 return -1; 4860 } 4861 4862 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 4863 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 4864 return 0; 4865 4866 dts = (msr >> 16) & 0x7F; 4867 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", cpu, msr, tj_max - dts); 4868 4869 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 4870 return 0; 4871 4872 dts = (msr >> 16) & 0x7F; 4873 dts2 = (msr >> 8) & 0x7F; 4874 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4875 cpu, msr, tj_max - dts, tj_max - dts2); 4876 } 4877 4878 if (do_dts && debug) { 4879 unsigned int resolution; 4880 4881 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 4882 return 0; 4883 4884 dts = (msr >> 16) & 0x7F; 4885 resolution = (msr >> 27) & 0xF; 4886 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 4887 cpu, msr, tj_max - dts, resolution); 4888 4889 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 4890 return 0; 4891 4892 dts = (msr >> 16) & 0x7F; 4893 dts2 = (msr >> 8) & 0x7F; 4894 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4895 cpu, msr, tj_max - dts, tj_max - dts2); 4896 } 4897 4898 return 0; 4899 } 4900 4901 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 4902 { 4903 fprintf(outf, "cpu%d: %s: %sabled (%0.3f Watts, %f sec, clamp %sabled)\n", 4904 cpu, label, 4905 ((msr >> 15) & 1) ? "EN" : "DIS", 4906 ((msr >> 0) & 0x7FFF) * rapl_power_units, 4907 (1.0 + (((msr >> 22) & 0x3) / 4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 4908 (((msr >> 16) & 1) ? "EN" : "DIS")); 4909 4910 return; 4911 } 4912 4913 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4914 { 4915 unsigned long long msr; 4916 const char *msr_name; 4917 int cpu; 4918 4919 UNUSED(c); 4920 UNUSED(p); 4921 4922 if (!do_rapl) 4923 return 0; 4924 4925 /* RAPL counters are per package, so print only for 1st thread/package */ 4926 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4927 return 0; 4928 4929 cpu = t->cpu_id; 4930 if (cpu_migrate(cpu)) { 4931 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu); 4932 return -1; 4933 } 4934 4935 if (do_rapl & RAPL_AMD_F17H) { 4936 msr_name = "MSR_RAPL_PWR_UNIT"; 4937 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr)) 4938 return -1; 4939 } else { 4940 msr_name = "MSR_RAPL_POWER_UNIT"; 4941 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 4942 return -1; 4943 } 4944 4945 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr, 4946 rapl_power_units, rapl_energy_units, rapl_time_units); 4947 4948 if (do_rapl & RAPL_PKG_POWER_INFO) { 4949 4950 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 4951 return -5; 4952 4953 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4954 cpu, msr, 4955 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4956 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4957 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4958 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4959 4960 } 4961 if (do_rapl & RAPL_PKG) { 4962 4963 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 4964 return -9; 4965 4966 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 4967 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 4968 4969 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 4970 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%0.3f Watts, %f* sec, clamp %sabled)\n", 4971 cpu, 4972 ((msr >> 47) & 1) ? "EN" : "DIS", 4973 ((msr >> 32) & 0x7FFF) * rapl_power_units, 4974 (1.0 + (((msr >> 54) & 0x3) / 4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 4975 ((msr >> 48) & 1) ? "EN" : "DIS"); 4976 4977 if (get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr)) 4978 return -9; 4979 4980 fprintf(outf, "cpu%d: MSR_VR_CURRENT_CONFIG: 0x%08llx\n", cpu, msr); 4981 fprintf(outf, "cpu%d: PKG Limit #4: %f Watts (%slocked)\n", 4982 cpu, ((msr >> 0) & 0x1FFF) * rapl_power_units, (msr >> 31) & 1 ? "" : "UN"); 4983 } 4984 4985 if (do_rapl & RAPL_DRAM_POWER_INFO) { 4986 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 4987 return -6; 4988 4989 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4990 cpu, msr, 4991 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4992 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4993 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4994 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4995 } 4996 if (do_rapl & RAPL_DRAM) { 4997 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 4998 return -9; 4999 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 5000 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 5001 5002 print_power_limit_msr(cpu, msr, "DRAM Limit"); 5003 } 5004 if (do_rapl & RAPL_CORE_POLICY) { 5005 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 5006 return -7; 5007 5008 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 5009 } 5010 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 5011 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 5012 return -9; 5013 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 5014 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 5015 print_power_limit_msr(cpu, msr, "Cores Limit"); 5016 } 5017 if (do_rapl & RAPL_GFX) { 5018 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 5019 return -8; 5020 5021 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 5022 5023 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 5024 return -9; 5025 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 5026 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 5027 print_power_limit_msr(cpu, msr, "GFX Limit"); 5028 } 5029 return 0; 5030 } 5031 5032 /* 5033 * SNB adds support for additional MSRs: 5034 * 5035 * MSR_PKG_C7_RESIDENCY 0x000003fa 5036 * MSR_CORE_C7_RESIDENCY 0x000003fe 5037 * MSR_PKG_C2_RESIDENCY 0x0000060d 5038 */ 5039 5040 int has_snb_msrs(unsigned int family, unsigned int model) 5041 { 5042 if (!genuine_intel) 5043 return 0; 5044 5045 if (family != 6) 5046 return 0; 5047 5048 switch (model) { 5049 case INTEL_FAM6_SANDYBRIDGE: 5050 case INTEL_FAM6_SANDYBRIDGE_X: 5051 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 5052 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 5053 case INTEL_FAM6_HASWELL: /* HSW */ 5054 case INTEL_FAM6_HASWELL_X: /* HSW */ 5055 case INTEL_FAM6_HASWELL_L: /* HSW */ 5056 case INTEL_FAM6_HASWELL_G: /* HSW */ 5057 case INTEL_FAM6_BROADWELL: /* BDW */ 5058 case INTEL_FAM6_BROADWELL_G: /* BDW */ 5059 case INTEL_FAM6_BROADWELL_X: /* BDX */ 5060 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5061 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 5062 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 5063 case INTEL_FAM6_ICELAKE_X: /* ICX */ 5064 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */ 5065 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 5066 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5067 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 5068 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 5069 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 5070 return 1; 5071 } 5072 return 0; 5073 } 5074 5075 /* 5076 * HSW ULT added support for C8/C9/C10 MSRs: 5077 * 5078 * MSR_PKG_C8_RESIDENCY 0x00000630 5079 * MSR_PKG_C9_RESIDENCY 0x00000631 5080 * MSR_PKG_C10_RESIDENCY 0x00000632 5081 * 5082 * MSR_PKGC8_IRTL 0x00000633 5083 * MSR_PKGC9_IRTL 0x00000634 5084 * MSR_PKGC10_IRTL 0x00000635 5085 * 5086 */ 5087 int has_c8910_msrs(unsigned int family, unsigned int model) 5088 { 5089 if (!genuine_intel) 5090 return 0; 5091 5092 if (family != 6) 5093 return 0; 5094 5095 switch (model) { 5096 case INTEL_FAM6_HASWELL_L: /* HSW */ 5097 case INTEL_FAM6_BROADWELL: /* BDW */ 5098 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5099 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 5100 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 5101 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5102 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 5103 return 1; 5104 } 5105 return 0; 5106 } 5107 5108 /* 5109 * SKL adds support for additional MSRS: 5110 * 5111 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 5112 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 5113 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 5114 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 5115 */ 5116 int has_skl_msrs(unsigned int family, unsigned int model) 5117 { 5118 if (!genuine_intel) 5119 return 0; 5120 5121 if (family != 6) 5122 return 0; 5123 5124 switch (model) { 5125 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5126 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 5127 return 1; 5128 } 5129 return 0; 5130 } 5131 5132 int is_slm(unsigned int family, unsigned int model) 5133 { 5134 if (!genuine_intel) 5135 return 0; 5136 5137 if (family != 6) 5138 return 0; 5139 5140 switch (model) { 5141 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 5142 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 5143 return 1; 5144 } 5145 return 0; 5146 } 5147 5148 int is_knl(unsigned int family, unsigned int model) 5149 { 5150 if (!genuine_intel) 5151 return 0; 5152 5153 if (family != 6) 5154 return 0; 5155 5156 switch (model) { 5157 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 5158 return 1; 5159 } 5160 return 0; 5161 } 5162 5163 int is_cnl(unsigned int family, unsigned int model) 5164 { 5165 if (!genuine_intel) 5166 return 0; 5167 5168 if (family != 6) 5169 return 0; 5170 5171 switch (model) { 5172 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 5173 return 1; 5174 } 5175 5176 return 0; 5177 } 5178 5179 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 5180 { 5181 if (is_knl(family, model)) 5182 return 1024; 5183 return 1; 5184 } 5185 5186 #define SLM_BCLK_FREQS 5 5187 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0 }; 5188 5189 double slm_bclk(void) 5190 { 5191 unsigned long long msr = 3; 5192 unsigned int i; 5193 double freq; 5194 5195 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 5196 fprintf(outf, "SLM BCLK: unknown\n"); 5197 5198 i = msr & 0xf; 5199 if (i >= SLM_BCLK_FREQS) { 5200 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 5201 i = 3; 5202 } 5203 freq = slm_freq_table[i]; 5204 5205 if (!quiet) 5206 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 5207 5208 return freq; 5209 } 5210 5211 double discover_bclk(unsigned int family, unsigned int model) 5212 { 5213 if (has_snb_msrs(family, model) || is_knl(family, model)) 5214 return 100.00; 5215 else if (is_slm(family, model)) 5216 return slm_bclk(); 5217 else 5218 return 133.33; 5219 } 5220 5221 int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p) 5222 { 5223 unsigned int eax, ebx, ecx, edx; 5224 5225 UNUSED(c); 5226 UNUSED(p); 5227 5228 if (!genuine_intel) 5229 return 0; 5230 5231 if (cpu_migrate(t->cpu_id)) { 5232 fprintf(outf, "Could not migrate to CPU %d\n", t->cpu_id); 5233 return -1; 5234 } 5235 5236 if (max_level < 0x1a) 5237 return 0; 5238 5239 __cpuid(0x1a, eax, ebx, ecx, edx); 5240 eax = (eax >> 24) & 0xFF; 5241 if (eax == 0x20) 5242 t->is_atom = true; 5243 return 0; 5244 } 5245 5246 /* 5247 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 5248 * the Thermal Control Circuit (TCC) activates. 5249 * This is usually equal to tjMax. 5250 * 5251 * Older processors do not have this MSR, so there we guess, 5252 * but also allow cmdline over-ride with -T. 5253 * 5254 * Several MSR temperature values are in units of degrees-C 5255 * below this value, including the Digital Thermal Sensor (DTS), 5256 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 5257 */ 5258 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 5259 { 5260 unsigned long long msr; 5261 unsigned int tcc_default, tcc_offset; 5262 int cpu; 5263 5264 UNUSED(c); 5265 UNUSED(p); 5266 5267 /* tj_max is used only for dts or ptm */ 5268 if (!(do_dts || do_ptm)) 5269 return 0; 5270 5271 /* this is a per-package concept */ 5272 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 5273 return 0; 5274 5275 cpu = t->cpu_id; 5276 if (cpu_migrate(cpu)) { 5277 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 5278 return -1; 5279 } 5280 5281 if (tj_max_override != 0) { 5282 tj_max = tj_max_override; 5283 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", cpu, tj_max); 5284 return 0; 5285 } 5286 5287 /* Temperature Target MSR is Nehalem and newer only */ 5288 if (!do_nhm_platform_info) 5289 goto guess; 5290 5291 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 5292 goto guess; 5293 5294 tcc_default = (msr >> 16) & 0xFF; 5295 5296 if (!quiet) { 5297 switch (tcc_offset_bits) { 5298 case 4: 5299 tcc_offset = (msr >> 24) & 0xF; 5300 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n", 5301 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset); 5302 break; 5303 case 6: 5304 tcc_offset = (msr >> 24) & 0x3F; 5305 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n", 5306 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset); 5307 break; 5308 default: 5309 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", cpu, msr, tcc_default); 5310 break; 5311 } 5312 } 5313 5314 if (!tcc_default) 5315 goto guess; 5316 5317 tj_max = tcc_default; 5318 5319 return 0; 5320 5321 guess: 5322 tj_max = TJMAX_DEFAULT; 5323 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", cpu, tj_max); 5324 5325 return 0; 5326 } 5327 5328 void decode_feature_control_msr(void) 5329 { 5330 unsigned long long msr; 5331 5332 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr)) 5333 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 5334 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : ""); 5335 } 5336 5337 void decode_misc_enable_msr(void) 5338 { 5339 unsigned long long msr; 5340 5341 if (!genuine_intel) 5342 return; 5343 5344 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 5345 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 5346 base_cpu, msr, 5347 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 5348 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 5349 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 5350 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 5351 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 5352 } 5353 5354 void decode_misc_feature_control(void) 5355 { 5356 unsigned long long msr; 5357 5358 if (!has_misc_feature_control) 5359 return; 5360 5361 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 5362 fprintf(outf, 5363 "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 5364 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "", 5365 msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : ""); 5366 } 5367 5368 /* 5369 * Decode MSR_MISC_PWR_MGMT 5370 * 5371 * Decode the bits according to the Nehalem documentation 5372 * bit[0] seems to continue to have same meaning going forward 5373 * bit[1] less so... 5374 */ 5375 void decode_misc_pwr_mgmt_msr(void) 5376 { 5377 unsigned long long msr; 5378 5379 if (!do_nhm_platform_info) 5380 return; 5381 5382 if (no_MSR_MISC_PWR_MGMT) 5383 return; 5384 5385 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 5386 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 5387 base_cpu, msr, 5388 msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS"); 5389 } 5390 5391 /* 5392 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 5393 * 5394 * This MSRs are present on Silvermont processors, 5395 * Intel Atom processor E3000 series (Baytrail), and friends. 5396 */ 5397 void decode_c6_demotion_policy_msr(void) 5398 { 5399 unsigned long long msr; 5400 5401 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 5402 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 5403 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 5404 5405 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 5406 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 5407 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 5408 } 5409 5410 /* 5411 * When models are the same, for the purpose of turbostat, reuse 5412 */ 5413 unsigned int intel_model_duplicates(unsigned int model) 5414 { 5415 5416 switch (model) { 5417 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 5418 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 5419 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 5420 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 5421 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 5422 return INTEL_FAM6_NEHALEM; 5423 5424 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 5425 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 5426 return INTEL_FAM6_NEHALEM_EX; 5427 5428 case INTEL_FAM6_XEON_PHI_KNM: 5429 return INTEL_FAM6_XEON_PHI_KNL; 5430 5431 case INTEL_FAM6_BROADWELL_X: 5432 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */ 5433 return INTEL_FAM6_BROADWELL_X; 5434 5435 case INTEL_FAM6_SKYLAKE_L: 5436 case INTEL_FAM6_SKYLAKE: 5437 case INTEL_FAM6_KABYLAKE_L: 5438 case INTEL_FAM6_KABYLAKE: 5439 case INTEL_FAM6_COMETLAKE_L: 5440 case INTEL_FAM6_COMETLAKE: 5441 return INTEL_FAM6_SKYLAKE_L; 5442 5443 case INTEL_FAM6_ICELAKE_L: 5444 case INTEL_FAM6_ICELAKE_NNPI: 5445 case INTEL_FAM6_TIGERLAKE_L: 5446 case INTEL_FAM6_TIGERLAKE: 5447 case INTEL_FAM6_ROCKETLAKE: 5448 case INTEL_FAM6_LAKEFIELD: 5449 case INTEL_FAM6_ALDERLAKE: 5450 case INTEL_FAM6_ALDERLAKE_L: 5451 case INTEL_FAM6_ATOM_GRACEMONT: 5452 case INTEL_FAM6_RAPTORLAKE: 5453 case INTEL_FAM6_RAPTORLAKE_P: 5454 case INTEL_FAM6_RAPTORLAKE_S: 5455 case INTEL_FAM6_METEORLAKE: 5456 case INTEL_FAM6_METEORLAKE_L: 5457 return INTEL_FAM6_CANNONLAKE_L; 5458 5459 case INTEL_FAM6_ATOM_TREMONT_L: 5460 return INTEL_FAM6_ATOM_TREMONT; 5461 5462 case INTEL_FAM6_ICELAKE_D: 5463 return INTEL_FAM6_ICELAKE_X; 5464 5465 case INTEL_FAM6_EMERALDRAPIDS_X: 5466 return INTEL_FAM6_SAPPHIRERAPIDS_X; 5467 } 5468 return model; 5469 } 5470 5471 void print_dev_latency(void) 5472 { 5473 char *path = "/dev/cpu_dma_latency"; 5474 int fd; 5475 int value; 5476 int retval; 5477 5478 fd = open(path, O_RDONLY); 5479 if (fd < 0) { 5480 warnx("capget(CAP_SYS_ADMIN) failed, try \"# setcap cap_sys_admin=ep %s\"", progname); 5481 return; 5482 } 5483 5484 retval = read(fd, (void *)&value, sizeof(int)); 5485 if (retval != sizeof(int)) { 5486 warn("read failed %s", path); 5487 close(fd); 5488 return; 5489 } 5490 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", value, value == 2000000000 ? "default" : "constrained"); 5491 5492 close(fd); 5493 } 5494 5495 /* 5496 * Linux-perf manages the HW instructions-retired counter 5497 * by enabling when requested, and hiding rollover 5498 */ 5499 void linux_perf_init(void) 5500 { 5501 if (!BIC_IS_ENABLED(BIC_IPC)) 5502 return; 5503 5504 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK)) 5505 return; 5506 5507 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5508 if (fd_instr_count_percpu == NULL) 5509 err(-1, "calloc fd_instr_count_percpu"); 5510 5511 BIC_PRESENT(BIC_IPC); 5512 } 5513 5514 void process_cpuid() 5515 { 5516 unsigned int eax, ebx, ecx, edx; 5517 unsigned int fms, family, model, stepping, ecx_flags, edx_flags; 5518 unsigned long long ucode_patch = 0; 5519 5520 eax = ebx = ecx = edx = 0; 5521 5522 __cpuid(0, max_level, ebx, ecx, edx); 5523 5524 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) 5525 genuine_intel = 1; 5526 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) 5527 authentic_amd = 1; 5528 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e) 5529 hygon_genuine = 1; 5530 5531 if (!quiet) 5532 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n", 5533 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level); 5534 5535 __cpuid(1, fms, ebx, ecx, edx); 5536 family = (fms >> 8) & 0xf; 5537 model = (fms >> 4) & 0xf; 5538 stepping = fms & 0xf; 5539 if (family == 0xf) 5540 family += (fms >> 20) & 0xff; 5541 if (family >= 6) 5542 model += ((fms >> 16) & 0xf) << 4; 5543 ecx_flags = ecx; 5544 edx_flags = edx; 5545 5546 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch)) 5547 warnx("get_msr(UCODE)"); 5548 5549 /* 5550 * check max extended function levels of CPUID. 5551 * This is needed to check for invariant TSC. 5552 * This check is valid for both Intel and AMD. 5553 */ 5554 ebx = ecx = edx = 0; 5555 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 5556 5557 if (!quiet) { 5558 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d) microcode 0x%x\n", 5559 family, model, stepping, family, model, stepping, 5560 (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF)); 5561 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level); 5562 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 5563 ecx_flags & (1 << 0) ? "SSE3" : "-", 5564 ecx_flags & (1 << 3) ? "MONITOR" : "-", 5565 ecx_flags & (1 << 6) ? "SMX" : "-", 5566 ecx_flags & (1 << 7) ? "EIST" : "-", 5567 ecx_flags & (1 << 8) ? "TM2" : "-", 5568 edx_flags & (1 << 4) ? "TSC" : "-", 5569 edx_flags & (1 << 5) ? "MSR" : "-", 5570 edx_flags & (1 << 22) ? "ACPI-TM" : "-", 5571 edx_flags & (1 << 28) ? "HT" : "-", edx_flags & (1 << 29) ? "TM" : "-"); 5572 } 5573 if (genuine_intel) { 5574 model_orig = model; 5575 model = intel_model_duplicates(model); 5576 } 5577 5578 if (!(edx_flags & (1 << 5))) 5579 errx(1, "CPUID: no MSR"); 5580 5581 if (max_extended_level >= 0x80000007) { 5582 5583 /* 5584 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 5585 * this check is valid for both Intel and AMD 5586 */ 5587 __cpuid(0x80000007, eax, ebx, ecx, edx); 5588 has_invariant_tsc = edx & (1 << 8); 5589 } 5590 5591 /* 5592 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 5593 * this check is valid for both Intel and AMD 5594 */ 5595 5596 __cpuid(0x6, eax, ebx, ecx, edx); 5597 has_aperf = ecx & (1 << 0); 5598 if (has_aperf) { 5599 BIC_PRESENT(BIC_Avg_MHz); 5600 BIC_PRESENT(BIC_Busy); 5601 BIC_PRESENT(BIC_Bzy_MHz); 5602 } 5603 do_dts = eax & (1 << 0); 5604 if (do_dts) 5605 BIC_PRESENT(BIC_CoreTmp); 5606 has_turbo = eax & (1 << 1); 5607 do_ptm = eax & (1 << 6); 5608 if (do_ptm) 5609 BIC_PRESENT(BIC_PkgTmp); 5610 has_hwp = eax & (1 << 7); 5611 has_hwp_notify = eax & (1 << 8); 5612 has_hwp_activity_window = eax & (1 << 9); 5613 has_hwp_epp = eax & (1 << 10); 5614 has_hwp_pkg = eax & (1 << 11); 5615 has_epb = ecx & (1 << 3); 5616 5617 if (!quiet) 5618 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 5619 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 5620 has_aperf ? "" : "No-", 5621 has_turbo ? "" : "No-", 5622 do_dts ? "" : "No-", 5623 do_ptm ? "" : "No-", 5624 has_hwp ? "" : "No-", 5625 has_hwp_notify ? "" : "No-", 5626 has_hwp_activity_window ? "" : "No-", 5627 has_hwp_epp ? "" : "No-", has_hwp_pkg ? "" : "No-", has_epb ? "" : "No-"); 5628 5629 if (!quiet) 5630 decode_misc_enable_msr(); 5631 5632 if (max_level >= 0x7 && !quiet) { 5633 int has_sgx; 5634 5635 ecx = 0; 5636 5637 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 5638 5639 has_sgx = ebx & (1 << 2); 5640 5641 is_hybrid = edx & (1 << 15); 5642 5643 fprintf(outf, "CPUID(7): %sSGX %sHybrid\n", has_sgx ? "" : "No-", is_hybrid ? "" : "No-"); 5644 5645 if (has_sgx) 5646 decode_feature_control_msr(); 5647 } 5648 5649 if (max_level >= 0x15) { 5650 unsigned int eax_crystal; 5651 unsigned int ebx_tsc; 5652 5653 /* 5654 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 5655 */ 5656 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 5657 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 5658 5659 if (ebx_tsc != 0) { 5660 5661 if (!quiet && (ebx != 0)) 5662 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 5663 eax_crystal, ebx_tsc, crystal_hz); 5664 5665 if (crystal_hz == 0) 5666 switch (model) { 5667 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5668 crystal_hz = 24000000; /* 24.0 MHz */ 5669 break; 5670 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 5671 crystal_hz = 25000000; /* 25.0 MHz */ 5672 break; 5673 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 5674 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5675 crystal_hz = 19200000; /* 19.2 MHz */ 5676 break; 5677 default: 5678 crystal_hz = 0; 5679 } 5680 5681 if (crystal_hz) { 5682 tsc_hz = (unsigned long long)crystal_hz *ebx_tsc / eax_crystal; 5683 if (!quiet) 5684 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 5685 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 5686 } 5687 } 5688 } 5689 if (max_level >= 0x16) { 5690 unsigned int base_mhz, max_mhz, bus_mhz, edx; 5691 5692 /* 5693 * CPUID 16H Base MHz, Max MHz, Bus MHz 5694 */ 5695 base_mhz = max_mhz = bus_mhz = edx = 0; 5696 5697 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 5698 if (!quiet) 5699 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 5700 base_mhz, max_mhz, bus_mhz); 5701 } 5702 5703 if (has_aperf) 5704 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 5705 5706 BIC_PRESENT(BIC_IRQ); 5707 BIC_PRESENT(BIC_TSC_MHz); 5708 5709 if (probe_nhm_msrs(family, model)) { 5710 do_nhm_platform_info = 1; 5711 BIC_PRESENT(BIC_CPU_c1); 5712 BIC_PRESENT(BIC_CPU_c3); 5713 BIC_PRESENT(BIC_CPU_c6); 5714 BIC_PRESENT(BIC_SMI); 5715 } 5716 do_snb_cstates = has_snb_msrs(family, model); 5717 5718 if (do_snb_cstates) 5719 BIC_PRESENT(BIC_CPU_c7); 5720 5721 do_irtl_snb = has_snb_msrs(family, model); 5722 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 5723 BIC_PRESENT(BIC_Pkgpc2); 5724 if (pkg_cstate_limit >= PCL__3) 5725 BIC_PRESENT(BIC_Pkgpc3); 5726 if (pkg_cstate_limit >= PCL__6) 5727 BIC_PRESENT(BIC_Pkgpc6); 5728 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 5729 BIC_PRESENT(BIC_Pkgpc7); 5730 if (has_slv_msrs(family, model)) { 5731 BIC_NOT_PRESENT(BIC_Pkgpc2); 5732 BIC_NOT_PRESENT(BIC_Pkgpc3); 5733 BIC_PRESENT(BIC_Pkgpc6); 5734 BIC_NOT_PRESENT(BIC_Pkgpc7); 5735 BIC_PRESENT(BIC_Mod_c6); 5736 use_c1_residency_msr = 1; 5737 } 5738 if (is_jvl(family, model)) { 5739 BIC_NOT_PRESENT(BIC_CPU_c3); 5740 BIC_NOT_PRESENT(BIC_CPU_c7); 5741 BIC_NOT_PRESENT(BIC_Pkgpc2); 5742 BIC_NOT_PRESENT(BIC_Pkgpc3); 5743 BIC_NOT_PRESENT(BIC_Pkgpc6); 5744 BIC_NOT_PRESENT(BIC_Pkgpc7); 5745 } 5746 if (is_dnv(family, model)) { 5747 BIC_PRESENT(BIC_CPU_c1); 5748 BIC_NOT_PRESENT(BIC_CPU_c3); 5749 BIC_NOT_PRESENT(BIC_Pkgpc3); 5750 BIC_NOT_PRESENT(BIC_CPU_c7); 5751 BIC_NOT_PRESENT(BIC_Pkgpc7); 5752 use_c1_residency_msr = 1; 5753 } 5754 if (is_skx(family, model) || is_icx(family, model) || is_spr(family, model)) { 5755 BIC_NOT_PRESENT(BIC_CPU_c3); 5756 BIC_NOT_PRESENT(BIC_Pkgpc3); 5757 BIC_NOT_PRESENT(BIC_CPU_c7); 5758 BIC_NOT_PRESENT(BIC_Pkgpc7); 5759 } 5760 if (is_bdx(family, model)) { 5761 BIC_NOT_PRESENT(BIC_CPU_c7); 5762 BIC_NOT_PRESENT(BIC_Pkgpc7); 5763 } 5764 if (has_c8910_msrs(family, model)) { 5765 if (pkg_cstate_limit >= PCL__8) 5766 BIC_PRESENT(BIC_Pkgpc8); 5767 if (pkg_cstate_limit >= PCL__9) 5768 BIC_PRESENT(BIC_Pkgpc9); 5769 if (pkg_cstate_limit >= PCL_10) 5770 BIC_PRESENT(BIC_Pkgpc10); 5771 } 5772 do_irtl_hsw = has_c8910_msrs(family, model); 5773 if (has_skl_msrs(family, model)) { 5774 BIC_PRESENT(BIC_Totl_c0); 5775 BIC_PRESENT(BIC_Any_c0); 5776 BIC_PRESENT(BIC_GFX_c0); 5777 BIC_PRESENT(BIC_CPUGFX); 5778 } 5779 do_slm_cstates = is_slm(family, model); 5780 do_knl_cstates = is_knl(family, model); 5781 5782 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || is_ehl(family, model)) 5783 BIC_NOT_PRESENT(BIC_CPU_c3); 5784 5785 if (!quiet) 5786 decode_misc_pwr_mgmt_msr(); 5787 5788 if (!quiet && has_slv_msrs(family, model)) 5789 decode_c6_demotion_policy_msr(); 5790 5791 rapl_probe(family, model); 5792 perf_limit_reasons_probe(family, model); 5793 automatic_cstate_conversion_probe(family, model); 5794 prewake_cstate_probe(family, model); 5795 5796 check_tcc_offset(model_orig); 5797 5798 if (!quiet) 5799 dump_cstate_pstate_config_info(family, model); 5800 intel_uncore_frequency_probe(); 5801 5802 if (!quiet) 5803 print_dev_latency(); 5804 if (!quiet) 5805 dump_sysfs_cstate_config(); 5806 if (!quiet) 5807 dump_sysfs_pstate_config(); 5808 5809 if (has_skl_msrs(family, model) || is_ehl(family, model)) 5810 calculate_tsc_tweak(); 5811 5812 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 5813 BIC_PRESENT(BIC_GFX_rc6); 5814 5815 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 5816 BIC_PRESENT(BIC_GFXMHz); 5817 5818 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK)) 5819 BIC_PRESENT(BIC_GFXACTMHz); 5820 5821 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 5822 BIC_PRESENT(BIC_CPU_LPI); 5823 else 5824 BIC_NOT_PRESENT(BIC_CPU_LPI); 5825 5826 if (!access("/sys/devices/system/cpu/cpu0/thermal_throttle/core_throttle_count", R_OK)) 5827 BIC_PRESENT(BIC_CORE_THROT_CNT); 5828 else 5829 BIC_NOT_PRESENT(BIC_CORE_THROT_CNT); 5830 5831 if (!access(sys_lpi_file_sysfs, R_OK)) { 5832 sys_lpi_file = sys_lpi_file_sysfs; 5833 BIC_PRESENT(BIC_SYS_LPI); 5834 } else if (!access(sys_lpi_file_debugfs, R_OK)) { 5835 sys_lpi_file = sys_lpi_file_debugfs; 5836 BIC_PRESENT(BIC_SYS_LPI); 5837 } else { 5838 sys_lpi_file_sysfs = NULL; 5839 BIC_NOT_PRESENT(BIC_SYS_LPI); 5840 } 5841 5842 if (!quiet) 5843 decode_misc_feature_control(); 5844 5845 return; 5846 } 5847 5848 /* 5849 * in /dev/cpu/ return success for names that are numbers 5850 * ie. filter out ".", "..", "microcode". 5851 */ 5852 int dir_filter(const struct dirent *dirp) 5853 { 5854 if (isdigit(dirp->d_name[0])) 5855 return 1; 5856 else 5857 return 0; 5858 } 5859 5860 void topology_probe() 5861 { 5862 int i; 5863 int max_core_id = 0; 5864 int max_package_id = 0; 5865 int max_die_id = 0; 5866 int max_siblings = 0; 5867 5868 /* Initialize num_cpus, max_cpu_num */ 5869 set_max_cpu_num(); 5870 topo.num_cpus = 0; 5871 for_all_proc_cpus(count_cpus); 5872 if (!summary_only && topo.num_cpus > 1) 5873 BIC_PRESENT(BIC_CPU); 5874 5875 if (debug > 1) 5876 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 5877 5878 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 5879 if (cpus == NULL) 5880 err(1, "calloc cpus"); 5881 5882 /* 5883 * Allocate and initialize cpu_present_set 5884 */ 5885 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5886 if (cpu_present_set == NULL) 5887 err(3, "CPU_ALLOC"); 5888 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5889 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 5890 for_all_proc_cpus(mark_cpu_present); 5891 5892 /* 5893 * Validate that all cpus in cpu_subset are also in cpu_present_set 5894 */ 5895 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 5896 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 5897 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) 5898 err(1, "cpu%d not present", i); 5899 } 5900 5901 /* 5902 * Allocate and initialize cpu_affinity_set 5903 */ 5904 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5905 if (cpu_affinity_set == NULL) 5906 err(3, "CPU_ALLOC"); 5907 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5908 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 5909 5910 for_all_proc_cpus(init_thread_id); 5911 5912 /* 5913 * For online cpus 5914 * find max_core_id, max_package_id 5915 */ 5916 for (i = 0; i <= topo.max_cpu_num; ++i) { 5917 int siblings; 5918 5919 if (cpu_is_not_present(i)) { 5920 if (debug > 1) 5921 fprintf(outf, "cpu%d NOT PRESENT\n", i); 5922 continue; 5923 } 5924 5925 cpus[i].logical_cpu_id = i; 5926 5927 /* get package information */ 5928 cpus[i].physical_package_id = get_physical_package_id(i); 5929 if (cpus[i].physical_package_id > max_package_id) 5930 max_package_id = cpus[i].physical_package_id; 5931 5932 /* get die information */ 5933 cpus[i].die_id = get_die_id(i); 5934 if (cpus[i].die_id > max_die_id) 5935 max_die_id = cpus[i].die_id; 5936 5937 /* get numa node information */ 5938 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 5939 if (cpus[i].physical_node_id > topo.max_node_num) 5940 topo.max_node_num = cpus[i].physical_node_id; 5941 5942 /* get core information */ 5943 cpus[i].physical_core_id = get_core_id(i); 5944 if (cpus[i].physical_core_id > max_core_id) 5945 max_core_id = cpus[i].physical_core_id; 5946 5947 /* get thread information */ 5948 siblings = get_thread_siblings(&cpus[i]); 5949 if (siblings > max_siblings) 5950 max_siblings = siblings; 5951 if (cpus[i].thread_id == 0) 5952 topo.num_cores++; 5953 } 5954 5955 topo.cores_per_node = max_core_id + 1; 5956 if (debug > 1) 5957 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", max_core_id, topo.cores_per_node); 5958 if (!summary_only && topo.cores_per_node > 1) 5959 BIC_PRESENT(BIC_Core); 5960 5961 topo.num_die = max_die_id + 1; 5962 if (debug > 1) 5963 fprintf(outf, "max_die_id %d, sizing for %d die\n", max_die_id, topo.num_die); 5964 if (!summary_only && topo.num_die > 1) 5965 BIC_PRESENT(BIC_Die); 5966 5967 topo.num_packages = max_package_id + 1; 5968 if (debug > 1) 5969 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages); 5970 if (!summary_only && topo.num_packages > 1) 5971 BIC_PRESENT(BIC_Package); 5972 5973 set_node_data(); 5974 if (debug > 1) 5975 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 5976 if (!summary_only && topo.nodes_per_pkg > 1) 5977 BIC_PRESENT(BIC_Node); 5978 5979 topo.threads_per_core = max_siblings; 5980 if (debug > 1) 5981 fprintf(outf, "max_siblings %d\n", max_siblings); 5982 5983 if (debug < 1) 5984 return; 5985 5986 for (i = 0; i <= topo.max_cpu_num; ++i) { 5987 if (cpu_is_not_present(i)) 5988 continue; 5989 fprintf(outf, 5990 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n", 5991 i, cpus[i].physical_package_id, cpus[i].die_id, 5992 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id); 5993 } 5994 5995 } 5996 5997 void allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) 5998 { 5999 int i; 6000 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * topo.num_packages; 6001 int num_threads = topo.threads_per_core * num_cores; 6002 6003 *t = calloc(num_threads, sizeof(struct thread_data)); 6004 if (*t == NULL) 6005 goto error; 6006 6007 for (i = 0; i < num_threads; i++) 6008 (*t)[i].cpu_id = -1; 6009 6010 *c = calloc(num_cores, sizeof(struct core_data)); 6011 if (*c == NULL) 6012 goto error; 6013 6014 for (i = 0; i < num_cores; i++) 6015 (*c)[i].core_id = -1; 6016 6017 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 6018 if (*p == NULL) 6019 goto error; 6020 6021 for (i = 0; i < topo.num_packages; i++) 6022 (*p)[i].package_id = i; 6023 6024 return; 6025 error: 6026 err(1, "calloc counters"); 6027 } 6028 6029 /* 6030 * init_counter() 6031 * 6032 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 6033 */ 6034 void init_counter(struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base, int cpu_id) 6035 { 6036 int pkg_id = cpus[cpu_id].physical_package_id; 6037 int node_id = cpus[cpu_id].logical_node_id; 6038 int core_id = cpus[cpu_id].physical_core_id; 6039 int thread_id = cpus[cpu_id].thread_id; 6040 struct thread_data *t; 6041 struct core_data *c; 6042 struct pkg_data *p; 6043 6044 /* Workaround for systems where physical_node_id==-1 6045 * and logical_node_id==(-1 - topo.num_cpus) 6046 */ 6047 if (node_id < 0) 6048 node_id = 0; 6049 6050 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 6051 c = GET_CORE(core_base, core_id, node_id, pkg_id); 6052 p = GET_PKG(pkg_base, pkg_id); 6053 6054 t->cpu_id = cpu_id; 6055 if (thread_id == 0) { 6056 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 6057 if (cpu_is_first_core_in_package(cpu_id)) 6058 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 6059 } 6060 6061 c->core_id = core_id; 6062 p->package_id = pkg_id; 6063 } 6064 6065 int initialize_counters(int cpu_id) 6066 { 6067 init_counter(EVEN_COUNTERS, cpu_id); 6068 init_counter(ODD_COUNTERS, cpu_id); 6069 return 0; 6070 } 6071 6072 void allocate_output_buffer() 6073 { 6074 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048); 6075 outp = output_buffer; 6076 if (outp == NULL) 6077 err(-1, "calloc output buffer"); 6078 } 6079 6080 void allocate_fd_percpu(void) 6081 { 6082 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 6083 if (fd_percpu == NULL) 6084 err(-1, "calloc fd_percpu"); 6085 } 6086 6087 void allocate_irq_buffers(void) 6088 { 6089 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 6090 if (irq_column_2_cpu == NULL) 6091 err(-1, "calloc %d", topo.num_cpus); 6092 6093 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 6094 if (irqs_per_cpu == NULL) 6095 err(-1, "calloc %d", topo.max_cpu_num + 1); 6096 } 6097 6098 void setup_all_buffers(void) 6099 { 6100 topology_probe(); 6101 allocate_irq_buffers(); 6102 allocate_fd_percpu(); 6103 allocate_counters(&thread_even, &core_even, &package_even); 6104 allocate_counters(&thread_odd, &core_odd, &package_odd); 6105 allocate_output_buffer(); 6106 for_all_proc_cpus(initialize_counters); 6107 } 6108 6109 void set_base_cpu(void) 6110 { 6111 base_cpu = sched_getcpu(); 6112 if (base_cpu < 0) 6113 err(-ENODEV, "No valid cpus found"); 6114 6115 if (debug > 1) 6116 fprintf(outf, "base_cpu = %d\n", base_cpu); 6117 } 6118 6119 void turbostat_init() 6120 { 6121 setup_all_buffers(); 6122 set_base_cpu(); 6123 check_dev_msr(); 6124 check_permissions(); 6125 process_cpuid(); 6126 linux_perf_init(); 6127 6128 if (!quiet) 6129 for_all_cpus(print_hwp, ODD_COUNTERS); 6130 6131 if (!quiet) 6132 for_all_cpus(print_epb, ODD_COUNTERS); 6133 6134 if (!quiet) 6135 for_all_cpus(print_perf_limit, ODD_COUNTERS); 6136 6137 if (!quiet) 6138 for_all_cpus(print_rapl, ODD_COUNTERS); 6139 6140 for_all_cpus(set_temperature_target, ODD_COUNTERS); 6141 6142 for_all_cpus(get_cpu_type, ODD_COUNTERS); 6143 for_all_cpus(get_cpu_type, EVEN_COUNTERS); 6144 6145 if (!quiet) 6146 for_all_cpus(print_thermal, ODD_COUNTERS); 6147 6148 if (!quiet && do_irtl_snb) 6149 print_irtl(); 6150 6151 if (DO_BIC(BIC_IPC)) 6152 (void)get_instr_count_fd(base_cpu); 6153 } 6154 6155 int fork_it(char **argv) 6156 { 6157 pid_t child_pid; 6158 int status; 6159 6160 snapshot_proc_sysfs_files(); 6161 status = for_all_cpus(get_counters, EVEN_COUNTERS); 6162 first_counter_read = 0; 6163 if (status) 6164 exit(status); 6165 /* clear affinity side-effect of get_counters() */ 6166 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 6167 gettimeofday(&tv_even, (struct timezone *)NULL); 6168 6169 child_pid = fork(); 6170 if (!child_pid) { 6171 /* child */ 6172 execvp(argv[0], argv); 6173 err(errno, "exec %s", argv[0]); 6174 } else { 6175 6176 /* parent */ 6177 if (child_pid == -1) 6178 err(1, "fork"); 6179 6180 signal(SIGINT, SIG_IGN); 6181 signal(SIGQUIT, SIG_IGN); 6182 if (waitpid(child_pid, &status, 0) == -1) 6183 err(status, "waitpid"); 6184 6185 if (WIFEXITED(status)) 6186 status = WEXITSTATUS(status); 6187 } 6188 /* 6189 * n.b. fork_it() does not check for errors from for_all_cpus() 6190 * because re-starting is problematic when forking 6191 */ 6192 snapshot_proc_sysfs_files(); 6193 for_all_cpus(get_counters, ODD_COUNTERS); 6194 gettimeofday(&tv_odd, (struct timezone *)NULL); 6195 timersub(&tv_odd, &tv_even, &tv_delta); 6196 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 6197 fprintf(outf, "%s: Counter reset detected\n", progname); 6198 else { 6199 compute_average(EVEN_COUNTERS); 6200 format_all_counters(EVEN_COUNTERS); 6201 } 6202 6203 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec / 1000000.0); 6204 6205 flush_output_stderr(); 6206 6207 return status; 6208 } 6209 6210 int get_and_dump_counters(void) 6211 { 6212 int status; 6213 6214 snapshot_proc_sysfs_files(); 6215 status = for_all_cpus(get_counters, ODD_COUNTERS); 6216 if (status) 6217 return status; 6218 6219 status = for_all_cpus(dump_counters, ODD_COUNTERS); 6220 if (status) 6221 return status; 6222 6223 flush_output_stdout(); 6224 6225 return status; 6226 } 6227 6228 void print_version() 6229 { 6230 fprintf(outf, "turbostat version 2023.03.17 - Len Brown <lenb@kernel.org>\n"); 6231 } 6232 6233 #define COMMAND_LINE_SIZE 2048 6234 6235 void print_bootcmd(void) 6236 { 6237 char bootcmd[COMMAND_LINE_SIZE]; 6238 FILE *fp; 6239 int ret; 6240 6241 memset(bootcmd, 0, COMMAND_LINE_SIZE); 6242 fp = fopen("/proc/cmdline", "r"); 6243 if (!fp) 6244 return; 6245 6246 ret = fread(bootcmd, sizeof(char), COMMAND_LINE_SIZE - 1, fp); 6247 if (ret) { 6248 bootcmd[ret] = '\0'; 6249 /* the last character is already '\n' */ 6250 fprintf(outf, "Kernel command line: %s", bootcmd); 6251 } 6252 6253 fclose(fp); 6254 } 6255 6256 int add_counter(unsigned int msr_num, char *path, char *name, 6257 unsigned int width, enum counter_scope scope, 6258 enum counter_type type, enum counter_format format, int flags) 6259 { 6260 struct msr_counter *msrp; 6261 6262 msrp = calloc(1, sizeof(struct msr_counter)); 6263 if (msrp == NULL) { 6264 perror("calloc"); 6265 exit(1); 6266 } 6267 6268 msrp->msr_num = msr_num; 6269 strncpy(msrp->name, name, NAME_BYTES - 1); 6270 if (path) 6271 strncpy(msrp->path, path, PATH_BYTES - 1); 6272 msrp->width = width; 6273 msrp->type = type; 6274 msrp->format = format; 6275 msrp->flags = flags; 6276 6277 switch (scope) { 6278 6279 case SCOPE_CPU: 6280 msrp->next = sys.tp; 6281 sys.tp = msrp; 6282 sys.added_thread_counters++; 6283 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 6284 fprintf(stderr, "exceeded max %d added thread counters\n", MAX_ADDED_COUNTERS); 6285 exit(-1); 6286 } 6287 break; 6288 6289 case SCOPE_CORE: 6290 msrp->next = sys.cp; 6291 sys.cp = msrp; 6292 sys.added_core_counters++; 6293 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 6294 fprintf(stderr, "exceeded max %d added core counters\n", MAX_ADDED_COUNTERS); 6295 exit(-1); 6296 } 6297 break; 6298 6299 case SCOPE_PACKAGE: 6300 msrp->next = sys.pp; 6301 sys.pp = msrp; 6302 sys.added_package_counters++; 6303 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 6304 fprintf(stderr, "exceeded max %d added package counters\n", MAX_ADDED_COUNTERS); 6305 exit(-1); 6306 } 6307 break; 6308 } 6309 6310 return 0; 6311 } 6312 6313 void parse_add_command(char *add_command) 6314 { 6315 int msr_num = 0; 6316 char *path = NULL; 6317 char name_buffer[NAME_BYTES] = ""; 6318 int width = 64; 6319 int fail = 0; 6320 enum counter_scope scope = SCOPE_CPU; 6321 enum counter_type type = COUNTER_CYCLES; 6322 enum counter_format format = FORMAT_DELTA; 6323 6324 while (add_command) { 6325 6326 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 6327 goto next; 6328 6329 if (sscanf(add_command, "msr%d", &msr_num) == 1) 6330 goto next; 6331 6332 if (*add_command == '/') { 6333 path = add_command; 6334 goto next; 6335 } 6336 6337 if (sscanf(add_command, "u%d", &width) == 1) { 6338 if ((width == 32) || (width == 64)) 6339 goto next; 6340 width = 64; 6341 } 6342 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 6343 scope = SCOPE_CPU; 6344 goto next; 6345 } 6346 if (!strncmp(add_command, "core", strlen("core"))) { 6347 scope = SCOPE_CORE; 6348 goto next; 6349 } 6350 if (!strncmp(add_command, "package", strlen("package"))) { 6351 scope = SCOPE_PACKAGE; 6352 goto next; 6353 } 6354 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 6355 type = COUNTER_CYCLES; 6356 goto next; 6357 } 6358 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 6359 type = COUNTER_SECONDS; 6360 goto next; 6361 } 6362 if (!strncmp(add_command, "usec", strlen("usec"))) { 6363 type = COUNTER_USEC; 6364 goto next; 6365 } 6366 if (!strncmp(add_command, "raw", strlen("raw"))) { 6367 format = FORMAT_RAW; 6368 goto next; 6369 } 6370 if (!strncmp(add_command, "delta", strlen("delta"))) { 6371 format = FORMAT_DELTA; 6372 goto next; 6373 } 6374 if (!strncmp(add_command, "percent", strlen("percent"))) { 6375 format = FORMAT_PERCENT; 6376 goto next; 6377 } 6378 6379 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 6380 char *eos; 6381 6382 eos = strchr(name_buffer, ','); 6383 if (eos) 6384 *eos = '\0'; 6385 goto next; 6386 } 6387 6388 next: 6389 add_command = strchr(add_command, ','); 6390 if (add_command) { 6391 *add_command = '\0'; 6392 add_command++; 6393 } 6394 6395 } 6396 if ((msr_num == 0) && (path == NULL)) { 6397 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 6398 fail++; 6399 } 6400 6401 /* generate default column header */ 6402 if (*name_buffer == '\0') { 6403 if (width == 32) 6404 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 6405 else 6406 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 6407 } 6408 6409 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 6410 fail++; 6411 6412 if (fail) { 6413 help(); 6414 exit(1); 6415 } 6416 } 6417 6418 int is_deferred_add(char *name) 6419 { 6420 int i; 6421 6422 for (i = 0; i < deferred_add_index; ++i) 6423 if (!strcmp(name, deferred_add_names[i])) 6424 return 1; 6425 return 0; 6426 } 6427 6428 int is_deferred_skip(char *name) 6429 { 6430 int i; 6431 6432 for (i = 0; i < deferred_skip_index; ++i) 6433 if (!strcmp(name, deferred_skip_names[i])) 6434 return 1; 6435 return 0; 6436 } 6437 6438 void probe_sysfs(void) 6439 { 6440 char path[64]; 6441 char name_buf[16]; 6442 FILE *input; 6443 int state; 6444 char *sp; 6445 6446 for (state = 10; state >= 0; --state) { 6447 6448 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 6449 input = fopen(path, "r"); 6450 if (input == NULL) 6451 continue; 6452 if (!fgets(name_buf, sizeof(name_buf), input)) 6453 err(1, "%s: failed to read file", path); 6454 6455 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 6456 sp = strchr(name_buf, '-'); 6457 if (!sp) 6458 sp = strchrnul(name_buf, '\n'); 6459 *sp = '%'; 6460 *(sp + 1) = '\0'; 6461 6462 remove_underbar(name_buf); 6463 6464 fclose(input); 6465 6466 sprintf(path, "cpuidle/state%d/time", state); 6467 6468 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf)) 6469 continue; 6470 6471 if (is_deferred_skip(name_buf)) 6472 continue; 6473 6474 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, FORMAT_PERCENT, SYSFS_PERCPU); 6475 } 6476 6477 for (state = 10; state >= 0; --state) { 6478 6479 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 6480 input = fopen(path, "r"); 6481 if (input == NULL) 6482 continue; 6483 if (!fgets(name_buf, sizeof(name_buf), input)) 6484 err(1, "%s: failed to read file", path); 6485 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 6486 sp = strchr(name_buf, '-'); 6487 if (!sp) 6488 sp = strchrnul(name_buf, '\n'); 6489 *sp = '\0'; 6490 fclose(input); 6491 6492 remove_underbar(name_buf); 6493 6494 sprintf(path, "cpuidle/state%d/usage", state); 6495 6496 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf)) 6497 continue; 6498 6499 if (is_deferred_skip(name_buf)) 6500 continue; 6501 6502 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, FORMAT_DELTA, SYSFS_PERCPU); 6503 } 6504 6505 } 6506 6507 /* 6508 * parse cpuset with following syntax 6509 * 1,2,4..6,8-10 and set bits in cpu_subset 6510 */ 6511 void parse_cpu_command(char *optarg) 6512 { 6513 unsigned int start, end; 6514 char *next; 6515 6516 if (!strcmp(optarg, "core")) { 6517 if (cpu_subset) 6518 goto error; 6519 show_core_only++; 6520 return; 6521 } 6522 if (!strcmp(optarg, "package")) { 6523 if (cpu_subset) 6524 goto error; 6525 show_pkg_only++; 6526 return; 6527 } 6528 if (show_core_only || show_pkg_only) 6529 goto error; 6530 6531 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 6532 if (cpu_subset == NULL) 6533 err(3, "CPU_ALLOC"); 6534 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 6535 6536 CPU_ZERO_S(cpu_subset_size, cpu_subset); 6537 6538 next = optarg; 6539 6540 while (next && *next) { 6541 6542 if (*next == '-') /* no negative cpu numbers */ 6543 goto error; 6544 6545 start = strtoul(next, &next, 10); 6546 6547 if (start >= CPU_SUBSET_MAXCPUS) 6548 goto error; 6549 CPU_SET_S(start, cpu_subset_size, cpu_subset); 6550 6551 if (*next == '\0') 6552 break; 6553 6554 if (*next == ',') { 6555 next += 1; 6556 continue; 6557 } 6558 6559 if (*next == '-') { 6560 next += 1; /* start range */ 6561 } else if (*next == '.') { 6562 next += 1; 6563 if (*next == '.') 6564 next += 1; /* start range */ 6565 else 6566 goto error; 6567 } 6568 6569 end = strtoul(next, &next, 10); 6570 if (end <= start) 6571 goto error; 6572 6573 while (++start <= end) { 6574 if (start >= CPU_SUBSET_MAXCPUS) 6575 goto error; 6576 CPU_SET_S(start, cpu_subset_size, cpu_subset); 6577 } 6578 6579 if (*next == ',') 6580 next += 1; 6581 else if (*next != '\0') 6582 goto error; 6583 } 6584 6585 return; 6586 6587 error: 6588 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 6589 help(); 6590 exit(-1); 6591 } 6592 6593 void cmdline(int argc, char **argv) 6594 { 6595 int opt; 6596 int option_index = 0; 6597 static struct option long_options[] = { 6598 { "add", required_argument, 0, 'a' }, 6599 { "cpu", required_argument, 0, 'c' }, 6600 { "Dump", no_argument, 0, 'D' }, 6601 { "debug", no_argument, 0, 'd' }, /* internal, not documented */ 6602 { "enable", required_argument, 0, 'e' }, 6603 { "interval", required_argument, 0, 'i' }, 6604 { "IPC", no_argument, 0, 'I' }, 6605 { "num_iterations", required_argument, 0, 'n' }, 6606 { "header_iterations", required_argument, 0, 'N' }, 6607 { "help", no_argument, 0, 'h' }, 6608 { "hide", required_argument, 0, 'H' }, // meh, -h taken by --help 6609 { "Joules", no_argument, 0, 'J' }, 6610 { "list", no_argument, 0, 'l' }, 6611 { "out", required_argument, 0, 'o' }, 6612 { "quiet", no_argument, 0, 'q' }, 6613 { "show", required_argument, 0, 's' }, 6614 { "Summary", no_argument, 0, 'S' }, 6615 { "TCC", required_argument, 0, 'T' }, 6616 { "version", no_argument, 0, 'v' }, 6617 { 0, 0, 0, 0 } 6618 }; 6619 6620 progname = argv[0]; 6621 6622 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", long_options, &option_index)) != -1) { 6623 switch (opt) { 6624 case 'a': 6625 parse_add_command(optarg); 6626 break; 6627 case 'c': 6628 parse_cpu_command(optarg); 6629 break; 6630 case 'D': 6631 dump_only++; 6632 break; 6633 case 'e': 6634 /* --enable specified counter */ 6635 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 6636 break; 6637 case 'd': 6638 debug++; 6639 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6640 break; 6641 case 'H': 6642 /* 6643 * --hide: do not show those specified 6644 * multiple invocations simply clear more bits in enabled mask 6645 */ 6646 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 6647 break; 6648 case 'h': 6649 default: 6650 help(); 6651 exit(1); 6652 case 'i': 6653 { 6654 double interval = strtod(optarg, NULL); 6655 6656 if (interval < 0.001) { 6657 fprintf(outf, "interval %f seconds is too small\n", interval); 6658 exit(2); 6659 } 6660 6661 interval_tv.tv_sec = interval_ts.tv_sec = interval; 6662 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 6663 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 6664 } 6665 break; 6666 case 'J': 6667 rapl_joules++; 6668 break; 6669 case 'l': 6670 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6671 list_header_only++; 6672 quiet++; 6673 break; 6674 case 'o': 6675 outf = fopen_or_die(optarg, "w"); 6676 break; 6677 case 'q': 6678 quiet = 1; 6679 break; 6680 case 'n': 6681 num_iterations = strtod(optarg, NULL); 6682 6683 if (num_iterations <= 0) { 6684 fprintf(outf, "iterations %d should be positive number\n", num_iterations); 6685 exit(2); 6686 } 6687 break; 6688 case 'N': 6689 header_iterations = strtod(optarg, NULL); 6690 6691 if (header_iterations <= 0) { 6692 fprintf(outf, "iterations %d should be positive number\n", header_iterations); 6693 exit(2); 6694 } 6695 break; 6696 case 's': 6697 /* 6698 * --show: show only those specified 6699 * The 1st invocation will clear and replace the enabled mask 6700 * subsequent invocations can add to it. 6701 */ 6702 if (shown == 0) 6703 bic_enabled = bic_lookup(optarg, SHOW_LIST); 6704 else 6705 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 6706 shown = 1; 6707 break; 6708 case 'S': 6709 summary_only++; 6710 break; 6711 case 'T': 6712 tj_max_override = atoi(optarg); 6713 break; 6714 case 'v': 6715 print_version(); 6716 exit(0); 6717 break; 6718 } 6719 } 6720 } 6721 6722 int main(int argc, char **argv) 6723 { 6724 outf = stderr; 6725 cmdline(argc, argv); 6726 6727 if (!quiet) { 6728 print_version(); 6729 print_bootcmd(); 6730 } 6731 6732 probe_sysfs(); 6733 6734 turbostat_init(); 6735 6736 msr_sum_record(); 6737 6738 /* dump counters and exit */ 6739 if (dump_only) 6740 return get_and_dump_counters(); 6741 6742 /* list header and exit */ 6743 if (list_header_only) { 6744 print_header(","); 6745 flush_output_stdout(); 6746 return 0; 6747 } 6748 6749 /* 6750 * if any params left, it must be a command to fork 6751 */ 6752 if (argc - optind) 6753 return fork_it(argv + optind); 6754 else 6755 turbostat_loop(); 6756 6757 return 0; 6758 } 6759