1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * turbostat -- show CPU frequency and C-state residency 4 * on modern Intel and AMD processors. 5 * 6 * Copyright (c) 2022 Intel Corporation. 7 * Len Brown <len.brown@intel.com> 8 */ 9 10 #define _GNU_SOURCE 11 #include MSRHEADER 12 #include INTEL_FAMILY_HEADER 13 #include <stdarg.h> 14 #include <stdio.h> 15 #include <err.h> 16 #include <unistd.h> 17 #include <sys/types.h> 18 #include <sys/wait.h> 19 #include <sys/stat.h> 20 #include <sys/select.h> 21 #include <sys/resource.h> 22 #include <fcntl.h> 23 #include <signal.h> 24 #include <sys/time.h> 25 #include <stdlib.h> 26 #include <getopt.h> 27 #include <dirent.h> 28 #include <string.h> 29 #include <ctype.h> 30 #include <sched.h> 31 #include <time.h> 32 #include <cpuid.h> 33 #include <sys/capability.h> 34 #include <errno.h> 35 #include <math.h> 36 #include <linux/perf_event.h> 37 #include <asm/unistd.h> 38 #include <stdbool.h> 39 40 #define UNUSED(x) (void)(x) 41 42 /* 43 * This list matches the column headers, except 44 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 45 * 2. Core and CPU are moved to the end, we can't have strings that contain them 46 * matching on them for --show and --hide. 47 */ 48 49 /* 50 * buffer size used by sscanf() for added column names 51 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 52 */ 53 #define NAME_BYTES 20 54 #define PATH_BYTES 128 55 56 enum counter_scope { SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE }; 57 enum counter_type { COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC }; 58 enum counter_format { FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT }; 59 60 struct msr_counter { 61 unsigned int msr_num; 62 char name[NAME_BYTES]; 63 char path[PATH_BYTES]; 64 unsigned int width; 65 enum counter_type type; 66 enum counter_format format; 67 struct msr_counter *next; 68 unsigned int flags; 69 #define FLAGS_HIDE (1 << 0) 70 #define FLAGS_SHOW (1 << 1) 71 #define SYSFS_PERCPU (1 << 1) 72 }; 73 74 struct msr_counter bic[] = { 75 { 0x0, "usec", "", 0, 0, 0, NULL, 0 }, 76 { 0x0, "Time_Of_Day_Seconds", "", 0, 0, 0, NULL, 0 }, 77 { 0x0, "Package", "", 0, 0, 0, NULL, 0 }, 78 { 0x0, "Node", "", 0, 0, 0, NULL, 0 }, 79 { 0x0, "Avg_MHz", "", 0, 0, 0, NULL, 0 }, 80 { 0x0, "Busy%", "", 0, 0, 0, NULL, 0 }, 81 { 0x0, "Bzy_MHz", "", 0, 0, 0, NULL, 0 }, 82 { 0x0, "TSC_MHz", "", 0, 0, 0, NULL, 0 }, 83 { 0x0, "IRQ", "", 0, 0, 0, NULL, 0 }, 84 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL, 0 }, 85 { 0x0, "sysfs", "", 0, 0, 0, NULL, 0 }, 86 { 0x0, "CPU%c1", "", 0, 0, 0, NULL, 0 }, 87 { 0x0, "CPU%c3", "", 0, 0, 0, NULL, 0 }, 88 { 0x0, "CPU%c6", "", 0, 0, 0, NULL, 0 }, 89 { 0x0, "CPU%c7", "", 0, 0, 0, NULL, 0 }, 90 { 0x0, "ThreadC", "", 0, 0, 0, NULL, 0 }, 91 { 0x0, "CoreTmp", "", 0, 0, 0, NULL, 0 }, 92 { 0x0, "CoreCnt", "", 0, 0, 0, NULL, 0 }, 93 { 0x0, "PkgTmp", "", 0, 0, 0, NULL, 0 }, 94 { 0x0, "GFX%rc6", "", 0, 0, 0, NULL, 0 }, 95 { 0x0, "GFXMHz", "", 0, 0, 0, NULL, 0 }, 96 { 0x0, "Pkg%pc2", "", 0, 0, 0, NULL, 0 }, 97 { 0x0, "Pkg%pc3", "", 0, 0, 0, NULL, 0 }, 98 { 0x0, "Pkg%pc6", "", 0, 0, 0, NULL, 0 }, 99 { 0x0, "Pkg%pc7", "", 0, 0, 0, NULL, 0 }, 100 { 0x0, "Pkg%pc8", "", 0, 0, 0, NULL, 0 }, 101 { 0x0, "Pkg%pc9", "", 0, 0, 0, NULL, 0 }, 102 { 0x0, "Pk%pc10", "", 0, 0, 0, NULL, 0 }, 103 { 0x0, "CPU%LPI", "", 0, 0, 0, NULL, 0 }, 104 { 0x0, "SYS%LPI", "", 0, 0, 0, NULL, 0 }, 105 { 0x0, "PkgWatt", "", 0, 0, 0, NULL, 0 }, 106 { 0x0, "CorWatt", "", 0, 0, 0, NULL, 0 }, 107 { 0x0, "GFXWatt", "", 0, 0, 0, NULL, 0 }, 108 { 0x0, "PkgCnt", "", 0, 0, 0, NULL, 0 }, 109 { 0x0, "RAMWatt", "", 0, 0, 0, NULL, 0 }, 110 { 0x0, "PKG_%", "", 0, 0, 0, NULL, 0 }, 111 { 0x0, "RAM_%", "", 0, 0, 0, NULL, 0 }, 112 { 0x0, "Pkg_J", "", 0, 0, 0, NULL, 0 }, 113 { 0x0, "Cor_J", "", 0, 0, 0, NULL, 0 }, 114 { 0x0, "GFX_J", "", 0, 0, 0, NULL, 0 }, 115 { 0x0, "RAM_J", "", 0, 0, 0, NULL, 0 }, 116 { 0x0, "Mod%c6", "", 0, 0, 0, NULL, 0 }, 117 { 0x0, "Totl%C0", "", 0, 0, 0, NULL, 0 }, 118 { 0x0, "Any%C0", "", 0, 0, 0, NULL, 0 }, 119 { 0x0, "GFX%C0", "", 0, 0, 0, NULL, 0 }, 120 { 0x0, "CPUGFX%", "", 0, 0, 0, NULL, 0 }, 121 { 0x0, "Core", "", 0, 0, 0, NULL, 0 }, 122 { 0x0, "CPU", "", 0, 0, 0, NULL, 0 }, 123 { 0x0, "APIC", "", 0, 0, 0, NULL, 0 }, 124 { 0x0, "X2APIC", "", 0, 0, 0, NULL, 0 }, 125 { 0x0, "Die", "", 0, 0, 0, NULL, 0 }, 126 { 0x0, "GFXAMHz", "", 0, 0, 0, NULL, 0 }, 127 { 0x0, "IPC", "", 0, 0, 0, NULL, 0 }, 128 { 0x0, "CoreThr", "", 0, 0, 0, NULL, 0 }, 129 { 0x0, "UncMHz", "", 0, 0, 0, NULL, 0 }, 130 }; 131 132 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 133 #define BIC_USEC (1ULL << 0) 134 #define BIC_TOD (1ULL << 1) 135 #define BIC_Package (1ULL << 2) 136 #define BIC_Node (1ULL << 3) 137 #define BIC_Avg_MHz (1ULL << 4) 138 #define BIC_Busy (1ULL << 5) 139 #define BIC_Bzy_MHz (1ULL << 6) 140 #define BIC_TSC_MHz (1ULL << 7) 141 #define BIC_IRQ (1ULL << 8) 142 #define BIC_SMI (1ULL << 9) 143 #define BIC_sysfs (1ULL << 10) 144 #define BIC_CPU_c1 (1ULL << 11) 145 #define BIC_CPU_c3 (1ULL << 12) 146 #define BIC_CPU_c6 (1ULL << 13) 147 #define BIC_CPU_c7 (1ULL << 14) 148 #define BIC_ThreadC (1ULL << 15) 149 #define BIC_CoreTmp (1ULL << 16) 150 #define BIC_CoreCnt (1ULL << 17) 151 #define BIC_PkgTmp (1ULL << 18) 152 #define BIC_GFX_rc6 (1ULL << 19) 153 #define BIC_GFXMHz (1ULL << 20) 154 #define BIC_Pkgpc2 (1ULL << 21) 155 #define BIC_Pkgpc3 (1ULL << 22) 156 #define BIC_Pkgpc6 (1ULL << 23) 157 #define BIC_Pkgpc7 (1ULL << 24) 158 #define BIC_Pkgpc8 (1ULL << 25) 159 #define BIC_Pkgpc9 (1ULL << 26) 160 #define BIC_Pkgpc10 (1ULL << 27) 161 #define BIC_CPU_LPI (1ULL << 28) 162 #define BIC_SYS_LPI (1ULL << 29) 163 #define BIC_PkgWatt (1ULL << 30) 164 #define BIC_CorWatt (1ULL << 31) 165 #define BIC_GFXWatt (1ULL << 32) 166 #define BIC_PkgCnt (1ULL << 33) 167 #define BIC_RAMWatt (1ULL << 34) 168 #define BIC_PKG__ (1ULL << 35) 169 #define BIC_RAM__ (1ULL << 36) 170 #define BIC_Pkg_J (1ULL << 37) 171 #define BIC_Cor_J (1ULL << 38) 172 #define BIC_GFX_J (1ULL << 39) 173 #define BIC_RAM_J (1ULL << 40) 174 #define BIC_Mod_c6 (1ULL << 41) 175 #define BIC_Totl_c0 (1ULL << 42) 176 #define BIC_Any_c0 (1ULL << 43) 177 #define BIC_GFX_c0 (1ULL << 44) 178 #define BIC_CPUGFX (1ULL << 45) 179 #define BIC_Core (1ULL << 46) 180 #define BIC_CPU (1ULL << 47) 181 #define BIC_APIC (1ULL << 48) 182 #define BIC_X2APIC (1ULL << 49) 183 #define BIC_Die (1ULL << 50) 184 #define BIC_GFXACTMHz (1ULL << 51) 185 #define BIC_IPC (1ULL << 52) 186 #define BIC_CORE_THROT_CNT (1ULL << 53) 187 #define BIC_UNCORE_MHZ (1ULL << 54) 188 189 #define BIC_TOPOLOGY (BIC_Package | BIC_Node | BIC_CoreCnt | BIC_PkgCnt | BIC_Core | BIC_CPU | BIC_Die ) 190 #define BIC_THERMAL_PWR ( BIC_CoreTmp | BIC_PkgTmp | BIC_PkgWatt | BIC_CorWatt | BIC_GFXWatt | BIC_RAMWatt | BIC_PKG__ | BIC_RAM__) 191 #define BIC_FREQUENCY ( BIC_Avg_MHz | BIC_Busy | BIC_Bzy_MHz | BIC_TSC_MHz | BIC_GFXMHz | BIC_GFXACTMHz | BIC_UNCORE_MHZ) 192 #define BIC_IDLE ( BIC_sysfs | BIC_CPU_c1 | BIC_CPU_c3 | BIC_CPU_c6 | BIC_CPU_c7 | BIC_GFX_rc6 | BIC_Pkgpc2 | BIC_Pkgpc3 | BIC_Pkgpc6 | BIC_Pkgpc7 | BIC_Pkgpc8 | BIC_Pkgpc9 | BIC_Pkgpc10 | BIC_CPU_LPI | BIC_SYS_LPI | BIC_Mod_c6 | BIC_Totl_c0 | BIC_Any_c0 | BIC_GFX_c0 | BIC_CPUGFX) 193 #define BIC_OTHER ( BIC_IRQ | BIC_SMI | BIC_ThreadC | BIC_CoreTmp | BIC_IPC) 194 195 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 196 197 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 198 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 199 200 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 201 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME) 202 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 203 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 204 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 205 #define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT) 206 207 char *proc_stat = "/proc/stat"; 208 FILE *outf; 209 int *fd_percpu; 210 int *fd_instr_count_percpu; 211 struct timeval interval_tv = { 5, 0 }; 212 struct timespec interval_ts = { 5, 0 }; 213 214 /* Save original CPU model */ 215 unsigned int model_orig; 216 217 unsigned int num_iterations; 218 unsigned int header_iterations; 219 unsigned int debug; 220 unsigned int quiet; 221 unsigned int shown; 222 unsigned int sums_need_wide_columns; 223 unsigned int rapl_joules; 224 unsigned int summary_only; 225 unsigned int list_header_only; 226 unsigned int dump_only; 227 unsigned int do_snb_cstates; 228 unsigned int do_knl_cstates; 229 unsigned int do_slm_cstates; 230 unsigned int use_c1_residency_msr; 231 unsigned int has_aperf; 232 unsigned int has_epb; 233 unsigned int is_hybrid; 234 unsigned int do_irtl_snb; 235 unsigned int do_irtl_hsw; 236 unsigned int units = 1000000; /* MHz etc */ 237 unsigned int genuine_intel; 238 unsigned int authentic_amd; 239 unsigned int hygon_genuine; 240 unsigned int max_level, max_extended_level; 241 unsigned int has_invariant_tsc; 242 unsigned int do_nhm_platform_info; 243 unsigned int no_MSR_MISC_PWR_MGMT; 244 unsigned int aperf_mperf_multiplier = 1; 245 double bclk; 246 double base_hz; 247 unsigned int has_base_hz; 248 double tsc_tweak = 1.0; 249 unsigned int show_pkg_only; 250 unsigned int show_core_only; 251 char *output_buffer, *outp; 252 unsigned int do_rapl; 253 unsigned int do_dts; 254 unsigned int do_ptm; 255 unsigned int do_ipc; 256 unsigned long long gfx_cur_rc6_ms; 257 unsigned long long cpuidle_cur_cpu_lpi_us; 258 unsigned long long cpuidle_cur_sys_lpi_us; 259 unsigned int gfx_cur_mhz; 260 unsigned int gfx_act_mhz; 261 unsigned int tj_max; 262 unsigned int tj_max_override; 263 int tcc_offset_bits; 264 double rapl_power_units, rapl_time_units; 265 double rapl_dram_energy_units, rapl_energy_units; 266 double rapl_joule_counter_range; 267 unsigned int do_core_perf_limit_reasons; 268 unsigned int has_automatic_cstate_conversion; 269 unsigned int dis_cstate_prewake; 270 unsigned int do_gfx_perf_limit_reasons; 271 unsigned int do_ring_perf_limit_reasons; 272 unsigned int crystal_hz; 273 unsigned long long tsc_hz; 274 int base_cpu; 275 double discover_bclk(unsigned int family, unsigned int model); 276 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 277 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 278 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 279 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 280 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 281 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 282 unsigned int has_misc_feature_control; 283 unsigned int first_counter_read = 1; 284 int ignore_stdin; 285 286 #define RAPL_PKG (1 << 0) 287 /* 0x610 MSR_PKG_POWER_LIMIT */ 288 /* 0x611 MSR_PKG_ENERGY_STATUS */ 289 #define RAPL_PKG_PERF_STATUS (1 << 1) 290 /* 0x613 MSR_PKG_PERF_STATUS */ 291 #define RAPL_PKG_POWER_INFO (1 << 2) 292 /* 0x614 MSR_PKG_POWER_INFO */ 293 294 #define RAPL_DRAM (1 << 3) 295 /* 0x618 MSR_DRAM_POWER_LIMIT */ 296 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 297 #define RAPL_DRAM_PERF_STATUS (1 << 4) 298 /* 0x61b MSR_DRAM_PERF_STATUS */ 299 #define RAPL_DRAM_POWER_INFO (1 << 5) 300 /* 0x61c MSR_DRAM_POWER_INFO */ 301 302 #define RAPL_CORES_POWER_LIMIT (1 << 6) 303 /* 0x638 MSR_PP0_POWER_LIMIT */ 304 #define RAPL_CORE_POLICY (1 << 7) 305 /* 0x63a MSR_PP0_POLICY */ 306 307 #define RAPL_GFX (1 << 8) 308 /* 0x640 MSR_PP1_POWER_LIMIT */ 309 /* 0x641 MSR_PP1_ENERGY_STATUS */ 310 /* 0x642 MSR_PP1_POLICY */ 311 312 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 313 /* 0x639 MSR_PP0_ENERGY_STATUS */ 314 #define RAPL_PER_CORE_ENERGY (1 << 10) 315 /* Indicates cores energy collection is per-core, 316 * not per-package. */ 317 #define RAPL_AMD_F17H (1 << 11) 318 /* 0xc0010299 MSR_RAPL_PWR_UNIT */ 319 /* 0xc001029a MSR_CORE_ENERGY_STAT */ 320 /* 0xc001029b MSR_PKG_ENERGY_STAT */ 321 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 322 #define TJMAX_DEFAULT 100 323 324 /* MSRs that are not yet in the kernel-provided header. */ 325 #define MSR_RAPL_PWR_UNIT 0xc0010299 326 #define MSR_CORE_ENERGY_STAT 0xc001029a 327 #define MSR_PKG_ENERGY_STAT 0xc001029b 328 329 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 330 331 int backwards_count; 332 char *progname; 333 334 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 335 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset; 336 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size; 337 #define MAX_ADDED_COUNTERS 8 338 #define MAX_ADDED_THREAD_COUNTERS 24 339 #define BITMASK_SIZE 32 340 341 struct thread_data { 342 struct timeval tv_begin; 343 struct timeval tv_end; 344 struct timeval tv_delta; 345 unsigned long long tsc; 346 unsigned long long aperf; 347 unsigned long long mperf; 348 unsigned long long c1; 349 unsigned long long instr_count; 350 unsigned long long irq_count; 351 unsigned int smi_count; 352 unsigned int cpu_id; 353 unsigned int apic_id; 354 unsigned int x2apic_id; 355 unsigned int flags; 356 bool is_atom; 357 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 358 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 359 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 360 } *thread_even, *thread_odd; 361 362 struct core_data { 363 unsigned long long c3; 364 unsigned long long c6; 365 unsigned long long c7; 366 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 367 unsigned int core_temp_c; 368 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */ 369 unsigned int core_id; 370 unsigned long long core_throt_cnt; 371 unsigned long long counter[MAX_ADDED_COUNTERS]; 372 } *core_even, *core_odd; 373 374 struct pkg_data { 375 unsigned long long pc2; 376 unsigned long long pc3; 377 unsigned long long pc6; 378 unsigned long long pc7; 379 unsigned long long pc8; 380 unsigned long long pc9; 381 unsigned long long pc10; 382 unsigned long long cpu_lpi; 383 unsigned long long sys_lpi; 384 unsigned long long pkg_wtd_core_c0; 385 unsigned long long pkg_any_core_c0; 386 unsigned long long pkg_any_gfxe_c0; 387 unsigned long long pkg_both_core_gfxe_c0; 388 long long gfx_rc6_ms; 389 unsigned int gfx_mhz; 390 unsigned int gfx_act_mhz; 391 unsigned int package_id; 392 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 393 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 394 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */ 395 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 396 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 397 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 398 unsigned int pkg_temp_c; 399 unsigned int uncore_mhz; 400 unsigned long long counter[MAX_ADDED_COUNTERS]; 401 } *package_even, *package_odd; 402 403 #define ODD_COUNTERS thread_odd, core_odd, package_odd 404 #define EVEN_COUNTERS thread_even, core_even, package_even 405 406 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 407 ((thread_base) + \ 408 ((pkg_no) * \ 409 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 410 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 411 ((core_no) * topo.threads_per_core) + \ 412 (thread_no)) 413 414 #define GET_CORE(core_base, core_no, node_no, pkg_no) \ 415 ((core_base) + \ 416 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 417 ((node_no) * topo.cores_per_node) + \ 418 (core_no)) 419 420 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 421 422 /* 423 * The accumulated sum of MSR is defined as a monotonic 424 * increasing MSR, it will be accumulated periodically, 425 * despite its register's bit width. 426 */ 427 enum { 428 IDX_PKG_ENERGY, 429 IDX_DRAM_ENERGY, 430 IDX_PP0_ENERGY, 431 IDX_PP1_ENERGY, 432 IDX_PKG_PERF, 433 IDX_DRAM_PERF, 434 IDX_COUNT, 435 }; 436 437 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr); 438 439 struct msr_sum_array { 440 /* get_msr_sum() = sum + (get_msr() - last) */ 441 struct { 442 /*The accumulated MSR value is updated by the timer */ 443 unsigned long long sum; 444 /*The MSR footprint recorded in last timer */ 445 unsigned long long last; 446 } entries[IDX_COUNT]; 447 }; 448 449 /* The percpu MSR sum array.*/ 450 struct msr_sum_array *per_cpu_msr_sum; 451 452 off_t idx_to_offset(int idx) 453 { 454 off_t offset; 455 456 switch (idx) { 457 case IDX_PKG_ENERGY: 458 if (do_rapl & RAPL_AMD_F17H) 459 offset = MSR_PKG_ENERGY_STAT; 460 else 461 offset = MSR_PKG_ENERGY_STATUS; 462 break; 463 case IDX_DRAM_ENERGY: 464 offset = MSR_DRAM_ENERGY_STATUS; 465 break; 466 case IDX_PP0_ENERGY: 467 offset = MSR_PP0_ENERGY_STATUS; 468 break; 469 case IDX_PP1_ENERGY: 470 offset = MSR_PP1_ENERGY_STATUS; 471 break; 472 case IDX_PKG_PERF: 473 offset = MSR_PKG_PERF_STATUS; 474 break; 475 case IDX_DRAM_PERF: 476 offset = MSR_DRAM_PERF_STATUS; 477 break; 478 default: 479 offset = -1; 480 } 481 return offset; 482 } 483 484 int offset_to_idx(off_t offset) 485 { 486 int idx; 487 488 switch (offset) { 489 case MSR_PKG_ENERGY_STATUS: 490 case MSR_PKG_ENERGY_STAT: 491 idx = IDX_PKG_ENERGY; 492 break; 493 case MSR_DRAM_ENERGY_STATUS: 494 idx = IDX_DRAM_ENERGY; 495 break; 496 case MSR_PP0_ENERGY_STATUS: 497 idx = IDX_PP0_ENERGY; 498 break; 499 case MSR_PP1_ENERGY_STATUS: 500 idx = IDX_PP1_ENERGY; 501 break; 502 case MSR_PKG_PERF_STATUS: 503 idx = IDX_PKG_PERF; 504 break; 505 case MSR_DRAM_PERF_STATUS: 506 idx = IDX_DRAM_PERF; 507 break; 508 default: 509 idx = -1; 510 } 511 return idx; 512 } 513 514 int idx_valid(int idx) 515 { 516 switch (idx) { 517 case IDX_PKG_ENERGY: 518 return do_rapl & (RAPL_PKG | RAPL_AMD_F17H); 519 case IDX_DRAM_ENERGY: 520 return do_rapl & RAPL_DRAM; 521 case IDX_PP0_ENERGY: 522 return do_rapl & RAPL_CORES_ENERGY_STATUS; 523 case IDX_PP1_ENERGY: 524 return do_rapl & RAPL_GFX; 525 case IDX_PKG_PERF: 526 return do_rapl & RAPL_PKG_PERF_STATUS; 527 case IDX_DRAM_PERF: 528 return do_rapl & RAPL_DRAM_PERF_STATUS; 529 default: 530 return 0; 531 } 532 } 533 534 struct sys_counters { 535 unsigned int added_thread_counters; 536 unsigned int added_core_counters; 537 unsigned int added_package_counters; 538 struct msr_counter *tp; 539 struct msr_counter *cp; 540 struct msr_counter *pp; 541 } sys; 542 543 struct system_summary { 544 struct thread_data threads; 545 struct core_data cores; 546 struct pkg_data packages; 547 } average; 548 549 struct cpu_topology { 550 int physical_package_id; 551 int die_id; 552 int logical_cpu_id; 553 int physical_node_id; 554 int logical_node_id; /* 0-based count within the package */ 555 int physical_core_id; 556 int thread_id; 557 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 558 } *cpus; 559 560 struct topo_params { 561 int num_packages; 562 int num_die; 563 int num_cpus; 564 int num_cores; 565 int max_cpu_num; 566 int max_node_num; 567 int nodes_per_pkg; 568 int cores_per_node; 569 int threads_per_core; 570 } topo; 571 572 struct timeval tv_even, tv_odd, tv_delta; 573 574 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 575 int *irqs_per_cpu; /* indexed by cpu_num */ 576 577 void setup_all_buffers(void); 578 579 char *sys_lpi_file; 580 char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us"; 581 char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec"; 582 583 int cpu_is_not_present(int cpu) 584 { 585 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 586 } 587 588 /* 589 * run func(thread, core, package) in topology order 590 * skip non-present cpus 591 */ 592 593 int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *), 594 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 595 { 596 int retval, pkg_no, core_no, thread_no, node_no; 597 598 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 599 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) { 600 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 601 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) { 602 struct thread_data *t; 603 struct core_data *c; 604 struct pkg_data *p; 605 606 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no); 607 608 if (cpu_is_not_present(t->cpu_id)) 609 continue; 610 611 c = GET_CORE(core_base, core_no, node_no, pkg_no); 612 p = GET_PKG(pkg_base, pkg_no); 613 614 retval = func(t, c, p); 615 if (retval) 616 return retval; 617 } 618 } 619 } 620 } 621 return 0; 622 } 623 624 int cpu_migrate(int cpu) 625 { 626 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 627 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 628 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 629 return -1; 630 else 631 return 0; 632 } 633 634 int get_msr_fd(int cpu) 635 { 636 char pathname[32]; 637 int fd; 638 639 fd = fd_percpu[cpu]; 640 641 if (fd) 642 return fd; 643 644 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 645 fd = open(pathname, O_RDONLY); 646 if (fd < 0) 647 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 648 649 fd_percpu[cpu] = fd; 650 651 return fd; 652 } 653 654 static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags) 655 { 656 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags); 657 } 658 659 static int perf_instr_count_open(int cpu_num) 660 { 661 struct perf_event_attr pea; 662 int fd; 663 664 memset(&pea, 0, sizeof(struct perf_event_attr)); 665 pea.type = PERF_TYPE_HARDWARE; 666 pea.size = sizeof(struct perf_event_attr); 667 pea.config = PERF_COUNT_HW_INSTRUCTIONS; 668 669 /* counter for cpu_num, including user + kernel and all processes */ 670 fd = perf_event_open(&pea, -1, cpu_num, -1, 0); 671 if (fd == -1) { 672 warn("cpu%d: perf instruction counter", cpu_num); 673 BIC_NOT_PRESENT(BIC_IPC); 674 } 675 676 return fd; 677 } 678 679 int get_instr_count_fd(int cpu) 680 { 681 if (fd_instr_count_percpu[cpu]) 682 return fd_instr_count_percpu[cpu]; 683 684 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu); 685 686 return fd_instr_count_percpu[cpu]; 687 } 688 689 int get_msr(int cpu, off_t offset, unsigned long long *msr) 690 { 691 ssize_t retval; 692 693 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 694 695 if (retval != sizeof *msr) 696 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 697 698 return 0; 699 } 700 701 #define MAX_DEFERRED 16 702 char *deferred_add_names[MAX_DEFERRED]; 703 char *deferred_skip_names[MAX_DEFERRED]; 704 int deferred_add_index; 705 int deferred_skip_index; 706 707 /* 708 * HIDE_LIST - hide this list of counters, show the rest [default] 709 * SHOW_LIST - show this list of counters, hide the rest 710 */ 711 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 712 713 void help(void) 714 { 715 fprintf(outf, 716 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 717 "\n" 718 "Turbostat forks the specified COMMAND and prints statistics\n" 719 "when COMMAND completes.\n" 720 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 721 "to print statistics, until interrupted.\n" 722 " -a, --add add a counter\n" 723 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 724 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n" 725 " {core | package | j,k,l..m,n-p }\n" 726 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n" 727 " -D, --Dump displays the raw counter values\n" 728 " -e, --enable [all | column]\n" 729 " shows all or the specified disabled column\n" 730 " -H, --hide [column|column,column,...]\n" 731 " hide the specified column(s)\n" 732 " -i, --interval sec.subsec\n" 733 " Override default 5-second measurement interval\n" 734 " -J, --Joules displays energy in Joules instead of Watts\n" 735 " -l, --list list column headers only\n" 736 " -n, --num_iterations num\n" 737 " number of the measurement iterations\n" 738 " -N, --header_iterations num\n" 739 " print header every num iterations\n" 740 " -o, --out file\n" 741 " create or truncate \"file\" for all output\n" 742 " -q, --quiet skip decoding system configuration header\n" 743 " -s, --show [column|column,column,...]\n" 744 " show only the specified column(s)\n" 745 " -S, --Summary\n" 746 " limits output to 1-line system summary per interval\n" 747 " -T, --TCC temperature\n" 748 " sets the Thermal Control Circuit temperature in\n" 749 " degrees Celsius\n" 750 " -h, --help print this help message\n" 751 " -v, --version print version information\n" "\n" "For more help, run \"man turbostat\"\n"); 752 } 753 754 /* 755 * bic_lookup 756 * for all the strings in comma separate name_list, 757 * set the approprate bit in return value. 758 */ 759 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 760 { 761 unsigned int i; 762 unsigned long long retval = 0; 763 764 while (name_list) { 765 char *comma; 766 767 comma = strchr(name_list, ','); 768 769 if (comma) 770 *comma = '\0'; 771 772 for (i = 0; i < MAX_BIC; ++i) { 773 if (!strcmp(name_list, bic[i].name)) { 774 retval |= (1ULL << i); 775 break; 776 } 777 if (!strcmp(name_list, "all")) { 778 retval |= ~0; 779 break; 780 } else if (!strcmp(name_list, "topology")) { 781 retval |= BIC_TOPOLOGY; 782 break; 783 } else if (!strcmp(name_list, "power")) { 784 retval |= BIC_THERMAL_PWR; 785 break; 786 } else if (!strcmp(name_list, "idle")) { 787 retval |= BIC_IDLE; 788 break; 789 } else if (!strcmp(name_list, "frequency")) { 790 retval |= BIC_FREQUENCY; 791 break; 792 } else if (!strcmp(name_list, "other")) { 793 retval |= BIC_OTHER; 794 break; 795 } 796 797 } 798 if (i == MAX_BIC) { 799 if (mode == SHOW_LIST) { 800 deferred_add_names[deferred_add_index++] = name_list; 801 if (deferred_add_index >= MAX_DEFERRED) { 802 fprintf(stderr, "More than max %d un-recognized --add options '%s'\n", 803 MAX_DEFERRED, name_list); 804 help(); 805 exit(1); 806 } 807 } else { 808 deferred_skip_names[deferred_skip_index++] = name_list; 809 if (debug) 810 fprintf(stderr, "deferred \"%s\"\n", name_list); 811 if (deferred_skip_index >= MAX_DEFERRED) { 812 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 813 MAX_DEFERRED, name_list); 814 help(); 815 exit(1); 816 } 817 } 818 } 819 820 name_list = comma; 821 if (name_list) 822 name_list++; 823 824 } 825 return retval; 826 } 827 828 void print_header(char *delim) 829 { 830 struct msr_counter *mp; 831 int printed = 0; 832 833 if (DO_BIC(BIC_USEC)) 834 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 835 if (DO_BIC(BIC_TOD)) 836 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 837 if (DO_BIC(BIC_Package)) 838 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 839 if (DO_BIC(BIC_Die)) 840 outp += sprintf(outp, "%sDie", (printed++ ? delim : "")); 841 if (DO_BIC(BIC_Node)) 842 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 843 if (DO_BIC(BIC_Core)) 844 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 845 if (DO_BIC(BIC_CPU)) 846 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 847 if (DO_BIC(BIC_APIC)) 848 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 849 if (DO_BIC(BIC_X2APIC)) 850 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 851 if (DO_BIC(BIC_Avg_MHz)) 852 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 853 if (DO_BIC(BIC_Busy)) 854 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 855 if (DO_BIC(BIC_Bzy_MHz)) 856 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 857 if (DO_BIC(BIC_TSC_MHz)) 858 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 859 860 if (DO_BIC(BIC_IPC)) 861 outp += sprintf(outp, "%sIPC", (printed++ ? delim : "")); 862 863 if (DO_BIC(BIC_IRQ)) { 864 if (sums_need_wide_columns) 865 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 866 else 867 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 868 } 869 870 if (DO_BIC(BIC_SMI)) 871 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 872 873 for (mp = sys.tp; mp; mp = mp->next) { 874 875 if (mp->format == FORMAT_RAW) { 876 if (mp->width == 64) 877 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 878 else 879 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 880 } else { 881 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 882 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 883 else 884 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 885 } 886 } 887 888 if (DO_BIC(BIC_CPU_c1)) 889 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 890 if (DO_BIC(BIC_CPU_c3)) 891 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 892 if (DO_BIC(BIC_CPU_c6)) 893 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 894 if (DO_BIC(BIC_CPU_c7)) 895 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 896 897 if (DO_BIC(BIC_Mod_c6)) 898 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 899 900 if (DO_BIC(BIC_CoreTmp)) 901 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 902 903 if (DO_BIC(BIC_CORE_THROT_CNT)) 904 outp += sprintf(outp, "%sCoreThr", (printed++ ? delim : "")); 905 906 if (do_rapl && !rapl_joules) { 907 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 908 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 909 } else if (do_rapl && rapl_joules) { 910 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 911 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 912 } 913 914 for (mp = sys.cp; mp; mp = mp->next) { 915 if (mp->format == FORMAT_RAW) { 916 if (mp->width == 64) 917 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 918 else 919 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 920 } else { 921 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 922 outp += sprintf(outp, "%s%8s", delim, mp->name); 923 else 924 outp += sprintf(outp, "%s%s", delim, mp->name); 925 } 926 } 927 928 if (DO_BIC(BIC_PkgTmp)) 929 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 930 931 if (DO_BIC(BIC_GFX_rc6)) 932 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 933 934 if (DO_BIC(BIC_GFXMHz)) 935 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 936 937 if (DO_BIC(BIC_GFXACTMHz)) 938 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : "")); 939 940 if (DO_BIC(BIC_Totl_c0)) 941 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 942 if (DO_BIC(BIC_Any_c0)) 943 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 944 if (DO_BIC(BIC_GFX_c0)) 945 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 946 if (DO_BIC(BIC_CPUGFX)) 947 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 948 949 if (DO_BIC(BIC_Pkgpc2)) 950 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 951 if (DO_BIC(BIC_Pkgpc3)) 952 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 953 if (DO_BIC(BIC_Pkgpc6)) 954 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 955 if (DO_BIC(BIC_Pkgpc7)) 956 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 957 if (DO_BIC(BIC_Pkgpc8)) 958 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 959 if (DO_BIC(BIC_Pkgpc9)) 960 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 961 if (DO_BIC(BIC_Pkgpc10)) 962 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 963 if (DO_BIC(BIC_CPU_LPI)) 964 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 965 if (DO_BIC(BIC_SYS_LPI)) 966 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 967 968 if (do_rapl && !rapl_joules) { 969 if (DO_BIC(BIC_PkgWatt)) 970 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 971 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 972 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 973 if (DO_BIC(BIC_GFXWatt)) 974 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 975 if (DO_BIC(BIC_RAMWatt)) 976 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 977 if (DO_BIC(BIC_PKG__)) 978 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 979 if (DO_BIC(BIC_RAM__)) 980 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 981 } else if (do_rapl && rapl_joules) { 982 if (DO_BIC(BIC_Pkg_J)) 983 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 984 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 985 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 986 if (DO_BIC(BIC_GFX_J)) 987 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 988 if (DO_BIC(BIC_RAM_J)) 989 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 990 if (DO_BIC(BIC_PKG__)) 991 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 992 if (DO_BIC(BIC_RAM__)) 993 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 994 } 995 if (DO_BIC(BIC_UNCORE_MHZ)) 996 outp += sprintf(outp, "%sUncMHz", (printed++ ? delim : "")); 997 998 for (mp = sys.pp; mp; mp = mp->next) { 999 if (mp->format == FORMAT_RAW) { 1000 if (mp->width == 64) 1001 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 1002 else 1003 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 1004 } else { 1005 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1006 outp += sprintf(outp, "%s%8s", delim, mp->name); 1007 else 1008 outp += sprintf(outp, "%s%s", delim, mp->name); 1009 } 1010 } 1011 1012 outp += sprintf(outp, "\n"); 1013 } 1014 1015 int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1016 { 1017 int i; 1018 struct msr_counter *mp; 1019 1020 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 1021 1022 if (t) { 1023 outp += sprintf(outp, "CPU: %d flags 0x%x\n", t->cpu_id, t->flags); 1024 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 1025 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 1026 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 1027 outp += sprintf(outp, "c1: %016llX\n", t->c1); 1028 1029 if (DO_BIC(BIC_IPC)) 1030 outp += sprintf(outp, "IPC: %lld\n", t->instr_count); 1031 1032 if (DO_BIC(BIC_IRQ)) 1033 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 1034 if (DO_BIC(BIC_SMI)) 1035 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 1036 1037 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1038 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, t->counter[i]); 1039 } 1040 } 1041 1042 if (c) { 1043 outp += sprintf(outp, "core: %d\n", c->core_id); 1044 outp += sprintf(outp, "c3: %016llX\n", c->c3); 1045 outp += sprintf(outp, "c6: %016llX\n", c->c6); 1046 outp += sprintf(outp, "c7: %016llX\n", c->c7); 1047 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 1048 outp += sprintf(outp, "cpu_throt_count: %016llX\n", c->core_throt_cnt); 1049 outp += sprintf(outp, "Joules: %0X\n", c->core_energy); 1050 1051 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1052 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, c->counter[i]); 1053 } 1054 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 1055 } 1056 1057 if (p) { 1058 outp += sprintf(outp, "package: %d\n", p->package_id); 1059 1060 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 1061 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 1062 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 1063 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 1064 1065 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 1066 if (DO_BIC(BIC_Pkgpc3)) 1067 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 1068 if (DO_BIC(BIC_Pkgpc6)) 1069 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 1070 if (DO_BIC(BIC_Pkgpc7)) 1071 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 1072 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 1073 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 1074 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 1075 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 1076 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 1077 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg); 1078 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores); 1079 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx); 1080 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram); 1081 outp += sprintf(outp, "Throttle PKG: %0llX\n", p->rapl_pkg_perf_status); 1082 outp += sprintf(outp, "Throttle RAM: %0llX\n", p->rapl_dram_perf_status); 1083 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 1084 1085 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1086 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, p->counter[i]); 1087 } 1088 } 1089 1090 outp += sprintf(outp, "\n"); 1091 1092 return 0; 1093 } 1094 1095 /* 1096 * column formatting convention & formats 1097 */ 1098 int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1099 { 1100 double interval_float, tsc; 1101 char *fmt8; 1102 int i; 1103 struct msr_counter *mp; 1104 char *delim = "\t"; 1105 int printed = 0; 1106 1107 /* if showing only 1st thread in core and this isn't one, bail out */ 1108 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1109 return 0; 1110 1111 /* if showing only 1st thread in pkg and this isn't one, bail out */ 1112 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1113 return 0; 1114 1115 /*if not summary line and --cpu is used */ 1116 if ((t != &average.threads) && (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 1117 return 0; 1118 1119 if (DO_BIC(BIC_USEC)) { 1120 /* on each row, print how many usec each timestamp took to gather */ 1121 struct timeval tv; 1122 1123 timersub(&t->tv_end, &t->tv_begin, &tv); 1124 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 1125 } 1126 1127 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 1128 if (DO_BIC(BIC_TOD)) 1129 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 1130 1131 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec / 1000000.0; 1132 1133 tsc = t->tsc * tsc_tweak; 1134 1135 /* topo columns, print blanks on 1st (average) line */ 1136 if (t == &average.threads) { 1137 if (DO_BIC(BIC_Package)) 1138 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1139 if (DO_BIC(BIC_Die)) 1140 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1141 if (DO_BIC(BIC_Node)) 1142 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1143 if (DO_BIC(BIC_Core)) 1144 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1145 if (DO_BIC(BIC_CPU)) 1146 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1147 if (DO_BIC(BIC_APIC)) 1148 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1149 if (DO_BIC(BIC_X2APIC)) 1150 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1151 } else { 1152 if (DO_BIC(BIC_Package)) { 1153 if (p) 1154 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 1155 else 1156 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1157 } 1158 if (DO_BIC(BIC_Die)) { 1159 if (c) 1160 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id); 1161 else 1162 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1163 } 1164 if (DO_BIC(BIC_Node)) { 1165 if (t) 1166 outp += sprintf(outp, "%s%d", 1167 (printed++ ? delim : ""), cpus[t->cpu_id].physical_node_id); 1168 else 1169 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1170 } 1171 if (DO_BIC(BIC_Core)) { 1172 if (c) 1173 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 1174 else 1175 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1176 } 1177 if (DO_BIC(BIC_CPU)) 1178 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 1179 if (DO_BIC(BIC_APIC)) 1180 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 1181 if (DO_BIC(BIC_X2APIC)) 1182 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 1183 } 1184 1185 if (DO_BIC(BIC_Avg_MHz)) 1186 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 / units * t->aperf / interval_float); 1187 1188 if (DO_BIC(BIC_Busy)) 1189 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf / tsc); 1190 1191 if (DO_BIC(BIC_Bzy_MHz)) { 1192 if (has_base_hz) 1193 outp += 1194 sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 1195 else 1196 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1197 tsc / units * t->aperf / t->mperf / interval_float); 1198 } 1199 1200 if (DO_BIC(BIC_TSC_MHz)) 1201 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc / units / interval_float); 1202 1203 if (DO_BIC(BIC_IPC)) 1204 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf); 1205 1206 /* IRQ */ 1207 if (DO_BIC(BIC_IRQ)) { 1208 if (sums_need_wide_columns) 1209 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 1210 else 1211 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 1212 } 1213 1214 /* SMI */ 1215 if (DO_BIC(BIC_SMI)) 1216 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 1217 1218 /* Added counters */ 1219 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1220 if (mp->format == FORMAT_RAW) { 1221 if (mp->width == 32) 1222 outp += 1223 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]); 1224 else 1225 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 1226 } else if (mp->format == FORMAT_DELTA) { 1227 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1228 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 1229 else 1230 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 1231 } else if (mp->format == FORMAT_PERCENT) { 1232 if (mp->type == COUNTER_USEC) 1233 outp += 1234 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1235 t->counter[i] / interval_float / 10000); 1236 else 1237 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i] / tsc); 1238 } 1239 } 1240 1241 /* C1 */ 1242 if (DO_BIC(BIC_CPU_c1)) 1243 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1 / tsc); 1244 1245 /* print per-core data only for 1st thread in core */ 1246 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1247 goto done; 1248 1249 if (DO_BIC(BIC_CPU_c3)) 1250 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3 / tsc); 1251 if (DO_BIC(BIC_CPU_c6)) 1252 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6 / tsc); 1253 if (DO_BIC(BIC_CPU_c7)) 1254 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7 / tsc); 1255 1256 /* Mod%c6 */ 1257 if (DO_BIC(BIC_Mod_c6)) 1258 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 1259 1260 if (DO_BIC(BIC_CoreTmp)) 1261 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1262 1263 /* Core throttle count */ 1264 if (DO_BIC(BIC_CORE_THROT_CNT)) 1265 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->core_throt_cnt); 1266 1267 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1268 if (mp->format == FORMAT_RAW) { 1269 if (mp->width == 32) 1270 outp += 1271 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]); 1272 else 1273 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1274 } else if (mp->format == FORMAT_DELTA) { 1275 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1276 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1277 else 1278 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1279 } else if (mp->format == FORMAT_PERCENT) { 1280 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i] / tsc); 1281 } 1282 } 1283 1284 fmt8 = "%s%.2f"; 1285 1286 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1287 outp += 1288 sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float); 1289 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1290 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units); 1291 1292 /* print per-package data only for 1st core in package */ 1293 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1294 goto done; 1295 1296 /* PkgTmp */ 1297 if (DO_BIC(BIC_PkgTmp)) 1298 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1299 1300 /* GFXrc6 */ 1301 if (DO_BIC(BIC_GFX_rc6)) { 1302 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1303 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1304 } else { 1305 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1306 p->gfx_rc6_ms / 10.0 / interval_float); 1307 } 1308 } 1309 1310 /* GFXMHz */ 1311 if (DO_BIC(BIC_GFXMHz)) 1312 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1313 1314 /* GFXACTMHz */ 1315 if (DO_BIC(BIC_GFXACTMHz)) 1316 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz); 1317 1318 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1319 if (DO_BIC(BIC_Totl_c0)) 1320 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0 / tsc); 1321 if (DO_BIC(BIC_Any_c0)) 1322 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0 / tsc); 1323 if (DO_BIC(BIC_GFX_c0)) 1324 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0 / tsc); 1325 if (DO_BIC(BIC_CPUGFX)) 1326 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0 / tsc); 1327 1328 if (DO_BIC(BIC_Pkgpc2)) 1329 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2 / tsc); 1330 if (DO_BIC(BIC_Pkgpc3)) 1331 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3 / tsc); 1332 if (DO_BIC(BIC_Pkgpc6)) 1333 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6 / tsc); 1334 if (DO_BIC(BIC_Pkgpc7)) 1335 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7 / tsc); 1336 if (DO_BIC(BIC_Pkgpc8)) 1337 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8 / tsc); 1338 if (DO_BIC(BIC_Pkgpc9)) 1339 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9 / tsc); 1340 if (DO_BIC(BIC_Pkgpc10)) 1341 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10 / tsc); 1342 1343 if (DO_BIC(BIC_CPU_LPI)) 1344 outp += 1345 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1346 if (DO_BIC(BIC_SYS_LPI)) 1347 outp += 1348 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1349 1350 if (DO_BIC(BIC_PkgWatt)) 1351 outp += 1352 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1353 1354 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1355 outp += 1356 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1357 if (DO_BIC(BIC_GFXWatt)) 1358 outp += 1359 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1360 if (DO_BIC(BIC_RAMWatt)) 1361 outp += 1362 sprintf(outp, fmt8, (printed++ ? delim : ""), 1363 p->energy_dram * rapl_dram_energy_units / interval_float); 1364 if (DO_BIC(BIC_Pkg_J)) 1365 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 1366 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1367 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 1368 if (DO_BIC(BIC_GFX_J)) 1369 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 1370 if (DO_BIC(BIC_RAM_J)) 1371 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 1372 if (DO_BIC(BIC_PKG__)) 1373 outp += 1374 sprintf(outp, fmt8, (printed++ ? delim : ""), 1375 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 1376 if (DO_BIC(BIC_RAM__)) 1377 outp += 1378 sprintf(outp, fmt8, (printed++ ? delim : ""), 1379 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 1380 /* UncMHz */ 1381 if (DO_BIC(BIC_UNCORE_MHZ)) 1382 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->uncore_mhz); 1383 1384 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1385 if (mp->format == FORMAT_RAW) { 1386 if (mp->width == 32) 1387 outp += 1388 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]); 1389 else 1390 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 1391 } else if (mp->format == FORMAT_DELTA) { 1392 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1393 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 1394 else 1395 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 1396 } else if (mp->format == FORMAT_PERCENT) { 1397 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i] / tsc); 1398 } 1399 } 1400 1401 done: 1402 if (*(outp - 1) != '\n') 1403 outp += sprintf(outp, "\n"); 1404 1405 return 0; 1406 } 1407 1408 void flush_output_stdout(void) 1409 { 1410 FILE *filep; 1411 1412 if (outf == stderr) 1413 filep = stdout; 1414 else 1415 filep = outf; 1416 1417 fputs(output_buffer, filep); 1418 fflush(filep); 1419 1420 outp = output_buffer; 1421 } 1422 1423 void flush_output_stderr(void) 1424 { 1425 fputs(output_buffer, outf); 1426 fflush(outf); 1427 outp = output_buffer; 1428 } 1429 1430 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1431 { 1432 static int count; 1433 1434 if ((!count || (header_iterations && !(count % header_iterations))) || !summary_only) 1435 print_header("\t"); 1436 1437 format_counters(&average.threads, &average.cores, &average.packages); 1438 1439 count++; 1440 1441 if (summary_only) 1442 return; 1443 1444 for_all_cpus(format_counters, t, c, p); 1445 } 1446 1447 #define DELTA_WRAP32(new, old) \ 1448 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32); 1449 1450 int delta_package(struct pkg_data *new, struct pkg_data *old) 1451 { 1452 int i; 1453 struct msr_counter *mp; 1454 1455 if (DO_BIC(BIC_Totl_c0)) 1456 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 1457 if (DO_BIC(BIC_Any_c0)) 1458 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 1459 if (DO_BIC(BIC_GFX_c0)) 1460 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 1461 if (DO_BIC(BIC_CPUGFX)) 1462 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 1463 1464 old->pc2 = new->pc2 - old->pc2; 1465 if (DO_BIC(BIC_Pkgpc3)) 1466 old->pc3 = new->pc3 - old->pc3; 1467 if (DO_BIC(BIC_Pkgpc6)) 1468 old->pc6 = new->pc6 - old->pc6; 1469 if (DO_BIC(BIC_Pkgpc7)) 1470 old->pc7 = new->pc7 - old->pc7; 1471 old->pc8 = new->pc8 - old->pc8; 1472 old->pc9 = new->pc9 - old->pc9; 1473 old->pc10 = new->pc10 - old->pc10; 1474 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 1475 old->sys_lpi = new->sys_lpi - old->sys_lpi; 1476 old->pkg_temp_c = new->pkg_temp_c; 1477 1478 /* flag an error when rc6 counter resets/wraps */ 1479 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 1480 old->gfx_rc6_ms = -1; 1481 else 1482 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 1483 1484 old->uncore_mhz = new->uncore_mhz; 1485 old->gfx_mhz = new->gfx_mhz; 1486 old->gfx_act_mhz = new->gfx_act_mhz; 1487 1488 old->energy_pkg = new->energy_pkg - old->energy_pkg; 1489 old->energy_cores = new->energy_cores - old->energy_cores; 1490 old->energy_gfx = new->energy_gfx - old->energy_gfx; 1491 old->energy_dram = new->energy_dram - old->energy_dram; 1492 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status; 1493 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status; 1494 1495 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1496 if (mp->format == FORMAT_RAW) 1497 old->counter[i] = new->counter[i]; 1498 else 1499 old->counter[i] = new->counter[i] - old->counter[i]; 1500 } 1501 1502 return 0; 1503 } 1504 1505 void delta_core(struct core_data *new, struct core_data *old) 1506 { 1507 int i; 1508 struct msr_counter *mp; 1509 1510 old->c3 = new->c3 - old->c3; 1511 old->c6 = new->c6 - old->c6; 1512 old->c7 = new->c7 - old->c7; 1513 old->core_temp_c = new->core_temp_c; 1514 old->core_throt_cnt = new->core_throt_cnt; 1515 old->mc6_us = new->mc6_us - old->mc6_us; 1516 1517 DELTA_WRAP32(new->core_energy, old->core_energy); 1518 1519 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1520 if (mp->format == FORMAT_RAW) 1521 old->counter[i] = new->counter[i]; 1522 else 1523 old->counter[i] = new->counter[i] - old->counter[i]; 1524 } 1525 } 1526 1527 int soft_c1_residency_display(int bic) 1528 { 1529 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr) 1530 return 0; 1531 1532 return DO_BIC_READ(bic); 1533 } 1534 1535 /* 1536 * old = new - old 1537 */ 1538 int delta_thread(struct thread_data *new, struct thread_data *old, struct core_data *core_delta) 1539 { 1540 int i; 1541 struct msr_counter *mp; 1542 1543 /* we run cpuid just the 1st time, copy the results */ 1544 if (DO_BIC(BIC_APIC)) 1545 new->apic_id = old->apic_id; 1546 if (DO_BIC(BIC_X2APIC)) 1547 new->x2apic_id = old->x2apic_id; 1548 1549 /* 1550 * the timestamps from start of measurement interval are in "old" 1551 * the timestamp from end of measurement interval are in "new" 1552 * over-write old w/ new so we can print end of interval values 1553 */ 1554 1555 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta); 1556 old->tv_begin = new->tv_begin; 1557 old->tv_end = new->tv_end; 1558 1559 old->tsc = new->tsc - old->tsc; 1560 1561 /* check for TSC < 1 Mcycles over interval */ 1562 if (old->tsc < (1000 * 1000)) 1563 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1564 "You can disable all c-states by booting with \"idle=poll\"\n" 1565 "or just the deep ones with \"processor.max_cstate=1\""); 1566 1567 old->c1 = new->c1 - old->c1; 1568 1569 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) { 1570 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1571 old->aperf = new->aperf - old->aperf; 1572 old->mperf = new->mperf - old->mperf; 1573 } else { 1574 return -1; 1575 } 1576 } 1577 1578 if (use_c1_residency_msr) { 1579 /* 1580 * Some models have a dedicated C1 residency MSR, 1581 * which should be more accurate than the derivation below. 1582 */ 1583 } else { 1584 /* 1585 * As counter collection is not atomic, 1586 * it is possible for mperf's non-halted cycles + idle states 1587 * to exceed TSC's all cycles: show c1 = 0% in that case. 1588 */ 1589 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 1590 old->c1 = 0; 1591 else { 1592 /* normal case, derive c1 */ 1593 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1594 - core_delta->c6 - core_delta->c7; 1595 } 1596 } 1597 1598 if (old->mperf == 0) { 1599 if (debug > 1) 1600 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1601 old->mperf = 1; /* divide by 0 protection */ 1602 } 1603 1604 if (DO_BIC(BIC_IPC)) 1605 old->instr_count = new->instr_count - old->instr_count; 1606 1607 if (DO_BIC(BIC_IRQ)) 1608 old->irq_count = new->irq_count - old->irq_count; 1609 1610 if (DO_BIC(BIC_SMI)) 1611 old->smi_count = new->smi_count - old->smi_count; 1612 1613 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1614 if (mp->format == FORMAT_RAW) 1615 old->counter[i] = new->counter[i]; 1616 else 1617 old->counter[i] = new->counter[i] - old->counter[i]; 1618 } 1619 return 0; 1620 } 1621 1622 int delta_cpu(struct thread_data *t, struct core_data *c, 1623 struct pkg_data *p, struct thread_data *t2, struct core_data *c2, struct pkg_data *p2) 1624 { 1625 int retval = 0; 1626 1627 /* calculate core delta only for 1st thread in core */ 1628 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1629 delta_core(c, c2); 1630 1631 /* always calculate thread delta */ 1632 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1633 if (retval) 1634 return retval; 1635 1636 /* calculate package delta only for 1st core in package */ 1637 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1638 retval = delta_package(p, p2); 1639 1640 return retval; 1641 } 1642 1643 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1644 { 1645 int i; 1646 struct msr_counter *mp; 1647 1648 t->tv_begin.tv_sec = 0; 1649 t->tv_begin.tv_usec = 0; 1650 t->tv_end.tv_sec = 0; 1651 t->tv_end.tv_usec = 0; 1652 t->tv_delta.tv_sec = 0; 1653 t->tv_delta.tv_usec = 0; 1654 1655 t->tsc = 0; 1656 t->aperf = 0; 1657 t->mperf = 0; 1658 t->c1 = 0; 1659 1660 t->instr_count = 0; 1661 1662 t->irq_count = 0; 1663 t->smi_count = 0; 1664 1665 /* tells format_counters to dump all fields from this set */ 1666 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1667 1668 c->c3 = 0; 1669 c->c6 = 0; 1670 c->c7 = 0; 1671 c->mc6_us = 0; 1672 c->core_temp_c = 0; 1673 c->core_energy = 0; 1674 c->core_throt_cnt = 0; 1675 1676 p->pkg_wtd_core_c0 = 0; 1677 p->pkg_any_core_c0 = 0; 1678 p->pkg_any_gfxe_c0 = 0; 1679 p->pkg_both_core_gfxe_c0 = 0; 1680 1681 p->pc2 = 0; 1682 if (DO_BIC(BIC_Pkgpc3)) 1683 p->pc3 = 0; 1684 if (DO_BIC(BIC_Pkgpc6)) 1685 p->pc6 = 0; 1686 if (DO_BIC(BIC_Pkgpc7)) 1687 p->pc7 = 0; 1688 p->pc8 = 0; 1689 p->pc9 = 0; 1690 p->pc10 = 0; 1691 p->cpu_lpi = 0; 1692 p->sys_lpi = 0; 1693 1694 p->energy_pkg = 0; 1695 p->energy_dram = 0; 1696 p->energy_cores = 0; 1697 p->energy_gfx = 0; 1698 p->rapl_pkg_perf_status = 0; 1699 p->rapl_dram_perf_status = 0; 1700 p->pkg_temp_c = 0; 1701 1702 p->gfx_rc6_ms = 0; 1703 p->uncore_mhz = 0; 1704 p->gfx_mhz = 0; 1705 p->gfx_act_mhz = 0; 1706 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1707 t->counter[i] = 0; 1708 1709 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1710 c->counter[i] = 0; 1711 1712 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1713 p->counter[i] = 0; 1714 } 1715 1716 int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1717 { 1718 int i; 1719 struct msr_counter *mp; 1720 1721 /* copy un-changing apic_id's */ 1722 if (DO_BIC(BIC_APIC)) 1723 average.threads.apic_id = t->apic_id; 1724 if (DO_BIC(BIC_X2APIC)) 1725 average.threads.x2apic_id = t->x2apic_id; 1726 1727 /* remember first tv_begin */ 1728 if (average.threads.tv_begin.tv_sec == 0) 1729 average.threads.tv_begin = t->tv_begin; 1730 1731 /* remember last tv_end */ 1732 average.threads.tv_end = t->tv_end; 1733 1734 average.threads.tsc += t->tsc; 1735 average.threads.aperf += t->aperf; 1736 average.threads.mperf += t->mperf; 1737 average.threads.c1 += t->c1; 1738 1739 average.threads.instr_count += t->instr_count; 1740 1741 average.threads.irq_count += t->irq_count; 1742 average.threads.smi_count += t->smi_count; 1743 1744 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1745 if (mp->format == FORMAT_RAW) 1746 continue; 1747 average.threads.counter[i] += t->counter[i]; 1748 } 1749 1750 /* sum per-core values only for 1st thread in core */ 1751 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1752 return 0; 1753 1754 average.cores.c3 += c->c3; 1755 average.cores.c6 += c->c6; 1756 average.cores.c7 += c->c7; 1757 average.cores.mc6_us += c->mc6_us; 1758 1759 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1760 average.cores.core_throt_cnt = MAX(average.cores.core_throt_cnt, c->core_throt_cnt); 1761 1762 average.cores.core_energy += c->core_energy; 1763 1764 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1765 if (mp->format == FORMAT_RAW) 1766 continue; 1767 average.cores.counter[i] += c->counter[i]; 1768 } 1769 1770 /* sum per-pkg values only for 1st core in pkg */ 1771 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1772 return 0; 1773 1774 if (DO_BIC(BIC_Totl_c0)) 1775 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1776 if (DO_BIC(BIC_Any_c0)) 1777 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1778 if (DO_BIC(BIC_GFX_c0)) 1779 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1780 if (DO_BIC(BIC_CPUGFX)) 1781 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1782 1783 average.packages.pc2 += p->pc2; 1784 if (DO_BIC(BIC_Pkgpc3)) 1785 average.packages.pc3 += p->pc3; 1786 if (DO_BIC(BIC_Pkgpc6)) 1787 average.packages.pc6 += p->pc6; 1788 if (DO_BIC(BIC_Pkgpc7)) 1789 average.packages.pc7 += p->pc7; 1790 average.packages.pc8 += p->pc8; 1791 average.packages.pc9 += p->pc9; 1792 average.packages.pc10 += p->pc10; 1793 1794 average.packages.cpu_lpi = p->cpu_lpi; 1795 average.packages.sys_lpi = p->sys_lpi; 1796 1797 average.packages.energy_pkg += p->energy_pkg; 1798 average.packages.energy_dram += p->energy_dram; 1799 average.packages.energy_cores += p->energy_cores; 1800 average.packages.energy_gfx += p->energy_gfx; 1801 1802 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1803 average.packages.uncore_mhz = p->uncore_mhz; 1804 average.packages.gfx_mhz = p->gfx_mhz; 1805 average.packages.gfx_act_mhz = p->gfx_act_mhz; 1806 1807 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1808 1809 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1810 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1811 1812 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1813 if (mp->format == FORMAT_RAW) 1814 continue; 1815 average.packages.counter[i] += p->counter[i]; 1816 } 1817 return 0; 1818 } 1819 1820 /* 1821 * sum the counters for all cpus in the system 1822 * compute the weighted average 1823 */ 1824 void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1825 { 1826 int i; 1827 struct msr_counter *mp; 1828 1829 clear_counters(&average.threads, &average.cores, &average.packages); 1830 1831 for_all_cpus(sum_counters, t, c, p); 1832 1833 /* Use the global time delta for the average. */ 1834 average.threads.tv_delta = tv_delta; 1835 1836 average.threads.tsc /= topo.num_cpus; 1837 average.threads.aperf /= topo.num_cpus; 1838 average.threads.mperf /= topo.num_cpus; 1839 average.threads.instr_count /= topo.num_cpus; 1840 average.threads.c1 /= topo.num_cpus; 1841 1842 if (average.threads.irq_count > 9999999) 1843 sums_need_wide_columns = 1; 1844 1845 average.cores.c3 /= topo.num_cores; 1846 average.cores.c6 /= topo.num_cores; 1847 average.cores.c7 /= topo.num_cores; 1848 average.cores.mc6_us /= topo.num_cores; 1849 1850 if (DO_BIC(BIC_Totl_c0)) 1851 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1852 if (DO_BIC(BIC_Any_c0)) 1853 average.packages.pkg_any_core_c0 /= topo.num_packages; 1854 if (DO_BIC(BIC_GFX_c0)) 1855 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1856 if (DO_BIC(BIC_CPUGFX)) 1857 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1858 1859 average.packages.pc2 /= topo.num_packages; 1860 if (DO_BIC(BIC_Pkgpc3)) 1861 average.packages.pc3 /= topo.num_packages; 1862 if (DO_BIC(BIC_Pkgpc6)) 1863 average.packages.pc6 /= topo.num_packages; 1864 if (DO_BIC(BIC_Pkgpc7)) 1865 average.packages.pc7 /= topo.num_packages; 1866 1867 average.packages.pc8 /= topo.num_packages; 1868 average.packages.pc9 /= topo.num_packages; 1869 average.packages.pc10 /= topo.num_packages; 1870 1871 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1872 if (mp->format == FORMAT_RAW) 1873 continue; 1874 if (mp->type == COUNTER_ITEMS) { 1875 if (average.threads.counter[i] > 9999999) 1876 sums_need_wide_columns = 1; 1877 continue; 1878 } 1879 average.threads.counter[i] /= topo.num_cpus; 1880 } 1881 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1882 if (mp->format == FORMAT_RAW) 1883 continue; 1884 if (mp->type == COUNTER_ITEMS) { 1885 if (average.cores.counter[i] > 9999999) 1886 sums_need_wide_columns = 1; 1887 } 1888 average.cores.counter[i] /= topo.num_cores; 1889 } 1890 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1891 if (mp->format == FORMAT_RAW) 1892 continue; 1893 if (mp->type == COUNTER_ITEMS) { 1894 if (average.packages.counter[i] > 9999999) 1895 sums_need_wide_columns = 1; 1896 } 1897 average.packages.counter[i] /= topo.num_packages; 1898 } 1899 } 1900 1901 static unsigned long long rdtsc(void) 1902 { 1903 unsigned int low, high; 1904 1905 asm volatile ("rdtsc":"=a" (low), "=d"(high)); 1906 1907 return low | ((unsigned long long)high) << 32; 1908 } 1909 1910 /* 1911 * Open a file, and exit on failure 1912 */ 1913 FILE *fopen_or_die(const char *path, const char *mode) 1914 { 1915 FILE *filep = fopen(path, mode); 1916 1917 if (!filep) 1918 err(1, "%s: open failed", path); 1919 return filep; 1920 } 1921 1922 /* 1923 * snapshot_sysfs_counter() 1924 * 1925 * return snapshot of given counter 1926 */ 1927 unsigned long long snapshot_sysfs_counter(char *path) 1928 { 1929 FILE *fp; 1930 int retval; 1931 unsigned long long counter; 1932 1933 fp = fopen_or_die(path, "r"); 1934 1935 retval = fscanf(fp, "%lld", &counter); 1936 if (retval != 1) 1937 err(1, "snapshot_sysfs_counter(%s)", path); 1938 1939 fclose(fp); 1940 1941 return counter; 1942 } 1943 1944 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 1945 { 1946 if (mp->msr_num != 0) { 1947 if (get_msr(cpu, mp->msr_num, counterp)) 1948 return -1; 1949 } else { 1950 char path[128 + PATH_BYTES]; 1951 1952 if (mp->flags & SYSFS_PERCPU) { 1953 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", cpu, mp->path); 1954 1955 *counterp = snapshot_sysfs_counter(path); 1956 } else { 1957 *counterp = snapshot_sysfs_counter(mp->path); 1958 } 1959 } 1960 1961 return 0; 1962 } 1963 1964 unsigned long long get_uncore_mhz(int package, int die) 1965 { 1966 char path[128]; 1967 1968 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/current_freq_khz", package, 1969 die); 1970 1971 return (snapshot_sysfs_counter(path) / 1000); 1972 } 1973 1974 int get_epb(int cpu) 1975 { 1976 char path[128 + PATH_BYTES]; 1977 unsigned long long msr; 1978 int ret, epb = -1; 1979 FILE *fp; 1980 1981 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu); 1982 1983 fp = fopen(path, "r"); 1984 if (!fp) 1985 goto msr_fallback; 1986 1987 ret = fscanf(fp, "%d", &epb); 1988 if (ret != 1) 1989 err(1, "%s(%s)", __func__, path); 1990 1991 fclose(fp); 1992 1993 return epb; 1994 1995 msr_fallback: 1996 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr); 1997 1998 return msr & 0xf; 1999 } 2000 2001 void get_apic_id(struct thread_data *t) 2002 { 2003 unsigned int eax, ebx, ecx, edx; 2004 2005 if (DO_BIC(BIC_APIC)) { 2006 eax = ebx = ecx = edx = 0; 2007 __cpuid(1, eax, ebx, ecx, edx); 2008 2009 t->apic_id = (ebx >> 24) & 0xff; 2010 } 2011 2012 if (!DO_BIC(BIC_X2APIC)) 2013 return; 2014 2015 if (authentic_amd || hygon_genuine) { 2016 unsigned int topology_extensions; 2017 2018 if (max_extended_level < 0x8000001e) 2019 return; 2020 2021 eax = ebx = ecx = edx = 0; 2022 __cpuid(0x80000001, eax, ebx, ecx, edx); 2023 topology_extensions = ecx & (1 << 22); 2024 2025 if (topology_extensions == 0) 2026 return; 2027 2028 eax = ebx = ecx = edx = 0; 2029 __cpuid(0x8000001e, eax, ebx, ecx, edx); 2030 2031 t->x2apic_id = eax; 2032 return; 2033 } 2034 2035 if (!genuine_intel) 2036 return; 2037 2038 if (max_level < 0xb) 2039 return; 2040 2041 ecx = 0; 2042 __cpuid(0xb, eax, ebx, ecx, edx); 2043 t->x2apic_id = edx; 2044 2045 if (debug && (t->apic_id != (t->x2apic_id & 0xff))) 2046 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id); 2047 } 2048 2049 int get_core_throt_cnt(int cpu, unsigned long long *cnt) 2050 { 2051 char path[128 + PATH_BYTES]; 2052 unsigned long long tmp; 2053 FILE *fp; 2054 int ret; 2055 2056 sprintf(path, "/sys/devices/system/cpu/cpu%d/thermal_throttle/core_throttle_count", cpu); 2057 fp = fopen(path, "r"); 2058 if (!fp) 2059 return -1; 2060 ret = fscanf(fp, "%lld", &tmp); 2061 fclose(fp); 2062 if (ret != 1) 2063 return -1; 2064 *cnt = tmp; 2065 2066 return 0; 2067 } 2068 2069 /* 2070 * get_counters(...) 2071 * migrate to cpu 2072 * acquire and record local counters for that cpu 2073 */ 2074 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2075 { 2076 int cpu = t->cpu_id; 2077 unsigned long long msr; 2078 int aperf_mperf_retry_count = 0; 2079 struct msr_counter *mp; 2080 int i; 2081 2082 if (cpu_migrate(cpu)) { 2083 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu); 2084 return -1; 2085 } 2086 2087 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 2088 2089 if (first_counter_read) 2090 get_apic_id(t); 2091 retry: 2092 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 2093 2094 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) { 2095 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 2096 2097 /* 2098 * The TSC, APERF and MPERF must be read together for 2099 * APERF/MPERF and MPERF/TSC to give accurate results. 2100 * 2101 * Unfortunately, APERF and MPERF are read by 2102 * individual system call, so delays may occur 2103 * between them. If the time to read them 2104 * varies by a large amount, we re-read them. 2105 */ 2106 2107 /* 2108 * This initial dummy APERF read has been seen to 2109 * reduce jitter in the subsequent reads. 2110 */ 2111 2112 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 2113 return -3; 2114 2115 t->tsc = rdtsc(); /* re-read close to APERF */ 2116 2117 tsc_before = t->tsc; 2118 2119 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 2120 return -3; 2121 2122 tsc_between = rdtsc(); 2123 2124 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 2125 return -4; 2126 2127 tsc_after = rdtsc(); 2128 2129 aperf_time = tsc_between - tsc_before; 2130 mperf_time = tsc_after - tsc_between; 2131 2132 /* 2133 * If the system call latency to read APERF and MPERF 2134 * differ by more than 2x, then try again. 2135 */ 2136 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 2137 aperf_mperf_retry_count++; 2138 if (aperf_mperf_retry_count < 5) 2139 goto retry; 2140 else 2141 warnx("cpu%d jitter %lld %lld", cpu, aperf_time, mperf_time); 2142 } 2143 aperf_mperf_retry_count = 0; 2144 2145 t->aperf = t->aperf * aperf_mperf_multiplier; 2146 t->mperf = t->mperf * aperf_mperf_multiplier; 2147 } 2148 2149 if (DO_BIC(BIC_IPC)) 2150 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long)) 2151 return -4; 2152 2153 if (DO_BIC(BIC_IRQ)) 2154 t->irq_count = irqs_per_cpu[cpu]; 2155 if (DO_BIC(BIC_SMI)) { 2156 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 2157 return -5; 2158 t->smi_count = msr & 0xFFFFFFFF; 2159 } 2160 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 2161 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 2162 return -6; 2163 } 2164 2165 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 2166 if (get_mp(cpu, mp, &t->counter[i])) 2167 return -10; 2168 } 2169 2170 /* collect core counters only for 1st thread in core */ 2171 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 2172 goto done; 2173 2174 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) { 2175 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 2176 return -6; 2177 } 2178 2179 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) { 2180 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 2181 return -7; 2182 } else if (do_knl_cstates || soft_c1_residency_display(BIC_CPU_c6)) { 2183 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 2184 return -7; 2185 } 2186 2187 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) { 2188 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 2189 return -8; 2190 else if (t->is_atom) { 2191 /* 2192 * For Atom CPUs that has core cstate deeper than c6, 2193 * MSR_CORE_C6_RESIDENCY returns residency of cc6 and deeper. 2194 * Minus CC7 (and deeper cstates) residency to get 2195 * accturate cc6 residency. 2196 */ 2197 c->c6 -= c->c7; 2198 } 2199 } 2200 2201 if (DO_BIC(BIC_Mod_c6)) 2202 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 2203 return -8; 2204 2205 if (DO_BIC(BIC_CoreTmp)) { 2206 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 2207 return -9; 2208 c->core_temp_c = tj_max - ((msr >> 16) & 0x7F); 2209 } 2210 2211 if (DO_BIC(BIC_CORE_THROT_CNT)) 2212 get_core_throt_cnt(cpu, &c->core_throt_cnt); 2213 2214 if (do_rapl & RAPL_AMD_F17H) { 2215 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr)) 2216 return -14; 2217 c->core_energy = msr & 0xFFFFFFFF; 2218 } 2219 2220 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 2221 if (get_mp(cpu, mp, &c->counter[i])) 2222 return -10; 2223 } 2224 2225 /* collect package counters only for 1st core in package */ 2226 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2227 goto done; 2228 2229 if (DO_BIC(BIC_Totl_c0)) { 2230 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 2231 return -10; 2232 } 2233 if (DO_BIC(BIC_Any_c0)) { 2234 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 2235 return -11; 2236 } 2237 if (DO_BIC(BIC_GFX_c0)) { 2238 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 2239 return -12; 2240 } 2241 if (DO_BIC(BIC_CPUGFX)) { 2242 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 2243 return -13; 2244 } 2245 if (DO_BIC(BIC_Pkgpc3)) 2246 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 2247 return -9; 2248 if (DO_BIC(BIC_Pkgpc6)) { 2249 if (do_slm_cstates) { 2250 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 2251 return -10; 2252 } else { 2253 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 2254 return -10; 2255 } 2256 } 2257 2258 if (DO_BIC(BIC_Pkgpc2)) 2259 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 2260 return -11; 2261 if (DO_BIC(BIC_Pkgpc7)) 2262 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 2263 return -12; 2264 if (DO_BIC(BIC_Pkgpc8)) 2265 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 2266 return -13; 2267 if (DO_BIC(BIC_Pkgpc9)) 2268 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 2269 return -13; 2270 if (DO_BIC(BIC_Pkgpc10)) 2271 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 2272 return -13; 2273 2274 if (DO_BIC(BIC_CPU_LPI)) 2275 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 2276 if (DO_BIC(BIC_SYS_LPI)) 2277 p->sys_lpi = cpuidle_cur_sys_lpi_us; 2278 2279 if (do_rapl & RAPL_PKG) { 2280 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 2281 return -13; 2282 p->energy_pkg = msr; 2283 } 2284 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 2285 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 2286 return -14; 2287 p->energy_cores = msr; 2288 } 2289 if (do_rapl & RAPL_DRAM) { 2290 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 2291 return -15; 2292 p->energy_dram = msr; 2293 } 2294 if (do_rapl & RAPL_GFX) { 2295 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 2296 return -16; 2297 p->energy_gfx = msr; 2298 } 2299 if (do_rapl & RAPL_PKG_PERF_STATUS) { 2300 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr)) 2301 return -16; 2302 p->rapl_pkg_perf_status = msr; 2303 } 2304 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 2305 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr)) 2306 return -16; 2307 p->rapl_dram_perf_status = msr; 2308 } 2309 if (do_rapl & RAPL_AMD_F17H) { 2310 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr)) 2311 return -13; 2312 p->energy_pkg = msr; 2313 } 2314 if (DO_BIC(BIC_PkgTmp)) { 2315 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 2316 return -17; 2317 p->pkg_temp_c = tj_max - ((msr >> 16) & 0x7F); 2318 } 2319 2320 if (DO_BIC(BIC_GFX_rc6)) 2321 p->gfx_rc6_ms = gfx_cur_rc6_ms; 2322 2323 /* n.b. assume die0 uncore frequency applies to whole package */ 2324 if (DO_BIC(BIC_UNCORE_MHZ)) 2325 p->uncore_mhz = get_uncore_mhz(p->package_id, 0); 2326 2327 if (DO_BIC(BIC_GFXMHz)) 2328 p->gfx_mhz = gfx_cur_mhz; 2329 2330 if (DO_BIC(BIC_GFXACTMHz)) 2331 p->gfx_act_mhz = gfx_act_mhz; 2332 2333 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2334 if (get_mp(cpu, mp, &p->counter[i])) 2335 return -10; 2336 } 2337 done: 2338 gettimeofday(&t->tv_end, (struct timezone *)NULL); 2339 2340 return 0; 2341 } 2342 2343 /* 2344 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 2345 * If you change the values, note they are used both in comparisons 2346 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 2347 */ 2348 2349 #define PCLUKN 0 /* Unknown */ 2350 #define PCLRSV 1 /* Reserved */ 2351 #define PCL__0 2 /* PC0 */ 2352 #define PCL__1 3 /* PC1 */ 2353 #define PCL__2 4 /* PC2 */ 2354 #define PCL__3 5 /* PC3 */ 2355 #define PCL__4 6 /* PC4 */ 2356 #define PCL__6 7 /* PC6 */ 2357 #define PCL_6N 8 /* PC6 No Retention */ 2358 #define PCL_6R 9 /* PC6 Retention */ 2359 #define PCL__7 10 /* PC7 */ 2360 #define PCL_7S 11 /* PC7 Shrink */ 2361 #define PCL__8 12 /* PC8 */ 2362 #define PCL__9 13 /* PC9 */ 2363 #define PCL_10 14 /* PC10 */ 2364 #define PCLUNL 15 /* Unlimited */ 2365 2366 int pkg_cstate_limit = PCLUKN; 2367 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 2368 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited" 2369 }; 2370 2371 int nhm_pkg_cstate_limits[16] = 2372 { PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2373 PCLRSV, PCLRSV 2374 }; 2375 2376 int snb_pkg_cstate_limits[16] = 2377 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2378 PCLRSV, PCLRSV 2379 }; 2380 2381 int hsw_pkg_cstate_limits[16] = 2382 { PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2383 PCLRSV, PCLRSV 2384 }; 2385 2386 int slv_pkg_cstate_limits[16] = 2387 { PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2388 PCL__6, PCL__7 2389 }; 2390 2391 int amt_pkg_cstate_limits[16] = 2392 { PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2393 PCLRSV, PCLRSV 2394 }; 2395 2396 int phi_pkg_cstate_limits[16] = 2397 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2398 PCLRSV, PCLRSV 2399 }; 2400 2401 int glm_pkg_cstate_limits[16] = 2402 { PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2403 PCLRSV, PCLRSV 2404 }; 2405 2406 int skx_pkg_cstate_limits[16] = 2407 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2408 PCLRSV, PCLRSV 2409 }; 2410 2411 int icx_pkg_cstate_limits[16] = 2412 { PCL__0, PCL__2, PCL__6, PCL__6, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2413 PCLRSV, PCLRSV 2414 }; 2415 2416 static void calculate_tsc_tweak() 2417 { 2418 tsc_tweak = base_hz / tsc_hz; 2419 } 2420 2421 void prewake_cstate_probe(unsigned int family, unsigned int model); 2422 2423 static void dump_nhm_platform_info(void) 2424 { 2425 unsigned long long msr; 2426 unsigned int ratio; 2427 2428 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2429 2430 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 2431 2432 ratio = (msr >> 40) & 0xFF; 2433 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk); 2434 2435 ratio = (msr >> 8) & 0xFF; 2436 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk); 2437 2438 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 2439 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 2440 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 2441 2442 /* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */ 2443 if (dis_cstate_prewake) 2444 fprintf(outf, "C-state Pre-wake: %sabled\n", msr & 0x40000000 ? "DIS" : "EN"); 2445 2446 return; 2447 } 2448 2449 static void dump_hsw_turbo_ratio_limits(void) 2450 { 2451 unsigned long long msr; 2452 unsigned int ratio; 2453 2454 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 2455 2456 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 2457 2458 ratio = (msr >> 8) & 0xFF; 2459 if (ratio) 2460 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk); 2461 2462 ratio = (msr >> 0) & 0xFF; 2463 if (ratio) 2464 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk); 2465 return; 2466 } 2467 2468 static void dump_ivt_turbo_ratio_limits(void) 2469 { 2470 unsigned long long msr; 2471 unsigned int ratio; 2472 2473 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 2474 2475 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 2476 2477 ratio = (msr >> 56) & 0xFF; 2478 if (ratio) 2479 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk); 2480 2481 ratio = (msr >> 48) & 0xFF; 2482 if (ratio) 2483 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk); 2484 2485 ratio = (msr >> 40) & 0xFF; 2486 if (ratio) 2487 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk); 2488 2489 ratio = (msr >> 32) & 0xFF; 2490 if (ratio) 2491 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk); 2492 2493 ratio = (msr >> 24) & 0xFF; 2494 if (ratio) 2495 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk); 2496 2497 ratio = (msr >> 16) & 0xFF; 2498 if (ratio) 2499 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk); 2500 2501 ratio = (msr >> 8) & 0xFF; 2502 if (ratio) 2503 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk); 2504 2505 ratio = (msr >> 0) & 0xFF; 2506 if (ratio) 2507 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk); 2508 return; 2509 } 2510 2511 int has_turbo_ratio_group_limits(int family, int model) 2512 { 2513 2514 if (!genuine_intel) 2515 return 0; 2516 2517 if (family != 6) 2518 return 0; 2519 2520 switch (model) { 2521 case INTEL_FAM6_ATOM_GOLDMONT: 2522 case INTEL_FAM6_SKYLAKE_X: 2523 case INTEL_FAM6_ICELAKE_X: 2524 case INTEL_FAM6_ATOM_GOLDMONT_D: 2525 case INTEL_FAM6_ATOM_TREMONT_D: 2526 return 1; 2527 default: 2528 return 0; 2529 } 2530 } 2531 2532 static void dump_turbo_ratio_limits(int family, int model) 2533 { 2534 unsigned long long msr, core_counts; 2535 unsigned int ratio, group_size; 2536 2537 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2538 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2539 2540 if (has_turbo_ratio_group_limits(family, model)) { 2541 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 2542 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 2543 } else { 2544 core_counts = 0x0807060504030201; 2545 } 2546 2547 ratio = (msr >> 56) & 0xFF; 2548 group_size = (core_counts >> 56) & 0xFF; 2549 if (ratio) 2550 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2551 ratio, bclk, ratio * bclk, group_size); 2552 2553 ratio = (msr >> 48) & 0xFF; 2554 group_size = (core_counts >> 48) & 0xFF; 2555 if (ratio) 2556 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2557 ratio, bclk, ratio * bclk, group_size); 2558 2559 ratio = (msr >> 40) & 0xFF; 2560 group_size = (core_counts >> 40) & 0xFF; 2561 if (ratio) 2562 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2563 ratio, bclk, ratio * bclk, group_size); 2564 2565 ratio = (msr >> 32) & 0xFF; 2566 group_size = (core_counts >> 32) & 0xFF; 2567 if (ratio) 2568 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2569 ratio, bclk, ratio * bclk, group_size); 2570 2571 ratio = (msr >> 24) & 0xFF; 2572 group_size = (core_counts >> 24) & 0xFF; 2573 if (ratio) 2574 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2575 ratio, bclk, ratio * bclk, group_size); 2576 2577 ratio = (msr >> 16) & 0xFF; 2578 group_size = (core_counts >> 16) & 0xFF; 2579 if (ratio) 2580 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2581 ratio, bclk, ratio * bclk, group_size); 2582 2583 ratio = (msr >> 8) & 0xFF; 2584 group_size = (core_counts >> 8) & 0xFF; 2585 if (ratio) 2586 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2587 ratio, bclk, ratio * bclk, group_size); 2588 2589 ratio = (msr >> 0) & 0xFF; 2590 group_size = (core_counts >> 0) & 0xFF; 2591 if (ratio) 2592 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2593 ratio, bclk, ratio * bclk, group_size); 2594 return; 2595 } 2596 2597 static void dump_atom_turbo_ratio_limits(void) 2598 { 2599 unsigned long long msr; 2600 unsigned int ratio; 2601 2602 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 2603 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2604 2605 ratio = (msr >> 0) & 0x3F; 2606 if (ratio) 2607 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", ratio, bclk, ratio * bclk); 2608 2609 ratio = (msr >> 8) & 0x3F; 2610 if (ratio) 2611 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", ratio, bclk, ratio * bclk); 2612 2613 ratio = (msr >> 16) & 0x3F; 2614 if (ratio) 2615 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk); 2616 2617 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 2618 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2619 2620 ratio = (msr >> 24) & 0x3F; 2621 if (ratio) 2622 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk); 2623 2624 ratio = (msr >> 16) & 0x3F; 2625 if (ratio) 2626 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk); 2627 2628 ratio = (msr >> 8) & 0x3F; 2629 if (ratio) 2630 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk); 2631 2632 ratio = (msr >> 0) & 0x3F; 2633 if (ratio) 2634 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", ratio, bclk, ratio * bclk); 2635 } 2636 2637 static void dump_knl_turbo_ratio_limits(void) 2638 { 2639 const unsigned int buckets_no = 7; 2640 2641 unsigned long long msr; 2642 int delta_cores, delta_ratio; 2643 int i, b_nr; 2644 unsigned int cores[buckets_no]; 2645 unsigned int ratio[buckets_no]; 2646 2647 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2648 2649 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2650 2651 /* 2652 * Turbo encoding in KNL is as follows: 2653 * [0] -- Reserved 2654 * [7:1] -- Base value of number of active cores of bucket 1. 2655 * [15:8] -- Base value of freq ratio of bucket 1. 2656 * [20:16] -- +ve delta of number of active cores of bucket 2. 2657 * i.e. active cores of bucket 2 = 2658 * active cores of bucket 1 + delta 2659 * [23:21] -- Negative delta of freq ratio of bucket 2. 2660 * i.e. freq ratio of bucket 2 = 2661 * freq ratio of bucket 1 - delta 2662 * [28:24]-- +ve delta of number of active cores of bucket 3. 2663 * [31:29]-- -ve delta of freq ratio of bucket 3. 2664 * [36:32]-- +ve delta of number of active cores of bucket 4. 2665 * [39:37]-- -ve delta of freq ratio of bucket 4. 2666 * [44:40]-- +ve delta of number of active cores of bucket 5. 2667 * [47:45]-- -ve delta of freq ratio of bucket 5. 2668 * [52:48]-- +ve delta of number of active cores of bucket 6. 2669 * [55:53]-- -ve delta of freq ratio of bucket 6. 2670 * [60:56]-- +ve delta of number of active cores of bucket 7. 2671 * [63:61]-- -ve delta of freq ratio of bucket 7. 2672 */ 2673 2674 b_nr = 0; 2675 cores[b_nr] = (msr & 0xFF) >> 1; 2676 ratio[b_nr] = (msr >> 8) & 0xFF; 2677 2678 for (i = 16; i < 64; i += 8) { 2679 delta_cores = (msr >> i) & 0x1F; 2680 delta_ratio = (msr >> (i + 5)) & 0x7; 2681 2682 cores[b_nr + 1] = cores[b_nr] + delta_cores; 2683 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 2684 b_nr++; 2685 } 2686 2687 for (i = buckets_no - 1; i >= 0; i--) 2688 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 2689 fprintf(outf, 2690 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2691 ratio[i], bclk, ratio[i] * bclk, cores[i]); 2692 } 2693 2694 static void dump_nhm_cst_cfg(void) 2695 { 2696 unsigned long long msr; 2697 2698 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2699 2700 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 2701 2702 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 2703 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 2704 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 2705 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 2706 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 2707 (msr & (1 << 15)) ? "" : "UN", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]); 2708 2709 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 2710 if (has_automatic_cstate_conversion) { 2711 fprintf(outf, ", automatic c-state conversion=%s", (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 2712 } 2713 2714 fprintf(outf, ")\n"); 2715 2716 return; 2717 } 2718 2719 static void dump_config_tdp(void) 2720 { 2721 unsigned long long msr; 2722 2723 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 2724 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 2725 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 2726 2727 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 2728 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 2729 if (msr) { 2730 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2731 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2732 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2733 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 2734 } 2735 fprintf(outf, ")\n"); 2736 2737 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 2738 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 2739 if (msr) { 2740 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2741 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2742 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2743 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 2744 } 2745 fprintf(outf, ")\n"); 2746 2747 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 2748 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 2749 if ((msr) & 0x3) 2750 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 2751 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2752 fprintf(outf, ")\n"); 2753 2754 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 2755 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 2756 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 2757 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2758 fprintf(outf, ")\n"); 2759 } 2760 2761 unsigned int irtl_time_units[] = { 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 2762 2763 void print_irtl(void) 2764 { 2765 unsigned long long msr; 2766 2767 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 2768 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 2769 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2770 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2771 2772 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 2773 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 2774 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2775 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2776 2777 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 2778 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 2779 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2780 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2781 2782 if (!do_irtl_hsw) 2783 return; 2784 2785 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 2786 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 2787 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2788 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2789 2790 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 2791 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 2792 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2793 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2794 2795 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 2796 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 2797 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2798 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2799 2800 } 2801 2802 void free_fd_percpu(void) 2803 { 2804 int i; 2805 2806 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 2807 if (fd_percpu[i] != 0) 2808 close(fd_percpu[i]); 2809 } 2810 2811 free(fd_percpu); 2812 } 2813 2814 void free_all_buffers(void) 2815 { 2816 int i; 2817 2818 CPU_FREE(cpu_present_set); 2819 cpu_present_set = NULL; 2820 cpu_present_setsize = 0; 2821 2822 CPU_FREE(cpu_affinity_set); 2823 cpu_affinity_set = NULL; 2824 cpu_affinity_setsize = 0; 2825 2826 free(thread_even); 2827 free(core_even); 2828 free(package_even); 2829 2830 thread_even = NULL; 2831 core_even = NULL; 2832 package_even = NULL; 2833 2834 free(thread_odd); 2835 free(core_odd); 2836 free(package_odd); 2837 2838 thread_odd = NULL; 2839 core_odd = NULL; 2840 package_odd = NULL; 2841 2842 free(output_buffer); 2843 output_buffer = NULL; 2844 outp = NULL; 2845 2846 free_fd_percpu(); 2847 2848 free(irq_column_2_cpu); 2849 free(irqs_per_cpu); 2850 2851 for (i = 0; i <= topo.max_cpu_num; ++i) { 2852 if (cpus[i].put_ids) 2853 CPU_FREE(cpus[i].put_ids); 2854 } 2855 free(cpus); 2856 } 2857 2858 /* 2859 * Parse a file containing a single int. 2860 * Return 0 if file can not be opened 2861 * Exit if file can be opened, but can not be parsed 2862 */ 2863 int parse_int_file(const char *fmt, ...) 2864 { 2865 va_list args; 2866 char path[PATH_MAX]; 2867 FILE *filep; 2868 int value; 2869 2870 va_start(args, fmt); 2871 vsnprintf(path, sizeof(path), fmt, args); 2872 va_end(args); 2873 filep = fopen(path, "r"); 2874 if (!filep) 2875 return 0; 2876 if (fscanf(filep, "%d", &value) != 1) 2877 err(1, "%s: failed to parse number from file", path); 2878 fclose(filep); 2879 return value; 2880 } 2881 2882 /* 2883 * cpu_is_first_core_in_package(cpu) 2884 * return 1 if given CPU is 1st core in package 2885 */ 2886 int cpu_is_first_core_in_package(int cpu) 2887 { 2888 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2889 } 2890 2891 int get_physical_package_id(int cpu) 2892 { 2893 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2894 } 2895 2896 int get_die_id(int cpu) 2897 { 2898 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu); 2899 } 2900 2901 int get_core_id(int cpu) 2902 { 2903 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2904 } 2905 2906 void set_node_data(void) 2907 { 2908 int pkg, node, lnode, cpu, cpux; 2909 int cpu_count; 2910 2911 /* initialize logical_node_id */ 2912 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) 2913 cpus[cpu].logical_node_id = -1; 2914 2915 cpu_count = 0; 2916 for (pkg = 0; pkg < topo.num_packages; pkg++) { 2917 lnode = 0; 2918 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) { 2919 if (cpus[cpu].physical_package_id != pkg) 2920 continue; 2921 /* find a cpu with an unset logical_node_id */ 2922 if (cpus[cpu].logical_node_id != -1) 2923 continue; 2924 cpus[cpu].logical_node_id = lnode; 2925 node = cpus[cpu].physical_node_id; 2926 cpu_count++; 2927 /* 2928 * find all matching cpus on this pkg and set 2929 * the logical_node_id 2930 */ 2931 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) { 2932 if ((cpus[cpux].physical_package_id == pkg) && (cpus[cpux].physical_node_id == node)) { 2933 cpus[cpux].logical_node_id = lnode; 2934 cpu_count++; 2935 } 2936 } 2937 lnode++; 2938 if (lnode > topo.nodes_per_pkg) 2939 topo.nodes_per_pkg = lnode; 2940 } 2941 if (cpu_count >= topo.max_cpu_num) 2942 break; 2943 } 2944 } 2945 2946 int get_physical_node_id(struct cpu_topology *thiscpu) 2947 { 2948 char path[80]; 2949 FILE *filep; 2950 int i; 2951 int cpu = thiscpu->logical_cpu_id; 2952 2953 for (i = 0; i <= topo.max_cpu_num; i++) { 2954 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", cpu, i); 2955 filep = fopen(path, "r"); 2956 if (!filep) 2957 continue; 2958 fclose(filep); 2959 return i; 2960 } 2961 return -1; 2962 } 2963 2964 int get_thread_siblings(struct cpu_topology *thiscpu) 2965 { 2966 char path[80], character; 2967 FILE *filep; 2968 unsigned long map; 2969 int so, shift, sib_core; 2970 int cpu = thiscpu->logical_cpu_id; 2971 int offset = topo.max_cpu_num + 1; 2972 size_t size; 2973 int thread_id = 0; 2974 2975 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 2976 if (thiscpu->thread_id < 0) 2977 thiscpu->thread_id = thread_id++; 2978 if (!thiscpu->put_ids) 2979 return -1; 2980 2981 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 2982 CPU_ZERO_S(size, thiscpu->put_ids); 2983 2984 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 2985 filep = fopen(path, "r"); 2986 2987 if (!filep) { 2988 warnx("%s: open failed", path); 2989 return -1; 2990 } 2991 do { 2992 offset -= BITMASK_SIZE; 2993 if (fscanf(filep, "%lx%c", &map, &character) != 2) 2994 err(1, "%s: failed to parse file", path); 2995 for (shift = 0; shift < BITMASK_SIZE; shift++) { 2996 if ((map >> shift) & 0x1) { 2997 so = shift + offset; 2998 sib_core = get_core_id(so); 2999 if (sib_core == thiscpu->physical_core_id) { 3000 CPU_SET_S(so, size, thiscpu->put_ids); 3001 if ((so != cpu) && (cpus[so].thread_id < 0)) 3002 cpus[so].thread_id = thread_id++; 3003 } 3004 } 3005 } 3006 } while (character == ','); 3007 fclose(filep); 3008 3009 return CPU_COUNT_S(size, thiscpu->put_ids); 3010 } 3011 3012 /* 3013 * run func(thread, core, package) in topology order 3014 * skip non-present cpus 3015 */ 3016 3017 int for_all_cpus_2(int (func) (struct thread_data *, struct core_data *, 3018 struct pkg_data *, struct thread_data *, struct core_data *, 3019 struct pkg_data *), struct thread_data *thread_base, 3020 struct core_data *core_base, struct pkg_data *pkg_base, 3021 struct thread_data *thread_base2, struct core_data *core_base2, struct pkg_data *pkg_base2) 3022 { 3023 int retval, pkg_no, node_no, core_no, thread_no; 3024 3025 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 3026 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 3027 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 3028 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) { 3029 struct thread_data *t, *t2; 3030 struct core_data *c, *c2; 3031 struct pkg_data *p, *p2; 3032 3033 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no); 3034 3035 if (cpu_is_not_present(t->cpu_id)) 3036 continue; 3037 3038 t2 = GET_THREAD(thread_base2, thread_no, core_no, node_no, pkg_no); 3039 3040 c = GET_CORE(core_base, core_no, node_no, pkg_no); 3041 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no); 3042 3043 p = GET_PKG(pkg_base, pkg_no); 3044 p2 = GET_PKG(pkg_base2, pkg_no); 3045 3046 retval = func(t, c, p, t2, c2, p2); 3047 if (retval) 3048 return retval; 3049 } 3050 } 3051 } 3052 } 3053 return 0; 3054 } 3055 3056 /* 3057 * run func(cpu) on every cpu in /proc/stat 3058 * return max_cpu number 3059 */ 3060 int for_all_proc_cpus(int (func) (int)) 3061 { 3062 FILE *fp; 3063 int cpu_num; 3064 int retval; 3065 3066 fp = fopen_or_die(proc_stat, "r"); 3067 3068 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 3069 if (retval != 0) 3070 err(1, "%s: failed to parse format", proc_stat); 3071 3072 while (1) { 3073 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 3074 if (retval != 1) 3075 break; 3076 3077 retval = func(cpu_num); 3078 if (retval) { 3079 fclose(fp); 3080 return (retval); 3081 } 3082 } 3083 fclose(fp); 3084 return 0; 3085 } 3086 3087 void re_initialize(void) 3088 { 3089 free_all_buffers(); 3090 setup_all_buffers(); 3091 fprintf(outf, "turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 3092 } 3093 3094 void set_max_cpu_num(void) 3095 { 3096 FILE *filep; 3097 int base_cpu; 3098 unsigned long dummy; 3099 char pathname[64]; 3100 3101 base_cpu = sched_getcpu(); 3102 if (base_cpu < 0) 3103 err(1, "cannot find calling cpu ID"); 3104 sprintf(pathname, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", base_cpu); 3105 3106 filep = fopen_or_die(pathname, "r"); 3107 topo.max_cpu_num = 0; 3108 while (fscanf(filep, "%lx,", &dummy) == 1) 3109 topo.max_cpu_num += BITMASK_SIZE; 3110 fclose(filep); 3111 topo.max_cpu_num--; /* 0 based */ 3112 } 3113 3114 /* 3115 * count_cpus() 3116 * remember the last one seen, it will be the max 3117 */ 3118 int count_cpus(int cpu) 3119 { 3120 UNUSED(cpu); 3121 3122 topo.num_cpus++; 3123 return 0; 3124 } 3125 3126 int mark_cpu_present(int cpu) 3127 { 3128 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 3129 return 0; 3130 } 3131 3132 int init_thread_id(int cpu) 3133 { 3134 cpus[cpu].thread_id = -1; 3135 return 0; 3136 } 3137 3138 /* 3139 * snapshot_proc_interrupts() 3140 * 3141 * read and record summary of /proc/interrupts 3142 * 3143 * return 1 if config change requires a restart, else return 0 3144 */ 3145 int snapshot_proc_interrupts(void) 3146 { 3147 static FILE *fp; 3148 int column, retval; 3149 3150 if (fp == NULL) 3151 fp = fopen_or_die("/proc/interrupts", "r"); 3152 else 3153 rewind(fp); 3154 3155 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 3156 for (column = 0; column < topo.num_cpus; ++column) { 3157 int cpu_number; 3158 3159 retval = fscanf(fp, " CPU%d", &cpu_number); 3160 if (retval != 1) 3161 break; 3162 3163 if (cpu_number > topo.max_cpu_num) { 3164 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 3165 return 1; 3166 } 3167 3168 irq_column_2_cpu[column] = cpu_number; 3169 irqs_per_cpu[cpu_number] = 0; 3170 } 3171 3172 /* read /proc/interrupt count lines and sum up irqs per cpu */ 3173 while (1) { 3174 int column; 3175 char buf[64]; 3176 3177 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 3178 if (retval != 1) 3179 break; 3180 3181 /* read the count per cpu */ 3182 for (column = 0; column < topo.num_cpus; ++column) { 3183 3184 int cpu_number, irq_count; 3185 3186 retval = fscanf(fp, " %d", &irq_count); 3187 if (retval != 1) 3188 break; 3189 3190 cpu_number = irq_column_2_cpu[column]; 3191 irqs_per_cpu[cpu_number] += irq_count; 3192 3193 } 3194 3195 while (getc(fp) != '\n') ; /* flush interrupt description */ 3196 3197 } 3198 return 0; 3199 } 3200 3201 /* 3202 * snapshot_gfx_rc6_ms() 3203 * 3204 * record snapshot of 3205 * /sys/class/drm/card0/power/rc6_residency_ms 3206 * 3207 * return 1 if config change requires a restart, else return 0 3208 */ 3209 int snapshot_gfx_rc6_ms(void) 3210 { 3211 FILE *fp; 3212 int retval; 3213 3214 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 3215 3216 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 3217 if (retval != 1) 3218 err(1, "GFX rc6"); 3219 3220 fclose(fp); 3221 3222 return 0; 3223 } 3224 3225 /* 3226 * snapshot_gfx_mhz() 3227 * 3228 * record snapshot of 3229 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 3230 * 3231 * return 1 if config change requires a restart, else return 0 3232 */ 3233 int snapshot_gfx_mhz(void) 3234 { 3235 static FILE *fp; 3236 int retval; 3237 3238 if (fp == NULL) 3239 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 3240 else { 3241 rewind(fp); 3242 fflush(fp); 3243 } 3244 3245 retval = fscanf(fp, "%d", &gfx_cur_mhz); 3246 if (retval != 1) 3247 err(1, "GFX MHz"); 3248 3249 return 0; 3250 } 3251 3252 /* 3253 * snapshot_gfx_cur_mhz() 3254 * 3255 * record snapshot of 3256 * /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz 3257 * 3258 * return 1 if config change requires a restart, else return 0 3259 */ 3260 int snapshot_gfx_act_mhz(void) 3261 { 3262 static FILE *fp; 3263 int retval; 3264 3265 if (fp == NULL) 3266 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r"); 3267 else { 3268 rewind(fp); 3269 fflush(fp); 3270 } 3271 3272 retval = fscanf(fp, "%d", &gfx_act_mhz); 3273 if (retval != 1) 3274 err(1, "GFX ACT MHz"); 3275 3276 return 0; 3277 } 3278 3279 /* 3280 * snapshot_cpu_lpi() 3281 * 3282 * record snapshot of 3283 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 3284 */ 3285 int snapshot_cpu_lpi_us(void) 3286 { 3287 FILE *fp; 3288 int retval; 3289 3290 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 3291 3292 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 3293 if (retval != 1) { 3294 fprintf(stderr, "Disabling Low Power Idle CPU output\n"); 3295 BIC_NOT_PRESENT(BIC_CPU_LPI); 3296 fclose(fp); 3297 return -1; 3298 } 3299 3300 fclose(fp); 3301 3302 return 0; 3303 } 3304 3305 /* 3306 * snapshot_sys_lpi() 3307 * 3308 * record snapshot of sys_lpi_file 3309 */ 3310 int snapshot_sys_lpi_us(void) 3311 { 3312 FILE *fp; 3313 int retval; 3314 3315 fp = fopen_or_die(sys_lpi_file, "r"); 3316 3317 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 3318 if (retval != 1) { 3319 fprintf(stderr, "Disabling Low Power Idle System output\n"); 3320 BIC_NOT_PRESENT(BIC_SYS_LPI); 3321 fclose(fp); 3322 return -1; 3323 } 3324 fclose(fp); 3325 3326 return 0; 3327 } 3328 3329 /* 3330 * snapshot /proc and /sys files 3331 * 3332 * return 1 if configuration restart needed, else return 0 3333 */ 3334 int snapshot_proc_sysfs_files(void) 3335 { 3336 if (DO_BIC(BIC_IRQ)) 3337 if (snapshot_proc_interrupts()) 3338 return 1; 3339 3340 if (DO_BIC(BIC_GFX_rc6)) 3341 snapshot_gfx_rc6_ms(); 3342 3343 if (DO_BIC(BIC_GFXMHz)) 3344 snapshot_gfx_mhz(); 3345 3346 if (DO_BIC(BIC_GFXACTMHz)) 3347 snapshot_gfx_act_mhz(); 3348 3349 if (DO_BIC(BIC_CPU_LPI)) 3350 snapshot_cpu_lpi_us(); 3351 3352 if (DO_BIC(BIC_SYS_LPI)) 3353 snapshot_sys_lpi_us(); 3354 3355 return 0; 3356 } 3357 3358 int exit_requested; 3359 3360 static void signal_handler(int signal) 3361 { 3362 switch (signal) { 3363 case SIGINT: 3364 exit_requested = 1; 3365 if (debug) 3366 fprintf(stderr, " SIGINT\n"); 3367 break; 3368 case SIGUSR1: 3369 if (debug > 1) 3370 fprintf(stderr, "SIGUSR1\n"); 3371 break; 3372 } 3373 } 3374 3375 void setup_signal_handler(void) 3376 { 3377 struct sigaction sa; 3378 3379 memset(&sa, 0, sizeof(sa)); 3380 3381 sa.sa_handler = &signal_handler; 3382 3383 if (sigaction(SIGINT, &sa, NULL) < 0) 3384 err(1, "sigaction SIGINT"); 3385 if (sigaction(SIGUSR1, &sa, NULL) < 0) 3386 err(1, "sigaction SIGUSR1"); 3387 } 3388 3389 void do_sleep(void) 3390 { 3391 struct timeval tout; 3392 struct timespec rest; 3393 fd_set readfds; 3394 int retval; 3395 3396 FD_ZERO(&readfds); 3397 FD_SET(0, &readfds); 3398 3399 if (ignore_stdin) { 3400 nanosleep(&interval_ts, NULL); 3401 return; 3402 } 3403 3404 tout = interval_tv; 3405 retval = select(1, &readfds, NULL, NULL, &tout); 3406 3407 if (retval == 1) { 3408 switch (getc(stdin)) { 3409 case 'q': 3410 exit_requested = 1; 3411 break; 3412 case EOF: 3413 /* 3414 * 'stdin' is a pipe closed on the other end. There 3415 * won't be any further input. 3416 */ 3417 ignore_stdin = 1; 3418 /* Sleep the rest of the time */ 3419 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000); 3420 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000; 3421 nanosleep(&rest, NULL); 3422 } 3423 } 3424 } 3425 3426 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr) 3427 { 3428 int ret, idx; 3429 unsigned long long msr_cur, msr_last; 3430 3431 if (!per_cpu_msr_sum) 3432 return 1; 3433 3434 idx = offset_to_idx(offset); 3435 if (idx < 0) 3436 return idx; 3437 /* get_msr_sum() = sum + (get_msr() - last) */ 3438 ret = get_msr(cpu, offset, &msr_cur); 3439 if (ret) 3440 return ret; 3441 msr_last = per_cpu_msr_sum[cpu].entries[idx].last; 3442 DELTA_WRAP32(msr_cur, msr_last); 3443 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum; 3444 3445 return 0; 3446 } 3447 3448 timer_t timerid; 3449 3450 /* Timer callback, update the sum of MSRs periodically. */ 3451 static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3452 { 3453 int i, ret; 3454 int cpu = t->cpu_id; 3455 3456 UNUSED(c); 3457 UNUSED(p); 3458 3459 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) { 3460 unsigned long long msr_cur, msr_last; 3461 off_t offset; 3462 3463 if (!idx_valid(i)) 3464 continue; 3465 offset = idx_to_offset(i); 3466 if (offset < 0) 3467 continue; 3468 ret = get_msr(cpu, offset, &msr_cur); 3469 if (ret) { 3470 fprintf(outf, "Can not update msr(0x%llx)\n", (unsigned long long)offset); 3471 continue; 3472 } 3473 3474 msr_last = per_cpu_msr_sum[cpu].entries[i].last; 3475 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff; 3476 3477 DELTA_WRAP32(msr_cur, msr_last); 3478 per_cpu_msr_sum[cpu].entries[i].sum += msr_last; 3479 } 3480 return 0; 3481 } 3482 3483 static void msr_record_handler(union sigval v) 3484 { 3485 UNUSED(v); 3486 3487 for_all_cpus(update_msr_sum, EVEN_COUNTERS); 3488 } 3489 3490 void msr_sum_record(void) 3491 { 3492 struct itimerspec its; 3493 struct sigevent sev; 3494 3495 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array)); 3496 if (!per_cpu_msr_sum) { 3497 fprintf(outf, "Can not allocate memory for long time MSR.\n"); 3498 return; 3499 } 3500 /* 3501 * Signal handler might be restricted, so use thread notifier instead. 3502 */ 3503 memset(&sev, 0, sizeof(struct sigevent)); 3504 sev.sigev_notify = SIGEV_THREAD; 3505 sev.sigev_notify_function = msr_record_handler; 3506 3507 sev.sigev_value.sival_ptr = &timerid; 3508 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) { 3509 fprintf(outf, "Can not create timer.\n"); 3510 goto release_msr; 3511 } 3512 3513 its.it_value.tv_sec = 0; 3514 its.it_value.tv_nsec = 1; 3515 /* 3516 * A wraparound time has been calculated early. 3517 * Some sources state that the peak power for a 3518 * microprocessor is usually 1.5 times the TDP rating, 3519 * use 2 * TDP for safety. 3520 */ 3521 its.it_interval.tv_sec = rapl_joule_counter_range / 2; 3522 its.it_interval.tv_nsec = 0; 3523 3524 if (timer_settime(timerid, 0, &its, NULL) == -1) { 3525 fprintf(outf, "Can not set timer.\n"); 3526 goto release_timer; 3527 } 3528 return; 3529 3530 release_timer: 3531 timer_delete(timerid); 3532 release_msr: 3533 free(per_cpu_msr_sum); 3534 } 3535 3536 /* 3537 * set_my_sched_priority(pri) 3538 * return previous 3539 * 3540 * if non-root, do this: 3541 * # /sbin/setcap cap_sys_rawio,cap_sys_nice=+ep /usr/bin/turbostat 3542 */ 3543 int set_my_sched_priority(int priority) 3544 { 3545 int retval; 3546 int original_priority; 3547 3548 errno = 0; 3549 original_priority = getpriority(PRIO_PROCESS, 0); 3550 if (errno && (original_priority == -1)) 3551 err(errno, "getpriority"); 3552 3553 retval = setpriority(PRIO_PROCESS, 0, priority); 3554 if (retval) 3555 err(retval, "setpriority(%d)", priority); 3556 3557 errno = 0; 3558 retval = getpriority(PRIO_PROCESS, 0); 3559 if (retval != priority) 3560 err(retval, "getpriority(%d) != setpriority(%d)", retval, priority); 3561 3562 return original_priority; 3563 } 3564 3565 void turbostat_loop() 3566 { 3567 int retval; 3568 int restarted = 0; 3569 unsigned int done_iters = 0; 3570 3571 setup_signal_handler(); 3572 3573 /* 3574 * elevate own priority for interval mode 3575 */ 3576 set_my_sched_priority(-20); 3577 3578 restart: 3579 restarted++; 3580 3581 snapshot_proc_sysfs_files(); 3582 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3583 first_counter_read = 0; 3584 if (retval < -1) { 3585 exit(retval); 3586 } else if (retval == -1) { 3587 if (restarted > 10) { 3588 exit(retval); 3589 } 3590 re_initialize(); 3591 goto restart; 3592 } 3593 restarted = 0; 3594 done_iters = 0; 3595 gettimeofday(&tv_even, (struct timezone *)NULL); 3596 3597 while (1) { 3598 if (for_all_proc_cpus(cpu_is_not_present)) { 3599 re_initialize(); 3600 goto restart; 3601 } 3602 do_sleep(); 3603 if (snapshot_proc_sysfs_files()) 3604 goto restart; 3605 retval = for_all_cpus(get_counters, ODD_COUNTERS); 3606 if (retval < -1) { 3607 exit(retval); 3608 } else if (retval == -1) { 3609 re_initialize(); 3610 goto restart; 3611 } 3612 gettimeofday(&tv_odd, (struct timezone *)NULL); 3613 timersub(&tv_odd, &tv_even, &tv_delta); 3614 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 3615 re_initialize(); 3616 goto restart; 3617 } 3618 compute_average(EVEN_COUNTERS); 3619 format_all_counters(EVEN_COUNTERS); 3620 flush_output_stdout(); 3621 if (exit_requested) 3622 break; 3623 if (num_iterations && ++done_iters >= num_iterations) 3624 break; 3625 do_sleep(); 3626 if (snapshot_proc_sysfs_files()) 3627 goto restart; 3628 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3629 if (retval < -1) { 3630 exit(retval); 3631 } else if (retval == -1) { 3632 re_initialize(); 3633 goto restart; 3634 } 3635 gettimeofday(&tv_even, (struct timezone *)NULL); 3636 timersub(&tv_even, &tv_odd, &tv_delta); 3637 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 3638 re_initialize(); 3639 goto restart; 3640 } 3641 compute_average(ODD_COUNTERS); 3642 format_all_counters(ODD_COUNTERS); 3643 flush_output_stdout(); 3644 if (exit_requested) 3645 break; 3646 if (num_iterations && ++done_iters >= num_iterations) 3647 break; 3648 } 3649 } 3650 3651 void check_dev_msr() 3652 { 3653 struct stat sb; 3654 char pathname[32]; 3655 3656 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3657 if (stat(pathname, &sb)) 3658 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 3659 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 3660 } 3661 3662 /* 3663 * check for CAP_SYS_RAWIO 3664 * return 0 on success 3665 * return 1 on fail 3666 */ 3667 int check_for_cap_sys_rawio(void) 3668 { 3669 cap_t caps; 3670 cap_flag_value_t cap_flag_value; 3671 3672 caps = cap_get_proc(); 3673 if (caps == NULL) 3674 err(-6, "cap_get_proc\n"); 3675 3676 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value)) 3677 err(-6, "cap_get\n"); 3678 3679 if (cap_flag_value != CAP_SET) { 3680 warnx("capget(CAP_SYS_RAWIO) failed," " try \"# setcap cap_sys_rawio=ep %s\"", progname); 3681 return 1; 3682 } 3683 3684 if (cap_free(caps) == -1) 3685 err(-6, "cap_free\n"); 3686 3687 return 0; 3688 } 3689 3690 void check_permissions(void) 3691 { 3692 int do_exit = 0; 3693 char pathname[32]; 3694 3695 /* check for CAP_SYS_RAWIO */ 3696 do_exit += check_for_cap_sys_rawio(); 3697 3698 /* test file permissions */ 3699 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3700 if (euidaccess(pathname, R_OK)) { 3701 do_exit++; 3702 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 3703 } 3704 3705 /* if all else fails, thell them to be root */ 3706 if (do_exit) 3707 if (getuid() != 0) 3708 warnx("... or simply run as root"); 3709 3710 if (do_exit) 3711 exit(-6); 3712 } 3713 3714 /* 3715 * NHM adds support for additional MSRs: 3716 * 3717 * MSR_SMI_COUNT 0x00000034 3718 * 3719 * MSR_PLATFORM_INFO 0x000000ce 3720 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 3721 * 3722 * MSR_MISC_PWR_MGMT 0x000001aa 3723 * 3724 * MSR_PKG_C3_RESIDENCY 0x000003f8 3725 * MSR_PKG_C6_RESIDENCY 0x000003f9 3726 * MSR_CORE_C3_RESIDENCY 0x000003fc 3727 * MSR_CORE_C6_RESIDENCY 0x000003fd 3728 * 3729 * Side effect: 3730 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 3731 * sets has_misc_feature_control 3732 */ 3733 int probe_nhm_msrs(unsigned int family, unsigned int model) 3734 { 3735 unsigned long long msr; 3736 unsigned int base_ratio; 3737 int *pkg_cstate_limits; 3738 3739 if (!genuine_intel) 3740 return 0; 3741 3742 if (family != 6) 3743 return 0; 3744 3745 bclk = discover_bclk(family, model); 3746 3747 switch (model) { 3748 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 3749 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3750 pkg_cstate_limits = nhm_pkg_cstate_limits; 3751 break; 3752 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 3753 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 3754 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3755 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3756 pkg_cstate_limits = snb_pkg_cstate_limits; 3757 has_misc_feature_control = 1; 3758 break; 3759 case INTEL_FAM6_HASWELL: /* HSW */ 3760 case INTEL_FAM6_HASWELL_G: /* HSW */ 3761 case INTEL_FAM6_HASWELL_X: /* HSX */ 3762 case INTEL_FAM6_HASWELL_L: /* HSW */ 3763 case INTEL_FAM6_BROADWELL: /* BDW */ 3764 case INTEL_FAM6_BROADWELL_G: /* BDW */ 3765 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3766 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 3767 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 3768 pkg_cstate_limits = hsw_pkg_cstate_limits; 3769 has_misc_feature_control = 1; 3770 break; 3771 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3772 pkg_cstate_limits = skx_pkg_cstate_limits; 3773 has_misc_feature_control = 1; 3774 break; 3775 case INTEL_FAM6_ICELAKE_X: /* ICX */ 3776 pkg_cstate_limits = icx_pkg_cstate_limits; 3777 has_misc_feature_control = 1; 3778 break; 3779 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3780 no_MSR_MISC_PWR_MGMT = 1; 3781 /* FALLTHRU */ 3782 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 3783 pkg_cstate_limits = slv_pkg_cstate_limits; 3784 break; 3785 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 3786 pkg_cstate_limits = amt_pkg_cstate_limits; 3787 no_MSR_MISC_PWR_MGMT = 1; 3788 break; 3789 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 3790 pkg_cstate_limits = phi_pkg_cstate_limits; 3791 break; 3792 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3793 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3794 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 3795 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 3796 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 3797 pkg_cstate_limits = glm_pkg_cstate_limits; 3798 break; 3799 default: 3800 return 0; 3801 } 3802 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3803 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3804 3805 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3806 base_ratio = (msr >> 8) & 0xFF; 3807 3808 base_hz = base_ratio * bclk * 1000000; 3809 has_base_hz = 1; 3810 return 1; 3811 } 3812 3813 /* 3814 * SLV client has support for unique MSRs: 3815 * 3816 * MSR_CC6_DEMOTION_POLICY_CONFIG 3817 * MSR_MC6_DEMOTION_POLICY_CONFIG 3818 */ 3819 3820 int has_slv_msrs(unsigned int family, unsigned int model) 3821 { 3822 if (!genuine_intel) 3823 return 0; 3824 3825 if (family != 6) 3826 return 0; 3827 3828 switch (model) { 3829 case INTEL_FAM6_ATOM_SILVERMONT: 3830 case INTEL_FAM6_ATOM_SILVERMONT_MID: 3831 case INTEL_FAM6_ATOM_AIRMONT_MID: 3832 return 1; 3833 } 3834 return 0; 3835 } 3836 3837 int is_dnv(unsigned int family, unsigned int model) 3838 { 3839 3840 if (!genuine_intel) 3841 return 0; 3842 3843 if (family != 6) 3844 return 0; 3845 3846 switch (model) { 3847 case INTEL_FAM6_ATOM_GOLDMONT_D: 3848 return 1; 3849 } 3850 return 0; 3851 } 3852 3853 int is_bdx(unsigned int family, unsigned int model) 3854 { 3855 3856 if (!genuine_intel) 3857 return 0; 3858 3859 if (family != 6) 3860 return 0; 3861 3862 switch (model) { 3863 case INTEL_FAM6_BROADWELL_X: 3864 return 1; 3865 } 3866 return 0; 3867 } 3868 3869 int is_skx(unsigned int family, unsigned int model) 3870 { 3871 3872 if (!genuine_intel) 3873 return 0; 3874 3875 if (family != 6) 3876 return 0; 3877 3878 switch (model) { 3879 case INTEL_FAM6_SKYLAKE_X: 3880 return 1; 3881 } 3882 return 0; 3883 } 3884 3885 int is_icx(unsigned int family, unsigned int model) 3886 { 3887 3888 if (!genuine_intel) 3889 return 0; 3890 3891 if (family != 6) 3892 return 0; 3893 3894 switch (model) { 3895 case INTEL_FAM6_ICELAKE_X: 3896 return 1; 3897 } 3898 return 0; 3899 } 3900 3901 int is_ehl(unsigned int family, unsigned int model) 3902 { 3903 if (!genuine_intel) 3904 return 0; 3905 3906 if (family != 6) 3907 return 0; 3908 3909 switch (model) { 3910 case INTEL_FAM6_ATOM_TREMONT: 3911 return 1; 3912 } 3913 return 0; 3914 } 3915 3916 int is_jvl(unsigned int family, unsigned int model) 3917 { 3918 if (!genuine_intel) 3919 return 0; 3920 3921 if (family != 6) 3922 return 0; 3923 3924 switch (model) { 3925 case INTEL_FAM6_ATOM_TREMONT_D: 3926 return 1; 3927 } 3928 return 0; 3929 } 3930 3931 int has_turbo_ratio_limit(unsigned int family, unsigned int model) 3932 { 3933 if (has_slv_msrs(family, model)) 3934 return 0; 3935 3936 if (family != 6) 3937 return 0; 3938 3939 switch (model) { 3940 /* Nehalem compatible, but do not include turbo-ratio limit support */ 3941 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3942 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 3943 return 0; 3944 default: 3945 return 1; 3946 } 3947 } 3948 3949 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 3950 { 3951 if (has_slv_msrs(family, model)) 3952 return 1; 3953 3954 return 0; 3955 } 3956 3957 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 3958 { 3959 if (!genuine_intel) 3960 return 0; 3961 3962 if (family != 6) 3963 return 0; 3964 3965 switch (model) { 3966 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3967 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3968 return 1; 3969 default: 3970 return 0; 3971 } 3972 } 3973 3974 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 3975 { 3976 if (!genuine_intel) 3977 return 0; 3978 3979 if (family != 6) 3980 return 0; 3981 3982 switch (model) { 3983 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3984 return 1; 3985 default: 3986 return 0; 3987 } 3988 } 3989 3990 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 3991 { 3992 if (!genuine_intel) 3993 return 0; 3994 3995 if (family != 6) 3996 return 0; 3997 3998 switch (model) { 3999 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 4000 return 1; 4001 default: 4002 return 0; 4003 } 4004 } 4005 4006 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) 4007 { 4008 if (!genuine_intel) 4009 return 0; 4010 4011 if (family != 6) 4012 return 0; 4013 4014 switch (model) { 4015 case INTEL_FAM6_ATOM_GOLDMONT: 4016 case INTEL_FAM6_SKYLAKE_X: 4017 case INTEL_FAM6_ICELAKE_X: 4018 return 1; 4019 default: 4020 return 0; 4021 } 4022 } 4023 4024 int has_config_tdp(unsigned int family, unsigned int model) 4025 { 4026 if (!genuine_intel) 4027 return 0; 4028 4029 if (family != 6) 4030 return 0; 4031 4032 switch (model) { 4033 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 4034 case INTEL_FAM6_HASWELL: /* HSW */ 4035 case INTEL_FAM6_HASWELL_X: /* HSX */ 4036 case INTEL_FAM6_HASWELL_L: /* HSW */ 4037 case INTEL_FAM6_HASWELL_G: /* HSW */ 4038 case INTEL_FAM6_BROADWELL: /* BDW */ 4039 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4040 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4041 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4042 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4043 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4044 case INTEL_FAM6_ICELAKE_X: /* ICX */ 4045 4046 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 4047 return 1; 4048 default: 4049 return 0; 4050 } 4051 } 4052 4053 /* 4054 * tcc_offset_bits: 4055 * 0: Tcc Offset not supported (Default) 4056 * 6: Bit 29:24 of MSR_PLATFORM_INFO 4057 * 4: Bit 27:24 of MSR_PLATFORM_INFO 4058 */ 4059 void check_tcc_offset(int model) 4060 { 4061 unsigned long long msr; 4062 4063 if (!genuine_intel) 4064 return; 4065 4066 switch (model) { 4067 case INTEL_FAM6_SKYLAKE_L: 4068 case INTEL_FAM6_SKYLAKE: 4069 case INTEL_FAM6_KABYLAKE_L: 4070 case INTEL_FAM6_KABYLAKE: 4071 case INTEL_FAM6_ICELAKE_L: 4072 case INTEL_FAM6_ICELAKE: 4073 case INTEL_FAM6_TIGERLAKE_L: 4074 case INTEL_FAM6_TIGERLAKE: 4075 case INTEL_FAM6_COMETLAKE: 4076 if (!get_msr(base_cpu, MSR_PLATFORM_INFO, &msr)) { 4077 msr = (msr >> 30) & 1; 4078 if (msr) 4079 tcc_offset_bits = 6; 4080 } 4081 return; 4082 default: 4083 return; 4084 } 4085 } 4086 4087 static void remove_underbar(char *s) 4088 { 4089 char *to = s; 4090 4091 while (*s) { 4092 if (*s != '_') 4093 *to++ = *s; 4094 s++; 4095 } 4096 4097 *to = 0; 4098 } 4099 4100 static void dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 4101 { 4102 if (!do_nhm_platform_info) 4103 return; 4104 4105 dump_nhm_platform_info(); 4106 4107 if (has_hsw_turbo_ratio_limit(family, model)) 4108 dump_hsw_turbo_ratio_limits(); 4109 4110 if (has_ivt_turbo_ratio_limit(family, model)) 4111 dump_ivt_turbo_ratio_limits(); 4112 4113 if (has_turbo_ratio_limit(family, model)) 4114 dump_turbo_ratio_limits(family, model); 4115 4116 if (has_atom_turbo_ratio_limit(family, model)) 4117 dump_atom_turbo_ratio_limits(); 4118 4119 if (has_knl_turbo_ratio_limit(family, model)) 4120 dump_knl_turbo_ratio_limits(); 4121 4122 if (has_config_tdp(family, model)) 4123 dump_config_tdp(); 4124 4125 dump_nhm_cst_cfg(); 4126 } 4127 4128 static int read_sysfs_int(char *path) 4129 { 4130 FILE *input; 4131 int retval = -1; 4132 4133 input = fopen(path, "r"); 4134 if (input == NULL) { 4135 if (debug) 4136 fprintf(outf, "NSFOD %s\n", path); 4137 return (-1); 4138 } 4139 if (fscanf(input, "%d", &retval) != 1) 4140 err(1, "%s: failed to read int from file", path); 4141 fclose(input); 4142 4143 return (retval); 4144 } 4145 4146 static void dump_sysfs_file(char *path) 4147 { 4148 FILE *input; 4149 char cpuidle_buf[64]; 4150 4151 input = fopen(path, "r"); 4152 if (input == NULL) { 4153 if (debug) 4154 fprintf(outf, "NSFOD %s\n", path); 4155 return; 4156 } 4157 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input)) 4158 err(1, "%s: failed to read file", path); 4159 fclose(input); 4160 4161 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf); 4162 } 4163 4164 static void intel_uncore_frequency_probe(void) 4165 { 4166 int i, j; 4167 char path[128]; 4168 4169 if (!genuine_intel) 4170 return; 4171 4172 if (access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00", R_OK)) 4173 return; 4174 4175 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/current_freq_khz", R_OK)) 4176 BIC_PRESENT(BIC_UNCORE_MHZ); 4177 4178 if (quiet) 4179 return; 4180 4181 for (i = 0; i < topo.num_packages; ++i) { 4182 for (j = 0; j < topo.num_die; ++j) { 4183 int k, l; 4184 4185 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/min_freq_khz", 4186 i, j); 4187 k = read_sysfs_int(path); 4188 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/max_freq_khz", 4189 i, j); 4190 l = read_sysfs_int(path); 4191 fprintf(outf, "Uncore Frequency pkg%d die%d: %d - %d MHz ", i, j, k / 1000, l / 1000); 4192 4193 sprintf(path, 4194 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_min_freq_khz", 4195 i, j); 4196 k = read_sysfs_int(path); 4197 sprintf(path, 4198 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_max_freq_khz", 4199 i, j); 4200 l = read_sysfs_int(path); 4201 fprintf(outf, "(%d - %d MHz)\n", k / 1000, l / 1000); 4202 } 4203 } 4204 } 4205 4206 static void dump_sysfs_cstate_config(void) 4207 { 4208 char path[64]; 4209 char name_buf[16]; 4210 char desc[64]; 4211 FILE *input; 4212 int state; 4213 char *sp; 4214 4215 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) { 4216 fprintf(outf, "cpuidle not loaded\n"); 4217 return; 4218 } 4219 4220 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver"); 4221 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor"); 4222 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro"); 4223 4224 for (state = 0; state < 10; ++state) { 4225 4226 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 4227 input = fopen(path, "r"); 4228 if (input == NULL) 4229 continue; 4230 if (!fgets(name_buf, sizeof(name_buf), input)) 4231 err(1, "%s: failed to read file", path); 4232 4233 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 4234 sp = strchr(name_buf, '-'); 4235 if (!sp) 4236 sp = strchrnul(name_buf, '\n'); 4237 *sp = '\0'; 4238 fclose(input); 4239 4240 remove_underbar(name_buf); 4241 4242 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", base_cpu, state); 4243 input = fopen(path, "r"); 4244 if (input == NULL) 4245 continue; 4246 if (!fgets(desc, sizeof(desc), input)) 4247 err(1, "%s: failed to read file", path); 4248 4249 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 4250 fclose(input); 4251 } 4252 } 4253 4254 static void dump_sysfs_pstate_config(void) 4255 { 4256 char path[64]; 4257 char driver_buf[64]; 4258 char governor_buf[64]; 4259 FILE *input; 4260 int turbo; 4261 4262 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", base_cpu); 4263 input = fopen(path, "r"); 4264 if (input == NULL) { 4265 fprintf(outf, "NSFOD %s\n", path); 4266 return; 4267 } 4268 if (!fgets(driver_buf, sizeof(driver_buf), input)) 4269 err(1, "%s: failed to read file", path); 4270 fclose(input); 4271 4272 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", base_cpu); 4273 input = fopen(path, "r"); 4274 if (input == NULL) { 4275 fprintf(outf, "NSFOD %s\n", path); 4276 return; 4277 } 4278 if (!fgets(governor_buf, sizeof(governor_buf), input)) 4279 err(1, "%s: failed to read file", path); 4280 fclose(input); 4281 4282 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 4283 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 4284 4285 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 4286 input = fopen(path, "r"); 4287 if (input != NULL) { 4288 if (fscanf(input, "%d", &turbo) != 1) 4289 err(1, "%s: failed to parse number from file", path); 4290 fprintf(outf, "cpufreq boost: %d\n", turbo); 4291 fclose(input); 4292 } 4293 4294 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 4295 input = fopen(path, "r"); 4296 if (input != NULL) { 4297 if (fscanf(input, "%d", &turbo) != 1) 4298 err(1, "%s: failed to parse number from file", path); 4299 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 4300 fclose(input); 4301 } 4302 } 4303 4304 /* 4305 * print_epb() 4306 * Decode the ENERGY_PERF_BIAS MSR 4307 */ 4308 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4309 { 4310 char *epb_string; 4311 int cpu, epb; 4312 4313 UNUSED(c); 4314 UNUSED(p); 4315 4316 if (!has_epb) 4317 return 0; 4318 4319 cpu = t->cpu_id; 4320 4321 /* EPB is per-package */ 4322 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4323 return 0; 4324 4325 if (cpu_migrate(cpu)) { 4326 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu); 4327 return -1; 4328 } 4329 4330 epb = get_epb(cpu); 4331 if (epb < 0) 4332 return 0; 4333 4334 switch (epb) { 4335 case ENERGY_PERF_BIAS_PERFORMANCE: 4336 epb_string = "performance"; 4337 break; 4338 case ENERGY_PERF_BIAS_NORMAL: 4339 epb_string = "balanced"; 4340 break; 4341 case ENERGY_PERF_BIAS_POWERSAVE: 4342 epb_string = "powersave"; 4343 break; 4344 default: 4345 epb_string = "custom"; 4346 break; 4347 } 4348 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string); 4349 4350 return 0; 4351 } 4352 4353 /* 4354 * print_hwp() 4355 * Decode the MSR_HWP_CAPABILITIES 4356 */ 4357 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4358 { 4359 unsigned long long msr; 4360 int cpu; 4361 4362 UNUSED(c); 4363 UNUSED(p); 4364 4365 if (!has_hwp) 4366 return 0; 4367 4368 cpu = t->cpu_id; 4369 4370 /* MSR_HWP_CAPABILITIES is per-package */ 4371 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4372 return 0; 4373 4374 if (cpu_migrate(cpu)) { 4375 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu); 4376 return -1; 4377 } 4378 4379 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 4380 return 0; 4381 4382 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 4383 4384 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 4385 if ((msr & (1 << 0)) == 0) 4386 return 0; 4387 4388 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 4389 return 0; 4390 4391 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 4392 "(high %d guar %d eff %d low %d)\n", 4393 cpu, msr, 4394 (unsigned int)HWP_HIGHEST_PERF(msr), 4395 (unsigned int)HWP_GUARANTEED_PERF(msr), 4396 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), (unsigned int)HWP_LOWEST_PERF(msr)); 4397 4398 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 4399 return 0; 4400 4401 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 4402 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 4403 cpu, msr, 4404 (unsigned int)(((msr) >> 0) & 0xff), 4405 (unsigned int)(((msr) >> 8) & 0xff), 4406 (unsigned int)(((msr) >> 16) & 0xff), 4407 (unsigned int)(((msr) >> 24) & 0xff), 4408 (unsigned int)(((msr) >> 32) & 0xff3), (unsigned int)(((msr) >> 42) & 0x1)); 4409 4410 if (has_hwp_pkg) { 4411 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 4412 return 0; 4413 4414 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 4415 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 4416 cpu, msr, 4417 (unsigned int)(((msr) >> 0) & 0xff), 4418 (unsigned int)(((msr) >> 8) & 0xff), 4419 (unsigned int)(((msr) >> 16) & 0xff), 4420 (unsigned int)(((msr) >> 24) & 0xff), (unsigned int)(((msr) >> 32) & 0xff3)); 4421 } 4422 if (has_hwp_notify) { 4423 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 4424 return 0; 4425 4426 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 4427 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 4428 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis"); 4429 } 4430 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 4431 return 0; 4432 4433 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 4434 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 4435 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x2) ? "" : "No-"); 4436 4437 return 0; 4438 } 4439 4440 /* 4441 * print_perf_limit() 4442 */ 4443 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4444 { 4445 unsigned long long msr; 4446 int cpu; 4447 4448 UNUSED(c); 4449 UNUSED(p); 4450 4451 cpu = t->cpu_id; 4452 4453 /* per-package */ 4454 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4455 return 0; 4456 4457 if (cpu_migrate(cpu)) { 4458 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu); 4459 return -1; 4460 } 4461 4462 if (do_core_perf_limit_reasons) { 4463 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 4464 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4465 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 4466 (msr & 1 << 15) ? "bit15, " : "", 4467 (msr & 1 << 14) ? "bit14, " : "", 4468 (msr & 1 << 13) ? "Transitions, " : "", 4469 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 4470 (msr & 1 << 11) ? "PkgPwrL2, " : "", 4471 (msr & 1 << 10) ? "PkgPwrL1, " : "", 4472 (msr & 1 << 9) ? "CorePwr, " : "", 4473 (msr & 1 << 8) ? "Amps, " : "", 4474 (msr & 1 << 6) ? "VR-Therm, " : "", 4475 (msr & 1 << 5) ? "Auto-HWP, " : "", 4476 (msr & 1 << 4) ? "Graphics, " : "", 4477 (msr & 1 << 2) ? "bit2, " : "", 4478 (msr & 1 << 1) ? "ThermStatus, " : "", (msr & 1 << 0) ? "PROCHOT, " : ""); 4479 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 4480 (msr & 1 << 31) ? "bit31, " : "", 4481 (msr & 1 << 30) ? "bit30, " : "", 4482 (msr & 1 << 29) ? "Transitions, " : "", 4483 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 4484 (msr & 1 << 27) ? "PkgPwrL2, " : "", 4485 (msr & 1 << 26) ? "PkgPwrL1, " : "", 4486 (msr & 1 << 25) ? "CorePwr, " : "", 4487 (msr & 1 << 24) ? "Amps, " : "", 4488 (msr & 1 << 22) ? "VR-Therm, " : "", 4489 (msr & 1 << 21) ? "Auto-HWP, " : "", 4490 (msr & 1 << 20) ? "Graphics, " : "", 4491 (msr & 1 << 18) ? "bit18, " : "", 4492 (msr & 1 << 17) ? "ThermStatus, " : "", (msr & 1 << 16) ? "PROCHOT, " : ""); 4493 4494 } 4495 if (do_gfx_perf_limit_reasons) { 4496 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 4497 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4498 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 4499 (msr & 1 << 0) ? "PROCHOT, " : "", 4500 (msr & 1 << 1) ? "ThermStatus, " : "", 4501 (msr & 1 << 4) ? "Graphics, " : "", 4502 (msr & 1 << 6) ? "VR-Therm, " : "", 4503 (msr & 1 << 8) ? "Amps, " : "", 4504 (msr & 1 << 9) ? "GFXPwr, " : "", 4505 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4506 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 4507 (msr & 1 << 16) ? "PROCHOT, " : "", 4508 (msr & 1 << 17) ? "ThermStatus, " : "", 4509 (msr & 1 << 20) ? "Graphics, " : "", 4510 (msr & 1 << 22) ? "VR-Therm, " : "", 4511 (msr & 1 << 24) ? "Amps, " : "", 4512 (msr & 1 << 25) ? "GFXPwr, " : "", 4513 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4514 } 4515 if (do_ring_perf_limit_reasons) { 4516 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 4517 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4518 fprintf(outf, " (Active: %s%s%s%s%s%s)", 4519 (msr & 1 << 0) ? "PROCHOT, " : "", 4520 (msr & 1 << 1) ? "ThermStatus, " : "", 4521 (msr & 1 << 6) ? "VR-Therm, " : "", 4522 (msr & 1 << 8) ? "Amps, " : "", 4523 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4524 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 4525 (msr & 1 << 16) ? "PROCHOT, " : "", 4526 (msr & 1 << 17) ? "ThermStatus, " : "", 4527 (msr & 1 << 22) ? "VR-Therm, " : "", 4528 (msr & 1 << 24) ? "Amps, " : "", 4529 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4530 } 4531 return 0; 4532 } 4533 4534 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 4535 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 4536 4537 double get_tdp_intel(unsigned int model) 4538 { 4539 unsigned long long msr; 4540 4541 if (do_rapl & RAPL_PKG_POWER_INFO) 4542 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 4543 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 4544 4545 switch (model) { 4546 case INTEL_FAM6_ATOM_SILVERMONT: 4547 case INTEL_FAM6_ATOM_SILVERMONT_D: 4548 return 30.0; 4549 default: 4550 return 135.0; 4551 } 4552 } 4553 4554 double get_tdp_amd(unsigned int family) 4555 { 4556 UNUSED(family); 4557 4558 /* This is the max stock TDP of HEDT/Server Fam17h+ chips */ 4559 return 280.0; 4560 } 4561 4562 /* 4563 * rapl_dram_energy_units_probe() 4564 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 4565 */ 4566 static double rapl_dram_energy_units_probe(int model, double rapl_energy_units) 4567 { 4568 /* only called for genuine_intel, family 6 */ 4569 4570 switch (model) { 4571 case INTEL_FAM6_HASWELL_X: /* HSX */ 4572 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4573 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4574 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4575 case INTEL_FAM6_ICELAKE_X: /* ICX */ 4576 return (rapl_dram_energy_units = 15.3 / 1000000); 4577 default: 4578 return (rapl_energy_units); 4579 } 4580 } 4581 4582 void rapl_probe_intel(unsigned int family, unsigned int model) 4583 { 4584 unsigned long long msr; 4585 unsigned int time_unit; 4586 double tdp; 4587 4588 if (family != 6) 4589 return; 4590 4591 switch (model) { 4592 case INTEL_FAM6_SANDYBRIDGE: 4593 case INTEL_FAM6_IVYBRIDGE: 4594 case INTEL_FAM6_HASWELL: /* HSW */ 4595 case INTEL_FAM6_HASWELL_L: /* HSW */ 4596 case INTEL_FAM6_HASWELL_G: /* HSW */ 4597 case INTEL_FAM6_BROADWELL: /* BDW */ 4598 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4599 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 4600 if (rapl_joules) { 4601 BIC_PRESENT(BIC_Pkg_J); 4602 BIC_PRESENT(BIC_Cor_J); 4603 BIC_PRESENT(BIC_GFX_J); 4604 } else { 4605 BIC_PRESENT(BIC_PkgWatt); 4606 BIC_PRESENT(BIC_CorWatt); 4607 BIC_PRESENT(BIC_GFXWatt); 4608 } 4609 break; 4610 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4611 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4612 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 4613 if (rapl_joules) 4614 BIC_PRESENT(BIC_Pkg_J); 4615 else 4616 BIC_PRESENT(BIC_PkgWatt); 4617 break; 4618 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4619 do_rapl = 4620 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS 4621 | RAPL_GFX | RAPL_PKG_POWER_INFO; 4622 if (rapl_joules) { 4623 BIC_PRESENT(BIC_Pkg_J); 4624 BIC_PRESENT(BIC_Cor_J); 4625 BIC_PRESENT(BIC_RAM_J); 4626 BIC_PRESENT(BIC_GFX_J); 4627 } else { 4628 BIC_PRESENT(BIC_PkgWatt); 4629 BIC_PRESENT(BIC_CorWatt); 4630 BIC_PRESENT(BIC_RAMWatt); 4631 BIC_PRESENT(BIC_GFXWatt); 4632 } 4633 break; 4634 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 4635 do_rapl = RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 4636 BIC_PRESENT(BIC_PKG__); 4637 if (rapl_joules) 4638 BIC_PRESENT(BIC_Pkg_J); 4639 else 4640 BIC_PRESENT(BIC_PkgWatt); 4641 break; 4642 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4643 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4644 do_rapl = 4645 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS 4646 | RAPL_GFX | RAPL_PKG_POWER_INFO; 4647 BIC_PRESENT(BIC_PKG__); 4648 BIC_PRESENT(BIC_RAM__); 4649 if (rapl_joules) { 4650 BIC_PRESENT(BIC_Pkg_J); 4651 BIC_PRESENT(BIC_Cor_J); 4652 BIC_PRESENT(BIC_RAM_J); 4653 BIC_PRESENT(BIC_GFX_J); 4654 } else { 4655 BIC_PRESENT(BIC_PkgWatt); 4656 BIC_PRESENT(BIC_CorWatt); 4657 BIC_PRESENT(BIC_RAMWatt); 4658 BIC_PRESENT(BIC_GFXWatt); 4659 } 4660 break; 4661 case INTEL_FAM6_HASWELL_X: /* HSX */ 4662 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4663 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4664 case INTEL_FAM6_ICELAKE_X: /* ICX */ 4665 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4666 do_rapl = 4667 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | 4668 RAPL_PKG_POWER_INFO; 4669 BIC_PRESENT(BIC_PKG__); 4670 BIC_PRESENT(BIC_RAM__); 4671 if (rapl_joules) { 4672 BIC_PRESENT(BIC_Pkg_J); 4673 BIC_PRESENT(BIC_RAM_J); 4674 } else { 4675 BIC_PRESENT(BIC_PkgWatt); 4676 BIC_PRESENT(BIC_RAMWatt); 4677 } 4678 break; 4679 case INTEL_FAM6_SANDYBRIDGE_X: 4680 case INTEL_FAM6_IVYBRIDGE_X: 4681 do_rapl = 4682 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | 4683 RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 4684 BIC_PRESENT(BIC_PKG__); 4685 BIC_PRESENT(BIC_RAM__); 4686 if (rapl_joules) { 4687 BIC_PRESENT(BIC_Pkg_J); 4688 BIC_PRESENT(BIC_Cor_J); 4689 BIC_PRESENT(BIC_RAM_J); 4690 } else { 4691 BIC_PRESENT(BIC_PkgWatt); 4692 BIC_PRESENT(BIC_CorWatt); 4693 BIC_PRESENT(BIC_RAMWatt); 4694 } 4695 break; 4696 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4697 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 4698 do_rapl = RAPL_PKG | RAPL_CORES; 4699 if (rapl_joules) { 4700 BIC_PRESENT(BIC_Pkg_J); 4701 BIC_PRESENT(BIC_Cor_J); 4702 } else { 4703 BIC_PRESENT(BIC_PkgWatt); 4704 BIC_PRESENT(BIC_CorWatt); 4705 } 4706 break; 4707 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 4708 do_rapl = 4709 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | 4710 RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 4711 BIC_PRESENT(BIC_PKG__); 4712 BIC_PRESENT(BIC_RAM__); 4713 if (rapl_joules) { 4714 BIC_PRESENT(BIC_Pkg_J); 4715 BIC_PRESENT(BIC_Cor_J); 4716 BIC_PRESENT(BIC_RAM_J); 4717 } else { 4718 BIC_PRESENT(BIC_PkgWatt); 4719 BIC_PRESENT(BIC_CorWatt); 4720 BIC_PRESENT(BIC_RAMWatt); 4721 } 4722 break; 4723 default: 4724 return; 4725 } 4726 4727 /* units on package 0, verify later other packages match */ 4728 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 4729 return; 4730 4731 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 4732 if (model == INTEL_FAM6_ATOM_SILVERMONT) 4733 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 4734 else 4735 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 4736 4737 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 4738 4739 time_unit = msr >> 16 & 0xF; 4740 if (time_unit == 0) 4741 time_unit = 0xA; 4742 4743 rapl_time_units = 1.0 / (1 << (time_unit)); 4744 4745 tdp = get_tdp_intel(model); 4746 4747 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4748 if (!quiet) 4749 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4750 } 4751 4752 void rapl_probe_amd(unsigned int family, unsigned int model) 4753 { 4754 unsigned long long msr; 4755 unsigned int eax, ebx, ecx, edx; 4756 unsigned int has_rapl = 0; 4757 double tdp; 4758 4759 UNUSED(model); 4760 4761 if (max_extended_level >= 0x80000007) { 4762 __cpuid(0x80000007, eax, ebx, ecx, edx); 4763 /* RAPL (Fam 17h+) */ 4764 has_rapl = edx & (1 << 14); 4765 } 4766 4767 if (!has_rapl || family < 0x17) 4768 return; 4769 4770 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY; 4771 if (rapl_joules) { 4772 BIC_PRESENT(BIC_Pkg_J); 4773 BIC_PRESENT(BIC_Cor_J); 4774 } else { 4775 BIC_PRESENT(BIC_PkgWatt); 4776 BIC_PRESENT(BIC_CorWatt); 4777 } 4778 4779 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr)) 4780 return; 4781 4782 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf)); 4783 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f)); 4784 rapl_power_units = ldexp(1.0, -(msr & 0xf)); 4785 4786 tdp = get_tdp_amd(family); 4787 4788 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4789 if (!quiet) 4790 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4791 } 4792 4793 /* 4794 * rapl_probe() 4795 * 4796 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 4797 */ 4798 void rapl_probe(unsigned int family, unsigned int model) 4799 { 4800 if (genuine_intel) 4801 rapl_probe_intel(family, model); 4802 if (authentic_amd || hygon_genuine) 4803 rapl_probe_amd(family, model); 4804 } 4805 4806 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 4807 { 4808 if (!genuine_intel) 4809 return; 4810 4811 if (family != 6) 4812 return; 4813 4814 switch (model) { 4815 case INTEL_FAM6_HASWELL: /* HSW */ 4816 case INTEL_FAM6_HASWELL_L: /* HSW */ 4817 case INTEL_FAM6_HASWELL_G: /* HSW */ 4818 do_gfx_perf_limit_reasons = 1; 4819 /* FALLTHRU */ 4820 case INTEL_FAM6_HASWELL_X: /* HSX */ 4821 do_core_perf_limit_reasons = 1; 4822 do_ring_perf_limit_reasons = 1; 4823 default: 4824 return; 4825 } 4826 } 4827 4828 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model) 4829 { 4830 if (is_skx(family, model) || is_bdx(family, model) || is_icx(family, model)) 4831 has_automatic_cstate_conversion = 1; 4832 } 4833 4834 void prewake_cstate_probe(unsigned int family, unsigned int model) 4835 { 4836 if (is_icx(family, model)) 4837 dis_cstate_prewake = 1; 4838 } 4839 4840 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4841 { 4842 unsigned long long msr; 4843 unsigned int dts, dts2; 4844 int cpu; 4845 4846 UNUSED(c); 4847 UNUSED(p); 4848 4849 if (!(do_dts || do_ptm)) 4850 return 0; 4851 4852 cpu = t->cpu_id; 4853 4854 /* DTS is per-core, no need to print for each thread */ 4855 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 4856 return 0; 4857 4858 if (cpu_migrate(cpu)) { 4859 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu); 4860 return -1; 4861 } 4862 4863 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 4864 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 4865 return 0; 4866 4867 dts = (msr >> 16) & 0x7F; 4868 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", cpu, msr, tj_max - dts); 4869 4870 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 4871 return 0; 4872 4873 dts = (msr >> 16) & 0x7F; 4874 dts2 = (msr >> 8) & 0x7F; 4875 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4876 cpu, msr, tj_max - dts, tj_max - dts2); 4877 } 4878 4879 if (do_dts && debug) { 4880 unsigned int resolution; 4881 4882 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 4883 return 0; 4884 4885 dts = (msr >> 16) & 0x7F; 4886 resolution = (msr >> 27) & 0xF; 4887 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 4888 cpu, msr, tj_max - dts, resolution); 4889 4890 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 4891 return 0; 4892 4893 dts = (msr >> 16) & 0x7F; 4894 dts2 = (msr >> 8) & 0x7F; 4895 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4896 cpu, msr, tj_max - dts, tj_max - dts2); 4897 } 4898 4899 return 0; 4900 } 4901 4902 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 4903 { 4904 fprintf(outf, "cpu%d: %s: %sabled (%0.3f Watts, %f sec, clamp %sabled)\n", 4905 cpu, label, 4906 ((msr >> 15) & 1) ? "EN" : "DIS", 4907 ((msr >> 0) & 0x7FFF) * rapl_power_units, 4908 (1.0 + (((msr >> 22) & 0x3) / 4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 4909 (((msr >> 16) & 1) ? "EN" : "DIS")); 4910 4911 return; 4912 } 4913 4914 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4915 { 4916 unsigned long long msr; 4917 const char *msr_name; 4918 int cpu; 4919 4920 UNUSED(c); 4921 UNUSED(p); 4922 4923 if (!do_rapl) 4924 return 0; 4925 4926 /* RAPL counters are per package, so print only for 1st thread/package */ 4927 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4928 return 0; 4929 4930 cpu = t->cpu_id; 4931 if (cpu_migrate(cpu)) { 4932 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu); 4933 return -1; 4934 } 4935 4936 if (do_rapl & RAPL_AMD_F17H) { 4937 msr_name = "MSR_RAPL_PWR_UNIT"; 4938 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr)) 4939 return -1; 4940 } else { 4941 msr_name = "MSR_RAPL_POWER_UNIT"; 4942 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 4943 return -1; 4944 } 4945 4946 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr, 4947 rapl_power_units, rapl_energy_units, rapl_time_units); 4948 4949 if (do_rapl & RAPL_PKG_POWER_INFO) { 4950 4951 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 4952 return -5; 4953 4954 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4955 cpu, msr, 4956 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4957 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4958 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4959 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4960 4961 } 4962 if (do_rapl & RAPL_PKG) { 4963 4964 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 4965 return -9; 4966 4967 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 4968 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 4969 4970 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 4971 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%0.3f Watts, %f* sec, clamp %sabled)\n", 4972 cpu, 4973 ((msr >> 47) & 1) ? "EN" : "DIS", 4974 ((msr >> 32) & 0x7FFF) * rapl_power_units, 4975 (1.0 + (((msr >> 54) & 0x3) / 4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 4976 ((msr >> 48) & 1) ? "EN" : "DIS"); 4977 4978 if (get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr)) 4979 return -9; 4980 4981 fprintf(outf, "cpu%d: MSR_VR_CURRENT_CONFIG: 0x%08llx\n", cpu, msr); 4982 fprintf(outf, "cpu%d: PKG Limit #4: %f Watts (%slocked)\n", 4983 cpu, ((msr >> 0) & 0x1FFF) * rapl_power_units, (msr >> 31) & 1 ? "" : "UN"); 4984 } 4985 4986 if (do_rapl & RAPL_DRAM_POWER_INFO) { 4987 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 4988 return -6; 4989 4990 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4991 cpu, msr, 4992 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4993 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4994 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4995 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4996 } 4997 if (do_rapl & RAPL_DRAM) { 4998 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 4999 return -9; 5000 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 5001 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 5002 5003 print_power_limit_msr(cpu, msr, "DRAM Limit"); 5004 } 5005 if (do_rapl & RAPL_CORE_POLICY) { 5006 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 5007 return -7; 5008 5009 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 5010 } 5011 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 5012 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 5013 return -9; 5014 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 5015 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 5016 print_power_limit_msr(cpu, msr, "Cores Limit"); 5017 } 5018 if (do_rapl & RAPL_GFX) { 5019 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 5020 return -8; 5021 5022 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 5023 5024 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 5025 return -9; 5026 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 5027 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 5028 print_power_limit_msr(cpu, msr, "GFX Limit"); 5029 } 5030 return 0; 5031 } 5032 5033 /* 5034 * SNB adds support for additional MSRs: 5035 * 5036 * MSR_PKG_C7_RESIDENCY 0x000003fa 5037 * MSR_CORE_C7_RESIDENCY 0x000003fe 5038 * MSR_PKG_C2_RESIDENCY 0x0000060d 5039 */ 5040 5041 int has_snb_msrs(unsigned int family, unsigned int model) 5042 { 5043 if (!genuine_intel) 5044 return 0; 5045 5046 if (family != 6) 5047 return 0; 5048 5049 switch (model) { 5050 case INTEL_FAM6_SANDYBRIDGE: 5051 case INTEL_FAM6_SANDYBRIDGE_X: 5052 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 5053 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 5054 case INTEL_FAM6_HASWELL: /* HSW */ 5055 case INTEL_FAM6_HASWELL_X: /* HSW */ 5056 case INTEL_FAM6_HASWELL_L: /* HSW */ 5057 case INTEL_FAM6_HASWELL_G: /* HSW */ 5058 case INTEL_FAM6_BROADWELL: /* BDW */ 5059 case INTEL_FAM6_BROADWELL_G: /* BDW */ 5060 case INTEL_FAM6_BROADWELL_X: /* BDX */ 5061 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5062 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 5063 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 5064 case INTEL_FAM6_ICELAKE_X: /* ICX */ 5065 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 5066 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5067 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 5068 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 5069 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 5070 return 1; 5071 } 5072 return 0; 5073 } 5074 5075 /* 5076 * HSW ULT added support for C8/C9/C10 MSRs: 5077 * 5078 * MSR_PKG_C8_RESIDENCY 0x00000630 5079 * MSR_PKG_C9_RESIDENCY 0x00000631 5080 * MSR_PKG_C10_RESIDENCY 0x00000632 5081 * 5082 * MSR_PKGC8_IRTL 0x00000633 5083 * MSR_PKGC9_IRTL 0x00000634 5084 * MSR_PKGC10_IRTL 0x00000635 5085 * 5086 */ 5087 int has_c8910_msrs(unsigned int family, unsigned int model) 5088 { 5089 if (!genuine_intel) 5090 return 0; 5091 5092 if (family != 6) 5093 return 0; 5094 5095 switch (model) { 5096 case INTEL_FAM6_HASWELL_L: /* HSW */ 5097 case INTEL_FAM6_BROADWELL: /* BDW */ 5098 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5099 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 5100 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 5101 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5102 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 5103 return 1; 5104 } 5105 return 0; 5106 } 5107 5108 /* 5109 * SKL adds support for additional MSRS: 5110 * 5111 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 5112 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 5113 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 5114 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 5115 */ 5116 int has_skl_msrs(unsigned int family, unsigned int model) 5117 { 5118 if (!genuine_intel) 5119 return 0; 5120 5121 if (family != 6) 5122 return 0; 5123 5124 switch (model) { 5125 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5126 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 5127 return 1; 5128 } 5129 return 0; 5130 } 5131 5132 int is_slm(unsigned int family, unsigned int model) 5133 { 5134 if (!genuine_intel) 5135 return 0; 5136 5137 if (family != 6) 5138 return 0; 5139 5140 switch (model) { 5141 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 5142 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 5143 return 1; 5144 } 5145 return 0; 5146 } 5147 5148 int is_knl(unsigned int family, unsigned int model) 5149 { 5150 if (!genuine_intel) 5151 return 0; 5152 5153 if (family != 6) 5154 return 0; 5155 5156 switch (model) { 5157 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 5158 return 1; 5159 } 5160 return 0; 5161 } 5162 5163 int is_cnl(unsigned int family, unsigned int model) 5164 { 5165 if (!genuine_intel) 5166 return 0; 5167 5168 if (family != 6) 5169 return 0; 5170 5171 switch (model) { 5172 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 5173 return 1; 5174 } 5175 5176 return 0; 5177 } 5178 5179 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 5180 { 5181 if (is_knl(family, model)) 5182 return 1024; 5183 return 1; 5184 } 5185 5186 #define SLM_BCLK_FREQS 5 5187 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0 }; 5188 5189 double slm_bclk(void) 5190 { 5191 unsigned long long msr = 3; 5192 unsigned int i; 5193 double freq; 5194 5195 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 5196 fprintf(outf, "SLM BCLK: unknown\n"); 5197 5198 i = msr & 0xf; 5199 if (i >= SLM_BCLK_FREQS) { 5200 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 5201 i = 3; 5202 } 5203 freq = slm_freq_table[i]; 5204 5205 if (!quiet) 5206 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 5207 5208 return freq; 5209 } 5210 5211 double discover_bclk(unsigned int family, unsigned int model) 5212 { 5213 if (has_snb_msrs(family, model) || is_knl(family, model)) 5214 return 100.00; 5215 else if (is_slm(family, model)) 5216 return slm_bclk(); 5217 else 5218 return 133.33; 5219 } 5220 5221 int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p) 5222 { 5223 unsigned int eax, ebx, ecx, edx; 5224 5225 UNUSED(c); 5226 UNUSED(p); 5227 5228 if (!genuine_intel) 5229 return 0; 5230 5231 if (cpu_migrate(t->cpu_id)) { 5232 fprintf(outf, "Could not migrate to CPU %d\n", t->cpu_id); 5233 return -1; 5234 } 5235 5236 if (max_level < 0x1a) 5237 return 0; 5238 5239 __cpuid(0x1a, eax, ebx, ecx, edx); 5240 eax = (eax >> 24) & 0xFF; 5241 if (eax == 0x20) 5242 t->is_atom = true; 5243 return 0; 5244 } 5245 5246 /* 5247 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 5248 * the Thermal Control Circuit (TCC) activates. 5249 * This is usually equal to tjMax. 5250 * 5251 * Older processors do not have this MSR, so there we guess, 5252 * but also allow cmdline over-ride with -T. 5253 * 5254 * Several MSR temperature values are in units of degrees-C 5255 * below this value, including the Digital Thermal Sensor (DTS), 5256 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 5257 */ 5258 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 5259 { 5260 unsigned long long msr; 5261 unsigned int tcc_default, tcc_offset; 5262 int cpu; 5263 5264 UNUSED(c); 5265 UNUSED(p); 5266 5267 /* tj_max is used only for dts or ptm */ 5268 if (!(do_dts || do_ptm)) 5269 return 0; 5270 5271 /* this is a per-package concept */ 5272 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 5273 return 0; 5274 5275 cpu = t->cpu_id; 5276 if (cpu_migrate(cpu)) { 5277 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 5278 return -1; 5279 } 5280 5281 if (tj_max_override != 0) { 5282 tj_max = tj_max_override; 5283 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", cpu, tj_max); 5284 return 0; 5285 } 5286 5287 /* Temperature Target MSR is Nehalem and newer only */ 5288 if (!do_nhm_platform_info) 5289 goto guess; 5290 5291 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 5292 goto guess; 5293 5294 tcc_default = (msr >> 16) & 0xFF; 5295 5296 if (!quiet) { 5297 switch (tcc_offset_bits) { 5298 case 4: 5299 tcc_offset = (msr >> 24) & 0xF; 5300 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n", 5301 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset); 5302 break; 5303 case 6: 5304 tcc_offset = (msr >> 24) & 0x3F; 5305 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n", 5306 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset); 5307 break; 5308 default: 5309 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", cpu, msr, tcc_default); 5310 break; 5311 } 5312 } 5313 5314 if (!tcc_default) 5315 goto guess; 5316 5317 tj_max = tcc_default; 5318 5319 return 0; 5320 5321 guess: 5322 tj_max = TJMAX_DEFAULT; 5323 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", cpu, tj_max); 5324 5325 return 0; 5326 } 5327 5328 void decode_feature_control_msr(void) 5329 { 5330 unsigned long long msr; 5331 5332 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr)) 5333 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 5334 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : ""); 5335 } 5336 5337 void decode_misc_enable_msr(void) 5338 { 5339 unsigned long long msr; 5340 5341 if (!genuine_intel) 5342 return; 5343 5344 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 5345 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 5346 base_cpu, msr, 5347 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 5348 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 5349 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 5350 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 5351 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 5352 } 5353 5354 void decode_misc_feature_control(void) 5355 { 5356 unsigned long long msr; 5357 5358 if (!has_misc_feature_control) 5359 return; 5360 5361 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 5362 fprintf(outf, 5363 "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 5364 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "", 5365 msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : ""); 5366 } 5367 5368 /* 5369 * Decode MSR_MISC_PWR_MGMT 5370 * 5371 * Decode the bits according to the Nehalem documentation 5372 * bit[0] seems to continue to have same meaning going forward 5373 * bit[1] less so... 5374 */ 5375 void decode_misc_pwr_mgmt_msr(void) 5376 { 5377 unsigned long long msr; 5378 5379 if (!do_nhm_platform_info) 5380 return; 5381 5382 if (no_MSR_MISC_PWR_MGMT) 5383 return; 5384 5385 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 5386 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 5387 base_cpu, msr, 5388 msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS"); 5389 } 5390 5391 /* 5392 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 5393 * 5394 * This MSRs are present on Silvermont processors, 5395 * Intel Atom processor E3000 series (Baytrail), and friends. 5396 */ 5397 void decode_c6_demotion_policy_msr(void) 5398 { 5399 unsigned long long msr; 5400 5401 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 5402 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 5403 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 5404 5405 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 5406 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 5407 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 5408 } 5409 5410 /* 5411 * When models are the same, for the purpose of turbostat, reuse 5412 */ 5413 unsigned int intel_model_duplicates(unsigned int model) 5414 { 5415 5416 switch (model) { 5417 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 5418 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 5419 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 5420 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 5421 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 5422 return INTEL_FAM6_NEHALEM; 5423 5424 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 5425 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 5426 return INTEL_FAM6_NEHALEM_EX; 5427 5428 case INTEL_FAM6_XEON_PHI_KNM: 5429 return INTEL_FAM6_XEON_PHI_KNL; 5430 5431 case INTEL_FAM6_BROADWELL_X: 5432 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */ 5433 return INTEL_FAM6_BROADWELL_X; 5434 5435 case INTEL_FAM6_SKYLAKE_L: 5436 case INTEL_FAM6_SKYLAKE: 5437 case INTEL_FAM6_KABYLAKE_L: 5438 case INTEL_FAM6_KABYLAKE: 5439 case INTEL_FAM6_COMETLAKE_L: 5440 case INTEL_FAM6_COMETLAKE: 5441 return INTEL_FAM6_SKYLAKE_L; 5442 5443 case INTEL_FAM6_ICELAKE_L: 5444 case INTEL_FAM6_ICELAKE_NNPI: 5445 case INTEL_FAM6_TIGERLAKE_L: 5446 case INTEL_FAM6_TIGERLAKE: 5447 case INTEL_FAM6_ROCKETLAKE: 5448 case INTEL_FAM6_LAKEFIELD: 5449 case INTEL_FAM6_ALDERLAKE: 5450 case INTEL_FAM6_ALDERLAKE_L: 5451 case INTEL_FAM6_RAPTORLAKE: 5452 return INTEL_FAM6_CANNONLAKE_L; 5453 5454 case INTEL_FAM6_ATOM_TREMONT_L: 5455 return INTEL_FAM6_ATOM_TREMONT; 5456 5457 case INTEL_FAM6_ICELAKE_D: 5458 case INTEL_FAM6_SAPPHIRERAPIDS_X: 5459 return INTEL_FAM6_ICELAKE_X; 5460 } 5461 return model; 5462 } 5463 5464 void print_dev_latency(void) 5465 { 5466 char *path = "/dev/cpu_dma_latency"; 5467 int fd; 5468 int value; 5469 int retval; 5470 5471 fd = open(path, O_RDONLY); 5472 if (fd < 0) { 5473 warn("fopen %s\n", path); 5474 return; 5475 } 5476 5477 retval = read(fd, (void *)&value, sizeof(int)); 5478 if (retval != sizeof(int)) { 5479 warn("read %s\n", path); 5480 close(fd); 5481 return; 5482 } 5483 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", value, value == 2000000000 ? "default" : "constrained"); 5484 5485 close(fd); 5486 } 5487 5488 /* 5489 * Linux-perf manages the the HW instructions-retired counter 5490 * by enabling when requested, and hiding rollover 5491 */ 5492 void linux_perf_init(void) 5493 { 5494 if (!BIC_IS_ENABLED(BIC_IPC)) 5495 return; 5496 5497 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK)) 5498 return; 5499 5500 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5501 if (fd_instr_count_percpu == NULL) 5502 err(-1, "calloc fd_instr_count_percpu"); 5503 5504 BIC_PRESENT(BIC_IPC); 5505 } 5506 5507 void process_cpuid() 5508 { 5509 unsigned int eax, ebx, ecx, edx; 5510 unsigned int fms, family, model, stepping, ecx_flags, edx_flags; 5511 unsigned int has_turbo; 5512 unsigned long long ucode_patch = 0; 5513 5514 eax = ebx = ecx = edx = 0; 5515 5516 __cpuid(0, max_level, ebx, ecx, edx); 5517 5518 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) 5519 genuine_intel = 1; 5520 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) 5521 authentic_amd = 1; 5522 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e) 5523 hygon_genuine = 1; 5524 5525 if (!quiet) 5526 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n", 5527 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level); 5528 5529 __cpuid(1, fms, ebx, ecx, edx); 5530 family = (fms >> 8) & 0xf; 5531 model = (fms >> 4) & 0xf; 5532 stepping = fms & 0xf; 5533 if (family == 0xf) 5534 family += (fms >> 20) & 0xff; 5535 if (family >= 6) 5536 model += ((fms >> 16) & 0xf) << 4; 5537 ecx_flags = ecx; 5538 edx_flags = edx; 5539 5540 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch)) 5541 warnx("get_msr(UCODE)\n"); 5542 5543 /* 5544 * check max extended function levels of CPUID. 5545 * This is needed to check for invariant TSC. 5546 * This check is valid for both Intel and AMD. 5547 */ 5548 ebx = ecx = edx = 0; 5549 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 5550 5551 if (!quiet) { 5552 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d) microcode 0x%x\n", 5553 family, model, stepping, family, model, stepping, 5554 (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF)); 5555 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level); 5556 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 5557 ecx_flags & (1 << 0) ? "SSE3" : "-", 5558 ecx_flags & (1 << 3) ? "MONITOR" : "-", 5559 ecx_flags & (1 << 6) ? "SMX" : "-", 5560 ecx_flags & (1 << 7) ? "EIST" : "-", 5561 ecx_flags & (1 << 8) ? "TM2" : "-", 5562 edx_flags & (1 << 4) ? "TSC" : "-", 5563 edx_flags & (1 << 5) ? "MSR" : "-", 5564 edx_flags & (1 << 22) ? "ACPI-TM" : "-", 5565 edx_flags & (1 << 28) ? "HT" : "-", edx_flags & (1 << 29) ? "TM" : "-"); 5566 } 5567 if (genuine_intel) { 5568 model_orig = model; 5569 model = intel_model_duplicates(model); 5570 } 5571 5572 if (!(edx_flags & (1 << 5))) 5573 errx(1, "CPUID: no MSR"); 5574 5575 if (max_extended_level >= 0x80000007) { 5576 5577 /* 5578 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 5579 * this check is valid for both Intel and AMD 5580 */ 5581 __cpuid(0x80000007, eax, ebx, ecx, edx); 5582 has_invariant_tsc = edx & (1 << 8); 5583 } 5584 5585 /* 5586 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 5587 * this check is valid for both Intel and AMD 5588 */ 5589 5590 __cpuid(0x6, eax, ebx, ecx, edx); 5591 has_aperf = ecx & (1 << 0); 5592 if (has_aperf) { 5593 BIC_PRESENT(BIC_Avg_MHz); 5594 BIC_PRESENT(BIC_Busy); 5595 BIC_PRESENT(BIC_Bzy_MHz); 5596 } 5597 do_dts = eax & (1 << 0); 5598 if (do_dts) 5599 BIC_PRESENT(BIC_CoreTmp); 5600 has_turbo = eax & (1 << 1); 5601 do_ptm = eax & (1 << 6); 5602 if (do_ptm) 5603 BIC_PRESENT(BIC_PkgTmp); 5604 has_hwp = eax & (1 << 7); 5605 has_hwp_notify = eax & (1 << 8); 5606 has_hwp_activity_window = eax & (1 << 9); 5607 has_hwp_epp = eax & (1 << 10); 5608 has_hwp_pkg = eax & (1 << 11); 5609 has_epb = ecx & (1 << 3); 5610 5611 if (!quiet) 5612 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 5613 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 5614 has_aperf ? "" : "No-", 5615 has_turbo ? "" : "No-", 5616 do_dts ? "" : "No-", 5617 do_ptm ? "" : "No-", 5618 has_hwp ? "" : "No-", 5619 has_hwp_notify ? "" : "No-", 5620 has_hwp_activity_window ? "" : "No-", 5621 has_hwp_epp ? "" : "No-", has_hwp_pkg ? "" : "No-", has_epb ? "" : "No-"); 5622 5623 if (!quiet) 5624 decode_misc_enable_msr(); 5625 5626 if (max_level >= 0x7 && !quiet) { 5627 int has_sgx; 5628 5629 ecx = 0; 5630 5631 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 5632 5633 has_sgx = ebx & (1 << 2); 5634 5635 is_hybrid = edx & (1 << 15); 5636 5637 fprintf(outf, "CPUID(7): %sSGX %sHybrid\n", has_sgx ? "" : "No-", is_hybrid ? "" : "No-"); 5638 5639 if (has_sgx) 5640 decode_feature_control_msr(); 5641 } 5642 5643 if (max_level >= 0x15) { 5644 unsigned int eax_crystal; 5645 unsigned int ebx_tsc; 5646 5647 /* 5648 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 5649 */ 5650 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 5651 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 5652 5653 if (ebx_tsc != 0) { 5654 5655 if (!quiet && (ebx != 0)) 5656 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 5657 eax_crystal, ebx_tsc, crystal_hz); 5658 5659 if (crystal_hz == 0) 5660 switch (model) { 5661 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5662 crystal_hz = 24000000; /* 24.0 MHz */ 5663 break; 5664 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 5665 crystal_hz = 25000000; /* 25.0 MHz */ 5666 break; 5667 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 5668 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5669 crystal_hz = 19200000; /* 19.2 MHz */ 5670 break; 5671 default: 5672 crystal_hz = 0; 5673 } 5674 5675 if (crystal_hz) { 5676 tsc_hz = (unsigned long long)crystal_hz *ebx_tsc / eax_crystal; 5677 if (!quiet) 5678 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 5679 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 5680 } 5681 } 5682 } 5683 if (max_level >= 0x16) { 5684 unsigned int base_mhz, max_mhz, bus_mhz, edx; 5685 5686 /* 5687 * CPUID 16H Base MHz, Max MHz, Bus MHz 5688 */ 5689 base_mhz = max_mhz = bus_mhz = edx = 0; 5690 5691 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 5692 if (!quiet) 5693 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 5694 base_mhz, max_mhz, bus_mhz); 5695 } 5696 5697 if (has_aperf) 5698 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 5699 5700 BIC_PRESENT(BIC_IRQ); 5701 BIC_PRESENT(BIC_TSC_MHz); 5702 5703 if (probe_nhm_msrs(family, model)) { 5704 do_nhm_platform_info = 1; 5705 BIC_PRESENT(BIC_CPU_c1); 5706 BIC_PRESENT(BIC_CPU_c3); 5707 BIC_PRESENT(BIC_CPU_c6); 5708 BIC_PRESENT(BIC_SMI); 5709 } 5710 do_snb_cstates = has_snb_msrs(family, model); 5711 5712 if (do_snb_cstates) 5713 BIC_PRESENT(BIC_CPU_c7); 5714 5715 do_irtl_snb = has_snb_msrs(family, model); 5716 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 5717 BIC_PRESENT(BIC_Pkgpc2); 5718 if (pkg_cstate_limit >= PCL__3) 5719 BIC_PRESENT(BIC_Pkgpc3); 5720 if (pkg_cstate_limit >= PCL__6) 5721 BIC_PRESENT(BIC_Pkgpc6); 5722 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 5723 BIC_PRESENT(BIC_Pkgpc7); 5724 if (has_slv_msrs(family, model)) { 5725 BIC_NOT_PRESENT(BIC_Pkgpc2); 5726 BIC_NOT_PRESENT(BIC_Pkgpc3); 5727 BIC_PRESENT(BIC_Pkgpc6); 5728 BIC_NOT_PRESENT(BIC_Pkgpc7); 5729 BIC_PRESENT(BIC_Mod_c6); 5730 use_c1_residency_msr = 1; 5731 } 5732 if (is_jvl(family, model)) { 5733 BIC_NOT_PRESENT(BIC_CPU_c3); 5734 BIC_NOT_PRESENT(BIC_CPU_c7); 5735 BIC_NOT_PRESENT(BIC_Pkgpc2); 5736 BIC_NOT_PRESENT(BIC_Pkgpc3); 5737 BIC_NOT_PRESENT(BIC_Pkgpc6); 5738 BIC_NOT_PRESENT(BIC_Pkgpc7); 5739 } 5740 if (is_dnv(family, model)) { 5741 BIC_PRESENT(BIC_CPU_c1); 5742 BIC_NOT_PRESENT(BIC_CPU_c3); 5743 BIC_NOT_PRESENT(BIC_Pkgpc3); 5744 BIC_NOT_PRESENT(BIC_CPU_c7); 5745 BIC_NOT_PRESENT(BIC_Pkgpc7); 5746 use_c1_residency_msr = 1; 5747 } 5748 if (is_skx(family, model) || is_icx(family, model)) { 5749 BIC_NOT_PRESENT(BIC_CPU_c3); 5750 BIC_NOT_PRESENT(BIC_Pkgpc3); 5751 BIC_NOT_PRESENT(BIC_CPU_c7); 5752 BIC_NOT_PRESENT(BIC_Pkgpc7); 5753 } 5754 if (is_bdx(family, model)) { 5755 BIC_NOT_PRESENT(BIC_CPU_c7); 5756 BIC_NOT_PRESENT(BIC_Pkgpc7); 5757 } 5758 if (has_c8910_msrs(family, model)) { 5759 if (pkg_cstate_limit >= PCL__8) 5760 BIC_PRESENT(BIC_Pkgpc8); 5761 if (pkg_cstate_limit >= PCL__9) 5762 BIC_PRESENT(BIC_Pkgpc9); 5763 if (pkg_cstate_limit >= PCL_10) 5764 BIC_PRESENT(BIC_Pkgpc10); 5765 } 5766 do_irtl_hsw = has_c8910_msrs(family, model); 5767 if (has_skl_msrs(family, model)) { 5768 BIC_PRESENT(BIC_Totl_c0); 5769 BIC_PRESENT(BIC_Any_c0); 5770 BIC_PRESENT(BIC_GFX_c0); 5771 BIC_PRESENT(BIC_CPUGFX); 5772 } 5773 do_slm_cstates = is_slm(family, model); 5774 do_knl_cstates = is_knl(family, model); 5775 5776 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || is_ehl(family, model)) 5777 BIC_NOT_PRESENT(BIC_CPU_c3); 5778 5779 if (!quiet) 5780 decode_misc_pwr_mgmt_msr(); 5781 5782 if (!quiet && has_slv_msrs(family, model)) 5783 decode_c6_demotion_policy_msr(); 5784 5785 rapl_probe(family, model); 5786 perf_limit_reasons_probe(family, model); 5787 automatic_cstate_conversion_probe(family, model); 5788 5789 check_tcc_offset(model_orig); 5790 5791 if (!quiet) 5792 dump_cstate_pstate_config_info(family, model); 5793 intel_uncore_frequency_probe(); 5794 5795 if (!quiet) 5796 print_dev_latency(); 5797 if (!quiet) 5798 dump_sysfs_cstate_config(); 5799 if (!quiet) 5800 dump_sysfs_pstate_config(); 5801 5802 if (has_skl_msrs(family, model) || is_ehl(family, model)) 5803 calculate_tsc_tweak(); 5804 5805 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 5806 BIC_PRESENT(BIC_GFX_rc6); 5807 5808 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 5809 BIC_PRESENT(BIC_GFXMHz); 5810 5811 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK)) 5812 BIC_PRESENT(BIC_GFXACTMHz); 5813 5814 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 5815 BIC_PRESENT(BIC_CPU_LPI); 5816 else 5817 BIC_NOT_PRESENT(BIC_CPU_LPI); 5818 5819 if (!access("/sys/devices/system/cpu/cpu0/thermal_throttle/core_throttle_count", R_OK)) 5820 BIC_PRESENT(BIC_CORE_THROT_CNT); 5821 else 5822 BIC_NOT_PRESENT(BIC_CORE_THROT_CNT); 5823 5824 if (!access(sys_lpi_file_sysfs, R_OK)) { 5825 sys_lpi_file = sys_lpi_file_sysfs; 5826 BIC_PRESENT(BIC_SYS_LPI); 5827 } else if (!access(sys_lpi_file_debugfs, R_OK)) { 5828 sys_lpi_file = sys_lpi_file_debugfs; 5829 BIC_PRESENT(BIC_SYS_LPI); 5830 } else { 5831 sys_lpi_file_sysfs = NULL; 5832 BIC_NOT_PRESENT(BIC_SYS_LPI); 5833 } 5834 5835 if (!quiet) 5836 decode_misc_feature_control(); 5837 5838 return; 5839 } 5840 5841 /* 5842 * in /dev/cpu/ return success for names that are numbers 5843 * ie. filter out ".", "..", "microcode". 5844 */ 5845 int dir_filter(const struct dirent *dirp) 5846 { 5847 if (isdigit(dirp->d_name[0])) 5848 return 1; 5849 else 5850 return 0; 5851 } 5852 5853 void topology_probe() 5854 { 5855 int i; 5856 int max_core_id = 0; 5857 int max_package_id = 0; 5858 int max_die_id = 0; 5859 int max_siblings = 0; 5860 5861 /* Initialize num_cpus, max_cpu_num */ 5862 set_max_cpu_num(); 5863 topo.num_cpus = 0; 5864 for_all_proc_cpus(count_cpus); 5865 if (!summary_only && topo.num_cpus > 1) 5866 BIC_PRESENT(BIC_CPU); 5867 5868 if (debug > 1) 5869 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 5870 5871 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 5872 if (cpus == NULL) 5873 err(1, "calloc cpus"); 5874 5875 /* 5876 * Allocate and initialize cpu_present_set 5877 */ 5878 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5879 if (cpu_present_set == NULL) 5880 err(3, "CPU_ALLOC"); 5881 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5882 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 5883 for_all_proc_cpus(mark_cpu_present); 5884 5885 /* 5886 * Validate that all cpus in cpu_subset are also in cpu_present_set 5887 */ 5888 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 5889 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 5890 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) 5891 err(1, "cpu%d not present", i); 5892 } 5893 5894 /* 5895 * Allocate and initialize cpu_affinity_set 5896 */ 5897 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5898 if (cpu_affinity_set == NULL) 5899 err(3, "CPU_ALLOC"); 5900 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5901 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 5902 5903 for_all_proc_cpus(init_thread_id); 5904 5905 /* 5906 * For online cpus 5907 * find max_core_id, max_package_id 5908 */ 5909 for (i = 0; i <= topo.max_cpu_num; ++i) { 5910 int siblings; 5911 5912 if (cpu_is_not_present(i)) { 5913 if (debug > 1) 5914 fprintf(outf, "cpu%d NOT PRESENT\n", i); 5915 continue; 5916 } 5917 5918 cpus[i].logical_cpu_id = i; 5919 5920 /* get package information */ 5921 cpus[i].physical_package_id = get_physical_package_id(i); 5922 if (cpus[i].physical_package_id > max_package_id) 5923 max_package_id = cpus[i].physical_package_id; 5924 5925 /* get die information */ 5926 cpus[i].die_id = get_die_id(i); 5927 if (cpus[i].die_id > max_die_id) 5928 max_die_id = cpus[i].die_id; 5929 5930 /* get numa node information */ 5931 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 5932 if (cpus[i].physical_node_id > topo.max_node_num) 5933 topo.max_node_num = cpus[i].physical_node_id; 5934 5935 /* get core information */ 5936 cpus[i].physical_core_id = get_core_id(i); 5937 if (cpus[i].physical_core_id > max_core_id) 5938 max_core_id = cpus[i].physical_core_id; 5939 5940 /* get thread information */ 5941 siblings = get_thread_siblings(&cpus[i]); 5942 if (siblings > max_siblings) 5943 max_siblings = siblings; 5944 if (cpus[i].thread_id == 0) 5945 topo.num_cores++; 5946 } 5947 5948 topo.cores_per_node = max_core_id + 1; 5949 if (debug > 1) 5950 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", max_core_id, topo.cores_per_node); 5951 if (!summary_only && topo.cores_per_node > 1) 5952 BIC_PRESENT(BIC_Core); 5953 5954 topo.num_die = max_die_id + 1; 5955 if (debug > 1) 5956 fprintf(outf, "max_die_id %d, sizing for %d die\n", max_die_id, topo.num_die); 5957 if (!summary_only && topo.num_die > 1) 5958 BIC_PRESENT(BIC_Die); 5959 5960 topo.num_packages = max_package_id + 1; 5961 if (debug > 1) 5962 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages); 5963 if (!summary_only && topo.num_packages > 1) 5964 BIC_PRESENT(BIC_Package); 5965 5966 set_node_data(); 5967 if (debug > 1) 5968 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 5969 if (!summary_only && topo.nodes_per_pkg > 1) 5970 BIC_PRESENT(BIC_Node); 5971 5972 topo.threads_per_core = max_siblings; 5973 if (debug > 1) 5974 fprintf(outf, "max_siblings %d\n", max_siblings); 5975 5976 if (debug < 1) 5977 return; 5978 5979 for (i = 0; i <= topo.max_cpu_num; ++i) { 5980 if (cpu_is_not_present(i)) 5981 continue; 5982 fprintf(outf, 5983 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n", 5984 i, cpus[i].physical_package_id, cpus[i].die_id, 5985 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id); 5986 } 5987 5988 } 5989 5990 void allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) 5991 { 5992 int i; 5993 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * topo.num_packages; 5994 int num_threads = topo.threads_per_core * num_cores; 5995 5996 *t = calloc(num_threads, sizeof(struct thread_data)); 5997 if (*t == NULL) 5998 goto error; 5999 6000 for (i = 0; i < num_threads; i++) 6001 (*t)[i].cpu_id = -1; 6002 6003 *c = calloc(num_cores, sizeof(struct core_data)); 6004 if (*c == NULL) 6005 goto error; 6006 6007 for (i = 0; i < num_cores; i++) 6008 (*c)[i].core_id = -1; 6009 6010 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 6011 if (*p == NULL) 6012 goto error; 6013 6014 for (i = 0; i < topo.num_packages; i++) 6015 (*p)[i].package_id = i; 6016 6017 return; 6018 error: 6019 err(1, "calloc counters"); 6020 } 6021 6022 /* 6023 * init_counter() 6024 * 6025 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 6026 */ 6027 void init_counter(struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base, int cpu_id) 6028 { 6029 int pkg_id = cpus[cpu_id].physical_package_id; 6030 int node_id = cpus[cpu_id].logical_node_id; 6031 int core_id = cpus[cpu_id].physical_core_id; 6032 int thread_id = cpus[cpu_id].thread_id; 6033 struct thread_data *t; 6034 struct core_data *c; 6035 struct pkg_data *p; 6036 6037 /* Workaround for systems where physical_node_id==-1 6038 * and logical_node_id==(-1 - topo.num_cpus) 6039 */ 6040 if (node_id < 0) 6041 node_id = 0; 6042 6043 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 6044 c = GET_CORE(core_base, core_id, node_id, pkg_id); 6045 p = GET_PKG(pkg_base, pkg_id); 6046 6047 t->cpu_id = cpu_id; 6048 if (thread_id == 0) { 6049 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 6050 if (cpu_is_first_core_in_package(cpu_id)) 6051 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 6052 } 6053 6054 c->core_id = core_id; 6055 p->package_id = pkg_id; 6056 } 6057 6058 int initialize_counters(int cpu_id) 6059 { 6060 init_counter(EVEN_COUNTERS, cpu_id); 6061 init_counter(ODD_COUNTERS, cpu_id); 6062 return 0; 6063 } 6064 6065 void allocate_output_buffer() 6066 { 6067 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048); 6068 outp = output_buffer; 6069 if (outp == NULL) 6070 err(-1, "calloc output buffer"); 6071 } 6072 6073 void allocate_fd_percpu(void) 6074 { 6075 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 6076 if (fd_percpu == NULL) 6077 err(-1, "calloc fd_percpu"); 6078 } 6079 6080 void allocate_irq_buffers(void) 6081 { 6082 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 6083 if (irq_column_2_cpu == NULL) 6084 err(-1, "calloc %d", topo.num_cpus); 6085 6086 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 6087 if (irqs_per_cpu == NULL) 6088 err(-1, "calloc %d", topo.max_cpu_num + 1); 6089 } 6090 6091 void setup_all_buffers(void) 6092 { 6093 topology_probe(); 6094 allocate_irq_buffers(); 6095 allocate_fd_percpu(); 6096 allocate_counters(&thread_even, &core_even, &package_even); 6097 allocate_counters(&thread_odd, &core_odd, &package_odd); 6098 allocate_output_buffer(); 6099 for_all_proc_cpus(initialize_counters); 6100 } 6101 6102 void set_base_cpu(void) 6103 { 6104 base_cpu = sched_getcpu(); 6105 if (base_cpu < 0) 6106 err(-ENODEV, "No valid cpus found"); 6107 6108 if (debug > 1) 6109 fprintf(outf, "base_cpu = %d\n", base_cpu); 6110 } 6111 6112 void turbostat_init() 6113 { 6114 setup_all_buffers(); 6115 set_base_cpu(); 6116 check_dev_msr(); 6117 check_permissions(); 6118 process_cpuid(); 6119 linux_perf_init(); 6120 6121 if (!quiet) 6122 for_all_cpus(print_hwp, ODD_COUNTERS); 6123 6124 if (!quiet) 6125 for_all_cpus(print_epb, ODD_COUNTERS); 6126 6127 if (!quiet) 6128 for_all_cpus(print_perf_limit, ODD_COUNTERS); 6129 6130 if (!quiet) 6131 for_all_cpus(print_rapl, ODD_COUNTERS); 6132 6133 for_all_cpus(set_temperature_target, ODD_COUNTERS); 6134 6135 for_all_cpus(get_cpu_type, ODD_COUNTERS); 6136 for_all_cpus(get_cpu_type, EVEN_COUNTERS); 6137 6138 if (!quiet) 6139 for_all_cpus(print_thermal, ODD_COUNTERS); 6140 6141 if (!quiet && do_irtl_snb) 6142 print_irtl(); 6143 6144 if (DO_BIC(BIC_IPC)) 6145 (void)get_instr_count_fd(base_cpu); 6146 } 6147 6148 int fork_it(char **argv) 6149 { 6150 pid_t child_pid; 6151 int status; 6152 6153 snapshot_proc_sysfs_files(); 6154 status = for_all_cpus(get_counters, EVEN_COUNTERS); 6155 first_counter_read = 0; 6156 if (status) 6157 exit(status); 6158 /* clear affinity side-effect of get_counters() */ 6159 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 6160 gettimeofday(&tv_even, (struct timezone *)NULL); 6161 6162 child_pid = fork(); 6163 if (!child_pid) { 6164 /* child */ 6165 execvp(argv[0], argv); 6166 err(errno, "exec %s", argv[0]); 6167 } else { 6168 6169 /* parent */ 6170 if (child_pid == -1) 6171 err(1, "fork"); 6172 6173 signal(SIGINT, SIG_IGN); 6174 signal(SIGQUIT, SIG_IGN); 6175 if (waitpid(child_pid, &status, 0) == -1) 6176 err(status, "waitpid"); 6177 6178 if (WIFEXITED(status)) 6179 status = WEXITSTATUS(status); 6180 } 6181 /* 6182 * n.b. fork_it() does not check for errors from for_all_cpus() 6183 * because re-starting is problematic when forking 6184 */ 6185 snapshot_proc_sysfs_files(); 6186 for_all_cpus(get_counters, ODD_COUNTERS); 6187 gettimeofday(&tv_odd, (struct timezone *)NULL); 6188 timersub(&tv_odd, &tv_even, &tv_delta); 6189 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 6190 fprintf(outf, "%s: Counter reset detected\n", progname); 6191 else { 6192 compute_average(EVEN_COUNTERS); 6193 format_all_counters(EVEN_COUNTERS); 6194 } 6195 6196 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec / 1000000.0); 6197 6198 flush_output_stderr(); 6199 6200 return status; 6201 } 6202 6203 int get_and_dump_counters(void) 6204 { 6205 int status; 6206 6207 snapshot_proc_sysfs_files(); 6208 status = for_all_cpus(get_counters, ODD_COUNTERS); 6209 if (status) 6210 return status; 6211 6212 status = for_all_cpus(dump_counters, ODD_COUNTERS); 6213 if (status) 6214 return status; 6215 6216 flush_output_stdout(); 6217 6218 return status; 6219 } 6220 6221 void print_version() 6222 { 6223 fprintf(outf, "turbostat version 2022.04.16 - Len Brown <lenb@kernel.org>\n"); 6224 } 6225 6226 #define COMMAND_LINE_SIZE 2048 6227 6228 void print_bootcmd(void) 6229 { 6230 char bootcmd[COMMAND_LINE_SIZE]; 6231 FILE *fp; 6232 int ret; 6233 6234 memset(bootcmd, 0, COMMAND_LINE_SIZE); 6235 fp = fopen("/proc/cmdline", "r"); 6236 if (!fp) 6237 return; 6238 6239 ret = fread(bootcmd, sizeof(char), COMMAND_LINE_SIZE - 1, fp); 6240 if (ret) { 6241 bootcmd[ret] = '\0'; 6242 /* the last character is already '\n' */ 6243 fprintf(outf, "Kernel command line: %s", bootcmd); 6244 } 6245 6246 fclose(fp); 6247 } 6248 6249 int add_counter(unsigned int msr_num, char *path, char *name, 6250 unsigned int width, enum counter_scope scope, 6251 enum counter_type type, enum counter_format format, int flags) 6252 { 6253 struct msr_counter *msrp; 6254 6255 msrp = calloc(1, sizeof(struct msr_counter)); 6256 if (msrp == NULL) { 6257 perror("calloc"); 6258 exit(1); 6259 } 6260 6261 msrp->msr_num = msr_num; 6262 strncpy(msrp->name, name, NAME_BYTES - 1); 6263 if (path) 6264 strncpy(msrp->path, path, PATH_BYTES - 1); 6265 msrp->width = width; 6266 msrp->type = type; 6267 msrp->format = format; 6268 msrp->flags = flags; 6269 6270 switch (scope) { 6271 6272 case SCOPE_CPU: 6273 msrp->next = sys.tp; 6274 sys.tp = msrp; 6275 sys.added_thread_counters++; 6276 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 6277 fprintf(stderr, "exceeded max %d added thread counters\n", MAX_ADDED_COUNTERS); 6278 exit(-1); 6279 } 6280 break; 6281 6282 case SCOPE_CORE: 6283 msrp->next = sys.cp; 6284 sys.cp = msrp; 6285 sys.added_core_counters++; 6286 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 6287 fprintf(stderr, "exceeded max %d added core counters\n", MAX_ADDED_COUNTERS); 6288 exit(-1); 6289 } 6290 break; 6291 6292 case SCOPE_PACKAGE: 6293 msrp->next = sys.pp; 6294 sys.pp = msrp; 6295 sys.added_package_counters++; 6296 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 6297 fprintf(stderr, "exceeded max %d added package counters\n", MAX_ADDED_COUNTERS); 6298 exit(-1); 6299 } 6300 break; 6301 } 6302 6303 return 0; 6304 } 6305 6306 void parse_add_command(char *add_command) 6307 { 6308 int msr_num = 0; 6309 char *path = NULL; 6310 char name_buffer[NAME_BYTES] = ""; 6311 int width = 64; 6312 int fail = 0; 6313 enum counter_scope scope = SCOPE_CPU; 6314 enum counter_type type = COUNTER_CYCLES; 6315 enum counter_format format = FORMAT_DELTA; 6316 6317 while (add_command) { 6318 6319 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 6320 goto next; 6321 6322 if (sscanf(add_command, "msr%d", &msr_num) == 1) 6323 goto next; 6324 6325 if (*add_command == '/') { 6326 path = add_command; 6327 goto next; 6328 } 6329 6330 if (sscanf(add_command, "u%d", &width) == 1) { 6331 if ((width == 32) || (width == 64)) 6332 goto next; 6333 width = 64; 6334 } 6335 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 6336 scope = SCOPE_CPU; 6337 goto next; 6338 } 6339 if (!strncmp(add_command, "core", strlen("core"))) { 6340 scope = SCOPE_CORE; 6341 goto next; 6342 } 6343 if (!strncmp(add_command, "package", strlen("package"))) { 6344 scope = SCOPE_PACKAGE; 6345 goto next; 6346 } 6347 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 6348 type = COUNTER_CYCLES; 6349 goto next; 6350 } 6351 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 6352 type = COUNTER_SECONDS; 6353 goto next; 6354 } 6355 if (!strncmp(add_command, "usec", strlen("usec"))) { 6356 type = COUNTER_USEC; 6357 goto next; 6358 } 6359 if (!strncmp(add_command, "raw", strlen("raw"))) { 6360 format = FORMAT_RAW; 6361 goto next; 6362 } 6363 if (!strncmp(add_command, "delta", strlen("delta"))) { 6364 format = FORMAT_DELTA; 6365 goto next; 6366 } 6367 if (!strncmp(add_command, "percent", strlen("percent"))) { 6368 format = FORMAT_PERCENT; 6369 goto next; 6370 } 6371 6372 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 6373 char *eos; 6374 6375 eos = strchr(name_buffer, ','); 6376 if (eos) 6377 *eos = '\0'; 6378 goto next; 6379 } 6380 6381 next: 6382 add_command = strchr(add_command, ','); 6383 if (add_command) { 6384 *add_command = '\0'; 6385 add_command++; 6386 } 6387 6388 } 6389 if ((msr_num == 0) && (path == NULL)) { 6390 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 6391 fail++; 6392 } 6393 6394 /* generate default column header */ 6395 if (*name_buffer == '\0') { 6396 if (width == 32) 6397 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 6398 else 6399 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 6400 } 6401 6402 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 6403 fail++; 6404 6405 if (fail) { 6406 help(); 6407 exit(1); 6408 } 6409 } 6410 6411 int is_deferred_add(char *name) 6412 { 6413 int i; 6414 6415 for (i = 0; i < deferred_add_index; ++i) 6416 if (!strcmp(name, deferred_add_names[i])) 6417 return 1; 6418 return 0; 6419 } 6420 6421 int is_deferred_skip(char *name) 6422 { 6423 int i; 6424 6425 for (i = 0; i < deferred_skip_index; ++i) 6426 if (!strcmp(name, deferred_skip_names[i])) 6427 return 1; 6428 return 0; 6429 } 6430 6431 void probe_sysfs(void) 6432 { 6433 char path[64]; 6434 char name_buf[16]; 6435 FILE *input; 6436 int state; 6437 char *sp; 6438 6439 for (state = 10; state >= 0; --state) { 6440 6441 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 6442 input = fopen(path, "r"); 6443 if (input == NULL) 6444 continue; 6445 if (!fgets(name_buf, sizeof(name_buf), input)) 6446 err(1, "%s: failed to read file", path); 6447 6448 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 6449 sp = strchr(name_buf, '-'); 6450 if (!sp) 6451 sp = strchrnul(name_buf, '\n'); 6452 *sp = '%'; 6453 *(sp + 1) = '\0'; 6454 6455 remove_underbar(name_buf); 6456 6457 fclose(input); 6458 6459 sprintf(path, "cpuidle/state%d/time", state); 6460 6461 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf)) 6462 continue; 6463 6464 if (is_deferred_skip(name_buf)) 6465 continue; 6466 6467 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, FORMAT_PERCENT, SYSFS_PERCPU); 6468 } 6469 6470 for (state = 10; state >= 0; --state) { 6471 6472 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 6473 input = fopen(path, "r"); 6474 if (input == NULL) 6475 continue; 6476 if (!fgets(name_buf, sizeof(name_buf), input)) 6477 err(1, "%s: failed to read file", path); 6478 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 6479 sp = strchr(name_buf, '-'); 6480 if (!sp) 6481 sp = strchrnul(name_buf, '\n'); 6482 *sp = '\0'; 6483 fclose(input); 6484 6485 remove_underbar(name_buf); 6486 6487 sprintf(path, "cpuidle/state%d/usage", state); 6488 6489 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf)) 6490 continue; 6491 6492 if (is_deferred_skip(name_buf)) 6493 continue; 6494 6495 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, FORMAT_DELTA, SYSFS_PERCPU); 6496 } 6497 6498 } 6499 6500 /* 6501 * parse cpuset with following syntax 6502 * 1,2,4..6,8-10 and set bits in cpu_subset 6503 */ 6504 void parse_cpu_command(char *optarg) 6505 { 6506 unsigned int start, end; 6507 char *next; 6508 6509 if (!strcmp(optarg, "core")) { 6510 if (cpu_subset) 6511 goto error; 6512 show_core_only++; 6513 return; 6514 } 6515 if (!strcmp(optarg, "package")) { 6516 if (cpu_subset) 6517 goto error; 6518 show_pkg_only++; 6519 return; 6520 } 6521 if (show_core_only || show_pkg_only) 6522 goto error; 6523 6524 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 6525 if (cpu_subset == NULL) 6526 err(3, "CPU_ALLOC"); 6527 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 6528 6529 CPU_ZERO_S(cpu_subset_size, cpu_subset); 6530 6531 next = optarg; 6532 6533 while (next && *next) { 6534 6535 if (*next == '-') /* no negative cpu numbers */ 6536 goto error; 6537 6538 start = strtoul(next, &next, 10); 6539 6540 if (start >= CPU_SUBSET_MAXCPUS) 6541 goto error; 6542 CPU_SET_S(start, cpu_subset_size, cpu_subset); 6543 6544 if (*next == '\0') 6545 break; 6546 6547 if (*next == ',') { 6548 next += 1; 6549 continue; 6550 } 6551 6552 if (*next == '-') { 6553 next += 1; /* start range */ 6554 } else if (*next == '.') { 6555 next += 1; 6556 if (*next == '.') 6557 next += 1; /* start range */ 6558 else 6559 goto error; 6560 } 6561 6562 end = strtoul(next, &next, 10); 6563 if (end <= start) 6564 goto error; 6565 6566 while (++start <= end) { 6567 if (start >= CPU_SUBSET_MAXCPUS) 6568 goto error; 6569 CPU_SET_S(start, cpu_subset_size, cpu_subset); 6570 } 6571 6572 if (*next == ',') 6573 next += 1; 6574 else if (*next != '\0') 6575 goto error; 6576 } 6577 6578 return; 6579 6580 error: 6581 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 6582 help(); 6583 exit(-1); 6584 } 6585 6586 void cmdline(int argc, char **argv) 6587 { 6588 int opt; 6589 int option_index = 0; 6590 static struct option long_options[] = { 6591 { "add", required_argument, 0, 'a' }, 6592 { "cpu", required_argument, 0, 'c' }, 6593 { "Dump", no_argument, 0, 'D' }, 6594 { "debug", no_argument, 0, 'd' }, /* internal, not documented */ 6595 { "enable", required_argument, 0, 'e' }, 6596 { "interval", required_argument, 0, 'i' }, 6597 { "IPC", no_argument, 0, 'I' }, 6598 { "num_iterations", required_argument, 0, 'n' }, 6599 { "header_iterations", required_argument, 0, 'N' }, 6600 { "help", no_argument, 0, 'h' }, 6601 { "hide", required_argument, 0, 'H' }, // meh, -h taken by --help 6602 { "Joules", no_argument, 0, 'J' }, 6603 { "list", no_argument, 0, 'l' }, 6604 { "out", required_argument, 0, 'o' }, 6605 { "quiet", no_argument, 0, 'q' }, 6606 { "show", required_argument, 0, 's' }, 6607 { "Summary", no_argument, 0, 'S' }, 6608 { "TCC", required_argument, 0, 'T' }, 6609 { "version", no_argument, 0, 'v' }, 6610 { 0, 0, 0, 0 } 6611 }; 6612 6613 progname = argv[0]; 6614 6615 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", long_options, &option_index)) != -1) { 6616 switch (opt) { 6617 case 'a': 6618 parse_add_command(optarg); 6619 break; 6620 case 'c': 6621 parse_cpu_command(optarg); 6622 break; 6623 case 'D': 6624 dump_only++; 6625 break; 6626 case 'e': 6627 /* --enable specified counter */ 6628 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 6629 break; 6630 case 'd': 6631 debug++; 6632 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6633 break; 6634 case 'H': 6635 /* 6636 * --hide: do not show those specified 6637 * multiple invocations simply clear more bits in enabled mask 6638 */ 6639 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 6640 break; 6641 case 'h': 6642 default: 6643 help(); 6644 exit(1); 6645 case 'i': 6646 { 6647 double interval = strtod(optarg, NULL); 6648 6649 if (interval < 0.001) { 6650 fprintf(outf, "interval %f seconds is too small\n", interval); 6651 exit(2); 6652 } 6653 6654 interval_tv.tv_sec = interval_ts.tv_sec = interval; 6655 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 6656 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 6657 } 6658 break; 6659 case 'J': 6660 rapl_joules++; 6661 break; 6662 case 'l': 6663 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6664 list_header_only++; 6665 quiet++; 6666 break; 6667 case 'o': 6668 outf = fopen_or_die(optarg, "w"); 6669 break; 6670 case 'q': 6671 quiet = 1; 6672 break; 6673 case 'n': 6674 num_iterations = strtod(optarg, NULL); 6675 6676 if (num_iterations <= 0) { 6677 fprintf(outf, "iterations %d should be positive number\n", num_iterations); 6678 exit(2); 6679 } 6680 break; 6681 case 'N': 6682 header_iterations = strtod(optarg, NULL); 6683 6684 if (header_iterations <= 0) { 6685 fprintf(outf, "iterations %d should be positive number\n", header_iterations); 6686 exit(2); 6687 } 6688 break; 6689 case 's': 6690 /* 6691 * --show: show only those specified 6692 * The 1st invocation will clear and replace the enabled mask 6693 * subsequent invocations can add to it. 6694 */ 6695 if (shown == 0) 6696 bic_enabled = bic_lookup(optarg, SHOW_LIST); 6697 else 6698 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 6699 shown = 1; 6700 break; 6701 case 'S': 6702 summary_only++; 6703 break; 6704 case 'T': 6705 tj_max_override = atoi(optarg); 6706 break; 6707 case 'v': 6708 print_version(); 6709 exit(0); 6710 break; 6711 } 6712 } 6713 } 6714 6715 int main(int argc, char **argv) 6716 { 6717 outf = stderr; 6718 cmdline(argc, argv); 6719 6720 if (!quiet) { 6721 print_version(); 6722 print_bootcmd(); 6723 } 6724 6725 probe_sysfs(); 6726 6727 turbostat_init(); 6728 6729 msr_sum_record(); 6730 6731 /* dump counters and exit */ 6732 if (dump_only) 6733 return get_and_dump_counters(); 6734 6735 /* list header and exit */ 6736 if (list_header_only) { 6737 print_header(","); 6738 flush_output_stdout(); 6739 return 0; 6740 } 6741 6742 /* 6743 * if any params left, it must be a command to fork 6744 */ 6745 if (argc - optind) 6746 return fork_it(argv + optind); 6747 else 6748 turbostat_loop(); 6749 6750 return 0; 6751 } 6752