1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * turbostat -- show CPU frequency and C-state residency 4 * on modern Intel and AMD processors. 5 * 6 * Copyright (c) 2013 Intel Corporation. 7 * Len Brown <len.brown@intel.com> 8 */ 9 10 #define _GNU_SOURCE 11 #include MSRHEADER 12 #include INTEL_FAMILY_HEADER 13 #include <stdarg.h> 14 #include <stdio.h> 15 #include <err.h> 16 #include <unistd.h> 17 #include <sys/types.h> 18 #include <sys/wait.h> 19 #include <sys/stat.h> 20 #include <sys/select.h> 21 #include <sys/resource.h> 22 #include <fcntl.h> 23 #include <signal.h> 24 #include <sys/time.h> 25 #include <stdlib.h> 26 #include <getopt.h> 27 #include <dirent.h> 28 #include <string.h> 29 #include <ctype.h> 30 #include <sched.h> 31 #include <time.h> 32 #include <cpuid.h> 33 #include <sys/capability.h> 34 #include <errno.h> 35 #include <math.h> 36 37 char *proc_stat = "/proc/stat"; 38 FILE *outf; 39 int *fd_percpu; 40 struct timeval interval_tv = {5, 0}; 41 struct timespec interval_ts = {5, 0}; 42 unsigned int num_iterations; 43 unsigned int debug; 44 unsigned int quiet; 45 unsigned int shown; 46 unsigned int sums_need_wide_columns; 47 unsigned int rapl_joules; 48 unsigned int summary_only; 49 unsigned int list_header_only; 50 unsigned int dump_only; 51 unsigned int do_snb_cstates; 52 unsigned int do_knl_cstates; 53 unsigned int do_slm_cstates; 54 unsigned int use_c1_residency_msr; 55 unsigned int has_aperf; 56 unsigned int has_epb; 57 unsigned int do_irtl_snb; 58 unsigned int do_irtl_hsw; 59 unsigned int units = 1000000; /* MHz etc */ 60 unsigned int genuine_intel; 61 unsigned int authentic_amd; 62 unsigned int hygon_genuine; 63 unsigned int max_level, max_extended_level; 64 unsigned int has_invariant_tsc; 65 unsigned int do_nhm_platform_info; 66 unsigned int no_MSR_MISC_PWR_MGMT; 67 unsigned int aperf_mperf_multiplier = 1; 68 double bclk; 69 double base_hz; 70 unsigned int has_base_hz; 71 double tsc_tweak = 1.0; 72 unsigned int show_pkg_only; 73 unsigned int show_core_only; 74 char *output_buffer, *outp; 75 unsigned int do_rapl; 76 unsigned int do_dts; 77 unsigned int do_ptm; 78 unsigned long long gfx_cur_rc6_ms; 79 unsigned long long cpuidle_cur_cpu_lpi_us; 80 unsigned long long cpuidle_cur_sys_lpi_us; 81 unsigned int gfx_cur_mhz; 82 unsigned int tcc_activation_temp; 83 unsigned int tcc_activation_temp_override; 84 double rapl_power_units, rapl_time_units; 85 double rapl_dram_energy_units, rapl_energy_units; 86 double rapl_joule_counter_range; 87 unsigned int do_core_perf_limit_reasons; 88 unsigned int has_automatic_cstate_conversion; 89 unsigned int do_gfx_perf_limit_reasons; 90 unsigned int do_ring_perf_limit_reasons; 91 unsigned int crystal_hz; 92 unsigned long long tsc_hz; 93 int base_cpu; 94 double discover_bclk(unsigned int family, unsigned int model); 95 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 96 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 97 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 98 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 99 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 100 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 101 unsigned int has_misc_feature_control; 102 unsigned int first_counter_read = 1; 103 int ignore_stdin; 104 105 #define RAPL_PKG (1 << 0) 106 /* 0x610 MSR_PKG_POWER_LIMIT */ 107 /* 0x611 MSR_PKG_ENERGY_STATUS */ 108 #define RAPL_PKG_PERF_STATUS (1 << 1) 109 /* 0x613 MSR_PKG_PERF_STATUS */ 110 #define RAPL_PKG_POWER_INFO (1 << 2) 111 /* 0x614 MSR_PKG_POWER_INFO */ 112 113 #define RAPL_DRAM (1 << 3) 114 /* 0x618 MSR_DRAM_POWER_LIMIT */ 115 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 116 #define RAPL_DRAM_PERF_STATUS (1 << 4) 117 /* 0x61b MSR_DRAM_PERF_STATUS */ 118 #define RAPL_DRAM_POWER_INFO (1 << 5) 119 /* 0x61c MSR_DRAM_POWER_INFO */ 120 121 #define RAPL_CORES_POWER_LIMIT (1 << 6) 122 /* 0x638 MSR_PP0_POWER_LIMIT */ 123 #define RAPL_CORE_POLICY (1 << 7) 124 /* 0x63a MSR_PP0_POLICY */ 125 126 #define RAPL_GFX (1 << 8) 127 /* 0x640 MSR_PP1_POWER_LIMIT */ 128 /* 0x641 MSR_PP1_ENERGY_STATUS */ 129 /* 0x642 MSR_PP1_POLICY */ 130 131 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 132 /* 0x639 MSR_PP0_ENERGY_STATUS */ 133 #define RAPL_PER_CORE_ENERGY (1 << 10) 134 /* Indicates cores energy collection is per-core, 135 * not per-package. */ 136 #define RAPL_AMD_F17H (1 << 11) 137 /* 0xc0010299 MSR_RAPL_PWR_UNIT */ 138 /* 0xc001029a MSR_CORE_ENERGY_STAT */ 139 /* 0xc001029b MSR_PKG_ENERGY_STAT */ 140 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 141 #define TJMAX_DEFAULT 100 142 143 /* MSRs that are not yet in the kernel-provided header. */ 144 #define MSR_RAPL_PWR_UNIT 0xc0010299 145 #define MSR_CORE_ENERGY_STAT 0xc001029a 146 #define MSR_PKG_ENERGY_STAT 0xc001029b 147 148 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 149 150 /* 151 * buffer size used by sscanf() for added column names 152 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 153 */ 154 #define NAME_BYTES 20 155 #define PATH_BYTES 128 156 157 int backwards_count; 158 char *progname; 159 160 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 161 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset; 162 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size; 163 #define MAX_ADDED_COUNTERS 8 164 #define MAX_ADDED_THREAD_COUNTERS 24 165 #define BITMASK_SIZE 32 166 167 struct thread_data { 168 struct timeval tv_begin; 169 struct timeval tv_end; 170 struct timeval tv_delta; 171 unsigned long long tsc; 172 unsigned long long aperf; 173 unsigned long long mperf; 174 unsigned long long c1; 175 unsigned long long irq_count; 176 unsigned int smi_count; 177 unsigned int cpu_id; 178 unsigned int apic_id; 179 unsigned int x2apic_id; 180 unsigned int flags; 181 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 182 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 183 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 184 } *thread_even, *thread_odd; 185 186 struct core_data { 187 unsigned long long c3; 188 unsigned long long c6; 189 unsigned long long c7; 190 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 191 unsigned int core_temp_c; 192 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */ 193 unsigned int core_id; 194 unsigned long long counter[MAX_ADDED_COUNTERS]; 195 } *core_even, *core_odd; 196 197 struct pkg_data { 198 unsigned long long pc2; 199 unsigned long long pc3; 200 unsigned long long pc6; 201 unsigned long long pc7; 202 unsigned long long pc8; 203 unsigned long long pc9; 204 unsigned long long pc10; 205 unsigned long long cpu_lpi; 206 unsigned long long sys_lpi; 207 unsigned long long pkg_wtd_core_c0; 208 unsigned long long pkg_any_core_c0; 209 unsigned long long pkg_any_gfxe_c0; 210 unsigned long long pkg_both_core_gfxe_c0; 211 long long gfx_rc6_ms; 212 unsigned int gfx_mhz; 213 unsigned int package_id; 214 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 215 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 216 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 217 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 218 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 219 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 220 unsigned int pkg_temp_c; 221 unsigned long long counter[MAX_ADDED_COUNTERS]; 222 } *package_even, *package_odd; 223 224 #define ODD_COUNTERS thread_odd, core_odd, package_odd 225 #define EVEN_COUNTERS thread_even, core_even, package_even 226 227 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 228 ((thread_base) + \ 229 ((pkg_no) * \ 230 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 231 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 232 ((core_no) * topo.threads_per_core) + \ 233 (thread_no)) 234 235 #define GET_CORE(core_base, core_no, node_no, pkg_no) \ 236 ((core_base) + \ 237 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 238 ((node_no) * topo.cores_per_node) + \ 239 (core_no)) 240 241 242 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 243 244 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; 245 enum counter_type {COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC}; 246 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; 247 248 struct msr_counter { 249 unsigned int msr_num; 250 char name[NAME_BYTES]; 251 char path[PATH_BYTES]; 252 unsigned int width; 253 enum counter_type type; 254 enum counter_format format; 255 struct msr_counter *next; 256 unsigned int flags; 257 #define FLAGS_HIDE (1 << 0) 258 #define FLAGS_SHOW (1 << 1) 259 #define SYSFS_PERCPU (1 << 1) 260 }; 261 262 struct sys_counters { 263 unsigned int added_thread_counters; 264 unsigned int added_core_counters; 265 unsigned int added_package_counters; 266 struct msr_counter *tp; 267 struct msr_counter *cp; 268 struct msr_counter *pp; 269 } sys; 270 271 struct system_summary { 272 struct thread_data threads; 273 struct core_data cores; 274 struct pkg_data packages; 275 } average; 276 277 struct cpu_topology { 278 int physical_package_id; 279 int die_id; 280 int logical_cpu_id; 281 int physical_node_id; 282 int logical_node_id; /* 0-based count within the package */ 283 int physical_core_id; 284 int thread_id; 285 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 286 } *cpus; 287 288 struct topo_params { 289 int num_packages; 290 int num_die; 291 int num_cpus; 292 int num_cores; 293 int max_cpu_num; 294 int max_node_num; 295 int nodes_per_pkg; 296 int cores_per_node; 297 int threads_per_core; 298 } topo; 299 300 struct timeval tv_even, tv_odd, tv_delta; 301 302 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 303 int *irqs_per_cpu; /* indexed by cpu_num */ 304 305 void setup_all_buffers(void); 306 307 char *sys_lpi_file; 308 char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us"; 309 char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec"; 310 311 int cpu_is_not_present(int cpu) 312 { 313 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 314 } 315 /* 316 * run func(thread, core, package) in topology order 317 * skip non-present cpus 318 */ 319 320 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 321 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 322 { 323 int retval, pkg_no, core_no, thread_no, node_no; 324 325 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 326 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) { 327 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 328 for (thread_no = 0; thread_no < 329 topo.threads_per_core; ++thread_no) { 330 struct thread_data *t; 331 struct core_data *c; 332 struct pkg_data *p; 333 334 t = GET_THREAD(thread_base, thread_no, 335 core_no, node_no, 336 pkg_no); 337 338 if (cpu_is_not_present(t->cpu_id)) 339 continue; 340 341 c = GET_CORE(core_base, core_no, 342 node_no, pkg_no); 343 p = GET_PKG(pkg_base, pkg_no); 344 345 retval = func(t, c, p); 346 if (retval) 347 return retval; 348 } 349 } 350 } 351 } 352 return 0; 353 } 354 355 int cpu_migrate(int cpu) 356 { 357 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 358 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 359 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 360 return -1; 361 else 362 return 0; 363 } 364 int get_msr_fd(int cpu) 365 { 366 char pathname[32]; 367 int fd; 368 369 fd = fd_percpu[cpu]; 370 371 if (fd) 372 return fd; 373 374 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 375 fd = open(pathname, O_RDONLY); 376 if (fd < 0) 377 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 378 379 fd_percpu[cpu] = fd; 380 381 return fd; 382 } 383 384 int get_msr(int cpu, off_t offset, unsigned long long *msr) 385 { 386 ssize_t retval; 387 388 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 389 390 if (retval != sizeof *msr) 391 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 392 393 return 0; 394 } 395 396 /* 397 * This list matches the column headers, except 398 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 399 * 2. Core and CPU are moved to the end, we can't have strings that contain them 400 * matching on them for --show and --hide. 401 */ 402 struct msr_counter bic[] = { 403 { 0x0, "usec" }, 404 { 0x0, "Time_Of_Day_Seconds" }, 405 { 0x0, "Package" }, 406 { 0x0, "Node" }, 407 { 0x0, "Avg_MHz" }, 408 { 0x0, "Busy%" }, 409 { 0x0, "Bzy_MHz" }, 410 { 0x0, "TSC_MHz" }, 411 { 0x0, "IRQ" }, 412 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL}, 413 { 0x0, "sysfs" }, 414 { 0x0, "CPU%c1" }, 415 { 0x0, "CPU%c3" }, 416 { 0x0, "CPU%c6" }, 417 { 0x0, "CPU%c7" }, 418 { 0x0, "ThreadC" }, 419 { 0x0, "CoreTmp" }, 420 { 0x0, "CoreCnt" }, 421 { 0x0, "PkgTmp" }, 422 { 0x0, "GFX%rc6" }, 423 { 0x0, "GFXMHz" }, 424 { 0x0, "Pkg%pc2" }, 425 { 0x0, "Pkg%pc3" }, 426 { 0x0, "Pkg%pc6" }, 427 { 0x0, "Pkg%pc7" }, 428 { 0x0, "Pkg%pc8" }, 429 { 0x0, "Pkg%pc9" }, 430 { 0x0, "Pk%pc10" }, 431 { 0x0, "CPU%LPI" }, 432 { 0x0, "SYS%LPI" }, 433 { 0x0, "PkgWatt" }, 434 { 0x0, "CorWatt" }, 435 { 0x0, "GFXWatt" }, 436 { 0x0, "PkgCnt" }, 437 { 0x0, "RAMWatt" }, 438 { 0x0, "PKG_%" }, 439 { 0x0, "RAM_%" }, 440 { 0x0, "Pkg_J" }, 441 { 0x0, "Cor_J" }, 442 { 0x0, "GFX_J" }, 443 { 0x0, "RAM_J" }, 444 { 0x0, "Mod%c6" }, 445 { 0x0, "Totl%C0" }, 446 { 0x0, "Any%C0" }, 447 { 0x0, "GFX%C0" }, 448 { 0x0, "CPUGFX%" }, 449 { 0x0, "Core" }, 450 { 0x0, "CPU" }, 451 { 0x0, "APIC" }, 452 { 0x0, "X2APIC" }, 453 { 0x0, "Die" }, 454 }; 455 456 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 457 #define BIC_USEC (1ULL << 0) 458 #define BIC_TOD (1ULL << 1) 459 #define BIC_Package (1ULL << 2) 460 #define BIC_Node (1ULL << 3) 461 #define BIC_Avg_MHz (1ULL << 4) 462 #define BIC_Busy (1ULL << 5) 463 #define BIC_Bzy_MHz (1ULL << 6) 464 #define BIC_TSC_MHz (1ULL << 7) 465 #define BIC_IRQ (1ULL << 8) 466 #define BIC_SMI (1ULL << 9) 467 #define BIC_sysfs (1ULL << 10) 468 #define BIC_CPU_c1 (1ULL << 11) 469 #define BIC_CPU_c3 (1ULL << 12) 470 #define BIC_CPU_c6 (1ULL << 13) 471 #define BIC_CPU_c7 (1ULL << 14) 472 #define BIC_ThreadC (1ULL << 15) 473 #define BIC_CoreTmp (1ULL << 16) 474 #define BIC_CoreCnt (1ULL << 17) 475 #define BIC_PkgTmp (1ULL << 18) 476 #define BIC_GFX_rc6 (1ULL << 19) 477 #define BIC_GFXMHz (1ULL << 20) 478 #define BIC_Pkgpc2 (1ULL << 21) 479 #define BIC_Pkgpc3 (1ULL << 22) 480 #define BIC_Pkgpc6 (1ULL << 23) 481 #define BIC_Pkgpc7 (1ULL << 24) 482 #define BIC_Pkgpc8 (1ULL << 25) 483 #define BIC_Pkgpc9 (1ULL << 26) 484 #define BIC_Pkgpc10 (1ULL << 27) 485 #define BIC_CPU_LPI (1ULL << 28) 486 #define BIC_SYS_LPI (1ULL << 29) 487 #define BIC_PkgWatt (1ULL << 30) 488 #define BIC_CorWatt (1ULL << 31) 489 #define BIC_GFXWatt (1ULL << 32) 490 #define BIC_PkgCnt (1ULL << 33) 491 #define BIC_RAMWatt (1ULL << 34) 492 #define BIC_PKG__ (1ULL << 35) 493 #define BIC_RAM__ (1ULL << 36) 494 #define BIC_Pkg_J (1ULL << 37) 495 #define BIC_Cor_J (1ULL << 38) 496 #define BIC_GFX_J (1ULL << 39) 497 #define BIC_RAM_J (1ULL << 40) 498 #define BIC_Mod_c6 (1ULL << 41) 499 #define BIC_Totl_c0 (1ULL << 42) 500 #define BIC_Any_c0 (1ULL << 43) 501 #define BIC_GFX_c0 (1ULL << 44) 502 #define BIC_CPUGFX (1ULL << 45) 503 #define BIC_Core (1ULL << 46) 504 #define BIC_CPU (1ULL << 47) 505 #define BIC_APIC (1ULL << 48) 506 #define BIC_X2APIC (1ULL << 49) 507 #define BIC_Die (1ULL << 50) 508 509 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 510 511 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 512 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 513 514 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 515 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME) 516 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 517 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 518 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 519 520 521 #define MAX_DEFERRED 16 522 char *deferred_skip_names[MAX_DEFERRED]; 523 int deferred_skip_index; 524 525 /* 526 * HIDE_LIST - hide this list of counters, show the rest [default] 527 * SHOW_LIST - show this list of counters, hide the rest 528 */ 529 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 530 531 void help(void) 532 { 533 fprintf(outf, 534 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 535 "\n" 536 "Turbostat forks the specified COMMAND and prints statistics\n" 537 "when COMMAND completes.\n" 538 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 539 "to print statistics, until interrupted.\n" 540 " -a, --add add a counter\n" 541 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 542 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n" 543 " {core | package | j,k,l..m,n-p }\n" 544 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n" 545 " -D, --Dump displays the raw counter values\n" 546 " -e, --enable [all | column]\n" 547 " shows all or the specified disabled column\n" 548 " -H, --hide [column|column,column,...]\n" 549 " hide the specified column(s)\n" 550 " -i, --interval sec.subsec\n" 551 " Override default 5-second measurement interval\n" 552 " -J, --Joules displays energy in Joules instead of Watts\n" 553 " -l, --list list column headers only\n" 554 " -n, --num_iterations num\n" 555 " number of the measurement iterations\n" 556 " -o, --out file\n" 557 " create or truncate \"file\" for all output\n" 558 " -q, --quiet skip decoding system configuration header\n" 559 " -s, --show [column|column,column,...]\n" 560 " show only the specified column(s)\n" 561 " -S, --Summary\n" 562 " limits output to 1-line system summary per interval\n" 563 " -T, --TCC temperature\n" 564 " sets the Thermal Control Circuit temperature in\n" 565 " degrees Celsius\n" 566 " -h, --help print this help message\n" 567 " -v, --version print version information\n" 568 "\n" 569 "For more help, run \"man turbostat\"\n"); 570 } 571 572 /* 573 * bic_lookup 574 * for all the strings in comma separate name_list, 575 * set the approprate bit in return value. 576 */ 577 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 578 { 579 int i; 580 unsigned long long retval = 0; 581 582 while (name_list) { 583 char *comma; 584 585 comma = strchr(name_list, ','); 586 587 if (comma) 588 *comma = '\0'; 589 590 if (!strcmp(name_list, "all")) 591 return ~0; 592 593 for (i = 0; i < MAX_BIC; ++i) { 594 if (!strcmp(name_list, bic[i].name)) { 595 retval |= (1ULL << i); 596 break; 597 } 598 } 599 if (i == MAX_BIC) { 600 if (mode == SHOW_LIST) { 601 fprintf(stderr, "Invalid counter name: %s\n", name_list); 602 exit(-1); 603 } 604 deferred_skip_names[deferred_skip_index++] = name_list; 605 if (debug) 606 fprintf(stderr, "deferred \"%s\"\n", name_list); 607 if (deferred_skip_index >= MAX_DEFERRED) { 608 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 609 MAX_DEFERRED, name_list); 610 help(); 611 exit(1); 612 } 613 } 614 615 name_list = comma; 616 if (name_list) 617 name_list++; 618 619 } 620 return retval; 621 } 622 623 624 void print_header(char *delim) 625 { 626 struct msr_counter *mp; 627 int printed = 0; 628 629 if (DO_BIC(BIC_USEC)) 630 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 631 if (DO_BIC(BIC_TOD)) 632 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 633 if (DO_BIC(BIC_Package)) 634 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 635 if (DO_BIC(BIC_Die)) 636 outp += sprintf(outp, "%sDie", (printed++ ? delim : "")); 637 if (DO_BIC(BIC_Node)) 638 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 639 if (DO_BIC(BIC_Core)) 640 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 641 if (DO_BIC(BIC_CPU)) 642 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 643 if (DO_BIC(BIC_APIC)) 644 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 645 if (DO_BIC(BIC_X2APIC)) 646 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 647 if (DO_BIC(BIC_Avg_MHz)) 648 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 649 if (DO_BIC(BIC_Busy)) 650 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 651 if (DO_BIC(BIC_Bzy_MHz)) 652 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 653 if (DO_BIC(BIC_TSC_MHz)) 654 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 655 656 if (DO_BIC(BIC_IRQ)) { 657 if (sums_need_wide_columns) 658 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 659 else 660 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 661 } 662 663 if (DO_BIC(BIC_SMI)) 664 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 665 666 for (mp = sys.tp; mp; mp = mp->next) { 667 668 if (mp->format == FORMAT_RAW) { 669 if (mp->width == 64) 670 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 671 else 672 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 673 } else { 674 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 675 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 676 else 677 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 678 } 679 } 680 681 if (DO_BIC(BIC_CPU_c1)) 682 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 683 if (DO_BIC(BIC_CPU_c3)) 684 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 685 if (DO_BIC(BIC_CPU_c6)) 686 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 687 if (DO_BIC(BIC_CPU_c7)) 688 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 689 690 if (DO_BIC(BIC_Mod_c6)) 691 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 692 693 if (DO_BIC(BIC_CoreTmp)) 694 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 695 696 if (do_rapl && !rapl_joules) { 697 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 698 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 699 } else if (do_rapl && rapl_joules) { 700 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 701 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 702 } 703 704 for (mp = sys.cp; mp; mp = mp->next) { 705 if (mp->format == FORMAT_RAW) { 706 if (mp->width == 64) 707 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 708 else 709 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 710 } else { 711 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 712 outp += sprintf(outp, "%s%8s", delim, mp->name); 713 else 714 outp += sprintf(outp, "%s%s", delim, mp->name); 715 } 716 } 717 718 if (DO_BIC(BIC_PkgTmp)) 719 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 720 721 if (DO_BIC(BIC_GFX_rc6)) 722 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 723 724 if (DO_BIC(BIC_GFXMHz)) 725 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 726 727 if (DO_BIC(BIC_Totl_c0)) 728 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 729 if (DO_BIC(BIC_Any_c0)) 730 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 731 if (DO_BIC(BIC_GFX_c0)) 732 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 733 if (DO_BIC(BIC_CPUGFX)) 734 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 735 736 if (DO_BIC(BIC_Pkgpc2)) 737 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 738 if (DO_BIC(BIC_Pkgpc3)) 739 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 740 if (DO_BIC(BIC_Pkgpc6)) 741 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 742 if (DO_BIC(BIC_Pkgpc7)) 743 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 744 if (DO_BIC(BIC_Pkgpc8)) 745 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 746 if (DO_BIC(BIC_Pkgpc9)) 747 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 748 if (DO_BIC(BIC_Pkgpc10)) 749 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 750 if (DO_BIC(BIC_CPU_LPI)) 751 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 752 if (DO_BIC(BIC_SYS_LPI)) 753 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 754 755 if (do_rapl && !rapl_joules) { 756 if (DO_BIC(BIC_PkgWatt)) 757 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 758 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 759 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 760 if (DO_BIC(BIC_GFXWatt)) 761 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 762 if (DO_BIC(BIC_RAMWatt)) 763 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 764 if (DO_BIC(BIC_PKG__)) 765 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 766 if (DO_BIC(BIC_RAM__)) 767 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 768 } else if (do_rapl && rapl_joules) { 769 if (DO_BIC(BIC_Pkg_J)) 770 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 771 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 772 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 773 if (DO_BIC(BIC_GFX_J)) 774 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 775 if (DO_BIC(BIC_RAM_J)) 776 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 777 if (DO_BIC(BIC_PKG__)) 778 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 779 if (DO_BIC(BIC_RAM__)) 780 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 781 } 782 for (mp = sys.pp; mp; mp = mp->next) { 783 if (mp->format == FORMAT_RAW) { 784 if (mp->width == 64) 785 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 786 else 787 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 788 } else { 789 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 790 outp += sprintf(outp, "%s%8s", delim, mp->name); 791 else 792 outp += sprintf(outp, "%s%s", delim, mp->name); 793 } 794 } 795 796 outp += sprintf(outp, "\n"); 797 } 798 799 int dump_counters(struct thread_data *t, struct core_data *c, 800 struct pkg_data *p) 801 { 802 int i; 803 struct msr_counter *mp; 804 805 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 806 807 if (t) { 808 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 809 t->cpu_id, t->flags); 810 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 811 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 812 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 813 outp += sprintf(outp, "c1: %016llX\n", t->c1); 814 815 if (DO_BIC(BIC_IRQ)) 816 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 817 if (DO_BIC(BIC_SMI)) 818 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 819 820 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 821 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", 822 i, mp->msr_num, t->counter[i]); 823 } 824 } 825 826 if (c) { 827 outp += sprintf(outp, "core: %d\n", c->core_id); 828 outp += sprintf(outp, "c3: %016llX\n", c->c3); 829 outp += sprintf(outp, "c6: %016llX\n", c->c6); 830 outp += sprintf(outp, "c7: %016llX\n", c->c7); 831 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 832 outp += sprintf(outp, "Joules: %0X\n", c->core_energy); 833 834 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 835 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", 836 i, mp->msr_num, c->counter[i]); 837 } 838 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 839 } 840 841 if (p) { 842 outp += sprintf(outp, "package: %d\n", p->package_id); 843 844 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 845 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 846 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 847 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 848 849 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 850 if (DO_BIC(BIC_Pkgpc3)) 851 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 852 if (DO_BIC(BIC_Pkgpc6)) 853 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 854 if (DO_BIC(BIC_Pkgpc7)) 855 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 856 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 857 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 858 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 859 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 860 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 861 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); 862 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); 863 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); 864 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); 865 outp += sprintf(outp, "Throttle PKG: %0X\n", 866 p->rapl_pkg_perf_status); 867 outp += sprintf(outp, "Throttle RAM: %0X\n", 868 p->rapl_dram_perf_status); 869 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 870 871 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 872 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", 873 i, mp->msr_num, p->counter[i]); 874 } 875 } 876 877 outp += sprintf(outp, "\n"); 878 879 return 0; 880 } 881 882 /* 883 * column formatting convention & formats 884 */ 885 int format_counters(struct thread_data *t, struct core_data *c, 886 struct pkg_data *p) 887 { 888 double interval_float, tsc; 889 char *fmt8; 890 int i; 891 struct msr_counter *mp; 892 char *delim = "\t"; 893 int printed = 0; 894 895 /* if showing only 1st thread in core and this isn't one, bail out */ 896 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 897 return 0; 898 899 /* if showing only 1st thread in pkg and this isn't one, bail out */ 900 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 901 return 0; 902 903 /*if not summary line and --cpu is used */ 904 if ((t != &average.threads) && 905 (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 906 return 0; 907 908 if (DO_BIC(BIC_USEC)) { 909 /* on each row, print how many usec each timestamp took to gather */ 910 struct timeval tv; 911 912 timersub(&t->tv_end, &t->tv_begin, &tv); 913 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 914 } 915 916 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 917 if (DO_BIC(BIC_TOD)) 918 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 919 920 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec/1000000.0; 921 922 tsc = t->tsc * tsc_tweak; 923 924 /* topo columns, print blanks on 1st (average) line */ 925 if (t == &average.threads) { 926 if (DO_BIC(BIC_Package)) 927 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 928 if (DO_BIC(BIC_Die)) 929 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 930 if (DO_BIC(BIC_Node)) 931 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 932 if (DO_BIC(BIC_Core)) 933 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 934 if (DO_BIC(BIC_CPU)) 935 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 936 if (DO_BIC(BIC_APIC)) 937 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 938 if (DO_BIC(BIC_X2APIC)) 939 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 940 } else { 941 if (DO_BIC(BIC_Package)) { 942 if (p) 943 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 944 else 945 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 946 } 947 if (DO_BIC(BIC_Die)) { 948 if (c) 949 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id); 950 else 951 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 952 } 953 if (DO_BIC(BIC_Node)) { 954 if (t) 955 outp += sprintf(outp, "%s%d", 956 (printed++ ? delim : ""), 957 cpus[t->cpu_id].physical_node_id); 958 else 959 outp += sprintf(outp, "%s-", 960 (printed++ ? delim : "")); 961 } 962 if (DO_BIC(BIC_Core)) { 963 if (c) 964 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 965 else 966 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 967 } 968 if (DO_BIC(BIC_CPU)) 969 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 970 if (DO_BIC(BIC_APIC)) 971 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 972 if (DO_BIC(BIC_X2APIC)) 973 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 974 } 975 976 if (DO_BIC(BIC_Avg_MHz)) 977 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 978 1.0 / units * t->aperf / interval_float); 979 980 if (DO_BIC(BIC_Busy)) 981 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf/tsc); 982 983 if (DO_BIC(BIC_Bzy_MHz)) { 984 if (has_base_hz) 985 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 986 else 987 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 988 tsc / units * t->aperf / t->mperf / interval_float); 989 } 990 991 if (DO_BIC(BIC_TSC_MHz)) 992 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc/units/interval_float); 993 994 /* IRQ */ 995 if (DO_BIC(BIC_IRQ)) { 996 if (sums_need_wide_columns) 997 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 998 else 999 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 1000 } 1001 1002 /* SMI */ 1003 if (DO_BIC(BIC_SMI)) 1004 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 1005 1006 /* Added counters */ 1007 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1008 if (mp->format == FORMAT_RAW) { 1009 if (mp->width == 32) 1010 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) t->counter[i]); 1011 else 1012 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 1013 } else if (mp->format == FORMAT_DELTA) { 1014 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1015 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 1016 else 1017 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 1018 } else if (mp->format == FORMAT_PERCENT) { 1019 if (mp->type == COUNTER_USEC) 1020 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), t->counter[i]/interval_float/10000); 1021 else 1022 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i]/tsc); 1023 } 1024 } 1025 1026 /* C1 */ 1027 if (DO_BIC(BIC_CPU_c1)) 1028 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1/tsc); 1029 1030 1031 /* print per-core data only for 1st thread in core */ 1032 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1033 goto done; 1034 1035 if (DO_BIC(BIC_CPU_c3)) 1036 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3/tsc); 1037 if (DO_BIC(BIC_CPU_c6)) 1038 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6/tsc); 1039 if (DO_BIC(BIC_CPU_c7)) 1040 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7/tsc); 1041 1042 /* Mod%c6 */ 1043 if (DO_BIC(BIC_Mod_c6)) 1044 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 1045 1046 if (DO_BIC(BIC_CoreTmp)) 1047 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1048 1049 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1050 if (mp->format == FORMAT_RAW) { 1051 if (mp->width == 32) 1052 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) c->counter[i]); 1053 else 1054 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1055 } else if (mp->format == FORMAT_DELTA) { 1056 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1057 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1058 else 1059 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1060 } else if (mp->format == FORMAT_PERCENT) { 1061 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i]/tsc); 1062 } 1063 } 1064 1065 /* 1066 * If measurement interval exceeds minimum RAPL Joule Counter range, 1067 * indicate that results are suspect by printing "**" in fraction place. 1068 */ 1069 if (interval_float < rapl_joule_counter_range) 1070 fmt8 = "%s%.2f"; 1071 else 1072 fmt8 = "%6.0f**"; 1073 1074 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1075 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float); 1076 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1077 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units); 1078 1079 /* print per-package data only for 1st core in package */ 1080 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1081 goto done; 1082 1083 /* PkgTmp */ 1084 if (DO_BIC(BIC_PkgTmp)) 1085 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1086 1087 /* GFXrc6 */ 1088 if (DO_BIC(BIC_GFX_rc6)) { 1089 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1090 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1091 } else { 1092 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1093 p->gfx_rc6_ms / 10.0 / interval_float); 1094 } 1095 } 1096 1097 /* GFXMHz */ 1098 if (DO_BIC(BIC_GFXMHz)) 1099 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1100 1101 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1102 if (DO_BIC(BIC_Totl_c0)) 1103 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0/tsc); 1104 if (DO_BIC(BIC_Any_c0)) 1105 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0/tsc); 1106 if (DO_BIC(BIC_GFX_c0)) 1107 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0/tsc); 1108 if (DO_BIC(BIC_CPUGFX)) 1109 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0/tsc); 1110 1111 if (DO_BIC(BIC_Pkgpc2)) 1112 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2/tsc); 1113 if (DO_BIC(BIC_Pkgpc3)) 1114 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3/tsc); 1115 if (DO_BIC(BIC_Pkgpc6)) 1116 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6/tsc); 1117 if (DO_BIC(BIC_Pkgpc7)) 1118 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7/tsc); 1119 if (DO_BIC(BIC_Pkgpc8)) 1120 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8/tsc); 1121 if (DO_BIC(BIC_Pkgpc9)) 1122 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9/tsc); 1123 if (DO_BIC(BIC_Pkgpc10)) 1124 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10/tsc); 1125 1126 if (DO_BIC(BIC_CPU_LPI)) 1127 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1128 if (DO_BIC(BIC_SYS_LPI)) 1129 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1130 1131 if (DO_BIC(BIC_PkgWatt)) 1132 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1133 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1134 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1135 if (DO_BIC(BIC_GFXWatt)) 1136 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1137 if (DO_BIC(BIC_RAMWatt)) 1138 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units / interval_float); 1139 if (DO_BIC(BIC_Pkg_J)) 1140 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 1141 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1142 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 1143 if (DO_BIC(BIC_GFX_J)) 1144 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 1145 if (DO_BIC(BIC_RAM_J)) 1146 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 1147 if (DO_BIC(BIC_PKG__)) 1148 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 1149 if (DO_BIC(BIC_RAM__)) 1150 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 1151 1152 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1153 if (mp->format == FORMAT_RAW) { 1154 if (mp->width == 32) 1155 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) p->counter[i]); 1156 else 1157 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 1158 } else if (mp->format == FORMAT_DELTA) { 1159 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1160 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 1161 else 1162 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 1163 } else if (mp->format == FORMAT_PERCENT) { 1164 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i]/tsc); 1165 } 1166 } 1167 1168 done: 1169 if (*(outp - 1) != '\n') 1170 outp += sprintf(outp, "\n"); 1171 1172 return 0; 1173 } 1174 1175 void flush_output_stdout(void) 1176 { 1177 FILE *filep; 1178 1179 if (outf == stderr) 1180 filep = stdout; 1181 else 1182 filep = outf; 1183 1184 fputs(output_buffer, filep); 1185 fflush(filep); 1186 1187 outp = output_buffer; 1188 } 1189 void flush_output_stderr(void) 1190 { 1191 fputs(output_buffer, outf); 1192 fflush(outf); 1193 outp = output_buffer; 1194 } 1195 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1196 { 1197 static int printed; 1198 1199 if (!printed || !summary_only) 1200 print_header("\t"); 1201 1202 format_counters(&average.threads, &average.cores, &average.packages); 1203 1204 printed = 1; 1205 1206 if (summary_only) 1207 return; 1208 1209 for_all_cpus(format_counters, t, c, p); 1210 } 1211 1212 #define DELTA_WRAP32(new, old) \ 1213 if (new > old) { \ 1214 old = new - old; \ 1215 } else { \ 1216 old = 0x100000000 + new - old; \ 1217 } 1218 1219 int 1220 delta_package(struct pkg_data *new, struct pkg_data *old) 1221 { 1222 int i; 1223 struct msr_counter *mp; 1224 1225 1226 if (DO_BIC(BIC_Totl_c0)) 1227 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 1228 if (DO_BIC(BIC_Any_c0)) 1229 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 1230 if (DO_BIC(BIC_GFX_c0)) 1231 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 1232 if (DO_BIC(BIC_CPUGFX)) 1233 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 1234 1235 old->pc2 = new->pc2 - old->pc2; 1236 if (DO_BIC(BIC_Pkgpc3)) 1237 old->pc3 = new->pc3 - old->pc3; 1238 if (DO_BIC(BIC_Pkgpc6)) 1239 old->pc6 = new->pc6 - old->pc6; 1240 if (DO_BIC(BIC_Pkgpc7)) 1241 old->pc7 = new->pc7 - old->pc7; 1242 old->pc8 = new->pc8 - old->pc8; 1243 old->pc9 = new->pc9 - old->pc9; 1244 old->pc10 = new->pc10 - old->pc10; 1245 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 1246 old->sys_lpi = new->sys_lpi - old->sys_lpi; 1247 old->pkg_temp_c = new->pkg_temp_c; 1248 1249 /* flag an error when rc6 counter resets/wraps */ 1250 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 1251 old->gfx_rc6_ms = -1; 1252 else 1253 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 1254 1255 old->gfx_mhz = new->gfx_mhz; 1256 1257 DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 1258 DELTA_WRAP32(new->energy_cores, old->energy_cores); 1259 DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 1260 DELTA_WRAP32(new->energy_dram, old->energy_dram); 1261 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 1262 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 1263 1264 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1265 if (mp->format == FORMAT_RAW) 1266 old->counter[i] = new->counter[i]; 1267 else 1268 old->counter[i] = new->counter[i] - old->counter[i]; 1269 } 1270 1271 return 0; 1272 } 1273 1274 void 1275 delta_core(struct core_data *new, struct core_data *old) 1276 { 1277 int i; 1278 struct msr_counter *mp; 1279 1280 old->c3 = new->c3 - old->c3; 1281 old->c6 = new->c6 - old->c6; 1282 old->c7 = new->c7 - old->c7; 1283 old->core_temp_c = new->core_temp_c; 1284 old->mc6_us = new->mc6_us - old->mc6_us; 1285 1286 DELTA_WRAP32(new->core_energy, old->core_energy); 1287 1288 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1289 if (mp->format == FORMAT_RAW) 1290 old->counter[i] = new->counter[i]; 1291 else 1292 old->counter[i] = new->counter[i] - old->counter[i]; 1293 } 1294 } 1295 1296 int soft_c1_residency_display(int bic) 1297 { 1298 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr) 1299 return 0; 1300 1301 return DO_BIC_READ(bic); 1302 } 1303 1304 /* 1305 * old = new - old 1306 */ 1307 int 1308 delta_thread(struct thread_data *new, struct thread_data *old, 1309 struct core_data *core_delta) 1310 { 1311 int i; 1312 struct msr_counter *mp; 1313 1314 /* we run cpuid just the 1st time, copy the results */ 1315 if (DO_BIC(BIC_APIC)) 1316 new->apic_id = old->apic_id; 1317 if (DO_BIC(BIC_X2APIC)) 1318 new->x2apic_id = old->x2apic_id; 1319 1320 /* 1321 * the timestamps from start of measurement interval are in "old" 1322 * the timestamp from end of measurement interval are in "new" 1323 * over-write old w/ new so we can print end of interval values 1324 */ 1325 1326 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta); 1327 old->tv_begin = new->tv_begin; 1328 old->tv_end = new->tv_end; 1329 1330 old->tsc = new->tsc - old->tsc; 1331 1332 /* check for TSC < 1 Mcycles over interval */ 1333 if (old->tsc < (1000 * 1000)) 1334 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1335 "You can disable all c-states by booting with \"idle=poll\"\n" 1336 "or just the deep ones with \"processor.max_cstate=1\""); 1337 1338 old->c1 = new->c1 - old->c1; 1339 1340 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || 1341 soft_c1_residency_display(BIC_Avg_MHz)) { 1342 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1343 old->aperf = new->aperf - old->aperf; 1344 old->mperf = new->mperf - old->mperf; 1345 } else { 1346 return -1; 1347 } 1348 } 1349 1350 1351 if (use_c1_residency_msr) { 1352 /* 1353 * Some models have a dedicated C1 residency MSR, 1354 * which should be more accurate than the derivation below. 1355 */ 1356 } else { 1357 /* 1358 * As counter collection is not atomic, 1359 * it is possible for mperf's non-halted cycles + idle states 1360 * to exceed TSC's all cycles: show c1 = 0% in that case. 1361 */ 1362 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 1363 old->c1 = 0; 1364 else { 1365 /* normal case, derive c1 */ 1366 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1367 - core_delta->c6 - core_delta->c7; 1368 } 1369 } 1370 1371 if (old->mperf == 0) { 1372 if (debug > 1) 1373 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1374 old->mperf = 1; /* divide by 0 protection */ 1375 } 1376 1377 if (DO_BIC(BIC_IRQ)) 1378 old->irq_count = new->irq_count - old->irq_count; 1379 1380 if (DO_BIC(BIC_SMI)) 1381 old->smi_count = new->smi_count - old->smi_count; 1382 1383 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1384 if (mp->format == FORMAT_RAW) 1385 old->counter[i] = new->counter[i]; 1386 else 1387 old->counter[i] = new->counter[i] - old->counter[i]; 1388 } 1389 return 0; 1390 } 1391 1392 int delta_cpu(struct thread_data *t, struct core_data *c, 1393 struct pkg_data *p, struct thread_data *t2, 1394 struct core_data *c2, struct pkg_data *p2) 1395 { 1396 int retval = 0; 1397 1398 /* calculate core delta only for 1st thread in core */ 1399 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1400 delta_core(c, c2); 1401 1402 /* always calculate thread delta */ 1403 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1404 if (retval) 1405 return retval; 1406 1407 /* calculate package delta only for 1st core in package */ 1408 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1409 retval = delta_package(p, p2); 1410 1411 return retval; 1412 } 1413 1414 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1415 { 1416 int i; 1417 struct msr_counter *mp; 1418 1419 t->tv_begin.tv_sec = 0; 1420 t->tv_begin.tv_usec = 0; 1421 t->tv_end.tv_sec = 0; 1422 t->tv_end.tv_usec = 0; 1423 t->tv_delta.tv_sec = 0; 1424 t->tv_delta.tv_usec = 0; 1425 1426 t->tsc = 0; 1427 t->aperf = 0; 1428 t->mperf = 0; 1429 t->c1 = 0; 1430 1431 t->irq_count = 0; 1432 t->smi_count = 0; 1433 1434 /* tells format_counters to dump all fields from this set */ 1435 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1436 1437 c->c3 = 0; 1438 c->c6 = 0; 1439 c->c7 = 0; 1440 c->mc6_us = 0; 1441 c->core_temp_c = 0; 1442 c->core_energy = 0; 1443 1444 p->pkg_wtd_core_c0 = 0; 1445 p->pkg_any_core_c0 = 0; 1446 p->pkg_any_gfxe_c0 = 0; 1447 p->pkg_both_core_gfxe_c0 = 0; 1448 1449 p->pc2 = 0; 1450 if (DO_BIC(BIC_Pkgpc3)) 1451 p->pc3 = 0; 1452 if (DO_BIC(BIC_Pkgpc6)) 1453 p->pc6 = 0; 1454 if (DO_BIC(BIC_Pkgpc7)) 1455 p->pc7 = 0; 1456 p->pc8 = 0; 1457 p->pc9 = 0; 1458 p->pc10 = 0; 1459 p->cpu_lpi = 0; 1460 p->sys_lpi = 0; 1461 1462 p->energy_pkg = 0; 1463 p->energy_dram = 0; 1464 p->energy_cores = 0; 1465 p->energy_gfx = 0; 1466 p->rapl_pkg_perf_status = 0; 1467 p->rapl_dram_perf_status = 0; 1468 p->pkg_temp_c = 0; 1469 1470 p->gfx_rc6_ms = 0; 1471 p->gfx_mhz = 0; 1472 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1473 t->counter[i] = 0; 1474 1475 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1476 c->counter[i] = 0; 1477 1478 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1479 p->counter[i] = 0; 1480 } 1481 int sum_counters(struct thread_data *t, struct core_data *c, 1482 struct pkg_data *p) 1483 { 1484 int i; 1485 struct msr_counter *mp; 1486 1487 /* copy un-changing apic_id's */ 1488 if (DO_BIC(BIC_APIC)) 1489 average.threads.apic_id = t->apic_id; 1490 if (DO_BIC(BIC_X2APIC)) 1491 average.threads.x2apic_id = t->x2apic_id; 1492 1493 /* remember first tv_begin */ 1494 if (average.threads.tv_begin.tv_sec == 0) 1495 average.threads.tv_begin = t->tv_begin; 1496 1497 /* remember last tv_end */ 1498 average.threads.tv_end = t->tv_end; 1499 1500 average.threads.tsc += t->tsc; 1501 average.threads.aperf += t->aperf; 1502 average.threads.mperf += t->mperf; 1503 average.threads.c1 += t->c1; 1504 1505 average.threads.irq_count += t->irq_count; 1506 average.threads.smi_count += t->smi_count; 1507 1508 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1509 if (mp->format == FORMAT_RAW) 1510 continue; 1511 average.threads.counter[i] += t->counter[i]; 1512 } 1513 1514 /* sum per-core values only for 1st thread in core */ 1515 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1516 return 0; 1517 1518 average.cores.c3 += c->c3; 1519 average.cores.c6 += c->c6; 1520 average.cores.c7 += c->c7; 1521 average.cores.mc6_us += c->mc6_us; 1522 1523 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1524 1525 average.cores.core_energy += c->core_energy; 1526 1527 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1528 if (mp->format == FORMAT_RAW) 1529 continue; 1530 average.cores.counter[i] += c->counter[i]; 1531 } 1532 1533 /* sum per-pkg values only for 1st core in pkg */ 1534 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1535 return 0; 1536 1537 if (DO_BIC(BIC_Totl_c0)) 1538 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1539 if (DO_BIC(BIC_Any_c0)) 1540 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1541 if (DO_BIC(BIC_GFX_c0)) 1542 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1543 if (DO_BIC(BIC_CPUGFX)) 1544 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1545 1546 average.packages.pc2 += p->pc2; 1547 if (DO_BIC(BIC_Pkgpc3)) 1548 average.packages.pc3 += p->pc3; 1549 if (DO_BIC(BIC_Pkgpc6)) 1550 average.packages.pc6 += p->pc6; 1551 if (DO_BIC(BIC_Pkgpc7)) 1552 average.packages.pc7 += p->pc7; 1553 average.packages.pc8 += p->pc8; 1554 average.packages.pc9 += p->pc9; 1555 average.packages.pc10 += p->pc10; 1556 1557 average.packages.cpu_lpi = p->cpu_lpi; 1558 average.packages.sys_lpi = p->sys_lpi; 1559 1560 average.packages.energy_pkg += p->energy_pkg; 1561 average.packages.energy_dram += p->energy_dram; 1562 average.packages.energy_cores += p->energy_cores; 1563 average.packages.energy_gfx += p->energy_gfx; 1564 1565 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1566 average.packages.gfx_mhz = p->gfx_mhz; 1567 1568 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1569 1570 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1571 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1572 1573 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1574 if (mp->format == FORMAT_RAW) 1575 continue; 1576 average.packages.counter[i] += p->counter[i]; 1577 } 1578 return 0; 1579 } 1580 /* 1581 * sum the counters for all cpus in the system 1582 * compute the weighted average 1583 */ 1584 void compute_average(struct thread_data *t, struct core_data *c, 1585 struct pkg_data *p) 1586 { 1587 int i; 1588 struct msr_counter *mp; 1589 1590 clear_counters(&average.threads, &average.cores, &average.packages); 1591 1592 for_all_cpus(sum_counters, t, c, p); 1593 1594 /* Use the global time delta for the average. */ 1595 average.threads.tv_delta = tv_delta; 1596 1597 average.threads.tsc /= topo.num_cpus; 1598 average.threads.aperf /= topo.num_cpus; 1599 average.threads.mperf /= topo.num_cpus; 1600 average.threads.c1 /= topo.num_cpus; 1601 1602 if (average.threads.irq_count > 9999999) 1603 sums_need_wide_columns = 1; 1604 1605 average.cores.c3 /= topo.num_cores; 1606 average.cores.c6 /= topo.num_cores; 1607 average.cores.c7 /= topo.num_cores; 1608 average.cores.mc6_us /= topo.num_cores; 1609 1610 if (DO_BIC(BIC_Totl_c0)) 1611 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1612 if (DO_BIC(BIC_Any_c0)) 1613 average.packages.pkg_any_core_c0 /= topo.num_packages; 1614 if (DO_BIC(BIC_GFX_c0)) 1615 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1616 if (DO_BIC(BIC_CPUGFX)) 1617 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1618 1619 average.packages.pc2 /= topo.num_packages; 1620 if (DO_BIC(BIC_Pkgpc3)) 1621 average.packages.pc3 /= topo.num_packages; 1622 if (DO_BIC(BIC_Pkgpc6)) 1623 average.packages.pc6 /= topo.num_packages; 1624 if (DO_BIC(BIC_Pkgpc7)) 1625 average.packages.pc7 /= topo.num_packages; 1626 1627 average.packages.pc8 /= topo.num_packages; 1628 average.packages.pc9 /= topo.num_packages; 1629 average.packages.pc10 /= topo.num_packages; 1630 1631 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1632 if (mp->format == FORMAT_RAW) 1633 continue; 1634 if (mp->type == COUNTER_ITEMS) { 1635 if (average.threads.counter[i] > 9999999) 1636 sums_need_wide_columns = 1; 1637 continue; 1638 } 1639 average.threads.counter[i] /= topo.num_cpus; 1640 } 1641 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1642 if (mp->format == FORMAT_RAW) 1643 continue; 1644 if (mp->type == COUNTER_ITEMS) { 1645 if (average.cores.counter[i] > 9999999) 1646 sums_need_wide_columns = 1; 1647 } 1648 average.cores.counter[i] /= topo.num_cores; 1649 } 1650 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1651 if (mp->format == FORMAT_RAW) 1652 continue; 1653 if (mp->type == COUNTER_ITEMS) { 1654 if (average.packages.counter[i] > 9999999) 1655 sums_need_wide_columns = 1; 1656 } 1657 average.packages.counter[i] /= topo.num_packages; 1658 } 1659 } 1660 1661 static unsigned long long rdtsc(void) 1662 { 1663 unsigned int low, high; 1664 1665 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1666 1667 return low | ((unsigned long long)high) << 32; 1668 } 1669 1670 /* 1671 * Open a file, and exit on failure 1672 */ 1673 FILE *fopen_or_die(const char *path, const char *mode) 1674 { 1675 FILE *filep = fopen(path, mode); 1676 1677 if (!filep) 1678 err(1, "%s: open failed", path); 1679 return filep; 1680 } 1681 /* 1682 * snapshot_sysfs_counter() 1683 * 1684 * return snapshot of given counter 1685 */ 1686 unsigned long long snapshot_sysfs_counter(char *path) 1687 { 1688 FILE *fp; 1689 int retval; 1690 unsigned long long counter; 1691 1692 fp = fopen_or_die(path, "r"); 1693 1694 retval = fscanf(fp, "%lld", &counter); 1695 if (retval != 1) 1696 err(1, "snapshot_sysfs_counter(%s)", path); 1697 1698 fclose(fp); 1699 1700 return counter; 1701 } 1702 1703 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 1704 { 1705 if (mp->msr_num != 0) { 1706 if (get_msr(cpu, mp->msr_num, counterp)) 1707 return -1; 1708 } else { 1709 char path[128 + PATH_BYTES]; 1710 1711 if (mp->flags & SYSFS_PERCPU) { 1712 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", 1713 cpu, mp->path); 1714 1715 *counterp = snapshot_sysfs_counter(path); 1716 } else { 1717 *counterp = snapshot_sysfs_counter(mp->path); 1718 } 1719 } 1720 1721 return 0; 1722 } 1723 1724 int get_epb(int cpu) 1725 { 1726 char path[128 + PATH_BYTES]; 1727 int ret, epb = -1; 1728 FILE *fp; 1729 1730 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu); 1731 1732 fp = fopen_or_die(path, "r"); 1733 1734 ret = fscanf(fp, "%d", &epb); 1735 if (ret != 1) 1736 err(1, "%s(%s)", __func__, path); 1737 1738 fclose(fp); 1739 1740 return epb; 1741 } 1742 1743 void get_apic_id(struct thread_data *t) 1744 { 1745 unsigned int eax, ebx, ecx, edx; 1746 1747 if (DO_BIC(BIC_APIC)) { 1748 eax = ebx = ecx = edx = 0; 1749 __cpuid(1, eax, ebx, ecx, edx); 1750 1751 t->apic_id = (ebx >> 24) & 0xff; 1752 } 1753 1754 if (!DO_BIC(BIC_X2APIC)) 1755 return; 1756 1757 if (authentic_amd || hygon_genuine) { 1758 unsigned int topology_extensions; 1759 1760 if (max_extended_level < 0x8000001e) 1761 return; 1762 1763 eax = ebx = ecx = edx = 0; 1764 __cpuid(0x80000001, eax, ebx, ecx, edx); 1765 topology_extensions = ecx & (1 << 22); 1766 1767 if (topology_extensions == 0) 1768 return; 1769 1770 eax = ebx = ecx = edx = 0; 1771 __cpuid(0x8000001e, eax, ebx, ecx, edx); 1772 1773 t->x2apic_id = eax; 1774 return; 1775 } 1776 1777 if (!genuine_intel) 1778 return; 1779 1780 if (max_level < 0xb) 1781 return; 1782 1783 ecx = 0; 1784 __cpuid(0xb, eax, ebx, ecx, edx); 1785 t->x2apic_id = edx; 1786 1787 if (debug && (t->apic_id != (t->x2apic_id & 0xff))) 1788 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", 1789 t->cpu_id, t->apic_id, t->x2apic_id); 1790 } 1791 1792 /* 1793 * get_counters(...) 1794 * migrate to cpu 1795 * acquire and record local counters for that cpu 1796 */ 1797 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1798 { 1799 int cpu = t->cpu_id; 1800 unsigned long long msr; 1801 int aperf_mperf_retry_count = 0; 1802 struct msr_counter *mp; 1803 int i; 1804 1805 if (cpu_migrate(cpu)) { 1806 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1807 return -1; 1808 } 1809 1810 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 1811 1812 if (first_counter_read) 1813 get_apic_id(t); 1814 retry: 1815 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1816 1817 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || 1818 soft_c1_residency_display(BIC_Avg_MHz)) { 1819 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1820 1821 /* 1822 * The TSC, APERF and MPERF must be read together for 1823 * APERF/MPERF and MPERF/TSC to give accurate results. 1824 * 1825 * Unfortunately, APERF and MPERF are read by 1826 * individual system call, so delays may occur 1827 * between them. If the time to read them 1828 * varies by a large amount, we re-read them. 1829 */ 1830 1831 /* 1832 * This initial dummy APERF read has been seen to 1833 * reduce jitter in the subsequent reads. 1834 */ 1835 1836 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1837 return -3; 1838 1839 t->tsc = rdtsc(); /* re-read close to APERF */ 1840 1841 tsc_before = t->tsc; 1842 1843 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1844 return -3; 1845 1846 tsc_between = rdtsc(); 1847 1848 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1849 return -4; 1850 1851 tsc_after = rdtsc(); 1852 1853 aperf_time = tsc_between - tsc_before; 1854 mperf_time = tsc_after - tsc_between; 1855 1856 /* 1857 * If the system call latency to read APERF and MPERF 1858 * differ by more than 2x, then try again. 1859 */ 1860 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1861 aperf_mperf_retry_count++; 1862 if (aperf_mperf_retry_count < 5) 1863 goto retry; 1864 else 1865 warnx("cpu%d jitter %lld %lld", 1866 cpu, aperf_time, mperf_time); 1867 } 1868 aperf_mperf_retry_count = 0; 1869 1870 t->aperf = t->aperf * aperf_mperf_multiplier; 1871 t->mperf = t->mperf * aperf_mperf_multiplier; 1872 } 1873 1874 if (DO_BIC(BIC_IRQ)) 1875 t->irq_count = irqs_per_cpu[cpu]; 1876 if (DO_BIC(BIC_SMI)) { 1877 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1878 return -5; 1879 t->smi_count = msr & 0xFFFFFFFF; 1880 } 1881 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 1882 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 1883 return -6; 1884 } 1885 1886 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1887 if (get_mp(cpu, mp, &t->counter[i])) 1888 return -10; 1889 } 1890 1891 /* collect core counters only for 1st thread in core */ 1892 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1893 goto done; 1894 1895 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) { 1896 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1897 return -6; 1898 } 1899 1900 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) { 1901 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1902 return -7; 1903 } else if (do_knl_cstates || soft_c1_residency_display(BIC_CPU_c6)) { 1904 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1905 return -7; 1906 } 1907 1908 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) 1909 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1910 return -8; 1911 1912 if (DO_BIC(BIC_Mod_c6)) 1913 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 1914 return -8; 1915 1916 if (DO_BIC(BIC_CoreTmp)) { 1917 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1918 return -9; 1919 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1920 } 1921 1922 if (do_rapl & RAPL_AMD_F17H) { 1923 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr)) 1924 return -14; 1925 c->core_energy = msr & 0xFFFFFFFF; 1926 } 1927 1928 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1929 if (get_mp(cpu, mp, &c->counter[i])) 1930 return -10; 1931 } 1932 1933 /* collect package counters only for 1st core in package */ 1934 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1935 goto done; 1936 1937 if (DO_BIC(BIC_Totl_c0)) { 1938 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 1939 return -10; 1940 } 1941 if (DO_BIC(BIC_Any_c0)) { 1942 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 1943 return -11; 1944 } 1945 if (DO_BIC(BIC_GFX_c0)) { 1946 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 1947 return -12; 1948 } 1949 if (DO_BIC(BIC_CPUGFX)) { 1950 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 1951 return -13; 1952 } 1953 if (DO_BIC(BIC_Pkgpc3)) 1954 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 1955 return -9; 1956 if (DO_BIC(BIC_Pkgpc6)) { 1957 if (do_slm_cstates) { 1958 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 1959 return -10; 1960 } else { 1961 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 1962 return -10; 1963 } 1964 } 1965 1966 if (DO_BIC(BIC_Pkgpc2)) 1967 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 1968 return -11; 1969 if (DO_BIC(BIC_Pkgpc7)) 1970 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 1971 return -12; 1972 if (DO_BIC(BIC_Pkgpc8)) 1973 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 1974 return -13; 1975 if (DO_BIC(BIC_Pkgpc9)) 1976 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 1977 return -13; 1978 if (DO_BIC(BIC_Pkgpc10)) 1979 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 1980 return -13; 1981 1982 if (DO_BIC(BIC_CPU_LPI)) 1983 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 1984 if (DO_BIC(BIC_SYS_LPI)) 1985 p->sys_lpi = cpuidle_cur_sys_lpi_us; 1986 1987 if (do_rapl & RAPL_PKG) { 1988 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 1989 return -13; 1990 p->energy_pkg = msr & 0xFFFFFFFF; 1991 } 1992 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 1993 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 1994 return -14; 1995 p->energy_cores = msr & 0xFFFFFFFF; 1996 } 1997 if (do_rapl & RAPL_DRAM) { 1998 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 1999 return -15; 2000 p->energy_dram = msr & 0xFFFFFFFF; 2001 } 2002 if (do_rapl & RAPL_GFX) { 2003 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 2004 return -16; 2005 p->energy_gfx = msr & 0xFFFFFFFF; 2006 } 2007 if (do_rapl & RAPL_PKG_PERF_STATUS) { 2008 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 2009 return -16; 2010 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 2011 } 2012 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 2013 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 2014 return -16; 2015 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 2016 } 2017 if (do_rapl & RAPL_AMD_F17H) { 2018 if (get_msr(cpu, MSR_PKG_ENERGY_STAT, &msr)) 2019 return -13; 2020 p->energy_pkg = msr & 0xFFFFFFFF; 2021 } 2022 if (DO_BIC(BIC_PkgTmp)) { 2023 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 2024 return -17; 2025 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 2026 } 2027 2028 if (DO_BIC(BIC_GFX_rc6)) 2029 p->gfx_rc6_ms = gfx_cur_rc6_ms; 2030 2031 if (DO_BIC(BIC_GFXMHz)) 2032 p->gfx_mhz = gfx_cur_mhz; 2033 2034 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2035 if (get_mp(cpu, mp, &p->counter[i])) 2036 return -10; 2037 } 2038 done: 2039 gettimeofday(&t->tv_end, (struct timezone *)NULL); 2040 2041 return 0; 2042 } 2043 2044 /* 2045 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 2046 * If you change the values, note they are used both in comparisons 2047 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 2048 */ 2049 2050 #define PCLUKN 0 /* Unknown */ 2051 #define PCLRSV 1 /* Reserved */ 2052 #define PCL__0 2 /* PC0 */ 2053 #define PCL__1 3 /* PC1 */ 2054 #define PCL__2 4 /* PC2 */ 2055 #define PCL__3 5 /* PC3 */ 2056 #define PCL__4 6 /* PC4 */ 2057 #define PCL__6 7 /* PC6 */ 2058 #define PCL_6N 8 /* PC6 No Retention */ 2059 #define PCL_6R 9 /* PC6 Retention */ 2060 #define PCL__7 10 /* PC7 */ 2061 #define PCL_7S 11 /* PC7 Shrink */ 2062 #define PCL__8 12 /* PC8 */ 2063 #define PCL__9 13 /* PC9 */ 2064 #define PCL_10 14 /* PC10 */ 2065 #define PCLUNL 15 /* Unlimited */ 2066 2067 int pkg_cstate_limit = PCLUKN; 2068 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 2069 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"}; 2070 2071 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2072 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2073 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2074 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7}; 2075 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2076 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2077 int glm_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2078 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2079 2080 2081 static void 2082 calculate_tsc_tweak() 2083 { 2084 tsc_tweak = base_hz / tsc_hz; 2085 } 2086 2087 static void 2088 dump_nhm_platform_info(void) 2089 { 2090 unsigned long long msr; 2091 unsigned int ratio; 2092 2093 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2094 2095 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 2096 2097 ratio = (msr >> 40) & 0xFF; 2098 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", 2099 ratio, bclk, ratio * bclk); 2100 2101 ratio = (msr >> 8) & 0xFF; 2102 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2103 ratio, bclk, ratio * bclk); 2104 2105 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 2106 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 2107 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 2108 2109 return; 2110 } 2111 2112 static void 2113 dump_hsw_turbo_ratio_limits(void) 2114 { 2115 unsigned long long msr; 2116 unsigned int ratio; 2117 2118 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 2119 2120 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 2121 2122 ratio = (msr >> 8) & 0xFF; 2123 if (ratio) 2124 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", 2125 ratio, bclk, ratio * bclk); 2126 2127 ratio = (msr >> 0) & 0xFF; 2128 if (ratio) 2129 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", 2130 ratio, bclk, ratio * bclk); 2131 return; 2132 } 2133 2134 static void 2135 dump_ivt_turbo_ratio_limits(void) 2136 { 2137 unsigned long long msr; 2138 unsigned int ratio; 2139 2140 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 2141 2142 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 2143 2144 ratio = (msr >> 56) & 0xFF; 2145 if (ratio) 2146 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", 2147 ratio, bclk, ratio * bclk); 2148 2149 ratio = (msr >> 48) & 0xFF; 2150 if (ratio) 2151 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", 2152 ratio, bclk, ratio * bclk); 2153 2154 ratio = (msr >> 40) & 0xFF; 2155 if (ratio) 2156 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", 2157 ratio, bclk, ratio * bclk); 2158 2159 ratio = (msr >> 32) & 0xFF; 2160 if (ratio) 2161 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", 2162 ratio, bclk, ratio * bclk); 2163 2164 ratio = (msr >> 24) & 0xFF; 2165 if (ratio) 2166 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", 2167 ratio, bclk, ratio * bclk); 2168 2169 ratio = (msr >> 16) & 0xFF; 2170 if (ratio) 2171 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", 2172 ratio, bclk, ratio * bclk); 2173 2174 ratio = (msr >> 8) & 0xFF; 2175 if (ratio) 2176 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", 2177 ratio, bclk, ratio * bclk); 2178 2179 ratio = (msr >> 0) & 0xFF; 2180 if (ratio) 2181 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", 2182 ratio, bclk, ratio * bclk); 2183 return; 2184 } 2185 int has_turbo_ratio_group_limits(int family, int model) 2186 { 2187 2188 if (!genuine_intel) 2189 return 0; 2190 2191 switch (model) { 2192 case INTEL_FAM6_ATOM_GOLDMONT: 2193 case INTEL_FAM6_SKYLAKE_X: 2194 case INTEL_FAM6_ATOM_GOLDMONT_D: 2195 return 1; 2196 } 2197 return 0; 2198 } 2199 2200 static void 2201 dump_turbo_ratio_limits(int family, int model) 2202 { 2203 unsigned long long msr, core_counts; 2204 unsigned int ratio, group_size; 2205 2206 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2207 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2208 2209 if (has_turbo_ratio_group_limits(family, model)) { 2210 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 2211 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 2212 } else { 2213 core_counts = 0x0807060504030201; 2214 } 2215 2216 ratio = (msr >> 56) & 0xFF; 2217 group_size = (core_counts >> 56) & 0xFF; 2218 if (ratio) 2219 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2220 ratio, bclk, ratio * bclk, group_size); 2221 2222 ratio = (msr >> 48) & 0xFF; 2223 group_size = (core_counts >> 48) & 0xFF; 2224 if (ratio) 2225 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2226 ratio, bclk, ratio * bclk, group_size); 2227 2228 ratio = (msr >> 40) & 0xFF; 2229 group_size = (core_counts >> 40) & 0xFF; 2230 if (ratio) 2231 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2232 ratio, bclk, ratio * bclk, group_size); 2233 2234 ratio = (msr >> 32) & 0xFF; 2235 group_size = (core_counts >> 32) & 0xFF; 2236 if (ratio) 2237 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2238 ratio, bclk, ratio * bclk, group_size); 2239 2240 ratio = (msr >> 24) & 0xFF; 2241 group_size = (core_counts >> 24) & 0xFF; 2242 if (ratio) 2243 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2244 ratio, bclk, ratio * bclk, group_size); 2245 2246 ratio = (msr >> 16) & 0xFF; 2247 group_size = (core_counts >> 16) & 0xFF; 2248 if (ratio) 2249 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2250 ratio, bclk, ratio * bclk, group_size); 2251 2252 ratio = (msr >> 8) & 0xFF; 2253 group_size = (core_counts >> 8) & 0xFF; 2254 if (ratio) 2255 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2256 ratio, bclk, ratio * bclk, group_size); 2257 2258 ratio = (msr >> 0) & 0xFF; 2259 group_size = (core_counts >> 0) & 0xFF; 2260 if (ratio) 2261 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2262 ratio, bclk, ratio * bclk, group_size); 2263 return; 2264 } 2265 2266 static void 2267 dump_atom_turbo_ratio_limits(void) 2268 { 2269 unsigned long long msr; 2270 unsigned int ratio; 2271 2272 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 2273 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2274 2275 ratio = (msr >> 0) & 0x3F; 2276 if (ratio) 2277 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", 2278 ratio, bclk, ratio * bclk); 2279 2280 ratio = (msr >> 8) & 0x3F; 2281 if (ratio) 2282 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", 2283 ratio, bclk, ratio * bclk); 2284 2285 ratio = (msr >> 16) & 0x3F; 2286 if (ratio) 2287 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2288 ratio, bclk, ratio * bclk); 2289 2290 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 2291 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2292 2293 ratio = (msr >> 24) & 0x3F; 2294 if (ratio) 2295 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", 2296 ratio, bclk, ratio * bclk); 2297 2298 ratio = (msr >> 16) & 0x3F; 2299 if (ratio) 2300 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", 2301 ratio, bclk, ratio * bclk); 2302 2303 ratio = (msr >> 8) & 0x3F; 2304 if (ratio) 2305 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", 2306 ratio, bclk, ratio * bclk); 2307 2308 ratio = (msr >> 0) & 0x3F; 2309 if (ratio) 2310 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", 2311 ratio, bclk, ratio * bclk); 2312 } 2313 2314 static void 2315 dump_knl_turbo_ratio_limits(void) 2316 { 2317 const unsigned int buckets_no = 7; 2318 2319 unsigned long long msr; 2320 int delta_cores, delta_ratio; 2321 int i, b_nr; 2322 unsigned int cores[buckets_no]; 2323 unsigned int ratio[buckets_no]; 2324 2325 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2326 2327 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 2328 base_cpu, msr); 2329 2330 /** 2331 * Turbo encoding in KNL is as follows: 2332 * [0] -- Reserved 2333 * [7:1] -- Base value of number of active cores of bucket 1. 2334 * [15:8] -- Base value of freq ratio of bucket 1. 2335 * [20:16] -- +ve delta of number of active cores of bucket 2. 2336 * i.e. active cores of bucket 2 = 2337 * active cores of bucket 1 + delta 2338 * [23:21] -- Negative delta of freq ratio of bucket 2. 2339 * i.e. freq ratio of bucket 2 = 2340 * freq ratio of bucket 1 - delta 2341 * [28:24]-- +ve delta of number of active cores of bucket 3. 2342 * [31:29]-- -ve delta of freq ratio of bucket 3. 2343 * [36:32]-- +ve delta of number of active cores of bucket 4. 2344 * [39:37]-- -ve delta of freq ratio of bucket 4. 2345 * [44:40]-- +ve delta of number of active cores of bucket 5. 2346 * [47:45]-- -ve delta of freq ratio of bucket 5. 2347 * [52:48]-- +ve delta of number of active cores of bucket 6. 2348 * [55:53]-- -ve delta of freq ratio of bucket 6. 2349 * [60:56]-- +ve delta of number of active cores of bucket 7. 2350 * [63:61]-- -ve delta of freq ratio of bucket 7. 2351 */ 2352 2353 b_nr = 0; 2354 cores[b_nr] = (msr & 0xFF) >> 1; 2355 ratio[b_nr] = (msr >> 8) & 0xFF; 2356 2357 for (i = 16; i < 64; i += 8) { 2358 delta_cores = (msr >> i) & 0x1F; 2359 delta_ratio = (msr >> (i + 5)) & 0x7; 2360 2361 cores[b_nr + 1] = cores[b_nr] + delta_cores; 2362 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 2363 b_nr++; 2364 } 2365 2366 for (i = buckets_no - 1; i >= 0; i--) 2367 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 2368 fprintf(outf, 2369 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2370 ratio[i], bclk, ratio[i] * bclk, cores[i]); 2371 } 2372 2373 static void 2374 dump_nhm_cst_cfg(void) 2375 { 2376 unsigned long long msr; 2377 2378 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2379 2380 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 2381 2382 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 2383 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 2384 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 2385 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 2386 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 2387 (msr & (1 << 15)) ? "" : "UN", 2388 (unsigned int)msr & 0xF, 2389 pkg_cstate_limit_strings[pkg_cstate_limit]); 2390 2391 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 2392 if (has_automatic_cstate_conversion) { 2393 fprintf(outf, ", automatic c-state conversion=%s", 2394 (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 2395 } 2396 2397 fprintf(outf, ")\n"); 2398 2399 return; 2400 } 2401 2402 static void 2403 dump_config_tdp(void) 2404 { 2405 unsigned long long msr; 2406 2407 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 2408 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 2409 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 2410 2411 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 2412 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 2413 if (msr) { 2414 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2415 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2416 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2417 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 2418 } 2419 fprintf(outf, ")\n"); 2420 2421 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 2422 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 2423 if (msr) { 2424 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2425 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2426 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2427 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 2428 } 2429 fprintf(outf, ")\n"); 2430 2431 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 2432 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 2433 if ((msr) & 0x3) 2434 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 2435 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2436 fprintf(outf, ")\n"); 2437 2438 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 2439 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 2440 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 2441 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2442 fprintf(outf, ")\n"); 2443 } 2444 2445 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 2446 2447 void print_irtl(void) 2448 { 2449 unsigned long long msr; 2450 2451 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 2452 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 2453 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2454 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2455 2456 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 2457 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 2458 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2459 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2460 2461 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 2462 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 2463 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2464 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2465 2466 if (!do_irtl_hsw) 2467 return; 2468 2469 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 2470 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 2471 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2472 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2473 2474 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 2475 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 2476 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2477 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2478 2479 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 2480 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 2481 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2482 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2483 2484 } 2485 void free_fd_percpu(void) 2486 { 2487 int i; 2488 2489 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 2490 if (fd_percpu[i] != 0) 2491 close(fd_percpu[i]); 2492 } 2493 2494 free(fd_percpu); 2495 } 2496 2497 void free_all_buffers(void) 2498 { 2499 int i; 2500 2501 CPU_FREE(cpu_present_set); 2502 cpu_present_set = NULL; 2503 cpu_present_setsize = 0; 2504 2505 CPU_FREE(cpu_affinity_set); 2506 cpu_affinity_set = NULL; 2507 cpu_affinity_setsize = 0; 2508 2509 free(thread_even); 2510 free(core_even); 2511 free(package_even); 2512 2513 thread_even = NULL; 2514 core_even = NULL; 2515 package_even = NULL; 2516 2517 free(thread_odd); 2518 free(core_odd); 2519 free(package_odd); 2520 2521 thread_odd = NULL; 2522 core_odd = NULL; 2523 package_odd = NULL; 2524 2525 free(output_buffer); 2526 output_buffer = NULL; 2527 outp = NULL; 2528 2529 free_fd_percpu(); 2530 2531 free(irq_column_2_cpu); 2532 free(irqs_per_cpu); 2533 2534 for (i = 0; i <= topo.max_cpu_num; ++i) { 2535 if (cpus[i].put_ids) 2536 CPU_FREE(cpus[i].put_ids); 2537 } 2538 free(cpus); 2539 } 2540 2541 2542 /* 2543 * Parse a file containing a single int. 2544 * Return 0 if file can not be opened 2545 * Exit if file can be opened, but can not be parsed 2546 */ 2547 int parse_int_file(const char *fmt, ...) 2548 { 2549 va_list args; 2550 char path[PATH_MAX]; 2551 FILE *filep; 2552 int value; 2553 2554 va_start(args, fmt); 2555 vsnprintf(path, sizeof(path), fmt, args); 2556 va_end(args); 2557 filep = fopen(path, "r"); 2558 if (!filep) 2559 return 0; 2560 if (fscanf(filep, "%d", &value) != 1) 2561 err(1, "%s: failed to parse number from file", path); 2562 fclose(filep); 2563 return value; 2564 } 2565 2566 /* 2567 * cpu_is_first_core_in_package(cpu) 2568 * return 1 if given CPU is 1st core in package 2569 */ 2570 int cpu_is_first_core_in_package(int cpu) 2571 { 2572 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2573 } 2574 2575 int get_physical_package_id(int cpu) 2576 { 2577 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2578 } 2579 2580 int get_die_id(int cpu) 2581 { 2582 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu); 2583 } 2584 2585 int get_core_id(int cpu) 2586 { 2587 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2588 } 2589 2590 void set_node_data(void) 2591 { 2592 int pkg, node, lnode, cpu, cpux; 2593 int cpu_count; 2594 2595 /* initialize logical_node_id */ 2596 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) 2597 cpus[cpu].logical_node_id = -1; 2598 2599 cpu_count = 0; 2600 for (pkg = 0; pkg < topo.num_packages; pkg++) { 2601 lnode = 0; 2602 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) { 2603 if (cpus[cpu].physical_package_id != pkg) 2604 continue; 2605 /* find a cpu with an unset logical_node_id */ 2606 if (cpus[cpu].logical_node_id != -1) 2607 continue; 2608 cpus[cpu].logical_node_id = lnode; 2609 node = cpus[cpu].physical_node_id; 2610 cpu_count++; 2611 /* 2612 * find all matching cpus on this pkg and set 2613 * the logical_node_id 2614 */ 2615 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) { 2616 if ((cpus[cpux].physical_package_id == pkg) && 2617 (cpus[cpux].physical_node_id == node)) { 2618 cpus[cpux].logical_node_id = lnode; 2619 cpu_count++; 2620 } 2621 } 2622 lnode++; 2623 if (lnode > topo.nodes_per_pkg) 2624 topo.nodes_per_pkg = lnode; 2625 } 2626 if (cpu_count >= topo.max_cpu_num) 2627 break; 2628 } 2629 } 2630 2631 int get_physical_node_id(struct cpu_topology *thiscpu) 2632 { 2633 char path[80]; 2634 FILE *filep; 2635 int i; 2636 int cpu = thiscpu->logical_cpu_id; 2637 2638 for (i = 0; i <= topo.max_cpu_num; i++) { 2639 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", 2640 cpu, i); 2641 filep = fopen(path, "r"); 2642 if (!filep) 2643 continue; 2644 fclose(filep); 2645 return i; 2646 } 2647 return -1; 2648 } 2649 2650 int get_thread_siblings(struct cpu_topology *thiscpu) 2651 { 2652 char path[80], character; 2653 FILE *filep; 2654 unsigned long map; 2655 int so, shift, sib_core; 2656 int cpu = thiscpu->logical_cpu_id; 2657 int offset = topo.max_cpu_num + 1; 2658 size_t size; 2659 int thread_id = 0; 2660 2661 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 2662 if (thiscpu->thread_id < 0) 2663 thiscpu->thread_id = thread_id++; 2664 if (!thiscpu->put_ids) 2665 return -1; 2666 2667 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 2668 CPU_ZERO_S(size, thiscpu->put_ids); 2669 2670 sprintf(path, 2671 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 2672 filep = fopen_or_die(path, "r"); 2673 do { 2674 offset -= BITMASK_SIZE; 2675 if (fscanf(filep, "%lx%c", &map, &character) != 2) 2676 err(1, "%s: failed to parse file", path); 2677 for (shift = 0; shift < BITMASK_SIZE; shift++) { 2678 if ((map >> shift) & 0x1) { 2679 so = shift + offset; 2680 sib_core = get_core_id(so); 2681 if (sib_core == thiscpu->physical_core_id) { 2682 CPU_SET_S(so, size, thiscpu->put_ids); 2683 if ((so != cpu) && 2684 (cpus[so].thread_id < 0)) 2685 cpus[so].thread_id = 2686 thread_id++; 2687 } 2688 } 2689 } 2690 } while (!strncmp(&character, ",", 1)); 2691 fclose(filep); 2692 2693 return CPU_COUNT_S(size, thiscpu->put_ids); 2694 } 2695 2696 /* 2697 * run func(thread, core, package) in topology order 2698 * skip non-present cpus 2699 */ 2700 2701 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 2702 struct pkg_data *, struct thread_data *, struct core_data *, 2703 struct pkg_data *), struct thread_data *thread_base, 2704 struct core_data *core_base, struct pkg_data *pkg_base, 2705 struct thread_data *thread_base2, struct core_data *core_base2, 2706 struct pkg_data *pkg_base2) 2707 { 2708 int retval, pkg_no, node_no, core_no, thread_no; 2709 2710 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2711 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 2712 for (core_no = 0; core_no < topo.cores_per_node; 2713 ++core_no) { 2714 for (thread_no = 0; thread_no < 2715 topo.threads_per_core; ++thread_no) { 2716 struct thread_data *t, *t2; 2717 struct core_data *c, *c2; 2718 struct pkg_data *p, *p2; 2719 2720 t = GET_THREAD(thread_base, thread_no, 2721 core_no, node_no, 2722 pkg_no); 2723 2724 if (cpu_is_not_present(t->cpu_id)) 2725 continue; 2726 2727 t2 = GET_THREAD(thread_base2, thread_no, 2728 core_no, node_no, 2729 pkg_no); 2730 2731 c = GET_CORE(core_base, core_no, 2732 node_no, pkg_no); 2733 c2 = GET_CORE(core_base2, core_no, 2734 node_no, 2735 pkg_no); 2736 2737 p = GET_PKG(pkg_base, pkg_no); 2738 p2 = GET_PKG(pkg_base2, pkg_no); 2739 2740 retval = func(t, c, p, t2, c2, p2); 2741 if (retval) 2742 return retval; 2743 } 2744 } 2745 } 2746 } 2747 return 0; 2748 } 2749 2750 /* 2751 * run func(cpu) on every cpu in /proc/stat 2752 * return max_cpu number 2753 */ 2754 int for_all_proc_cpus(int (func)(int)) 2755 { 2756 FILE *fp; 2757 int cpu_num; 2758 int retval; 2759 2760 fp = fopen_or_die(proc_stat, "r"); 2761 2762 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 2763 if (retval != 0) 2764 err(1, "%s: failed to parse format", proc_stat); 2765 2766 while (1) { 2767 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 2768 if (retval != 1) 2769 break; 2770 2771 retval = func(cpu_num); 2772 if (retval) { 2773 fclose(fp); 2774 return(retval); 2775 } 2776 } 2777 fclose(fp); 2778 return 0; 2779 } 2780 2781 void re_initialize(void) 2782 { 2783 free_all_buffers(); 2784 setup_all_buffers(); 2785 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2786 } 2787 2788 void set_max_cpu_num(void) 2789 { 2790 FILE *filep; 2791 unsigned long dummy; 2792 2793 topo.max_cpu_num = 0; 2794 filep = fopen_or_die( 2795 "/sys/devices/system/cpu/cpu0/topology/thread_siblings", 2796 "r"); 2797 while (fscanf(filep, "%lx,", &dummy) == 1) 2798 topo.max_cpu_num += BITMASK_SIZE; 2799 fclose(filep); 2800 topo.max_cpu_num--; /* 0 based */ 2801 } 2802 2803 /* 2804 * count_cpus() 2805 * remember the last one seen, it will be the max 2806 */ 2807 int count_cpus(int cpu) 2808 { 2809 topo.num_cpus++; 2810 return 0; 2811 } 2812 int mark_cpu_present(int cpu) 2813 { 2814 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 2815 return 0; 2816 } 2817 2818 int init_thread_id(int cpu) 2819 { 2820 cpus[cpu].thread_id = -1; 2821 return 0; 2822 } 2823 2824 /* 2825 * snapshot_proc_interrupts() 2826 * 2827 * read and record summary of /proc/interrupts 2828 * 2829 * return 1 if config change requires a restart, else return 0 2830 */ 2831 int snapshot_proc_interrupts(void) 2832 { 2833 static FILE *fp; 2834 int column, retval; 2835 2836 if (fp == NULL) 2837 fp = fopen_or_die("/proc/interrupts", "r"); 2838 else 2839 rewind(fp); 2840 2841 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 2842 for (column = 0; column < topo.num_cpus; ++column) { 2843 int cpu_number; 2844 2845 retval = fscanf(fp, " CPU%d", &cpu_number); 2846 if (retval != 1) 2847 break; 2848 2849 if (cpu_number > topo.max_cpu_num) { 2850 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 2851 return 1; 2852 } 2853 2854 irq_column_2_cpu[column] = cpu_number; 2855 irqs_per_cpu[cpu_number] = 0; 2856 } 2857 2858 /* read /proc/interrupt count lines and sum up irqs per cpu */ 2859 while (1) { 2860 int column; 2861 char buf[64]; 2862 2863 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 2864 if (retval != 1) 2865 break; 2866 2867 /* read the count per cpu */ 2868 for (column = 0; column < topo.num_cpus; ++column) { 2869 2870 int cpu_number, irq_count; 2871 2872 retval = fscanf(fp, " %d", &irq_count); 2873 if (retval != 1) 2874 break; 2875 2876 cpu_number = irq_column_2_cpu[column]; 2877 irqs_per_cpu[cpu_number] += irq_count; 2878 2879 } 2880 2881 while (getc(fp) != '\n') 2882 ; /* flush interrupt description */ 2883 2884 } 2885 return 0; 2886 } 2887 /* 2888 * snapshot_gfx_rc6_ms() 2889 * 2890 * record snapshot of 2891 * /sys/class/drm/card0/power/rc6_residency_ms 2892 * 2893 * return 1 if config change requires a restart, else return 0 2894 */ 2895 int snapshot_gfx_rc6_ms(void) 2896 { 2897 FILE *fp; 2898 int retval; 2899 2900 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 2901 2902 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 2903 if (retval != 1) 2904 err(1, "GFX rc6"); 2905 2906 fclose(fp); 2907 2908 return 0; 2909 } 2910 /* 2911 * snapshot_gfx_mhz() 2912 * 2913 * record snapshot of 2914 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 2915 * 2916 * return 1 if config change requires a restart, else return 0 2917 */ 2918 int snapshot_gfx_mhz(void) 2919 { 2920 static FILE *fp; 2921 int retval; 2922 2923 if (fp == NULL) 2924 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 2925 else { 2926 rewind(fp); 2927 fflush(fp); 2928 } 2929 2930 retval = fscanf(fp, "%d", &gfx_cur_mhz); 2931 if (retval != 1) 2932 err(1, "GFX MHz"); 2933 2934 return 0; 2935 } 2936 2937 /* 2938 * snapshot_cpu_lpi() 2939 * 2940 * record snapshot of 2941 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 2942 */ 2943 int snapshot_cpu_lpi_us(void) 2944 { 2945 FILE *fp; 2946 int retval; 2947 2948 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 2949 2950 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 2951 if (retval != 1) { 2952 fprintf(stderr, "Disabling Low Power Idle CPU output\n"); 2953 BIC_NOT_PRESENT(BIC_CPU_LPI); 2954 fclose(fp); 2955 return -1; 2956 } 2957 2958 fclose(fp); 2959 2960 return 0; 2961 } 2962 /* 2963 * snapshot_sys_lpi() 2964 * 2965 * record snapshot of sys_lpi_file 2966 */ 2967 int snapshot_sys_lpi_us(void) 2968 { 2969 FILE *fp; 2970 int retval; 2971 2972 fp = fopen_or_die(sys_lpi_file, "r"); 2973 2974 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 2975 if (retval != 1) { 2976 fprintf(stderr, "Disabling Low Power Idle System output\n"); 2977 BIC_NOT_PRESENT(BIC_SYS_LPI); 2978 fclose(fp); 2979 return -1; 2980 } 2981 fclose(fp); 2982 2983 return 0; 2984 } 2985 /* 2986 * snapshot /proc and /sys files 2987 * 2988 * return 1 if configuration restart needed, else return 0 2989 */ 2990 int snapshot_proc_sysfs_files(void) 2991 { 2992 if (DO_BIC(BIC_IRQ)) 2993 if (snapshot_proc_interrupts()) 2994 return 1; 2995 2996 if (DO_BIC(BIC_GFX_rc6)) 2997 snapshot_gfx_rc6_ms(); 2998 2999 if (DO_BIC(BIC_GFXMHz)) 3000 snapshot_gfx_mhz(); 3001 3002 if (DO_BIC(BIC_CPU_LPI)) 3003 snapshot_cpu_lpi_us(); 3004 3005 if (DO_BIC(BIC_SYS_LPI)) 3006 snapshot_sys_lpi_us(); 3007 3008 return 0; 3009 } 3010 3011 int exit_requested; 3012 3013 static void signal_handler (int signal) 3014 { 3015 switch (signal) { 3016 case SIGINT: 3017 exit_requested = 1; 3018 if (debug) 3019 fprintf(stderr, " SIGINT\n"); 3020 break; 3021 case SIGUSR1: 3022 if (debug > 1) 3023 fprintf(stderr, "SIGUSR1\n"); 3024 break; 3025 } 3026 } 3027 3028 void setup_signal_handler(void) 3029 { 3030 struct sigaction sa; 3031 3032 memset(&sa, 0, sizeof(sa)); 3033 3034 sa.sa_handler = &signal_handler; 3035 3036 if (sigaction(SIGINT, &sa, NULL) < 0) 3037 err(1, "sigaction SIGINT"); 3038 if (sigaction(SIGUSR1, &sa, NULL) < 0) 3039 err(1, "sigaction SIGUSR1"); 3040 } 3041 3042 void do_sleep(void) 3043 { 3044 struct timeval tout; 3045 struct timespec rest; 3046 fd_set readfds; 3047 int retval; 3048 3049 FD_ZERO(&readfds); 3050 FD_SET(0, &readfds); 3051 3052 if (ignore_stdin) { 3053 nanosleep(&interval_ts, NULL); 3054 return; 3055 } 3056 3057 tout = interval_tv; 3058 retval = select(1, &readfds, NULL, NULL, &tout); 3059 3060 if (retval == 1) { 3061 switch (getc(stdin)) { 3062 case 'q': 3063 exit_requested = 1; 3064 break; 3065 case EOF: 3066 /* 3067 * 'stdin' is a pipe closed on the other end. There 3068 * won't be any further input. 3069 */ 3070 ignore_stdin = 1; 3071 /* Sleep the rest of the time */ 3072 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000); 3073 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000; 3074 nanosleep(&rest, NULL); 3075 } 3076 } 3077 } 3078 3079 3080 void turbostat_loop() 3081 { 3082 int retval; 3083 int restarted = 0; 3084 int done_iters = 0; 3085 3086 setup_signal_handler(); 3087 3088 restart: 3089 restarted++; 3090 3091 snapshot_proc_sysfs_files(); 3092 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3093 first_counter_read = 0; 3094 if (retval < -1) { 3095 exit(retval); 3096 } else if (retval == -1) { 3097 if (restarted > 1) { 3098 exit(retval); 3099 } 3100 re_initialize(); 3101 goto restart; 3102 } 3103 restarted = 0; 3104 done_iters = 0; 3105 gettimeofday(&tv_even, (struct timezone *)NULL); 3106 3107 while (1) { 3108 if (for_all_proc_cpus(cpu_is_not_present)) { 3109 re_initialize(); 3110 goto restart; 3111 } 3112 do_sleep(); 3113 if (snapshot_proc_sysfs_files()) 3114 goto restart; 3115 retval = for_all_cpus(get_counters, ODD_COUNTERS); 3116 if (retval < -1) { 3117 exit(retval); 3118 } else if (retval == -1) { 3119 re_initialize(); 3120 goto restart; 3121 } 3122 gettimeofday(&tv_odd, (struct timezone *)NULL); 3123 timersub(&tv_odd, &tv_even, &tv_delta); 3124 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 3125 re_initialize(); 3126 goto restart; 3127 } 3128 compute_average(EVEN_COUNTERS); 3129 format_all_counters(EVEN_COUNTERS); 3130 flush_output_stdout(); 3131 if (exit_requested) 3132 break; 3133 if (num_iterations && ++done_iters >= num_iterations) 3134 break; 3135 do_sleep(); 3136 if (snapshot_proc_sysfs_files()) 3137 goto restart; 3138 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3139 if (retval < -1) { 3140 exit(retval); 3141 } else if (retval == -1) { 3142 re_initialize(); 3143 goto restart; 3144 } 3145 gettimeofday(&tv_even, (struct timezone *)NULL); 3146 timersub(&tv_even, &tv_odd, &tv_delta); 3147 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 3148 re_initialize(); 3149 goto restart; 3150 } 3151 compute_average(ODD_COUNTERS); 3152 format_all_counters(ODD_COUNTERS); 3153 flush_output_stdout(); 3154 if (exit_requested) 3155 break; 3156 if (num_iterations && ++done_iters >= num_iterations) 3157 break; 3158 } 3159 } 3160 3161 void check_dev_msr() 3162 { 3163 struct stat sb; 3164 char pathname[32]; 3165 3166 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3167 if (stat(pathname, &sb)) 3168 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 3169 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 3170 } 3171 3172 /* 3173 * check for CAP_SYS_RAWIO 3174 * return 0 on success 3175 * return 1 on fail 3176 */ 3177 int check_for_cap_sys_rawio(void) 3178 { 3179 cap_t caps; 3180 cap_flag_value_t cap_flag_value; 3181 3182 caps = cap_get_proc(); 3183 if (caps == NULL) 3184 err(-6, "cap_get_proc\n"); 3185 3186 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value)) 3187 err(-6, "cap_get\n"); 3188 3189 if (cap_flag_value != CAP_SET) { 3190 warnx("capget(CAP_SYS_RAWIO) failed," 3191 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 3192 return 1; 3193 } 3194 3195 if (cap_free(caps) == -1) 3196 err(-6, "cap_free\n"); 3197 3198 return 0; 3199 } 3200 void check_permissions(void) 3201 { 3202 int do_exit = 0; 3203 char pathname[32]; 3204 3205 /* check for CAP_SYS_RAWIO */ 3206 do_exit += check_for_cap_sys_rawio(); 3207 3208 /* test file permissions */ 3209 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3210 if (euidaccess(pathname, R_OK)) { 3211 do_exit++; 3212 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 3213 } 3214 3215 /* if all else fails, thell them to be root */ 3216 if (do_exit) 3217 if (getuid() != 0) 3218 warnx("... or simply run as root"); 3219 3220 if (do_exit) 3221 exit(-6); 3222 } 3223 3224 /* 3225 * NHM adds support for additional MSRs: 3226 * 3227 * MSR_SMI_COUNT 0x00000034 3228 * 3229 * MSR_PLATFORM_INFO 0x000000ce 3230 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 3231 * 3232 * MSR_MISC_PWR_MGMT 0x000001aa 3233 * 3234 * MSR_PKG_C3_RESIDENCY 0x000003f8 3235 * MSR_PKG_C6_RESIDENCY 0x000003f9 3236 * MSR_CORE_C3_RESIDENCY 0x000003fc 3237 * MSR_CORE_C6_RESIDENCY 0x000003fd 3238 * 3239 * Side effect: 3240 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 3241 * sets has_misc_feature_control 3242 */ 3243 int probe_nhm_msrs(unsigned int family, unsigned int model) 3244 { 3245 unsigned long long msr; 3246 unsigned int base_ratio; 3247 int *pkg_cstate_limits; 3248 3249 if (!genuine_intel) 3250 return 0; 3251 3252 if (family != 6) 3253 return 0; 3254 3255 bclk = discover_bclk(family, model); 3256 3257 switch (model) { 3258 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 3259 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3260 pkg_cstate_limits = nhm_pkg_cstate_limits; 3261 break; 3262 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 3263 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 3264 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3265 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3266 pkg_cstate_limits = snb_pkg_cstate_limits; 3267 has_misc_feature_control = 1; 3268 break; 3269 case INTEL_FAM6_HASWELL: /* HSW */ 3270 case INTEL_FAM6_HASWELL_G: /* HSW */ 3271 case INTEL_FAM6_HASWELL_X: /* HSX */ 3272 case INTEL_FAM6_HASWELL_L: /* HSW */ 3273 case INTEL_FAM6_BROADWELL: /* BDW */ 3274 case INTEL_FAM6_BROADWELL_G: /* BDW */ 3275 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3276 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 3277 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 3278 pkg_cstate_limits = hsw_pkg_cstate_limits; 3279 has_misc_feature_control = 1; 3280 break; 3281 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3282 pkg_cstate_limits = skx_pkg_cstate_limits; 3283 has_misc_feature_control = 1; 3284 break; 3285 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3286 no_MSR_MISC_PWR_MGMT = 1; 3287 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 3288 pkg_cstate_limits = slv_pkg_cstate_limits; 3289 break; 3290 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 3291 pkg_cstate_limits = amt_pkg_cstate_limits; 3292 no_MSR_MISC_PWR_MGMT = 1; 3293 break; 3294 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 3295 pkg_cstate_limits = phi_pkg_cstate_limits; 3296 break; 3297 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3298 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3299 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 3300 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 3301 pkg_cstate_limits = glm_pkg_cstate_limits; 3302 break; 3303 default: 3304 return 0; 3305 } 3306 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3307 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3308 3309 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3310 base_ratio = (msr >> 8) & 0xFF; 3311 3312 base_hz = base_ratio * bclk * 1000000; 3313 has_base_hz = 1; 3314 return 1; 3315 } 3316 /* 3317 * SLV client has support for unique MSRs: 3318 * 3319 * MSR_CC6_DEMOTION_POLICY_CONFIG 3320 * MSR_MC6_DEMOTION_POLICY_CONFIG 3321 */ 3322 3323 int has_slv_msrs(unsigned int family, unsigned int model) 3324 { 3325 if (!genuine_intel) 3326 return 0; 3327 3328 switch (model) { 3329 case INTEL_FAM6_ATOM_SILVERMONT: 3330 case INTEL_FAM6_ATOM_SILVERMONT_MID: 3331 case INTEL_FAM6_ATOM_AIRMONT_MID: 3332 return 1; 3333 } 3334 return 0; 3335 } 3336 int is_dnv(unsigned int family, unsigned int model) 3337 { 3338 3339 if (!genuine_intel) 3340 return 0; 3341 3342 switch (model) { 3343 case INTEL_FAM6_ATOM_GOLDMONT_D: 3344 return 1; 3345 } 3346 return 0; 3347 } 3348 int is_bdx(unsigned int family, unsigned int model) 3349 { 3350 3351 if (!genuine_intel) 3352 return 0; 3353 3354 switch (model) { 3355 case INTEL_FAM6_BROADWELL_X: 3356 return 1; 3357 } 3358 return 0; 3359 } 3360 int is_skx(unsigned int family, unsigned int model) 3361 { 3362 3363 if (!genuine_intel) 3364 return 0; 3365 3366 switch (model) { 3367 case INTEL_FAM6_SKYLAKE_X: 3368 return 1; 3369 } 3370 return 0; 3371 } 3372 int is_ehl(unsigned int family, unsigned int model) 3373 { 3374 if (!genuine_intel) 3375 return 0; 3376 3377 switch (model) { 3378 case INTEL_FAM6_ATOM_TREMONT: 3379 return 1; 3380 } 3381 return 0; 3382 } 3383 3384 int has_turbo_ratio_limit(unsigned int family, unsigned int model) 3385 { 3386 if (has_slv_msrs(family, model)) 3387 return 0; 3388 3389 switch (model) { 3390 /* Nehalem compatible, but do not include turbo-ratio limit support */ 3391 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3392 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 3393 return 0; 3394 default: 3395 return 1; 3396 } 3397 } 3398 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 3399 { 3400 if (has_slv_msrs(family, model)) 3401 return 1; 3402 3403 return 0; 3404 } 3405 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 3406 { 3407 if (!genuine_intel) 3408 return 0; 3409 3410 if (family != 6) 3411 return 0; 3412 3413 switch (model) { 3414 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3415 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3416 return 1; 3417 default: 3418 return 0; 3419 } 3420 } 3421 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 3422 { 3423 if (!genuine_intel) 3424 return 0; 3425 3426 if (family != 6) 3427 return 0; 3428 3429 switch (model) { 3430 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3431 return 1; 3432 default: 3433 return 0; 3434 } 3435 } 3436 3437 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 3438 { 3439 if (!genuine_intel) 3440 return 0; 3441 3442 if (family != 6) 3443 return 0; 3444 3445 switch (model) { 3446 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3447 return 1; 3448 default: 3449 return 0; 3450 } 3451 } 3452 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) 3453 { 3454 if (!genuine_intel) 3455 return 0; 3456 3457 if (family != 6) 3458 return 0; 3459 3460 switch (model) { 3461 case INTEL_FAM6_ATOM_GOLDMONT: 3462 case INTEL_FAM6_SKYLAKE_X: 3463 return 1; 3464 default: 3465 return 0; 3466 } 3467 } 3468 int has_config_tdp(unsigned int family, unsigned int model) 3469 { 3470 if (!genuine_intel) 3471 return 0; 3472 3473 if (family != 6) 3474 return 0; 3475 3476 switch (model) { 3477 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3478 case INTEL_FAM6_HASWELL: /* HSW */ 3479 case INTEL_FAM6_HASWELL_X: /* HSX */ 3480 case INTEL_FAM6_HASWELL_L: /* HSW */ 3481 case INTEL_FAM6_HASWELL_G: /* HSW */ 3482 case INTEL_FAM6_BROADWELL: /* BDW */ 3483 case INTEL_FAM6_BROADWELL_G: /* BDW */ 3484 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3485 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 3486 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 3487 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3488 3489 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3490 return 1; 3491 default: 3492 return 0; 3493 } 3494 } 3495 3496 static void 3497 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 3498 { 3499 if (!do_nhm_platform_info) 3500 return; 3501 3502 dump_nhm_platform_info(); 3503 3504 if (has_hsw_turbo_ratio_limit(family, model)) 3505 dump_hsw_turbo_ratio_limits(); 3506 3507 if (has_ivt_turbo_ratio_limit(family, model)) 3508 dump_ivt_turbo_ratio_limits(); 3509 3510 if (has_turbo_ratio_limit(family, model)) 3511 dump_turbo_ratio_limits(family, model); 3512 3513 if (has_atom_turbo_ratio_limit(family, model)) 3514 dump_atom_turbo_ratio_limits(); 3515 3516 if (has_knl_turbo_ratio_limit(family, model)) 3517 dump_knl_turbo_ratio_limits(); 3518 3519 if (has_config_tdp(family, model)) 3520 dump_config_tdp(); 3521 3522 dump_nhm_cst_cfg(); 3523 } 3524 3525 static void dump_sysfs_file(char *path) 3526 { 3527 FILE *input; 3528 char cpuidle_buf[64]; 3529 3530 input = fopen(path, "r"); 3531 if (input == NULL) { 3532 if (debug) 3533 fprintf(outf, "NSFOD %s\n", path); 3534 return; 3535 } 3536 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input)) 3537 err(1, "%s: failed to read file", path); 3538 fclose(input); 3539 3540 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf); 3541 } 3542 static void 3543 dump_sysfs_cstate_config(void) 3544 { 3545 char path[64]; 3546 char name_buf[16]; 3547 char desc[64]; 3548 FILE *input; 3549 int state; 3550 char *sp; 3551 3552 if (!DO_BIC(BIC_sysfs)) 3553 return; 3554 3555 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) { 3556 fprintf(outf, "cpuidle not loaded\n"); 3557 return; 3558 } 3559 3560 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver"); 3561 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor"); 3562 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro"); 3563 3564 for (state = 0; state < 10; ++state) { 3565 3566 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 3567 base_cpu, state); 3568 input = fopen(path, "r"); 3569 if (input == NULL) 3570 continue; 3571 if (!fgets(name_buf, sizeof(name_buf), input)) 3572 err(1, "%s: failed to read file", path); 3573 3574 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 3575 sp = strchr(name_buf, '-'); 3576 if (!sp) 3577 sp = strchrnul(name_buf, '\n'); 3578 *sp = '\0'; 3579 fclose(input); 3580 3581 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", 3582 base_cpu, state); 3583 input = fopen(path, "r"); 3584 if (input == NULL) 3585 continue; 3586 if (!fgets(desc, sizeof(desc), input)) 3587 err(1, "%s: failed to read file", path); 3588 3589 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 3590 fclose(input); 3591 } 3592 } 3593 static void 3594 dump_sysfs_pstate_config(void) 3595 { 3596 char path[64]; 3597 char driver_buf[64]; 3598 char governor_buf[64]; 3599 FILE *input; 3600 int turbo; 3601 3602 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", 3603 base_cpu); 3604 input = fopen(path, "r"); 3605 if (input == NULL) { 3606 fprintf(outf, "NSFOD %s\n", path); 3607 return; 3608 } 3609 if (!fgets(driver_buf, sizeof(driver_buf), input)) 3610 err(1, "%s: failed to read file", path); 3611 fclose(input); 3612 3613 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", 3614 base_cpu); 3615 input = fopen(path, "r"); 3616 if (input == NULL) { 3617 fprintf(outf, "NSFOD %s\n", path); 3618 return; 3619 } 3620 if (!fgets(governor_buf, sizeof(governor_buf), input)) 3621 err(1, "%s: failed to read file", path); 3622 fclose(input); 3623 3624 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 3625 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 3626 3627 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 3628 input = fopen(path, "r"); 3629 if (input != NULL) { 3630 if (fscanf(input, "%d", &turbo) != 1) 3631 err(1, "%s: failed to parse number from file", path); 3632 fprintf(outf, "cpufreq boost: %d\n", turbo); 3633 fclose(input); 3634 } 3635 3636 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 3637 input = fopen(path, "r"); 3638 if (input != NULL) { 3639 if (fscanf(input, "%d", &turbo) != 1) 3640 err(1, "%s: failed to parse number from file", path); 3641 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 3642 fclose(input); 3643 } 3644 } 3645 3646 3647 /* 3648 * print_epb() 3649 * Decode the ENERGY_PERF_BIAS MSR 3650 */ 3651 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3652 { 3653 char *epb_string; 3654 int cpu, epb; 3655 3656 if (!has_epb) 3657 return 0; 3658 3659 cpu = t->cpu_id; 3660 3661 /* EPB is per-package */ 3662 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3663 return 0; 3664 3665 if (cpu_migrate(cpu)) { 3666 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3667 return -1; 3668 } 3669 3670 epb = get_epb(cpu); 3671 if (epb < 0) 3672 return 0; 3673 3674 switch (epb) { 3675 case ENERGY_PERF_BIAS_PERFORMANCE: 3676 epb_string = "performance"; 3677 break; 3678 case ENERGY_PERF_BIAS_NORMAL: 3679 epb_string = "balanced"; 3680 break; 3681 case ENERGY_PERF_BIAS_POWERSAVE: 3682 epb_string = "powersave"; 3683 break; 3684 default: 3685 epb_string = "custom"; 3686 break; 3687 } 3688 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string); 3689 3690 return 0; 3691 } 3692 /* 3693 * print_hwp() 3694 * Decode the MSR_HWP_CAPABILITIES 3695 */ 3696 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3697 { 3698 unsigned long long msr; 3699 int cpu; 3700 3701 if (!has_hwp) 3702 return 0; 3703 3704 cpu = t->cpu_id; 3705 3706 /* MSR_HWP_CAPABILITIES is per-package */ 3707 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3708 return 0; 3709 3710 if (cpu_migrate(cpu)) { 3711 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3712 return -1; 3713 } 3714 3715 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 3716 return 0; 3717 3718 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 3719 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 3720 3721 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 3722 if ((msr & (1 << 0)) == 0) 3723 return 0; 3724 3725 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 3726 return 0; 3727 3728 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 3729 "(high %d guar %d eff %d low %d)\n", 3730 cpu, msr, 3731 (unsigned int)HWP_HIGHEST_PERF(msr), 3732 (unsigned int)HWP_GUARANTEED_PERF(msr), 3733 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 3734 (unsigned int)HWP_LOWEST_PERF(msr)); 3735 3736 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 3737 return 0; 3738 3739 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 3740 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 3741 cpu, msr, 3742 (unsigned int)(((msr) >> 0) & 0xff), 3743 (unsigned int)(((msr) >> 8) & 0xff), 3744 (unsigned int)(((msr) >> 16) & 0xff), 3745 (unsigned int)(((msr) >> 24) & 0xff), 3746 (unsigned int)(((msr) >> 32) & 0xff3), 3747 (unsigned int)(((msr) >> 42) & 0x1)); 3748 3749 if (has_hwp_pkg) { 3750 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 3751 return 0; 3752 3753 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 3754 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 3755 cpu, msr, 3756 (unsigned int)(((msr) >> 0) & 0xff), 3757 (unsigned int)(((msr) >> 8) & 0xff), 3758 (unsigned int)(((msr) >> 16) & 0xff), 3759 (unsigned int)(((msr) >> 24) & 0xff), 3760 (unsigned int)(((msr) >> 32) & 0xff3)); 3761 } 3762 if (has_hwp_notify) { 3763 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 3764 return 0; 3765 3766 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 3767 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 3768 cpu, msr, 3769 ((msr) & 0x1) ? "EN" : "Dis", 3770 ((msr) & 0x2) ? "EN" : "Dis"); 3771 } 3772 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 3773 return 0; 3774 3775 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 3776 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 3777 cpu, msr, 3778 ((msr) & 0x1) ? "" : "No-", 3779 ((msr) & 0x2) ? "" : "No-"); 3780 3781 return 0; 3782 } 3783 3784 /* 3785 * print_perf_limit() 3786 */ 3787 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3788 { 3789 unsigned long long msr; 3790 int cpu; 3791 3792 cpu = t->cpu_id; 3793 3794 /* per-package */ 3795 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3796 return 0; 3797 3798 if (cpu_migrate(cpu)) { 3799 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3800 return -1; 3801 } 3802 3803 if (do_core_perf_limit_reasons) { 3804 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 3805 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3806 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 3807 (msr & 1 << 15) ? "bit15, " : "", 3808 (msr & 1 << 14) ? "bit14, " : "", 3809 (msr & 1 << 13) ? "Transitions, " : "", 3810 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 3811 (msr & 1 << 11) ? "PkgPwrL2, " : "", 3812 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3813 (msr & 1 << 9) ? "CorePwr, " : "", 3814 (msr & 1 << 8) ? "Amps, " : "", 3815 (msr & 1 << 6) ? "VR-Therm, " : "", 3816 (msr & 1 << 5) ? "Auto-HWP, " : "", 3817 (msr & 1 << 4) ? "Graphics, " : "", 3818 (msr & 1 << 2) ? "bit2, " : "", 3819 (msr & 1 << 1) ? "ThermStatus, " : "", 3820 (msr & 1 << 0) ? "PROCHOT, " : ""); 3821 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 3822 (msr & 1 << 31) ? "bit31, " : "", 3823 (msr & 1 << 30) ? "bit30, " : "", 3824 (msr & 1 << 29) ? "Transitions, " : "", 3825 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 3826 (msr & 1 << 27) ? "PkgPwrL2, " : "", 3827 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3828 (msr & 1 << 25) ? "CorePwr, " : "", 3829 (msr & 1 << 24) ? "Amps, " : "", 3830 (msr & 1 << 22) ? "VR-Therm, " : "", 3831 (msr & 1 << 21) ? "Auto-HWP, " : "", 3832 (msr & 1 << 20) ? "Graphics, " : "", 3833 (msr & 1 << 18) ? "bit18, " : "", 3834 (msr & 1 << 17) ? "ThermStatus, " : "", 3835 (msr & 1 << 16) ? "PROCHOT, " : ""); 3836 3837 } 3838 if (do_gfx_perf_limit_reasons) { 3839 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 3840 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3841 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 3842 (msr & 1 << 0) ? "PROCHOT, " : "", 3843 (msr & 1 << 1) ? "ThermStatus, " : "", 3844 (msr & 1 << 4) ? "Graphics, " : "", 3845 (msr & 1 << 6) ? "VR-Therm, " : "", 3846 (msr & 1 << 8) ? "Amps, " : "", 3847 (msr & 1 << 9) ? "GFXPwr, " : "", 3848 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3849 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 3850 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 3851 (msr & 1 << 16) ? "PROCHOT, " : "", 3852 (msr & 1 << 17) ? "ThermStatus, " : "", 3853 (msr & 1 << 20) ? "Graphics, " : "", 3854 (msr & 1 << 22) ? "VR-Therm, " : "", 3855 (msr & 1 << 24) ? "Amps, " : "", 3856 (msr & 1 << 25) ? "GFXPwr, " : "", 3857 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3858 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 3859 } 3860 if (do_ring_perf_limit_reasons) { 3861 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 3862 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3863 fprintf(outf, " (Active: %s%s%s%s%s%s)", 3864 (msr & 1 << 0) ? "PROCHOT, " : "", 3865 (msr & 1 << 1) ? "ThermStatus, " : "", 3866 (msr & 1 << 6) ? "VR-Therm, " : "", 3867 (msr & 1 << 8) ? "Amps, " : "", 3868 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3869 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 3870 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 3871 (msr & 1 << 16) ? "PROCHOT, " : "", 3872 (msr & 1 << 17) ? "ThermStatus, " : "", 3873 (msr & 1 << 22) ? "VR-Therm, " : "", 3874 (msr & 1 << 24) ? "Amps, " : "", 3875 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3876 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 3877 } 3878 return 0; 3879 } 3880 3881 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 3882 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 3883 3884 double get_tdp_intel(unsigned int model) 3885 { 3886 unsigned long long msr; 3887 3888 if (do_rapl & RAPL_PKG_POWER_INFO) 3889 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 3890 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 3891 3892 switch (model) { 3893 case INTEL_FAM6_ATOM_SILVERMONT: 3894 case INTEL_FAM6_ATOM_SILVERMONT_D: 3895 return 30.0; 3896 default: 3897 return 135.0; 3898 } 3899 } 3900 3901 double get_tdp_amd(unsigned int family) 3902 { 3903 switch (family) { 3904 case 0x17: 3905 case 0x18: 3906 default: 3907 /* This is the max stock TDP of HEDT/Server Fam17h chips */ 3908 return 250.0; 3909 } 3910 } 3911 3912 /* 3913 * rapl_dram_energy_units_probe() 3914 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 3915 */ 3916 static double 3917 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 3918 { 3919 /* only called for genuine_intel, family 6 */ 3920 3921 switch (model) { 3922 case INTEL_FAM6_HASWELL_X: /* HSX */ 3923 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3924 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3925 return (rapl_dram_energy_units = 15.3 / 1000000); 3926 default: 3927 return (rapl_energy_units); 3928 } 3929 } 3930 3931 void rapl_probe_intel(unsigned int family, unsigned int model) 3932 { 3933 unsigned long long msr; 3934 unsigned int time_unit; 3935 double tdp; 3936 3937 if (family != 6) 3938 return; 3939 3940 switch (model) { 3941 case INTEL_FAM6_SANDYBRIDGE: 3942 case INTEL_FAM6_IVYBRIDGE: 3943 case INTEL_FAM6_HASWELL: /* HSW */ 3944 case INTEL_FAM6_HASWELL_L: /* HSW */ 3945 case INTEL_FAM6_HASWELL_G: /* HSW */ 3946 case INTEL_FAM6_BROADWELL: /* BDW */ 3947 case INTEL_FAM6_BROADWELL_G: /* BDW */ 3948 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 3949 if (rapl_joules) { 3950 BIC_PRESENT(BIC_Pkg_J); 3951 BIC_PRESENT(BIC_Cor_J); 3952 BIC_PRESENT(BIC_GFX_J); 3953 } else { 3954 BIC_PRESENT(BIC_PkgWatt); 3955 BIC_PRESENT(BIC_CorWatt); 3956 BIC_PRESENT(BIC_GFXWatt); 3957 } 3958 break; 3959 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3960 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3961 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 3962 if (rapl_joules) 3963 BIC_PRESENT(BIC_Pkg_J); 3964 else 3965 BIC_PRESENT(BIC_PkgWatt); 3966 break; 3967 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 3968 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO; 3969 if (rapl_joules) { 3970 BIC_PRESENT(BIC_Pkg_J); 3971 BIC_PRESENT(BIC_Cor_J); 3972 BIC_PRESENT(BIC_RAM_J); 3973 BIC_PRESENT(BIC_GFX_J); 3974 } else { 3975 BIC_PRESENT(BIC_PkgWatt); 3976 BIC_PRESENT(BIC_CorWatt); 3977 BIC_PRESENT(BIC_RAMWatt); 3978 BIC_PRESENT(BIC_GFXWatt); 3979 } 3980 break; 3981 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 3982 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 3983 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO; 3984 BIC_PRESENT(BIC_PKG__); 3985 BIC_PRESENT(BIC_RAM__); 3986 if (rapl_joules) { 3987 BIC_PRESENT(BIC_Pkg_J); 3988 BIC_PRESENT(BIC_Cor_J); 3989 BIC_PRESENT(BIC_RAM_J); 3990 BIC_PRESENT(BIC_GFX_J); 3991 } else { 3992 BIC_PRESENT(BIC_PkgWatt); 3993 BIC_PRESENT(BIC_CorWatt); 3994 BIC_PRESENT(BIC_RAMWatt); 3995 BIC_PRESENT(BIC_GFXWatt); 3996 } 3997 break; 3998 case INTEL_FAM6_HASWELL_X: /* HSX */ 3999 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4000 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4001 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4002 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 4003 BIC_PRESENT(BIC_PKG__); 4004 BIC_PRESENT(BIC_RAM__); 4005 if (rapl_joules) { 4006 BIC_PRESENT(BIC_Pkg_J); 4007 BIC_PRESENT(BIC_RAM_J); 4008 } else { 4009 BIC_PRESENT(BIC_PkgWatt); 4010 BIC_PRESENT(BIC_RAMWatt); 4011 } 4012 break; 4013 case INTEL_FAM6_SANDYBRIDGE_X: 4014 case INTEL_FAM6_IVYBRIDGE_X: 4015 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 4016 BIC_PRESENT(BIC_PKG__); 4017 BIC_PRESENT(BIC_RAM__); 4018 if (rapl_joules) { 4019 BIC_PRESENT(BIC_Pkg_J); 4020 BIC_PRESENT(BIC_Cor_J); 4021 BIC_PRESENT(BIC_RAM_J); 4022 } else { 4023 BIC_PRESENT(BIC_PkgWatt); 4024 BIC_PRESENT(BIC_CorWatt); 4025 BIC_PRESENT(BIC_RAMWatt); 4026 } 4027 break; 4028 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4029 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 4030 do_rapl = RAPL_PKG | RAPL_CORES; 4031 if (rapl_joules) { 4032 BIC_PRESENT(BIC_Pkg_J); 4033 BIC_PRESENT(BIC_Cor_J); 4034 } else { 4035 BIC_PRESENT(BIC_PkgWatt); 4036 BIC_PRESENT(BIC_CorWatt); 4037 } 4038 break; 4039 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 4040 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 4041 BIC_PRESENT(BIC_PKG__); 4042 BIC_PRESENT(BIC_RAM__); 4043 if (rapl_joules) { 4044 BIC_PRESENT(BIC_Pkg_J); 4045 BIC_PRESENT(BIC_Cor_J); 4046 BIC_PRESENT(BIC_RAM_J); 4047 } else { 4048 BIC_PRESENT(BIC_PkgWatt); 4049 BIC_PRESENT(BIC_CorWatt); 4050 BIC_PRESENT(BIC_RAMWatt); 4051 } 4052 break; 4053 default: 4054 return; 4055 } 4056 4057 /* units on package 0, verify later other packages match */ 4058 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 4059 return; 4060 4061 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 4062 if (model == INTEL_FAM6_ATOM_SILVERMONT) 4063 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 4064 else 4065 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 4066 4067 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 4068 4069 time_unit = msr >> 16 & 0xF; 4070 if (time_unit == 0) 4071 time_unit = 0xA; 4072 4073 rapl_time_units = 1.0 / (1 << (time_unit)); 4074 4075 tdp = get_tdp_intel(model); 4076 4077 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4078 if (!quiet) 4079 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4080 } 4081 4082 void rapl_probe_amd(unsigned int family, unsigned int model) 4083 { 4084 unsigned long long msr; 4085 unsigned int eax, ebx, ecx, edx; 4086 unsigned int has_rapl = 0; 4087 double tdp; 4088 4089 if (max_extended_level >= 0x80000007) { 4090 __cpuid(0x80000007, eax, ebx, ecx, edx); 4091 /* RAPL (Fam 17h) */ 4092 has_rapl = edx & (1 << 14); 4093 } 4094 4095 if (!has_rapl) 4096 return; 4097 4098 switch (family) { 4099 case 0x17: /* Zen, Zen+ */ 4100 case 0x18: /* Hygon Dhyana */ 4101 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY; 4102 if (rapl_joules) { 4103 BIC_PRESENT(BIC_Pkg_J); 4104 BIC_PRESENT(BIC_Cor_J); 4105 } else { 4106 BIC_PRESENT(BIC_PkgWatt); 4107 BIC_PRESENT(BIC_CorWatt); 4108 } 4109 break; 4110 default: 4111 return; 4112 } 4113 4114 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr)) 4115 return; 4116 4117 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf)); 4118 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f)); 4119 rapl_power_units = ldexp(1.0, -(msr & 0xf)); 4120 4121 tdp = get_tdp_amd(family); 4122 4123 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4124 if (!quiet) 4125 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4126 } 4127 4128 /* 4129 * rapl_probe() 4130 * 4131 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 4132 */ 4133 void rapl_probe(unsigned int family, unsigned int model) 4134 { 4135 if (genuine_intel) 4136 rapl_probe_intel(family, model); 4137 if (authentic_amd || hygon_genuine) 4138 rapl_probe_amd(family, model); 4139 } 4140 4141 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 4142 { 4143 if (!genuine_intel) 4144 return; 4145 4146 if (family != 6) 4147 return; 4148 4149 switch (model) { 4150 case INTEL_FAM6_HASWELL: /* HSW */ 4151 case INTEL_FAM6_HASWELL_L: /* HSW */ 4152 case INTEL_FAM6_HASWELL_G: /* HSW */ 4153 do_gfx_perf_limit_reasons = 1; 4154 case INTEL_FAM6_HASWELL_X: /* HSX */ 4155 do_core_perf_limit_reasons = 1; 4156 do_ring_perf_limit_reasons = 1; 4157 default: 4158 return; 4159 } 4160 } 4161 4162 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model) 4163 { 4164 if (is_skx(family, model) || is_bdx(family, model)) 4165 has_automatic_cstate_conversion = 1; 4166 } 4167 4168 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4169 { 4170 unsigned long long msr; 4171 unsigned int dts, dts2; 4172 int cpu; 4173 4174 if (!(do_dts || do_ptm)) 4175 return 0; 4176 4177 cpu = t->cpu_id; 4178 4179 /* DTS is per-core, no need to print for each thread */ 4180 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 4181 return 0; 4182 4183 if (cpu_migrate(cpu)) { 4184 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4185 return -1; 4186 } 4187 4188 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 4189 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 4190 return 0; 4191 4192 dts = (msr >> 16) & 0x7F; 4193 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 4194 cpu, msr, tcc_activation_temp - dts); 4195 4196 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 4197 return 0; 4198 4199 dts = (msr >> 16) & 0x7F; 4200 dts2 = (msr >> 8) & 0x7F; 4201 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4202 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 4203 } 4204 4205 4206 if (do_dts && debug) { 4207 unsigned int resolution; 4208 4209 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 4210 return 0; 4211 4212 dts = (msr >> 16) & 0x7F; 4213 resolution = (msr >> 27) & 0xF; 4214 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 4215 cpu, msr, tcc_activation_temp - dts, resolution); 4216 4217 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 4218 return 0; 4219 4220 dts = (msr >> 16) & 0x7F; 4221 dts2 = (msr >> 8) & 0x7F; 4222 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4223 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 4224 } 4225 4226 return 0; 4227 } 4228 4229 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 4230 { 4231 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 4232 cpu, label, 4233 ((msr >> 15) & 1) ? "EN" : "DIS", 4234 ((msr >> 0) & 0x7FFF) * rapl_power_units, 4235 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 4236 (((msr >> 16) & 1) ? "EN" : "DIS")); 4237 4238 return; 4239 } 4240 4241 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4242 { 4243 unsigned long long msr; 4244 const char *msr_name; 4245 int cpu; 4246 4247 if (!do_rapl) 4248 return 0; 4249 4250 /* RAPL counters are per package, so print only for 1st thread/package */ 4251 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4252 return 0; 4253 4254 cpu = t->cpu_id; 4255 if (cpu_migrate(cpu)) { 4256 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4257 return -1; 4258 } 4259 4260 if (do_rapl & RAPL_AMD_F17H) { 4261 msr_name = "MSR_RAPL_PWR_UNIT"; 4262 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr)) 4263 return -1; 4264 } else { 4265 msr_name = "MSR_RAPL_POWER_UNIT"; 4266 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 4267 return -1; 4268 } 4269 4270 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr, 4271 rapl_power_units, rapl_energy_units, rapl_time_units); 4272 4273 if (do_rapl & RAPL_PKG_POWER_INFO) { 4274 4275 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 4276 return -5; 4277 4278 4279 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4280 cpu, msr, 4281 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4282 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4283 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4284 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4285 4286 } 4287 if (do_rapl & RAPL_PKG) { 4288 4289 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 4290 return -9; 4291 4292 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 4293 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 4294 4295 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 4296 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 4297 cpu, 4298 ((msr >> 47) & 1) ? "EN" : "DIS", 4299 ((msr >> 32) & 0x7FFF) * rapl_power_units, 4300 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 4301 ((msr >> 48) & 1) ? "EN" : "DIS"); 4302 } 4303 4304 if (do_rapl & RAPL_DRAM_POWER_INFO) { 4305 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 4306 return -6; 4307 4308 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4309 cpu, msr, 4310 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4311 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4312 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4313 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4314 } 4315 if (do_rapl & RAPL_DRAM) { 4316 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 4317 return -9; 4318 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 4319 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4320 4321 print_power_limit_msr(cpu, msr, "DRAM Limit"); 4322 } 4323 if (do_rapl & RAPL_CORE_POLICY) { 4324 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 4325 return -7; 4326 4327 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 4328 } 4329 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 4330 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 4331 return -9; 4332 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 4333 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4334 print_power_limit_msr(cpu, msr, "Cores Limit"); 4335 } 4336 if (do_rapl & RAPL_GFX) { 4337 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 4338 return -8; 4339 4340 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 4341 4342 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 4343 return -9; 4344 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 4345 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4346 print_power_limit_msr(cpu, msr, "GFX Limit"); 4347 } 4348 return 0; 4349 } 4350 4351 /* 4352 * SNB adds support for additional MSRs: 4353 * 4354 * MSR_PKG_C7_RESIDENCY 0x000003fa 4355 * MSR_CORE_C7_RESIDENCY 0x000003fe 4356 * MSR_PKG_C2_RESIDENCY 0x0000060d 4357 */ 4358 4359 int has_snb_msrs(unsigned int family, unsigned int model) 4360 { 4361 if (!genuine_intel) 4362 return 0; 4363 4364 switch (model) { 4365 case INTEL_FAM6_SANDYBRIDGE: 4366 case INTEL_FAM6_SANDYBRIDGE_X: 4367 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 4368 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 4369 case INTEL_FAM6_HASWELL: /* HSW */ 4370 case INTEL_FAM6_HASWELL_X: /* HSW */ 4371 case INTEL_FAM6_HASWELL_L: /* HSW */ 4372 case INTEL_FAM6_HASWELL_G: /* HSW */ 4373 case INTEL_FAM6_BROADWELL: /* BDW */ 4374 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4375 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4376 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4377 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4378 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4379 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4380 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4381 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 4382 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4383 return 1; 4384 } 4385 return 0; 4386 } 4387 4388 /* 4389 * HSW ULT added support for C8/C9/C10 MSRs: 4390 * 4391 * MSR_PKG_C8_RESIDENCY 0x00000630 4392 * MSR_PKG_C9_RESIDENCY 0x00000631 4393 * MSR_PKG_C10_RESIDENCY 0x00000632 4394 * 4395 * MSR_PKGC8_IRTL 0x00000633 4396 * MSR_PKGC9_IRTL 0x00000634 4397 * MSR_PKGC10_IRTL 0x00000635 4398 * 4399 */ 4400 int has_c8910_msrs(unsigned int family, unsigned int model) 4401 { 4402 if (!genuine_intel) 4403 return 0; 4404 4405 switch (model) { 4406 case INTEL_FAM6_HASWELL_L: /* HSW */ 4407 case INTEL_FAM6_BROADWELL: /* BDW */ 4408 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4409 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4410 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4411 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4412 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4413 return 1; 4414 } 4415 return 0; 4416 } 4417 4418 /* 4419 * SKL adds support for additional MSRS: 4420 * 4421 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 4422 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 4423 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 4424 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 4425 */ 4426 int has_skl_msrs(unsigned int family, unsigned int model) 4427 { 4428 if (!genuine_intel) 4429 return 0; 4430 4431 switch (model) { 4432 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4433 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4434 return 1; 4435 } 4436 return 0; 4437 } 4438 4439 int is_slm(unsigned int family, unsigned int model) 4440 { 4441 if (!genuine_intel) 4442 return 0; 4443 switch (model) { 4444 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4445 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 4446 return 1; 4447 } 4448 return 0; 4449 } 4450 4451 int is_knl(unsigned int family, unsigned int model) 4452 { 4453 if (!genuine_intel) 4454 return 0; 4455 switch (model) { 4456 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4457 return 1; 4458 } 4459 return 0; 4460 } 4461 4462 int is_cnl(unsigned int family, unsigned int model) 4463 { 4464 if (!genuine_intel) 4465 return 0; 4466 4467 switch (model) { 4468 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4469 return 1; 4470 } 4471 4472 return 0; 4473 } 4474 4475 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 4476 { 4477 if (is_knl(family, model)) 4478 return 1024; 4479 return 1; 4480 } 4481 4482 #define SLM_BCLK_FREQS 5 4483 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 4484 4485 double slm_bclk(void) 4486 { 4487 unsigned long long msr = 3; 4488 unsigned int i; 4489 double freq; 4490 4491 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 4492 fprintf(outf, "SLM BCLK: unknown\n"); 4493 4494 i = msr & 0xf; 4495 if (i >= SLM_BCLK_FREQS) { 4496 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 4497 i = 3; 4498 } 4499 freq = slm_freq_table[i]; 4500 4501 if (!quiet) 4502 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 4503 4504 return freq; 4505 } 4506 4507 double discover_bclk(unsigned int family, unsigned int model) 4508 { 4509 if (has_snb_msrs(family, model) || is_knl(family, model)) 4510 return 100.00; 4511 else if (is_slm(family, model)) 4512 return slm_bclk(); 4513 else 4514 return 133.33; 4515 } 4516 4517 /* 4518 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 4519 * the Thermal Control Circuit (TCC) activates. 4520 * This is usually equal to tjMax. 4521 * 4522 * Older processors do not have this MSR, so there we guess, 4523 * but also allow cmdline over-ride with -T. 4524 * 4525 * Several MSR temperature values are in units of degrees-C 4526 * below this value, including the Digital Thermal Sensor (DTS), 4527 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 4528 */ 4529 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4530 { 4531 unsigned long long msr; 4532 unsigned int target_c_local; 4533 int cpu; 4534 4535 /* tcc_activation_temp is used only for dts or ptm */ 4536 if (!(do_dts || do_ptm)) 4537 return 0; 4538 4539 /* this is a per-package concept */ 4540 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4541 return 0; 4542 4543 cpu = t->cpu_id; 4544 if (cpu_migrate(cpu)) { 4545 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4546 return -1; 4547 } 4548 4549 if (tcc_activation_temp_override != 0) { 4550 tcc_activation_temp = tcc_activation_temp_override; 4551 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 4552 cpu, tcc_activation_temp); 4553 return 0; 4554 } 4555 4556 /* Temperature Target MSR is Nehalem and newer only */ 4557 if (!do_nhm_platform_info) 4558 goto guess; 4559 4560 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 4561 goto guess; 4562 4563 target_c_local = (msr >> 16) & 0xFF; 4564 4565 if (!quiet) 4566 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 4567 cpu, msr, target_c_local); 4568 4569 if (!target_c_local) 4570 goto guess; 4571 4572 tcc_activation_temp = target_c_local; 4573 4574 return 0; 4575 4576 guess: 4577 tcc_activation_temp = TJMAX_DEFAULT; 4578 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 4579 cpu, tcc_activation_temp); 4580 4581 return 0; 4582 } 4583 4584 void decode_feature_control_msr(void) 4585 { 4586 unsigned long long msr; 4587 4588 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr)) 4589 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 4590 base_cpu, msr, 4591 msr & FEAT_CTL_LOCKED ? "" : "UN-", 4592 msr & (1 << 18) ? "SGX" : ""); 4593 } 4594 4595 void decode_misc_enable_msr(void) 4596 { 4597 unsigned long long msr; 4598 4599 if (!genuine_intel) 4600 return; 4601 4602 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 4603 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 4604 base_cpu, msr, 4605 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 4606 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 4607 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 4608 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 4609 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 4610 } 4611 4612 void decode_misc_feature_control(void) 4613 { 4614 unsigned long long msr; 4615 4616 if (!has_misc_feature_control) 4617 return; 4618 4619 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 4620 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 4621 base_cpu, msr, 4622 msr & (0 << 0) ? "No-" : "", 4623 msr & (1 << 0) ? "No-" : "", 4624 msr & (2 << 0) ? "No-" : "", 4625 msr & (3 << 0) ? "No-" : ""); 4626 } 4627 /* 4628 * Decode MSR_MISC_PWR_MGMT 4629 * 4630 * Decode the bits according to the Nehalem documentation 4631 * bit[0] seems to continue to have same meaning going forward 4632 * bit[1] less so... 4633 */ 4634 void decode_misc_pwr_mgmt_msr(void) 4635 { 4636 unsigned long long msr; 4637 4638 if (!do_nhm_platform_info) 4639 return; 4640 4641 if (no_MSR_MISC_PWR_MGMT) 4642 return; 4643 4644 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 4645 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 4646 base_cpu, msr, 4647 msr & (1 << 0) ? "DIS" : "EN", 4648 msr & (1 << 1) ? "EN" : "DIS", 4649 msr & (1 << 8) ? "EN" : "DIS"); 4650 } 4651 /* 4652 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 4653 * 4654 * This MSRs are present on Silvermont processors, 4655 * Intel Atom processor E3000 series (Baytrail), and friends. 4656 */ 4657 void decode_c6_demotion_policy_msr(void) 4658 { 4659 unsigned long long msr; 4660 4661 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 4662 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 4663 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4664 4665 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 4666 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 4667 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4668 } 4669 4670 /* 4671 * When models are the same, for the purpose of turbostat, reuse 4672 */ 4673 unsigned int intel_model_duplicates(unsigned int model) 4674 { 4675 4676 switch(model) { 4677 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 4678 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 4679 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 4680 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 4681 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 4682 return INTEL_FAM6_NEHALEM; 4683 4684 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 4685 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 4686 return INTEL_FAM6_NEHALEM_EX; 4687 4688 case INTEL_FAM6_XEON_PHI_KNM: 4689 return INTEL_FAM6_XEON_PHI_KNL; 4690 4691 case INTEL_FAM6_BROADWELL_X: 4692 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */ 4693 return INTEL_FAM6_BROADWELL_X; 4694 4695 case INTEL_FAM6_SKYLAKE_L: 4696 case INTEL_FAM6_SKYLAKE: 4697 case INTEL_FAM6_KABYLAKE_L: 4698 case INTEL_FAM6_KABYLAKE: 4699 case INTEL_FAM6_COMETLAKE_L: 4700 case INTEL_FAM6_COMETLAKE: 4701 return INTEL_FAM6_SKYLAKE_L; 4702 4703 case INTEL_FAM6_ICELAKE_L: 4704 case INTEL_FAM6_ICELAKE_NNPI: 4705 case INTEL_FAM6_TIGERLAKE_L: 4706 case INTEL_FAM6_TIGERLAKE: 4707 return INTEL_FAM6_CANNONLAKE_L; 4708 4709 case INTEL_FAM6_ATOM_TREMONT_D: 4710 return INTEL_FAM6_ATOM_GOLDMONT_D; 4711 4712 case INTEL_FAM6_ATOM_TREMONT_L: 4713 return INTEL_FAM6_ATOM_TREMONT; 4714 4715 case INTEL_FAM6_ICELAKE_X: 4716 return INTEL_FAM6_SKYLAKE_X; 4717 } 4718 return model; 4719 } 4720 void process_cpuid() 4721 { 4722 unsigned int eax, ebx, ecx, edx; 4723 unsigned int fms, family, model, stepping, ecx_flags, edx_flags; 4724 unsigned int has_turbo; 4725 4726 eax = ebx = ecx = edx = 0; 4727 4728 __cpuid(0, max_level, ebx, ecx, edx); 4729 4730 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) 4731 genuine_intel = 1; 4732 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) 4733 authentic_amd = 1; 4734 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e) 4735 hygon_genuine = 1; 4736 4737 if (!quiet) 4738 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 4739 (char *)&ebx, (char *)&edx, (char *)&ecx); 4740 4741 __cpuid(1, fms, ebx, ecx, edx); 4742 family = (fms >> 8) & 0xf; 4743 model = (fms >> 4) & 0xf; 4744 stepping = fms & 0xf; 4745 if (family == 0xf) 4746 family += (fms >> 20) & 0xff; 4747 if (family >= 6) 4748 model += ((fms >> 16) & 0xf) << 4; 4749 ecx_flags = ecx; 4750 edx_flags = edx; 4751 4752 /* 4753 * check max extended function levels of CPUID. 4754 * This is needed to check for invariant TSC. 4755 * This check is valid for both Intel and AMD. 4756 */ 4757 ebx = ecx = edx = 0; 4758 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 4759 4760 if (!quiet) { 4761 fprintf(outf, "0x%x CPUID levels; 0x%x xlevels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 4762 max_level, max_extended_level, family, model, stepping, family, model, stepping); 4763 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 4764 ecx_flags & (1 << 0) ? "SSE3" : "-", 4765 ecx_flags & (1 << 3) ? "MONITOR" : "-", 4766 ecx_flags & (1 << 6) ? "SMX" : "-", 4767 ecx_flags & (1 << 7) ? "EIST" : "-", 4768 ecx_flags & (1 << 8) ? "TM2" : "-", 4769 edx_flags & (1 << 4) ? "TSC" : "-", 4770 edx_flags & (1 << 5) ? "MSR" : "-", 4771 edx_flags & (1 << 22) ? "ACPI-TM" : "-", 4772 edx_flags & (1 << 28) ? "HT" : "-", 4773 edx_flags & (1 << 29) ? "TM" : "-"); 4774 } 4775 if (genuine_intel) 4776 model = intel_model_duplicates(model); 4777 4778 if (!(edx_flags & (1 << 5))) 4779 errx(1, "CPUID: no MSR"); 4780 4781 if (max_extended_level >= 0x80000007) { 4782 4783 /* 4784 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 4785 * this check is valid for both Intel and AMD 4786 */ 4787 __cpuid(0x80000007, eax, ebx, ecx, edx); 4788 has_invariant_tsc = edx & (1 << 8); 4789 } 4790 4791 /* 4792 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 4793 * this check is valid for both Intel and AMD 4794 */ 4795 4796 __cpuid(0x6, eax, ebx, ecx, edx); 4797 has_aperf = ecx & (1 << 0); 4798 if (has_aperf) { 4799 BIC_PRESENT(BIC_Avg_MHz); 4800 BIC_PRESENT(BIC_Busy); 4801 BIC_PRESENT(BIC_Bzy_MHz); 4802 } 4803 do_dts = eax & (1 << 0); 4804 if (do_dts) 4805 BIC_PRESENT(BIC_CoreTmp); 4806 has_turbo = eax & (1 << 1); 4807 do_ptm = eax & (1 << 6); 4808 if (do_ptm) 4809 BIC_PRESENT(BIC_PkgTmp); 4810 has_hwp = eax & (1 << 7); 4811 has_hwp_notify = eax & (1 << 8); 4812 has_hwp_activity_window = eax & (1 << 9); 4813 has_hwp_epp = eax & (1 << 10); 4814 has_hwp_pkg = eax & (1 << 11); 4815 has_epb = ecx & (1 << 3); 4816 4817 if (!quiet) 4818 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 4819 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 4820 has_aperf ? "" : "No-", 4821 has_turbo ? "" : "No-", 4822 do_dts ? "" : "No-", 4823 do_ptm ? "" : "No-", 4824 has_hwp ? "" : "No-", 4825 has_hwp_notify ? "" : "No-", 4826 has_hwp_activity_window ? "" : "No-", 4827 has_hwp_epp ? "" : "No-", 4828 has_hwp_pkg ? "" : "No-", 4829 has_epb ? "" : "No-"); 4830 4831 if (!quiet) 4832 decode_misc_enable_msr(); 4833 4834 4835 if (max_level >= 0x7 && !quiet) { 4836 int has_sgx; 4837 4838 ecx = 0; 4839 4840 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 4841 4842 has_sgx = ebx & (1 << 2); 4843 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 4844 4845 if (has_sgx) 4846 decode_feature_control_msr(); 4847 } 4848 4849 if (max_level >= 0x15) { 4850 unsigned int eax_crystal; 4851 unsigned int ebx_tsc; 4852 4853 /* 4854 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 4855 */ 4856 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 4857 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 4858 4859 if (ebx_tsc != 0) { 4860 4861 if (!quiet && (ebx != 0)) 4862 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 4863 eax_crystal, ebx_tsc, crystal_hz); 4864 4865 if (crystal_hz == 0) 4866 switch(model) { 4867 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4868 crystal_hz = 24000000; /* 24.0 MHz */ 4869 break; 4870 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 4871 crystal_hz = 25000000; /* 25.0 MHz */ 4872 break; 4873 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4874 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4875 crystal_hz = 19200000; /* 19.2 MHz */ 4876 break; 4877 default: 4878 crystal_hz = 0; 4879 } 4880 4881 if (crystal_hz) { 4882 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 4883 if (!quiet) 4884 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 4885 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 4886 } 4887 } 4888 } 4889 if (max_level >= 0x16) { 4890 unsigned int base_mhz, max_mhz, bus_mhz, edx; 4891 4892 /* 4893 * CPUID 16H Base MHz, Max MHz, Bus MHz 4894 */ 4895 base_mhz = max_mhz = bus_mhz = edx = 0; 4896 4897 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 4898 if (!quiet) 4899 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 4900 base_mhz, max_mhz, bus_mhz); 4901 } 4902 4903 if (has_aperf) 4904 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 4905 4906 BIC_PRESENT(BIC_IRQ); 4907 BIC_PRESENT(BIC_TSC_MHz); 4908 4909 if (probe_nhm_msrs(family, model)) { 4910 do_nhm_platform_info = 1; 4911 BIC_PRESENT(BIC_CPU_c1); 4912 BIC_PRESENT(BIC_CPU_c3); 4913 BIC_PRESENT(BIC_CPU_c6); 4914 BIC_PRESENT(BIC_SMI); 4915 } 4916 do_snb_cstates = has_snb_msrs(family, model); 4917 4918 if (do_snb_cstates) 4919 BIC_PRESENT(BIC_CPU_c7); 4920 4921 do_irtl_snb = has_snb_msrs(family, model); 4922 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 4923 BIC_PRESENT(BIC_Pkgpc2); 4924 if (pkg_cstate_limit >= PCL__3) 4925 BIC_PRESENT(BIC_Pkgpc3); 4926 if (pkg_cstate_limit >= PCL__6) 4927 BIC_PRESENT(BIC_Pkgpc6); 4928 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 4929 BIC_PRESENT(BIC_Pkgpc7); 4930 if (has_slv_msrs(family, model)) { 4931 BIC_NOT_PRESENT(BIC_Pkgpc2); 4932 BIC_NOT_PRESENT(BIC_Pkgpc3); 4933 BIC_PRESENT(BIC_Pkgpc6); 4934 BIC_NOT_PRESENT(BIC_Pkgpc7); 4935 BIC_PRESENT(BIC_Mod_c6); 4936 use_c1_residency_msr = 1; 4937 } 4938 if (is_dnv(family, model)) { 4939 BIC_PRESENT(BIC_CPU_c1); 4940 BIC_NOT_PRESENT(BIC_CPU_c3); 4941 BIC_NOT_PRESENT(BIC_Pkgpc3); 4942 BIC_NOT_PRESENT(BIC_CPU_c7); 4943 BIC_NOT_PRESENT(BIC_Pkgpc7); 4944 use_c1_residency_msr = 1; 4945 } 4946 if (is_skx(family, model)) { 4947 BIC_NOT_PRESENT(BIC_CPU_c3); 4948 BIC_NOT_PRESENT(BIC_Pkgpc3); 4949 BIC_NOT_PRESENT(BIC_CPU_c7); 4950 BIC_NOT_PRESENT(BIC_Pkgpc7); 4951 } 4952 if (is_bdx(family, model)) { 4953 BIC_NOT_PRESENT(BIC_CPU_c7); 4954 BIC_NOT_PRESENT(BIC_Pkgpc7); 4955 } 4956 if (has_c8910_msrs(family, model)) { 4957 BIC_PRESENT(BIC_Pkgpc8); 4958 BIC_PRESENT(BIC_Pkgpc9); 4959 BIC_PRESENT(BIC_Pkgpc10); 4960 } 4961 do_irtl_hsw = has_c8910_msrs(family, model); 4962 if (has_skl_msrs(family, model)) { 4963 BIC_PRESENT(BIC_Totl_c0); 4964 BIC_PRESENT(BIC_Any_c0); 4965 BIC_PRESENT(BIC_GFX_c0); 4966 BIC_PRESENT(BIC_CPUGFX); 4967 } 4968 do_slm_cstates = is_slm(family, model); 4969 do_knl_cstates = is_knl(family, model); 4970 4971 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || 4972 is_ehl(family, model)) 4973 BIC_NOT_PRESENT(BIC_CPU_c3); 4974 4975 if (!quiet) 4976 decode_misc_pwr_mgmt_msr(); 4977 4978 if (!quiet && has_slv_msrs(family, model)) 4979 decode_c6_demotion_policy_msr(); 4980 4981 rapl_probe(family, model); 4982 perf_limit_reasons_probe(family, model); 4983 automatic_cstate_conversion_probe(family, model); 4984 4985 if (!quiet) 4986 dump_cstate_pstate_config_info(family, model); 4987 4988 if (!quiet) 4989 dump_sysfs_cstate_config(); 4990 if (!quiet) 4991 dump_sysfs_pstate_config(); 4992 4993 if (has_skl_msrs(family, model)) 4994 calculate_tsc_tweak(); 4995 4996 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 4997 BIC_PRESENT(BIC_GFX_rc6); 4998 4999 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 5000 BIC_PRESENT(BIC_GFXMHz); 5001 5002 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 5003 BIC_PRESENT(BIC_CPU_LPI); 5004 else 5005 BIC_NOT_PRESENT(BIC_CPU_LPI); 5006 5007 if (!access(sys_lpi_file_sysfs, R_OK)) { 5008 sys_lpi_file = sys_lpi_file_sysfs; 5009 BIC_PRESENT(BIC_SYS_LPI); 5010 } else if (!access(sys_lpi_file_debugfs, R_OK)) { 5011 sys_lpi_file = sys_lpi_file_debugfs; 5012 BIC_PRESENT(BIC_SYS_LPI); 5013 } else { 5014 sys_lpi_file_sysfs = NULL; 5015 BIC_NOT_PRESENT(BIC_SYS_LPI); 5016 } 5017 5018 if (!quiet) 5019 decode_misc_feature_control(); 5020 5021 return; 5022 } 5023 5024 /* 5025 * in /dev/cpu/ return success for names that are numbers 5026 * ie. filter out ".", "..", "microcode". 5027 */ 5028 int dir_filter(const struct dirent *dirp) 5029 { 5030 if (isdigit(dirp->d_name[0])) 5031 return 1; 5032 else 5033 return 0; 5034 } 5035 5036 int open_dev_cpu_msr(int dummy1) 5037 { 5038 return 0; 5039 } 5040 5041 void topology_probe() 5042 { 5043 int i; 5044 int max_core_id = 0; 5045 int max_package_id = 0; 5046 int max_die_id = 0; 5047 int max_siblings = 0; 5048 5049 /* Initialize num_cpus, max_cpu_num */ 5050 set_max_cpu_num(); 5051 topo.num_cpus = 0; 5052 for_all_proc_cpus(count_cpus); 5053 if (!summary_only && topo.num_cpus > 1) 5054 BIC_PRESENT(BIC_CPU); 5055 5056 if (debug > 1) 5057 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 5058 5059 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 5060 if (cpus == NULL) 5061 err(1, "calloc cpus"); 5062 5063 /* 5064 * Allocate and initialize cpu_present_set 5065 */ 5066 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5067 if (cpu_present_set == NULL) 5068 err(3, "CPU_ALLOC"); 5069 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5070 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 5071 for_all_proc_cpus(mark_cpu_present); 5072 5073 /* 5074 * Validate that all cpus in cpu_subset are also in cpu_present_set 5075 */ 5076 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 5077 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 5078 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) 5079 err(1, "cpu%d not present", i); 5080 } 5081 5082 /* 5083 * Allocate and initialize cpu_affinity_set 5084 */ 5085 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5086 if (cpu_affinity_set == NULL) 5087 err(3, "CPU_ALLOC"); 5088 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5089 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 5090 5091 for_all_proc_cpus(init_thread_id); 5092 5093 /* 5094 * For online cpus 5095 * find max_core_id, max_package_id 5096 */ 5097 for (i = 0; i <= topo.max_cpu_num; ++i) { 5098 int siblings; 5099 5100 if (cpu_is_not_present(i)) { 5101 if (debug > 1) 5102 fprintf(outf, "cpu%d NOT PRESENT\n", i); 5103 continue; 5104 } 5105 5106 cpus[i].logical_cpu_id = i; 5107 5108 /* get package information */ 5109 cpus[i].physical_package_id = get_physical_package_id(i); 5110 if (cpus[i].physical_package_id > max_package_id) 5111 max_package_id = cpus[i].physical_package_id; 5112 5113 /* get die information */ 5114 cpus[i].die_id = get_die_id(i); 5115 if (cpus[i].die_id > max_die_id) 5116 max_die_id = cpus[i].die_id; 5117 5118 /* get numa node information */ 5119 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 5120 if (cpus[i].physical_node_id > topo.max_node_num) 5121 topo.max_node_num = cpus[i].physical_node_id; 5122 5123 /* get core information */ 5124 cpus[i].physical_core_id = get_core_id(i); 5125 if (cpus[i].physical_core_id > max_core_id) 5126 max_core_id = cpus[i].physical_core_id; 5127 5128 /* get thread information */ 5129 siblings = get_thread_siblings(&cpus[i]); 5130 if (siblings > max_siblings) 5131 max_siblings = siblings; 5132 if (cpus[i].thread_id == 0) 5133 topo.num_cores++; 5134 } 5135 5136 topo.cores_per_node = max_core_id + 1; 5137 if (debug > 1) 5138 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 5139 max_core_id, topo.cores_per_node); 5140 if (!summary_only && topo.cores_per_node > 1) 5141 BIC_PRESENT(BIC_Core); 5142 5143 topo.num_die = max_die_id + 1; 5144 if (debug > 1) 5145 fprintf(outf, "max_die_id %d, sizing for %d die\n", 5146 max_die_id, topo.num_die); 5147 if (!summary_only && topo.num_die > 1) 5148 BIC_PRESENT(BIC_Die); 5149 5150 topo.num_packages = max_package_id + 1; 5151 if (debug > 1) 5152 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 5153 max_package_id, topo.num_packages); 5154 if (!summary_only && topo.num_packages > 1) 5155 BIC_PRESENT(BIC_Package); 5156 5157 set_node_data(); 5158 if (debug > 1) 5159 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 5160 if (!summary_only && topo.nodes_per_pkg > 1) 5161 BIC_PRESENT(BIC_Node); 5162 5163 topo.threads_per_core = max_siblings; 5164 if (debug > 1) 5165 fprintf(outf, "max_siblings %d\n", max_siblings); 5166 5167 if (debug < 1) 5168 return; 5169 5170 for (i = 0; i <= topo.max_cpu_num; ++i) { 5171 if (cpu_is_not_present(i)) 5172 continue; 5173 fprintf(outf, 5174 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n", 5175 i, cpus[i].physical_package_id, cpus[i].die_id, 5176 cpus[i].physical_node_id, 5177 cpus[i].logical_node_id, 5178 cpus[i].physical_core_id, 5179 cpus[i].thread_id); 5180 } 5181 5182 } 5183 5184 void 5185 allocate_counters(struct thread_data **t, struct core_data **c, 5186 struct pkg_data **p) 5187 { 5188 int i; 5189 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * 5190 topo.num_packages; 5191 int num_threads = topo.threads_per_core * num_cores; 5192 5193 *t = calloc(num_threads, sizeof(struct thread_data)); 5194 if (*t == NULL) 5195 goto error; 5196 5197 for (i = 0; i < num_threads; i++) 5198 (*t)[i].cpu_id = -1; 5199 5200 *c = calloc(num_cores, sizeof(struct core_data)); 5201 if (*c == NULL) 5202 goto error; 5203 5204 for (i = 0; i < num_cores; i++) 5205 (*c)[i].core_id = -1; 5206 5207 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 5208 if (*p == NULL) 5209 goto error; 5210 5211 for (i = 0; i < topo.num_packages; i++) 5212 (*p)[i].package_id = i; 5213 5214 return; 5215 error: 5216 err(1, "calloc counters"); 5217 } 5218 /* 5219 * init_counter() 5220 * 5221 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 5222 */ 5223 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 5224 struct pkg_data *pkg_base, int cpu_id) 5225 { 5226 int pkg_id = cpus[cpu_id].physical_package_id; 5227 int node_id = cpus[cpu_id].logical_node_id; 5228 int core_id = cpus[cpu_id].physical_core_id; 5229 int thread_id = cpus[cpu_id].thread_id; 5230 struct thread_data *t; 5231 struct core_data *c; 5232 struct pkg_data *p; 5233 5234 5235 /* Workaround for systems where physical_node_id==-1 5236 * and logical_node_id==(-1 - topo.num_cpus) 5237 */ 5238 if (node_id < 0) 5239 node_id = 0; 5240 5241 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 5242 c = GET_CORE(core_base, core_id, node_id, pkg_id); 5243 p = GET_PKG(pkg_base, pkg_id); 5244 5245 t->cpu_id = cpu_id; 5246 if (thread_id == 0) { 5247 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 5248 if (cpu_is_first_core_in_package(cpu_id)) 5249 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 5250 } 5251 5252 c->core_id = core_id; 5253 p->package_id = pkg_id; 5254 } 5255 5256 5257 int initialize_counters(int cpu_id) 5258 { 5259 init_counter(EVEN_COUNTERS, cpu_id); 5260 init_counter(ODD_COUNTERS, cpu_id); 5261 return 0; 5262 } 5263 5264 void allocate_output_buffer() 5265 { 5266 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048); 5267 outp = output_buffer; 5268 if (outp == NULL) 5269 err(-1, "calloc output buffer"); 5270 } 5271 void allocate_fd_percpu(void) 5272 { 5273 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5274 if (fd_percpu == NULL) 5275 err(-1, "calloc fd_percpu"); 5276 } 5277 void allocate_irq_buffers(void) 5278 { 5279 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 5280 if (irq_column_2_cpu == NULL) 5281 err(-1, "calloc %d", topo.num_cpus); 5282 5283 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5284 if (irqs_per_cpu == NULL) 5285 err(-1, "calloc %d", topo.max_cpu_num + 1); 5286 } 5287 void setup_all_buffers(void) 5288 { 5289 topology_probe(); 5290 allocate_irq_buffers(); 5291 allocate_fd_percpu(); 5292 allocate_counters(&thread_even, &core_even, &package_even); 5293 allocate_counters(&thread_odd, &core_odd, &package_odd); 5294 allocate_output_buffer(); 5295 for_all_proc_cpus(initialize_counters); 5296 } 5297 5298 void set_base_cpu(void) 5299 { 5300 base_cpu = sched_getcpu(); 5301 if (base_cpu < 0) 5302 err(-ENODEV, "No valid cpus found"); 5303 5304 if (debug > 1) 5305 fprintf(outf, "base_cpu = %d\n", base_cpu); 5306 } 5307 5308 void turbostat_init() 5309 { 5310 setup_all_buffers(); 5311 set_base_cpu(); 5312 check_dev_msr(); 5313 check_permissions(); 5314 process_cpuid(); 5315 5316 5317 if (!quiet) 5318 for_all_cpus(print_hwp, ODD_COUNTERS); 5319 5320 if (!quiet) 5321 for_all_cpus(print_epb, ODD_COUNTERS); 5322 5323 if (!quiet) 5324 for_all_cpus(print_perf_limit, ODD_COUNTERS); 5325 5326 if (!quiet) 5327 for_all_cpus(print_rapl, ODD_COUNTERS); 5328 5329 for_all_cpus(set_temperature_target, ODD_COUNTERS); 5330 5331 if (!quiet) 5332 for_all_cpus(print_thermal, ODD_COUNTERS); 5333 5334 if (!quiet && do_irtl_snb) 5335 print_irtl(); 5336 } 5337 5338 int fork_it(char **argv) 5339 { 5340 pid_t child_pid; 5341 int status; 5342 5343 snapshot_proc_sysfs_files(); 5344 status = for_all_cpus(get_counters, EVEN_COUNTERS); 5345 first_counter_read = 0; 5346 if (status) 5347 exit(status); 5348 /* clear affinity side-effect of get_counters() */ 5349 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 5350 gettimeofday(&tv_even, (struct timezone *)NULL); 5351 5352 child_pid = fork(); 5353 if (!child_pid) { 5354 /* child */ 5355 execvp(argv[0], argv); 5356 err(errno, "exec %s", argv[0]); 5357 } else { 5358 5359 /* parent */ 5360 if (child_pid == -1) 5361 err(1, "fork"); 5362 5363 signal(SIGINT, SIG_IGN); 5364 signal(SIGQUIT, SIG_IGN); 5365 if (waitpid(child_pid, &status, 0) == -1) 5366 err(status, "waitpid"); 5367 5368 if (WIFEXITED(status)) 5369 status = WEXITSTATUS(status); 5370 } 5371 /* 5372 * n.b. fork_it() does not check for errors from for_all_cpus() 5373 * because re-starting is problematic when forking 5374 */ 5375 snapshot_proc_sysfs_files(); 5376 for_all_cpus(get_counters, ODD_COUNTERS); 5377 gettimeofday(&tv_odd, (struct timezone *)NULL); 5378 timersub(&tv_odd, &tv_even, &tv_delta); 5379 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 5380 fprintf(outf, "%s: Counter reset detected\n", progname); 5381 else { 5382 compute_average(EVEN_COUNTERS); 5383 format_all_counters(EVEN_COUNTERS); 5384 } 5385 5386 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 5387 5388 flush_output_stderr(); 5389 5390 return status; 5391 } 5392 5393 int get_and_dump_counters(void) 5394 { 5395 int status; 5396 5397 snapshot_proc_sysfs_files(); 5398 status = for_all_cpus(get_counters, ODD_COUNTERS); 5399 if (status) 5400 return status; 5401 5402 status = for_all_cpus(dump_counters, ODD_COUNTERS); 5403 if (status) 5404 return status; 5405 5406 flush_output_stdout(); 5407 5408 return status; 5409 } 5410 5411 void print_version() { 5412 fprintf(outf, "turbostat version 20.03.20" 5413 " - Len Brown <lenb@kernel.org>\n"); 5414 } 5415 5416 int add_counter(unsigned int msr_num, char *path, char *name, 5417 unsigned int width, enum counter_scope scope, 5418 enum counter_type type, enum counter_format format, int flags) 5419 { 5420 struct msr_counter *msrp; 5421 5422 msrp = calloc(1, sizeof(struct msr_counter)); 5423 if (msrp == NULL) { 5424 perror("calloc"); 5425 exit(1); 5426 } 5427 5428 msrp->msr_num = msr_num; 5429 strncpy(msrp->name, name, NAME_BYTES - 1); 5430 if (path) 5431 strncpy(msrp->path, path, PATH_BYTES - 1); 5432 msrp->width = width; 5433 msrp->type = type; 5434 msrp->format = format; 5435 msrp->flags = flags; 5436 5437 switch (scope) { 5438 5439 case SCOPE_CPU: 5440 msrp->next = sys.tp; 5441 sys.tp = msrp; 5442 sys.added_thread_counters++; 5443 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 5444 fprintf(stderr, "exceeded max %d added thread counters\n", 5445 MAX_ADDED_COUNTERS); 5446 exit(-1); 5447 } 5448 break; 5449 5450 case SCOPE_CORE: 5451 msrp->next = sys.cp; 5452 sys.cp = msrp; 5453 sys.added_core_counters++; 5454 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 5455 fprintf(stderr, "exceeded max %d added core counters\n", 5456 MAX_ADDED_COUNTERS); 5457 exit(-1); 5458 } 5459 break; 5460 5461 case SCOPE_PACKAGE: 5462 msrp->next = sys.pp; 5463 sys.pp = msrp; 5464 sys.added_package_counters++; 5465 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 5466 fprintf(stderr, "exceeded max %d added package counters\n", 5467 MAX_ADDED_COUNTERS); 5468 exit(-1); 5469 } 5470 break; 5471 } 5472 5473 return 0; 5474 } 5475 5476 void parse_add_command(char *add_command) 5477 { 5478 int msr_num = 0; 5479 char *path = NULL; 5480 char name_buffer[NAME_BYTES] = ""; 5481 int width = 64; 5482 int fail = 0; 5483 enum counter_scope scope = SCOPE_CPU; 5484 enum counter_type type = COUNTER_CYCLES; 5485 enum counter_format format = FORMAT_DELTA; 5486 5487 while (add_command) { 5488 5489 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 5490 goto next; 5491 5492 if (sscanf(add_command, "msr%d", &msr_num) == 1) 5493 goto next; 5494 5495 if (*add_command == '/') { 5496 path = add_command; 5497 goto next; 5498 } 5499 5500 if (sscanf(add_command, "u%d", &width) == 1) { 5501 if ((width == 32) || (width == 64)) 5502 goto next; 5503 width = 64; 5504 } 5505 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 5506 scope = SCOPE_CPU; 5507 goto next; 5508 } 5509 if (!strncmp(add_command, "core", strlen("core"))) { 5510 scope = SCOPE_CORE; 5511 goto next; 5512 } 5513 if (!strncmp(add_command, "package", strlen("package"))) { 5514 scope = SCOPE_PACKAGE; 5515 goto next; 5516 } 5517 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 5518 type = COUNTER_CYCLES; 5519 goto next; 5520 } 5521 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 5522 type = COUNTER_SECONDS; 5523 goto next; 5524 } 5525 if (!strncmp(add_command, "usec", strlen("usec"))) { 5526 type = COUNTER_USEC; 5527 goto next; 5528 } 5529 if (!strncmp(add_command, "raw", strlen("raw"))) { 5530 format = FORMAT_RAW; 5531 goto next; 5532 } 5533 if (!strncmp(add_command, "delta", strlen("delta"))) { 5534 format = FORMAT_DELTA; 5535 goto next; 5536 } 5537 if (!strncmp(add_command, "percent", strlen("percent"))) { 5538 format = FORMAT_PERCENT; 5539 goto next; 5540 } 5541 5542 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 5543 char *eos; 5544 5545 eos = strchr(name_buffer, ','); 5546 if (eos) 5547 *eos = '\0'; 5548 goto next; 5549 } 5550 5551 next: 5552 add_command = strchr(add_command, ','); 5553 if (add_command) { 5554 *add_command = '\0'; 5555 add_command++; 5556 } 5557 5558 } 5559 if ((msr_num == 0) && (path == NULL)) { 5560 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 5561 fail++; 5562 } 5563 5564 /* generate default column header */ 5565 if (*name_buffer == '\0') { 5566 if (width == 32) 5567 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5568 else 5569 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5570 } 5571 5572 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 5573 fail++; 5574 5575 if (fail) { 5576 help(); 5577 exit(1); 5578 } 5579 } 5580 5581 int is_deferred_skip(char *name) 5582 { 5583 int i; 5584 5585 for (i = 0; i < deferred_skip_index; ++i) 5586 if (!strcmp(name, deferred_skip_names[i])) 5587 return 1; 5588 return 0; 5589 } 5590 5591 void probe_sysfs(void) 5592 { 5593 char path[64]; 5594 char name_buf[16]; 5595 FILE *input; 5596 int state; 5597 char *sp; 5598 5599 if (!DO_BIC(BIC_sysfs)) 5600 return; 5601 5602 for (state = 10; state >= 0; --state) { 5603 5604 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5605 base_cpu, state); 5606 input = fopen(path, "r"); 5607 if (input == NULL) 5608 continue; 5609 if (!fgets(name_buf, sizeof(name_buf), input)) 5610 err(1, "%s: failed to read file", path); 5611 5612 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5613 sp = strchr(name_buf, '-'); 5614 if (!sp) 5615 sp = strchrnul(name_buf, '\n'); 5616 *sp = '%'; 5617 *(sp + 1) = '\0'; 5618 5619 fclose(input); 5620 5621 sprintf(path, "cpuidle/state%d/time", state); 5622 5623 if (is_deferred_skip(name_buf)) 5624 continue; 5625 5626 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, 5627 FORMAT_PERCENT, SYSFS_PERCPU); 5628 } 5629 5630 for (state = 10; state >= 0; --state) { 5631 5632 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5633 base_cpu, state); 5634 input = fopen(path, "r"); 5635 if (input == NULL) 5636 continue; 5637 if (!fgets(name_buf, sizeof(name_buf), input)) 5638 err(1, "%s: failed to read file", path); 5639 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5640 sp = strchr(name_buf, '-'); 5641 if (!sp) 5642 sp = strchrnul(name_buf, '\n'); 5643 *sp = '\0'; 5644 fclose(input); 5645 5646 sprintf(path, "cpuidle/state%d/usage", state); 5647 5648 if (is_deferred_skip(name_buf)) 5649 continue; 5650 5651 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, 5652 FORMAT_DELTA, SYSFS_PERCPU); 5653 } 5654 5655 } 5656 5657 5658 /* 5659 * parse cpuset with following syntax 5660 * 1,2,4..6,8-10 and set bits in cpu_subset 5661 */ 5662 void parse_cpu_command(char *optarg) 5663 { 5664 unsigned int start, end; 5665 char *next; 5666 5667 if (!strcmp(optarg, "core")) { 5668 if (cpu_subset) 5669 goto error; 5670 show_core_only++; 5671 return; 5672 } 5673 if (!strcmp(optarg, "package")) { 5674 if (cpu_subset) 5675 goto error; 5676 show_pkg_only++; 5677 return; 5678 } 5679 if (show_core_only || show_pkg_only) 5680 goto error; 5681 5682 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 5683 if (cpu_subset == NULL) 5684 err(3, "CPU_ALLOC"); 5685 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 5686 5687 CPU_ZERO_S(cpu_subset_size, cpu_subset); 5688 5689 next = optarg; 5690 5691 while (next && *next) { 5692 5693 if (*next == '-') /* no negative cpu numbers */ 5694 goto error; 5695 5696 start = strtoul(next, &next, 10); 5697 5698 if (start >= CPU_SUBSET_MAXCPUS) 5699 goto error; 5700 CPU_SET_S(start, cpu_subset_size, cpu_subset); 5701 5702 if (*next == '\0') 5703 break; 5704 5705 if (*next == ',') { 5706 next += 1; 5707 continue; 5708 } 5709 5710 if (*next == '-') { 5711 next += 1; /* start range */ 5712 } else if (*next == '.') { 5713 next += 1; 5714 if (*next == '.') 5715 next += 1; /* start range */ 5716 else 5717 goto error; 5718 } 5719 5720 end = strtoul(next, &next, 10); 5721 if (end <= start) 5722 goto error; 5723 5724 while (++start <= end) { 5725 if (start >= CPU_SUBSET_MAXCPUS) 5726 goto error; 5727 CPU_SET_S(start, cpu_subset_size, cpu_subset); 5728 } 5729 5730 if (*next == ',') 5731 next += 1; 5732 else if (*next != '\0') 5733 goto error; 5734 } 5735 5736 return; 5737 5738 error: 5739 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 5740 help(); 5741 exit(-1); 5742 } 5743 5744 5745 void cmdline(int argc, char **argv) 5746 { 5747 int opt; 5748 int option_index = 0; 5749 static struct option long_options[] = { 5750 {"add", required_argument, 0, 'a'}, 5751 {"cpu", required_argument, 0, 'c'}, 5752 {"Dump", no_argument, 0, 'D'}, 5753 {"debug", no_argument, 0, 'd'}, /* internal, not documented */ 5754 {"enable", required_argument, 0, 'e'}, 5755 {"interval", required_argument, 0, 'i'}, 5756 {"num_iterations", required_argument, 0, 'n'}, 5757 {"help", no_argument, 0, 'h'}, 5758 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help 5759 {"Joules", no_argument, 0, 'J'}, 5760 {"list", no_argument, 0, 'l'}, 5761 {"out", required_argument, 0, 'o'}, 5762 {"quiet", no_argument, 0, 'q'}, 5763 {"show", required_argument, 0, 's'}, 5764 {"Summary", no_argument, 0, 'S'}, 5765 {"TCC", required_argument, 0, 'T'}, 5766 {"version", no_argument, 0, 'v' }, 5767 {0, 0, 0, 0 } 5768 }; 5769 5770 progname = argv[0]; 5771 5772 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", 5773 long_options, &option_index)) != -1) { 5774 switch (opt) { 5775 case 'a': 5776 parse_add_command(optarg); 5777 break; 5778 case 'c': 5779 parse_cpu_command(optarg); 5780 break; 5781 case 'D': 5782 dump_only++; 5783 break; 5784 case 'e': 5785 /* --enable specified counter */ 5786 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 5787 break; 5788 case 'd': 5789 debug++; 5790 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 5791 break; 5792 case 'H': 5793 /* 5794 * --hide: do not show those specified 5795 * multiple invocations simply clear more bits in enabled mask 5796 */ 5797 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 5798 break; 5799 case 'h': 5800 default: 5801 help(); 5802 exit(1); 5803 case 'i': 5804 { 5805 double interval = strtod(optarg, NULL); 5806 5807 if (interval < 0.001) { 5808 fprintf(outf, "interval %f seconds is too small\n", 5809 interval); 5810 exit(2); 5811 } 5812 5813 interval_tv.tv_sec = interval_ts.tv_sec = interval; 5814 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 5815 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 5816 } 5817 break; 5818 case 'J': 5819 rapl_joules++; 5820 break; 5821 case 'l': 5822 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 5823 list_header_only++; 5824 quiet++; 5825 break; 5826 case 'o': 5827 outf = fopen_or_die(optarg, "w"); 5828 break; 5829 case 'q': 5830 quiet = 1; 5831 break; 5832 case 'n': 5833 num_iterations = strtod(optarg, NULL); 5834 5835 if (num_iterations <= 0) { 5836 fprintf(outf, "iterations %d should be positive number\n", 5837 num_iterations); 5838 exit(2); 5839 } 5840 break; 5841 case 's': 5842 /* 5843 * --show: show only those specified 5844 * The 1st invocation will clear and replace the enabled mask 5845 * subsequent invocations can add to it. 5846 */ 5847 if (shown == 0) 5848 bic_enabled = bic_lookup(optarg, SHOW_LIST); 5849 else 5850 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 5851 shown = 1; 5852 break; 5853 case 'S': 5854 summary_only++; 5855 break; 5856 case 'T': 5857 tcc_activation_temp_override = atoi(optarg); 5858 break; 5859 case 'v': 5860 print_version(); 5861 exit(0); 5862 break; 5863 } 5864 } 5865 } 5866 5867 int main(int argc, char **argv) 5868 { 5869 outf = stderr; 5870 cmdline(argc, argv); 5871 5872 if (!quiet) 5873 print_version(); 5874 5875 probe_sysfs(); 5876 5877 turbostat_init(); 5878 5879 /* dump counters and exit */ 5880 if (dump_only) 5881 return get_and_dump_counters(); 5882 5883 /* list header and exit */ 5884 if (list_header_only) { 5885 print_header(","); 5886 flush_output_stdout(); 5887 return 0; 5888 } 5889 5890 /* 5891 * if any params left, it must be a command to fork 5892 */ 5893 if (argc - optind) 5894 return fork_it(argv + optind); 5895 else 5896 turbostat_loop(); 5897 5898 return 0; 5899 } 5900