1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * turbostat -- show CPU frequency and C-state residency 4 * on modern Intel and AMD processors. 5 * 6 * Copyright (c) 2013 Intel Corporation. 7 * Len Brown <len.brown@intel.com> 8 */ 9 10 #define _GNU_SOURCE 11 #include MSRHEADER 12 #include INTEL_FAMILY_HEADER 13 #include <stdarg.h> 14 #include <stdio.h> 15 #include <err.h> 16 #include <unistd.h> 17 #include <sys/types.h> 18 #include <sys/wait.h> 19 #include <sys/stat.h> 20 #include <sys/select.h> 21 #include <sys/resource.h> 22 #include <fcntl.h> 23 #include <signal.h> 24 #include <sys/time.h> 25 #include <stdlib.h> 26 #include <getopt.h> 27 #include <dirent.h> 28 #include <string.h> 29 #include <ctype.h> 30 #include <sched.h> 31 #include <time.h> 32 #include <cpuid.h> 33 #include <sys/capability.h> 34 #include <errno.h> 35 #include <math.h> 36 #include <linux/perf_event.h> 37 #include <asm/unistd.h> 38 #include <stdbool.h> 39 40 char *proc_stat = "/proc/stat"; 41 FILE *outf; 42 int *fd_percpu; 43 int *fd_instr_count_percpu; 44 struct timeval interval_tv = { 5, 0 }; 45 struct timespec interval_ts = { 5, 0 }; 46 47 /* Save original CPU model */ 48 unsigned int model_orig; 49 50 unsigned int num_iterations; 51 unsigned int debug; 52 unsigned int quiet; 53 unsigned int shown; 54 unsigned int sums_need_wide_columns; 55 unsigned int rapl_joules; 56 unsigned int summary_only; 57 unsigned int list_header_only; 58 unsigned int dump_only; 59 unsigned int do_snb_cstates; 60 unsigned int do_knl_cstates; 61 unsigned int do_slm_cstates; 62 unsigned int use_c1_residency_msr; 63 unsigned int has_aperf; 64 unsigned int has_epb; 65 unsigned int do_irtl_snb; 66 unsigned int do_irtl_hsw; 67 unsigned int units = 1000000; /* MHz etc */ 68 unsigned int genuine_intel; 69 unsigned int authentic_amd; 70 unsigned int hygon_genuine; 71 unsigned int max_level, max_extended_level; 72 unsigned int has_invariant_tsc; 73 unsigned int do_nhm_platform_info; 74 unsigned int no_MSR_MISC_PWR_MGMT; 75 unsigned int aperf_mperf_multiplier = 1; 76 double bclk; 77 double base_hz; 78 unsigned int has_base_hz; 79 double tsc_tweak = 1.0; 80 unsigned int show_pkg_only; 81 unsigned int show_core_only; 82 char *output_buffer, *outp; 83 unsigned int do_rapl; 84 unsigned int do_dts; 85 unsigned int do_ptm; 86 unsigned int do_ipc; 87 unsigned long long gfx_cur_rc6_ms; 88 unsigned long long cpuidle_cur_cpu_lpi_us; 89 unsigned long long cpuidle_cur_sys_lpi_us; 90 unsigned int gfx_cur_mhz; 91 unsigned int gfx_act_mhz; 92 unsigned int tj_max; 93 unsigned int tj_max_override; 94 int tcc_offset_bits; 95 double rapl_power_units, rapl_time_units; 96 double rapl_dram_energy_units, rapl_energy_units; 97 double rapl_joule_counter_range; 98 unsigned int do_core_perf_limit_reasons; 99 unsigned int has_automatic_cstate_conversion; 100 unsigned int dis_cstate_prewake; 101 unsigned int do_gfx_perf_limit_reasons; 102 unsigned int do_ring_perf_limit_reasons; 103 unsigned int crystal_hz; 104 unsigned long long tsc_hz; 105 int base_cpu; 106 double discover_bclk(unsigned int family, unsigned int model); 107 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 108 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 109 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 110 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 111 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 112 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 113 unsigned int has_misc_feature_control; 114 unsigned int first_counter_read = 1; 115 int ignore_stdin; 116 117 #define RAPL_PKG (1 << 0) 118 /* 0x610 MSR_PKG_POWER_LIMIT */ 119 /* 0x611 MSR_PKG_ENERGY_STATUS */ 120 #define RAPL_PKG_PERF_STATUS (1 << 1) 121 /* 0x613 MSR_PKG_PERF_STATUS */ 122 #define RAPL_PKG_POWER_INFO (1 << 2) 123 /* 0x614 MSR_PKG_POWER_INFO */ 124 125 #define RAPL_DRAM (1 << 3) 126 /* 0x618 MSR_DRAM_POWER_LIMIT */ 127 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 128 #define RAPL_DRAM_PERF_STATUS (1 << 4) 129 /* 0x61b MSR_DRAM_PERF_STATUS */ 130 #define RAPL_DRAM_POWER_INFO (1 << 5) 131 /* 0x61c MSR_DRAM_POWER_INFO */ 132 133 #define RAPL_CORES_POWER_LIMIT (1 << 6) 134 /* 0x638 MSR_PP0_POWER_LIMIT */ 135 #define RAPL_CORE_POLICY (1 << 7) 136 /* 0x63a MSR_PP0_POLICY */ 137 138 #define RAPL_GFX (1 << 8) 139 /* 0x640 MSR_PP1_POWER_LIMIT */ 140 /* 0x641 MSR_PP1_ENERGY_STATUS */ 141 /* 0x642 MSR_PP1_POLICY */ 142 143 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 144 /* 0x639 MSR_PP0_ENERGY_STATUS */ 145 #define RAPL_PER_CORE_ENERGY (1 << 10) 146 /* Indicates cores energy collection is per-core, 147 * not per-package. */ 148 #define RAPL_AMD_F17H (1 << 11) 149 /* 0xc0010299 MSR_RAPL_PWR_UNIT */ 150 /* 0xc001029a MSR_CORE_ENERGY_STAT */ 151 /* 0xc001029b MSR_PKG_ENERGY_STAT */ 152 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 153 #define TJMAX_DEFAULT 100 154 155 /* MSRs that are not yet in the kernel-provided header. */ 156 #define MSR_RAPL_PWR_UNIT 0xc0010299 157 #define MSR_CORE_ENERGY_STAT 0xc001029a 158 #define MSR_PKG_ENERGY_STAT 0xc001029b 159 160 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 161 162 /* 163 * buffer size used by sscanf() for added column names 164 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 165 */ 166 #define NAME_BYTES 20 167 #define PATH_BYTES 128 168 169 int backwards_count; 170 char *progname; 171 172 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 173 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset; 174 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size; 175 #define MAX_ADDED_COUNTERS 8 176 #define MAX_ADDED_THREAD_COUNTERS 24 177 #define BITMASK_SIZE 32 178 179 struct thread_data { 180 struct timeval tv_begin; 181 struct timeval tv_end; 182 struct timeval tv_delta; 183 unsigned long long tsc; 184 unsigned long long aperf; 185 unsigned long long mperf; 186 unsigned long long c1; 187 unsigned long long instr_count; 188 unsigned long long irq_count; 189 unsigned int smi_count; 190 unsigned int cpu_id; 191 unsigned int apic_id; 192 unsigned int x2apic_id; 193 unsigned int flags; 194 bool is_atom; 195 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 196 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 197 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 198 } *thread_even, *thread_odd; 199 200 struct core_data { 201 unsigned long long c3; 202 unsigned long long c6; 203 unsigned long long c7; 204 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 205 unsigned int core_temp_c; 206 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */ 207 unsigned int core_id; 208 unsigned long long counter[MAX_ADDED_COUNTERS]; 209 } *core_even, *core_odd; 210 211 struct pkg_data { 212 unsigned long long pc2; 213 unsigned long long pc3; 214 unsigned long long pc6; 215 unsigned long long pc7; 216 unsigned long long pc8; 217 unsigned long long pc9; 218 unsigned long long pc10; 219 unsigned long long cpu_lpi; 220 unsigned long long sys_lpi; 221 unsigned long long pkg_wtd_core_c0; 222 unsigned long long pkg_any_core_c0; 223 unsigned long long pkg_any_gfxe_c0; 224 unsigned long long pkg_both_core_gfxe_c0; 225 long long gfx_rc6_ms; 226 unsigned int gfx_mhz; 227 unsigned int gfx_act_mhz; 228 unsigned int package_id; 229 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 230 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 231 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */ 232 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 233 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 234 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 235 unsigned int pkg_temp_c; 236 unsigned long long counter[MAX_ADDED_COUNTERS]; 237 } *package_even, *package_odd; 238 239 #define ODD_COUNTERS thread_odd, core_odd, package_odd 240 #define EVEN_COUNTERS thread_even, core_even, package_even 241 242 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 243 ((thread_base) + \ 244 ((pkg_no) * \ 245 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 246 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 247 ((core_no) * topo.threads_per_core) + \ 248 (thread_no)) 249 250 #define GET_CORE(core_base, core_no, node_no, pkg_no) \ 251 ((core_base) + \ 252 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 253 ((node_no) * topo.cores_per_node) + \ 254 (core_no)) 255 256 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 257 258 enum counter_scope { SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE }; 259 enum counter_type { COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC }; 260 enum counter_format { FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT }; 261 262 struct msr_counter { 263 unsigned int msr_num; 264 char name[NAME_BYTES]; 265 char path[PATH_BYTES]; 266 unsigned int width; 267 enum counter_type type; 268 enum counter_format format; 269 struct msr_counter *next; 270 unsigned int flags; 271 #define FLAGS_HIDE (1 << 0) 272 #define FLAGS_SHOW (1 << 1) 273 #define SYSFS_PERCPU (1 << 1) 274 }; 275 276 /* 277 * The accumulated sum of MSR is defined as a monotonic 278 * increasing MSR, it will be accumulated periodically, 279 * despite its register's bit width. 280 */ 281 enum { 282 IDX_PKG_ENERGY, 283 IDX_DRAM_ENERGY, 284 IDX_PP0_ENERGY, 285 IDX_PP1_ENERGY, 286 IDX_PKG_PERF, 287 IDX_DRAM_PERF, 288 IDX_COUNT, 289 }; 290 291 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr); 292 293 struct msr_sum_array { 294 /* get_msr_sum() = sum + (get_msr() - last) */ 295 struct { 296 /*The accumulated MSR value is updated by the timer */ 297 unsigned long long sum; 298 /*The MSR footprint recorded in last timer */ 299 unsigned long long last; 300 } entries[IDX_COUNT]; 301 }; 302 303 /* The percpu MSR sum array.*/ 304 struct msr_sum_array *per_cpu_msr_sum; 305 306 off_t idx_to_offset(int idx) 307 { 308 off_t offset; 309 310 switch (idx) { 311 case IDX_PKG_ENERGY: 312 if (do_rapl & RAPL_AMD_F17H) 313 offset = MSR_PKG_ENERGY_STAT; 314 else 315 offset = MSR_PKG_ENERGY_STATUS; 316 break; 317 case IDX_DRAM_ENERGY: 318 offset = MSR_DRAM_ENERGY_STATUS; 319 break; 320 case IDX_PP0_ENERGY: 321 offset = MSR_PP0_ENERGY_STATUS; 322 break; 323 case IDX_PP1_ENERGY: 324 offset = MSR_PP1_ENERGY_STATUS; 325 break; 326 case IDX_PKG_PERF: 327 offset = MSR_PKG_PERF_STATUS; 328 break; 329 case IDX_DRAM_PERF: 330 offset = MSR_DRAM_PERF_STATUS; 331 break; 332 default: 333 offset = -1; 334 } 335 return offset; 336 } 337 338 int offset_to_idx(off_t offset) 339 { 340 int idx; 341 342 switch (offset) { 343 case MSR_PKG_ENERGY_STATUS: 344 case MSR_PKG_ENERGY_STAT: 345 idx = IDX_PKG_ENERGY; 346 break; 347 case MSR_DRAM_ENERGY_STATUS: 348 idx = IDX_DRAM_ENERGY; 349 break; 350 case MSR_PP0_ENERGY_STATUS: 351 idx = IDX_PP0_ENERGY; 352 break; 353 case MSR_PP1_ENERGY_STATUS: 354 idx = IDX_PP1_ENERGY; 355 break; 356 case MSR_PKG_PERF_STATUS: 357 idx = IDX_PKG_PERF; 358 break; 359 case MSR_DRAM_PERF_STATUS: 360 idx = IDX_DRAM_PERF; 361 break; 362 default: 363 idx = -1; 364 } 365 return idx; 366 } 367 368 int idx_valid(int idx) 369 { 370 switch (idx) { 371 case IDX_PKG_ENERGY: 372 return do_rapl & (RAPL_PKG | RAPL_AMD_F17H); 373 case IDX_DRAM_ENERGY: 374 return do_rapl & RAPL_DRAM; 375 case IDX_PP0_ENERGY: 376 return do_rapl & RAPL_CORES_ENERGY_STATUS; 377 case IDX_PP1_ENERGY: 378 return do_rapl & RAPL_GFX; 379 case IDX_PKG_PERF: 380 return do_rapl & RAPL_PKG_PERF_STATUS; 381 case IDX_DRAM_PERF: 382 return do_rapl & RAPL_DRAM_PERF_STATUS; 383 default: 384 return 0; 385 } 386 } 387 388 struct sys_counters { 389 unsigned int added_thread_counters; 390 unsigned int added_core_counters; 391 unsigned int added_package_counters; 392 struct msr_counter *tp; 393 struct msr_counter *cp; 394 struct msr_counter *pp; 395 } sys; 396 397 struct system_summary { 398 struct thread_data threads; 399 struct core_data cores; 400 struct pkg_data packages; 401 } average; 402 403 struct cpu_topology { 404 int physical_package_id; 405 int die_id; 406 int logical_cpu_id; 407 int physical_node_id; 408 int logical_node_id; /* 0-based count within the package */ 409 int physical_core_id; 410 int thread_id; 411 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 412 } *cpus; 413 414 struct topo_params { 415 int num_packages; 416 int num_die; 417 int num_cpus; 418 int num_cores; 419 int max_cpu_num; 420 int max_node_num; 421 int nodes_per_pkg; 422 int cores_per_node; 423 int threads_per_core; 424 } topo; 425 426 struct timeval tv_even, tv_odd, tv_delta; 427 428 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 429 int *irqs_per_cpu; /* indexed by cpu_num */ 430 431 void setup_all_buffers(void); 432 433 char *sys_lpi_file; 434 char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us"; 435 char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec"; 436 437 int cpu_is_not_present(int cpu) 438 { 439 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 440 } 441 442 /* 443 * run func(thread, core, package) in topology order 444 * skip non-present cpus 445 */ 446 447 int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *), 448 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 449 { 450 int retval, pkg_no, core_no, thread_no, node_no; 451 452 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 453 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) { 454 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 455 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) { 456 struct thread_data *t; 457 struct core_data *c; 458 struct pkg_data *p; 459 460 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no); 461 462 if (cpu_is_not_present(t->cpu_id)) 463 continue; 464 465 c = GET_CORE(core_base, core_no, node_no, pkg_no); 466 p = GET_PKG(pkg_base, pkg_no); 467 468 retval = func(t, c, p); 469 if (retval) 470 return retval; 471 } 472 } 473 } 474 } 475 return 0; 476 } 477 478 int cpu_migrate(int cpu) 479 { 480 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 481 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 482 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 483 return -1; 484 else 485 return 0; 486 } 487 488 int get_msr_fd(int cpu) 489 { 490 char pathname[32]; 491 int fd; 492 493 fd = fd_percpu[cpu]; 494 495 if (fd) 496 return fd; 497 498 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 499 fd = open(pathname, O_RDONLY); 500 if (fd < 0) 501 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 502 503 fd_percpu[cpu] = fd; 504 505 return fd; 506 } 507 508 static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags) 509 { 510 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags); 511 } 512 513 static int perf_instr_count_open(int cpu_num) 514 { 515 struct perf_event_attr pea; 516 int fd; 517 518 memset(&pea, 0, sizeof(struct perf_event_attr)); 519 pea.type = PERF_TYPE_HARDWARE; 520 pea.size = sizeof(struct perf_event_attr); 521 pea.config = PERF_COUNT_HW_INSTRUCTIONS; 522 523 /* counter for cpu_num, including user + kernel and all processes */ 524 fd = perf_event_open(&pea, -1, cpu_num, -1, 0); 525 if (fd == -1) 526 err(-1, "cpu%d: perf instruction counter\n", cpu_num); 527 528 return fd; 529 } 530 531 int get_instr_count_fd(int cpu) 532 { 533 if (fd_instr_count_percpu[cpu]) 534 return fd_instr_count_percpu[cpu]; 535 536 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu); 537 538 return fd_instr_count_percpu[cpu]; 539 } 540 541 int get_msr(int cpu, off_t offset, unsigned long long *msr) 542 { 543 ssize_t retval; 544 545 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 546 547 if (retval != sizeof *msr) 548 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 549 550 return 0; 551 } 552 553 /* 554 * This list matches the column headers, except 555 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 556 * 2. Core and CPU are moved to the end, we can't have strings that contain them 557 * matching on them for --show and --hide. 558 */ 559 struct msr_counter bic[] = { 560 { 0x0, "usec" }, 561 { 0x0, "Time_Of_Day_Seconds" }, 562 { 0x0, "Package" }, 563 { 0x0, "Node" }, 564 { 0x0, "Avg_MHz" }, 565 { 0x0, "Busy%" }, 566 { 0x0, "Bzy_MHz" }, 567 { 0x0, "TSC_MHz" }, 568 { 0x0, "IRQ" }, 569 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL }, 570 { 0x0, "sysfs" }, 571 { 0x0, "CPU%c1" }, 572 { 0x0, "CPU%c3" }, 573 { 0x0, "CPU%c6" }, 574 { 0x0, "CPU%c7" }, 575 { 0x0, "ThreadC" }, 576 { 0x0, "CoreTmp" }, 577 { 0x0, "CoreCnt" }, 578 { 0x0, "PkgTmp" }, 579 { 0x0, "GFX%rc6" }, 580 { 0x0, "GFXMHz" }, 581 { 0x0, "Pkg%pc2" }, 582 { 0x0, "Pkg%pc3" }, 583 { 0x0, "Pkg%pc6" }, 584 { 0x0, "Pkg%pc7" }, 585 { 0x0, "Pkg%pc8" }, 586 { 0x0, "Pkg%pc9" }, 587 { 0x0, "Pk%pc10" }, 588 { 0x0, "CPU%LPI" }, 589 { 0x0, "SYS%LPI" }, 590 { 0x0, "PkgWatt" }, 591 { 0x0, "CorWatt" }, 592 { 0x0, "GFXWatt" }, 593 { 0x0, "PkgCnt" }, 594 { 0x0, "RAMWatt" }, 595 { 0x0, "PKG_%" }, 596 { 0x0, "RAM_%" }, 597 { 0x0, "Pkg_J" }, 598 { 0x0, "Cor_J" }, 599 { 0x0, "GFX_J" }, 600 { 0x0, "RAM_J" }, 601 { 0x0, "Mod%c6" }, 602 { 0x0, "Totl%C0" }, 603 { 0x0, "Any%C0" }, 604 { 0x0, "GFX%C0" }, 605 { 0x0, "CPUGFX%" }, 606 { 0x0, "Core" }, 607 { 0x0, "CPU" }, 608 { 0x0, "APIC" }, 609 { 0x0, "X2APIC" }, 610 { 0x0, "Die" }, 611 { 0x0, "GFXAMHz" }, 612 { 0x0, "IPC" }, 613 }; 614 615 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 616 #define BIC_USEC (1ULL << 0) 617 #define BIC_TOD (1ULL << 1) 618 #define BIC_Package (1ULL << 2) 619 #define BIC_Node (1ULL << 3) 620 #define BIC_Avg_MHz (1ULL << 4) 621 #define BIC_Busy (1ULL << 5) 622 #define BIC_Bzy_MHz (1ULL << 6) 623 #define BIC_TSC_MHz (1ULL << 7) 624 #define BIC_IRQ (1ULL << 8) 625 #define BIC_SMI (1ULL << 9) 626 #define BIC_sysfs (1ULL << 10) 627 #define BIC_CPU_c1 (1ULL << 11) 628 #define BIC_CPU_c3 (1ULL << 12) 629 #define BIC_CPU_c6 (1ULL << 13) 630 #define BIC_CPU_c7 (1ULL << 14) 631 #define BIC_ThreadC (1ULL << 15) 632 #define BIC_CoreTmp (1ULL << 16) 633 #define BIC_CoreCnt (1ULL << 17) 634 #define BIC_PkgTmp (1ULL << 18) 635 #define BIC_GFX_rc6 (1ULL << 19) 636 #define BIC_GFXMHz (1ULL << 20) 637 #define BIC_Pkgpc2 (1ULL << 21) 638 #define BIC_Pkgpc3 (1ULL << 22) 639 #define BIC_Pkgpc6 (1ULL << 23) 640 #define BIC_Pkgpc7 (1ULL << 24) 641 #define BIC_Pkgpc8 (1ULL << 25) 642 #define BIC_Pkgpc9 (1ULL << 26) 643 #define BIC_Pkgpc10 (1ULL << 27) 644 #define BIC_CPU_LPI (1ULL << 28) 645 #define BIC_SYS_LPI (1ULL << 29) 646 #define BIC_PkgWatt (1ULL << 30) 647 #define BIC_CorWatt (1ULL << 31) 648 #define BIC_GFXWatt (1ULL << 32) 649 #define BIC_PkgCnt (1ULL << 33) 650 #define BIC_RAMWatt (1ULL << 34) 651 #define BIC_PKG__ (1ULL << 35) 652 #define BIC_RAM__ (1ULL << 36) 653 #define BIC_Pkg_J (1ULL << 37) 654 #define BIC_Cor_J (1ULL << 38) 655 #define BIC_GFX_J (1ULL << 39) 656 #define BIC_RAM_J (1ULL << 40) 657 #define BIC_Mod_c6 (1ULL << 41) 658 #define BIC_Totl_c0 (1ULL << 42) 659 #define BIC_Any_c0 (1ULL << 43) 660 #define BIC_GFX_c0 (1ULL << 44) 661 #define BIC_CPUGFX (1ULL << 45) 662 #define BIC_Core (1ULL << 46) 663 #define BIC_CPU (1ULL << 47) 664 #define BIC_APIC (1ULL << 48) 665 #define BIC_X2APIC (1ULL << 49) 666 #define BIC_Die (1ULL << 50) 667 #define BIC_GFXACTMHz (1ULL << 51) 668 #define BIC_IPC (1ULL << 52) 669 670 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 671 672 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 673 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 674 675 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 676 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME) 677 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 678 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 679 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 680 #define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT) 681 682 #define MAX_DEFERRED 16 683 char *deferred_skip_names[MAX_DEFERRED]; 684 int deferred_skip_index; 685 686 /* 687 * HIDE_LIST - hide this list of counters, show the rest [default] 688 * SHOW_LIST - show this list of counters, hide the rest 689 */ 690 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 691 692 void help(void) 693 { 694 fprintf(outf, 695 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 696 "\n" 697 "Turbostat forks the specified COMMAND and prints statistics\n" 698 "when COMMAND completes.\n" 699 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 700 "to print statistics, until interrupted.\n" 701 " -a, --add add a counter\n" 702 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 703 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n" 704 " {core | package | j,k,l..m,n-p }\n" 705 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n" 706 " -D, --Dump displays the raw counter values\n" 707 " -e, --enable [all | column]\n" 708 " shows all or the specified disabled column\n" 709 " -H, --hide [column|column,column,...]\n" 710 " hide the specified column(s)\n" 711 " -i, --interval sec.subsec\n" 712 " Override default 5-second measurement interval\n" 713 " -J, --Joules displays energy in Joules instead of Watts\n" 714 " -l, --list list column headers only\n" 715 " -n, --num_iterations num\n" 716 " number of the measurement iterations\n" 717 " -o, --out file\n" 718 " create or truncate \"file\" for all output\n" 719 " -q, --quiet skip decoding system configuration header\n" 720 " -s, --show [column|column,column,...]\n" 721 " show only the specified column(s)\n" 722 " -S, --Summary\n" 723 " limits output to 1-line system summary per interval\n" 724 " -T, --TCC temperature\n" 725 " sets the Thermal Control Circuit temperature in\n" 726 " degrees Celsius\n" 727 " -h, --help print this help message\n" 728 " -v, --version print version information\n" "\n" "For more help, run \"man turbostat\"\n"); 729 } 730 731 /* 732 * bic_lookup 733 * for all the strings in comma separate name_list, 734 * set the approprate bit in return value. 735 */ 736 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 737 { 738 int i; 739 unsigned long long retval = 0; 740 741 while (name_list) { 742 char *comma; 743 744 comma = strchr(name_list, ','); 745 746 if (comma) 747 *comma = '\0'; 748 749 if (!strcmp(name_list, "all")) 750 return ~0; 751 752 for (i = 0; i < MAX_BIC; ++i) { 753 if (!strcmp(name_list, bic[i].name)) { 754 retval |= (1ULL << i); 755 break; 756 } 757 } 758 if (i == MAX_BIC) { 759 if (mode == SHOW_LIST) { 760 fprintf(stderr, "Invalid counter name: %s\n", name_list); 761 exit(-1); 762 } 763 deferred_skip_names[deferred_skip_index++] = name_list; 764 if (debug) 765 fprintf(stderr, "deferred \"%s\"\n", name_list); 766 if (deferred_skip_index >= MAX_DEFERRED) { 767 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 768 MAX_DEFERRED, name_list); 769 help(); 770 exit(1); 771 } 772 } 773 774 name_list = comma; 775 if (name_list) 776 name_list++; 777 778 } 779 return retval; 780 } 781 782 void print_header(char *delim) 783 { 784 struct msr_counter *mp; 785 int printed = 0; 786 787 if (DO_BIC(BIC_USEC)) 788 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 789 if (DO_BIC(BIC_TOD)) 790 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 791 if (DO_BIC(BIC_Package)) 792 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 793 if (DO_BIC(BIC_Die)) 794 outp += sprintf(outp, "%sDie", (printed++ ? delim : "")); 795 if (DO_BIC(BIC_Node)) 796 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 797 if (DO_BIC(BIC_Core)) 798 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 799 if (DO_BIC(BIC_CPU)) 800 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 801 if (DO_BIC(BIC_APIC)) 802 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 803 if (DO_BIC(BIC_X2APIC)) 804 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 805 if (DO_BIC(BIC_Avg_MHz)) 806 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 807 if (DO_BIC(BIC_Busy)) 808 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 809 if (DO_BIC(BIC_Bzy_MHz)) 810 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 811 if (DO_BIC(BIC_TSC_MHz)) 812 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 813 814 if (DO_BIC(BIC_IPC)) 815 outp += sprintf(outp, "%sIPC", (printed++ ? delim : "")); 816 817 if (DO_BIC(BIC_IRQ)) { 818 if (sums_need_wide_columns) 819 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 820 else 821 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 822 } 823 824 if (DO_BIC(BIC_SMI)) 825 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 826 827 for (mp = sys.tp; mp; mp = mp->next) { 828 829 if (mp->format == FORMAT_RAW) { 830 if (mp->width == 64) 831 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 832 else 833 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 834 } else { 835 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 836 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 837 else 838 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 839 } 840 } 841 842 if (DO_BIC(BIC_CPU_c1)) 843 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 844 if (DO_BIC(BIC_CPU_c3)) 845 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 846 if (DO_BIC(BIC_CPU_c6)) 847 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 848 if (DO_BIC(BIC_CPU_c7)) 849 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 850 851 if (DO_BIC(BIC_Mod_c6)) 852 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 853 854 if (DO_BIC(BIC_CoreTmp)) 855 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 856 857 if (do_rapl && !rapl_joules) { 858 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 859 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 860 } else if (do_rapl && rapl_joules) { 861 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 862 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 863 } 864 865 for (mp = sys.cp; mp; mp = mp->next) { 866 if (mp->format == FORMAT_RAW) { 867 if (mp->width == 64) 868 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 869 else 870 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 871 } else { 872 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 873 outp += sprintf(outp, "%s%8s", delim, mp->name); 874 else 875 outp += sprintf(outp, "%s%s", delim, mp->name); 876 } 877 } 878 879 if (DO_BIC(BIC_PkgTmp)) 880 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 881 882 if (DO_BIC(BIC_GFX_rc6)) 883 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 884 885 if (DO_BIC(BIC_GFXMHz)) 886 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 887 888 if (DO_BIC(BIC_GFXACTMHz)) 889 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : "")); 890 891 if (DO_BIC(BIC_Totl_c0)) 892 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 893 if (DO_BIC(BIC_Any_c0)) 894 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 895 if (DO_BIC(BIC_GFX_c0)) 896 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 897 if (DO_BIC(BIC_CPUGFX)) 898 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 899 900 if (DO_BIC(BIC_Pkgpc2)) 901 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 902 if (DO_BIC(BIC_Pkgpc3)) 903 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 904 if (DO_BIC(BIC_Pkgpc6)) 905 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 906 if (DO_BIC(BIC_Pkgpc7)) 907 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 908 if (DO_BIC(BIC_Pkgpc8)) 909 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 910 if (DO_BIC(BIC_Pkgpc9)) 911 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 912 if (DO_BIC(BIC_Pkgpc10)) 913 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 914 if (DO_BIC(BIC_CPU_LPI)) 915 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 916 if (DO_BIC(BIC_SYS_LPI)) 917 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 918 919 if (do_rapl && !rapl_joules) { 920 if (DO_BIC(BIC_PkgWatt)) 921 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 922 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 923 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 924 if (DO_BIC(BIC_GFXWatt)) 925 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 926 if (DO_BIC(BIC_RAMWatt)) 927 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 928 if (DO_BIC(BIC_PKG__)) 929 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 930 if (DO_BIC(BIC_RAM__)) 931 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 932 } else if (do_rapl && rapl_joules) { 933 if (DO_BIC(BIC_Pkg_J)) 934 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 935 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 936 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 937 if (DO_BIC(BIC_GFX_J)) 938 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 939 if (DO_BIC(BIC_RAM_J)) 940 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 941 if (DO_BIC(BIC_PKG__)) 942 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 943 if (DO_BIC(BIC_RAM__)) 944 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 945 } 946 for (mp = sys.pp; mp; mp = mp->next) { 947 if (mp->format == FORMAT_RAW) { 948 if (mp->width == 64) 949 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 950 else 951 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 952 } else { 953 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 954 outp += sprintf(outp, "%s%8s", delim, mp->name); 955 else 956 outp += sprintf(outp, "%s%s", delim, mp->name); 957 } 958 } 959 960 outp += sprintf(outp, "\n"); 961 } 962 963 int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 964 { 965 int i; 966 struct msr_counter *mp; 967 968 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 969 970 if (t) { 971 outp += sprintf(outp, "CPU: %d flags 0x%x\n", t->cpu_id, t->flags); 972 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 973 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 974 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 975 outp += sprintf(outp, "c1: %016llX\n", t->c1); 976 977 if (DO_BIC(BIC_IPC)) 978 outp += sprintf(outp, "IPC: %lld\n", t->instr_count); 979 980 if (DO_BIC(BIC_IRQ)) 981 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 982 if (DO_BIC(BIC_SMI)) 983 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 984 985 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 986 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, t->counter[i]); 987 } 988 } 989 990 if (c) { 991 outp += sprintf(outp, "core: %d\n", c->core_id); 992 outp += sprintf(outp, "c3: %016llX\n", c->c3); 993 outp += sprintf(outp, "c6: %016llX\n", c->c6); 994 outp += sprintf(outp, "c7: %016llX\n", c->c7); 995 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 996 outp += sprintf(outp, "Joules: %0X\n", c->core_energy); 997 998 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 999 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, c->counter[i]); 1000 } 1001 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 1002 } 1003 1004 if (p) { 1005 outp += sprintf(outp, "package: %d\n", p->package_id); 1006 1007 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 1008 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 1009 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 1010 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 1011 1012 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 1013 if (DO_BIC(BIC_Pkgpc3)) 1014 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 1015 if (DO_BIC(BIC_Pkgpc6)) 1016 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 1017 if (DO_BIC(BIC_Pkgpc7)) 1018 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 1019 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 1020 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 1021 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 1022 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 1023 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 1024 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg); 1025 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores); 1026 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx); 1027 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram); 1028 outp += sprintf(outp, "Throttle PKG: %0llX\n", p->rapl_pkg_perf_status); 1029 outp += sprintf(outp, "Throttle RAM: %0llX\n", p->rapl_dram_perf_status); 1030 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 1031 1032 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1033 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, p->counter[i]); 1034 } 1035 } 1036 1037 outp += sprintf(outp, "\n"); 1038 1039 return 0; 1040 } 1041 1042 /* 1043 * column formatting convention & formats 1044 */ 1045 int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1046 { 1047 double interval_float, tsc; 1048 char *fmt8; 1049 int i; 1050 struct msr_counter *mp; 1051 char *delim = "\t"; 1052 int printed = 0; 1053 1054 /* if showing only 1st thread in core and this isn't one, bail out */ 1055 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1056 return 0; 1057 1058 /* if showing only 1st thread in pkg and this isn't one, bail out */ 1059 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1060 return 0; 1061 1062 /*if not summary line and --cpu is used */ 1063 if ((t != &average.threads) && (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 1064 return 0; 1065 1066 if (DO_BIC(BIC_USEC)) { 1067 /* on each row, print how many usec each timestamp took to gather */ 1068 struct timeval tv; 1069 1070 timersub(&t->tv_end, &t->tv_begin, &tv); 1071 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 1072 } 1073 1074 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 1075 if (DO_BIC(BIC_TOD)) 1076 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 1077 1078 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec / 1000000.0; 1079 1080 tsc = t->tsc * tsc_tweak; 1081 1082 /* topo columns, print blanks on 1st (average) line */ 1083 if (t == &average.threads) { 1084 if (DO_BIC(BIC_Package)) 1085 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1086 if (DO_BIC(BIC_Die)) 1087 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1088 if (DO_BIC(BIC_Node)) 1089 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1090 if (DO_BIC(BIC_Core)) 1091 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1092 if (DO_BIC(BIC_CPU)) 1093 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1094 if (DO_BIC(BIC_APIC)) 1095 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1096 if (DO_BIC(BIC_X2APIC)) 1097 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1098 } else { 1099 if (DO_BIC(BIC_Package)) { 1100 if (p) 1101 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 1102 else 1103 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1104 } 1105 if (DO_BIC(BIC_Die)) { 1106 if (c) 1107 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id); 1108 else 1109 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1110 } 1111 if (DO_BIC(BIC_Node)) { 1112 if (t) 1113 outp += sprintf(outp, "%s%d", 1114 (printed++ ? delim : ""), cpus[t->cpu_id].physical_node_id); 1115 else 1116 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1117 } 1118 if (DO_BIC(BIC_Core)) { 1119 if (c) 1120 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 1121 else 1122 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1123 } 1124 if (DO_BIC(BIC_CPU)) 1125 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 1126 if (DO_BIC(BIC_APIC)) 1127 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 1128 if (DO_BIC(BIC_X2APIC)) 1129 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 1130 } 1131 1132 if (DO_BIC(BIC_Avg_MHz)) 1133 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 / units * t->aperf / interval_float); 1134 1135 if (DO_BIC(BIC_Busy)) 1136 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf / tsc); 1137 1138 if (DO_BIC(BIC_Bzy_MHz)) { 1139 if (has_base_hz) 1140 outp += 1141 sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 1142 else 1143 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1144 tsc / units * t->aperf / t->mperf / interval_float); 1145 } 1146 1147 if (DO_BIC(BIC_TSC_MHz)) 1148 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc / units / interval_float); 1149 1150 if (DO_BIC(BIC_IPC)) 1151 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf); 1152 1153 /* IRQ */ 1154 if (DO_BIC(BIC_IRQ)) { 1155 if (sums_need_wide_columns) 1156 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 1157 else 1158 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 1159 } 1160 1161 /* SMI */ 1162 if (DO_BIC(BIC_SMI)) 1163 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 1164 1165 /* Added counters */ 1166 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1167 if (mp->format == FORMAT_RAW) { 1168 if (mp->width == 32) 1169 outp += 1170 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]); 1171 else 1172 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 1173 } else if (mp->format == FORMAT_DELTA) { 1174 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1175 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 1176 else 1177 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 1178 } else if (mp->format == FORMAT_PERCENT) { 1179 if (mp->type == COUNTER_USEC) 1180 outp += 1181 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1182 t->counter[i] / interval_float / 10000); 1183 else 1184 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i] / tsc); 1185 } 1186 } 1187 1188 /* C1 */ 1189 if (DO_BIC(BIC_CPU_c1)) 1190 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1 / tsc); 1191 1192 /* print per-core data only for 1st thread in core */ 1193 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1194 goto done; 1195 1196 if (DO_BIC(BIC_CPU_c3)) 1197 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3 / tsc); 1198 if (DO_BIC(BIC_CPU_c6)) 1199 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6 / tsc); 1200 if (DO_BIC(BIC_CPU_c7)) 1201 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7 / tsc); 1202 1203 /* Mod%c6 */ 1204 if (DO_BIC(BIC_Mod_c6)) 1205 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 1206 1207 if (DO_BIC(BIC_CoreTmp)) 1208 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1209 1210 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1211 if (mp->format == FORMAT_RAW) { 1212 if (mp->width == 32) 1213 outp += 1214 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]); 1215 else 1216 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1217 } else if (mp->format == FORMAT_DELTA) { 1218 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1219 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1220 else 1221 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1222 } else if (mp->format == FORMAT_PERCENT) { 1223 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i] / tsc); 1224 } 1225 } 1226 1227 fmt8 = "%s%.2f"; 1228 1229 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1230 outp += 1231 sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float); 1232 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1233 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units); 1234 1235 /* print per-package data only for 1st core in package */ 1236 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1237 goto done; 1238 1239 /* PkgTmp */ 1240 if (DO_BIC(BIC_PkgTmp)) 1241 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1242 1243 /* GFXrc6 */ 1244 if (DO_BIC(BIC_GFX_rc6)) { 1245 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1246 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1247 } else { 1248 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1249 p->gfx_rc6_ms / 10.0 / interval_float); 1250 } 1251 } 1252 1253 /* GFXMHz */ 1254 if (DO_BIC(BIC_GFXMHz)) 1255 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1256 1257 /* GFXACTMHz */ 1258 if (DO_BIC(BIC_GFXACTMHz)) 1259 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz); 1260 1261 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1262 if (DO_BIC(BIC_Totl_c0)) 1263 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0 / tsc); 1264 if (DO_BIC(BIC_Any_c0)) 1265 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0 / tsc); 1266 if (DO_BIC(BIC_GFX_c0)) 1267 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0 / tsc); 1268 if (DO_BIC(BIC_CPUGFX)) 1269 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0 / tsc); 1270 1271 if (DO_BIC(BIC_Pkgpc2)) 1272 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2 / tsc); 1273 if (DO_BIC(BIC_Pkgpc3)) 1274 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3 / tsc); 1275 if (DO_BIC(BIC_Pkgpc6)) 1276 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6 / tsc); 1277 if (DO_BIC(BIC_Pkgpc7)) 1278 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7 / tsc); 1279 if (DO_BIC(BIC_Pkgpc8)) 1280 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8 / tsc); 1281 if (DO_BIC(BIC_Pkgpc9)) 1282 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9 / tsc); 1283 if (DO_BIC(BIC_Pkgpc10)) 1284 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10 / tsc); 1285 1286 if (DO_BIC(BIC_CPU_LPI)) 1287 outp += 1288 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1289 if (DO_BIC(BIC_SYS_LPI)) 1290 outp += 1291 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1292 1293 if (DO_BIC(BIC_PkgWatt)) 1294 outp += 1295 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1296 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1297 outp += 1298 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1299 if (DO_BIC(BIC_GFXWatt)) 1300 outp += 1301 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1302 if (DO_BIC(BIC_RAMWatt)) 1303 outp += 1304 sprintf(outp, fmt8, (printed++ ? delim : ""), 1305 p->energy_dram * rapl_dram_energy_units / interval_float); 1306 if (DO_BIC(BIC_Pkg_J)) 1307 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 1308 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1309 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 1310 if (DO_BIC(BIC_GFX_J)) 1311 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 1312 if (DO_BIC(BIC_RAM_J)) 1313 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 1314 if (DO_BIC(BIC_PKG__)) 1315 outp += 1316 sprintf(outp, fmt8, (printed++ ? delim : ""), 1317 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 1318 if (DO_BIC(BIC_RAM__)) 1319 outp += 1320 sprintf(outp, fmt8, (printed++ ? delim : ""), 1321 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 1322 1323 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1324 if (mp->format == FORMAT_RAW) { 1325 if (mp->width == 32) 1326 outp += 1327 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]); 1328 else 1329 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 1330 } else if (mp->format == FORMAT_DELTA) { 1331 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1332 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 1333 else 1334 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 1335 } else if (mp->format == FORMAT_PERCENT) { 1336 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i] / tsc); 1337 } 1338 } 1339 1340 done: 1341 if (*(outp - 1) != '\n') 1342 outp += sprintf(outp, "\n"); 1343 1344 return 0; 1345 } 1346 1347 void flush_output_stdout(void) 1348 { 1349 FILE *filep; 1350 1351 if (outf == stderr) 1352 filep = stdout; 1353 else 1354 filep = outf; 1355 1356 fputs(output_buffer, filep); 1357 fflush(filep); 1358 1359 outp = output_buffer; 1360 } 1361 1362 void flush_output_stderr(void) 1363 { 1364 fputs(output_buffer, outf); 1365 fflush(outf); 1366 outp = output_buffer; 1367 } 1368 1369 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1370 { 1371 static int printed; 1372 1373 if (!printed || !summary_only) 1374 print_header("\t"); 1375 1376 format_counters(&average.threads, &average.cores, &average.packages); 1377 1378 printed = 1; 1379 1380 if (summary_only) 1381 return; 1382 1383 for_all_cpus(format_counters, t, c, p); 1384 } 1385 1386 #define DELTA_WRAP32(new, old) \ 1387 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32); 1388 1389 int delta_package(struct pkg_data *new, struct pkg_data *old) 1390 { 1391 int i; 1392 struct msr_counter *mp; 1393 1394 if (DO_BIC(BIC_Totl_c0)) 1395 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 1396 if (DO_BIC(BIC_Any_c0)) 1397 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 1398 if (DO_BIC(BIC_GFX_c0)) 1399 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 1400 if (DO_BIC(BIC_CPUGFX)) 1401 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 1402 1403 old->pc2 = new->pc2 - old->pc2; 1404 if (DO_BIC(BIC_Pkgpc3)) 1405 old->pc3 = new->pc3 - old->pc3; 1406 if (DO_BIC(BIC_Pkgpc6)) 1407 old->pc6 = new->pc6 - old->pc6; 1408 if (DO_BIC(BIC_Pkgpc7)) 1409 old->pc7 = new->pc7 - old->pc7; 1410 old->pc8 = new->pc8 - old->pc8; 1411 old->pc9 = new->pc9 - old->pc9; 1412 old->pc10 = new->pc10 - old->pc10; 1413 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 1414 old->sys_lpi = new->sys_lpi - old->sys_lpi; 1415 old->pkg_temp_c = new->pkg_temp_c; 1416 1417 /* flag an error when rc6 counter resets/wraps */ 1418 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 1419 old->gfx_rc6_ms = -1; 1420 else 1421 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 1422 1423 old->gfx_mhz = new->gfx_mhz; 1424 old->gfx_act_mhz = new->gfx_act_mhz; 1425 1426 old->energy_pkg = new->energy_pkg - old->energy_pkg; 1427 old->energy_cores = new->energy_cores - old->energy_cores; 1428 old->energy_gfx = new->energy_gfx - old->energy_gfx; 1429 old->energy_dram = new->energy_dram - old->energy_dram; 1430 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status; 1431 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status; 1432 1433 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1434 if (mp->format == FORMAT_RAW) 1435 old->counter[i] = new->counter[i]; 1436 else 1437 old->counter[i] = new->counter[i] - old->counter[i]; 1438 } 1439 1440 return 0; 1441 } 1442 1443 void delta_core(struct core_data *new, struct core_data *old) 1444 { 1445 int i; 1446 struct msr_counter *mp; 1447 1448 old->c3 = new->c3 - old->c3; 1449 old->c6 = new->c6 - old->c6; 1450 old->c7 = new->c7 - old->c7; 1451 old->core_temp_c = new->core_temp_c; 1452 old->mc6_us = new->mc6_us - old->mc6_us; 1453 1454 DELTA_WRAP32(new->core_energy, old->core_energy); 1455 1456 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1457 if (mp->format == FORMAT_RAW) 1458 old->counter[i] = new->counter[i]; 1459 else 1460 old->counter[i] = new->counter[i] - old->counter[i]; 1461 } 1462 } 1463 1464 int soft_c1_residency_display(int bic) 1465 { 1466 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr) 1467 return 0; 1468 1469 return DO_BIC_READ(bic); 1470 } 1471 1472 /* 1473 * old = new - old 1474 */ 1475 int delta_thread(struct thread_data *new, struct thread_data *old, struct core_data *core_delta) 1476 { 1477 int i; 1478 struct msr_counter *mp; 1479 1480 /* we run cpuid just the 1st time, copy the results */ 1481 if (DO_BIC(BIC_APIC)) 1482 new->apic_id = old->apic_id; 1483 if (DO_BIC(BIC_X2APIC)) 1484 new->x2apic_id = old->x2apic_id; 1485 1486 /* 1487 * the timestamps from start of measurement interval are in "old" 1488 * the timestamp from end of measurement interval are in "new" 1489 * over-write old w/ new so we can print end of interval values 1490 */ 1491 1492 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta); 1493 old->tv_begin = new->tv_begin; 1494 old->tv_end = new->tv_end; 1495 1496 old->tsc = new->tsc - old->tsc; 1497 1498 /* check for TSC < 1 Mcycles over interval */ 1499 if (old->tsc < (1000 * 1000)) 1500 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1501 "You can disable all c-states by booting with \"idle=poll\"\n" 1502 "or just the deep ones with \"processor.max_cstate=1\""); 1503 1504 old->c1 = new->c1 - old->c1; 1505 1506 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) { 1507 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1508 old->aperf = new->aperf - old->aperf; 1509 old->mperf = new->mperf - old->mperf; 1510 } else { 1511 return -1; 1512 } 1513 } 1514 1515 if (use_c1_residency_msr) { 1516 /* 1517 * Some models have a dedicated C1 residency MSR, 1518 * which should be more accurate than the derivation below. 1519 */ 1520 } else { 1521 /* 1522 * As counter collection is not atomic, 1523 * it is possible for mperf's non-halted cycles + idle states 1524 * to exceed TSC's all cycles: show c1 = 0% in that case. 1525 */ 1526 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 1527 old->c1 = 0; 1528 else { 1529 /* normal case, derive c1 */ 1530 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1531 - core_delta->c6 - core_delta->c7; 1532 } 1533 } 1534 1535 if (old->mperf == 0) { 1536 if (debug > 1) 1537 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1538 old->mperf = 1; /* divide by 0 protection */ 1539 } 1540 1541 if (DO_BIC(BIC_IPC)) 1542 old->instr_count = new->instr_count - old->instr_count; 1543 1544 if (DO_BIC(BIC_IRQ)) 1545 old->irq_count = new->irq_count - old->irq_count; 1546 1547 if (DO_BIC(BIC_SMI)) 1548 old->smi_count = new->smi_count - old->smi_count; 1549 1550 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1551 if (mp->format == FORMAT_RAW) 1552 old->counter[i] = new->counter[i]; 1553 else 1554 old->counter[i] = new->counter[i] - old->counter[i]; 1555 } 1556 return 0; 1557 } 1558 1559 int delta_cpu(struct thread_data *t, struct core_data *c, 1560 struct pkg_data *p, struct thread_data *t2, struct core_data *c2, struct pkg_data *p2) 1561 { 1562 int retval = 0; 1563 1564 /* calculate core delta only for 1st thread in core */ 1565 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1566 delta_core(c, c2); 1567 1568 /* always calculate thread delta */ 1569 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1570 if (retval) 1571 return retval; 1572 1573 /* calculate package delta only for 1st core in package */ 1574 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1575 retval = delta_package(p, p2); 1576 1577 return retval; 1578 } 1579 1580 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1581 { 1582 int i; 1583 struct msr_counter *mp; 1584 1585 t->tv_begin.tv_sec = 0; 1586 t->tv_begin.tv_usec = 0; 1587 t->tv_end.tv_sec = 0; 1588 t->tv_end.tv_usec = 0; 1589 t->tv_delta.tv_sec = 0; 1590 t->tv_delta.tv_usec = 0; 1591 1592 t->tsc = 0; 1593 t->aperf = 0; 1594 t->mperf = 0; 1595 t->c1 = 0; 1596 1597 t->instr_count = 0; 1598 1599 t->irq_count = 0; 1600 t->smi_count = 0; 1601 1602 /* tells format_counters to dump all fields from this set */ 1603 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1604 1605 c->c3 = 0; 1606 c->c6 = 0; 1607 c->c7 = 0; 1608 c->mc6_us = 0; 1609 c->core_temp_c = 0; 1610 c->core_energy = 0; 1611 1612 p->pkg_wtd_core_c0 = 0; 1613 p->pkg_any_core_c0 = 0; 1614 p->pkg_any_gfxe_c0 = 0; 1615 p->pkg_both_core_gfxe_c0 = 0; 1616 1617 p->pc2 = 0; 1618 if (DO_BIC(BIC_Pkgpc3)) 1619 p->pc3 = 0; 1620 if (DO_BIC(BIC_Pkgpc6)) 1621 p->pc6 = 0; 1622 if (DO_BIC(BIC_Pkgpc7)) 1623 p->pc7 = 0; 1624 p->pc8 = 0; 1625 p->pc9 = 0; 1626 p->pc10 = 0; 1627 p->cpu_lpi = 0; 1628 p->sys_lpi = 0; 1629 1630 p->energy_pkg = 0; 1631 p->energy_dram = 0; 1632 p->energy_cores = 0; 1633 p->energy_gfx = 0; 1634 p->rapl_pkg_perf_status = 0; 1635 p->rapl_dram_perf_status = 0; 1636 p->pkg_temp_c = 0; 1637 1638 p->gfx_rc6_ms = 0; 1639 p->gfx_mhz = 0; 1640 p->gfx_act_mhz = 0; 1641 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1642 t->counter[i] = 0; 1643 1644 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1645 c->counter[i] = 0; 1646 1647 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1648 p->counter[i] = 0; 1649 } 1650 1651 int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1652 { 1653 int i; 1654 struct msr_counter *mp; 1655 1656 /* copy un-changing apic_id's */ 1657 if (DO_BIC(BIC_APIC)) 1658 average.threads.apic_id = t->apic_id; 1659 if (DO_BIC(BIC_X2APIC)) 1660 average.threads.x2apic_id = t->x2apic_id; 1661 1662 /* remember first tv_begin */ 1663 if (average.threads.tv_begin.tv_sec == 0) 1664 average.threads.tv_begin = t->tv_begin; 1665 1666 /* remember last tv_end */ 1667 average.threads.tv_end = t->tv_end; 1668 1669 average.threads.tsc += t->tsc; 1670 average.threads.aperf += t->aperf; 1671 average.threads.mperf += t->mperf; 1672 average.threads.c1 += t->c1; 1673 1674 average.threads.instr_count += t->instr_count; 1675 1676 average.threads.irq_count += t->irq_count; 1677 average.threads.smi_count += t->smi_count; 1678 1679 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1680 if (mp->format == FORMAT_RAW) 1681 continue; 1682 average.threads.counter[i] += t->counter[i]; 1683 } 1684 1685 /* sum per-core values only for 1st thread in core */ 1686 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1687 return 0; 1688 1689 average.cores.c3 += c->c3; 1690 average.cores.c6 += c->c6; 1691 average.cores.c7 += c->c7; 1692 average.cores.mc6_us += c->mc6_us; 1693 1694 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1695 1696 average.cores.core_energy += c->core_energy; 1697 1698 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1699 if (mp->format == FORMAT_RAW) 1700 continue; 1701 average.cores.counter[i] += c->counter[i]; 1702 } 1703 1704 /* sum per-pkg values only for 1st core in pkg */ 1705 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1706 return 0; 1707 1708 if (DO_BIC(BIC_Totl_c0)) 1709 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1710 if (DO_BIC(BIC_Any_c0)) 1711 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1712 if (DO_BIC(BIC_GFX_c0)) 1713 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1714 if (DO_BIC(BIC_CPUGFX)) 1715 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1716 1717 average.packages.pc2 += p->pc2; 1718 if (DO_BIC(BIC_Pkgpc3)) 1719 average.packages.pc3 += p->pc3; 1720 if (DO_BIC(BIC_Pkgpc6)) 1721 average.packages.pc6 += p->pc6; 1722 if (DO_BIC(BIC_Pkgpc7)) 1723 average.packages.pc7 += p->pc7; 1724 average.packages.pc8 += p->pc8; 1725 average.packages.pc9 += p->pc9; 1726 average.packages.pc10 += p->pc10; 1727 1728 average.packages.cpu_lpi = p->cpu_lpi; 1729 average.packages.sys_lpi = p->sys_lpi; 1730 1731 average.packages.energy_pkg += p->energy_pkg; 1732 average.packages.energy_dram += p->energy_dram; 1733 average.packages.energy_cores += p->energy_cores; 1734 average.packages.energy_gfx += p->energy_gfx; 1735 1736 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1737 average.packages.gfx_mhz = p->gfx_mhz; 1738 average.packages.gfx_act_mhz = p->gfx_act_mhz; 1739 1740 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1741 1742 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1743 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1744 1745 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1746 if (mp->format == FORMAT_RAW) 1747 continue; 1748 average.packages.counter[i] += p->counter[i]; 1749 } 1750 return 0; 1751 } 1752 1753 /* 1754 * sum the counters for all cpus in the system 1755 * compute the weighted average 1756 */ 1757 void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1758 { 1759 int i; 1760 struct msr_counter *mp; 1761 1762 clear_counters(&average.threads, &average.cores, &average.packages); 1763 1764 for_all_cpus(sum_counters, t, c, p); 1765 1766 /* Use the global time delta for the average. */ 1767 average.threads.tv_delta = tv_delta; 1768 1769 average.threads.tsc /= topo.num_cpus; 1770 average.threads.aperf /= topo.num_cpus; 1771 average.threads.mperf /= topo.num_cpus; 1772 average.threads.instr_count /= topo.num_cpus; 1773 average.threads.c1 /= topo.num_cpus; 1774 1775 if (average.threads.irq_count > 9999999) 1776 sums_need_wide_columns = 1; 1777 1778 average.cores.c3 /= topo.num_cores; 1779 average.cores.c6 /= topo.num_cores; 1780 average.cores.c7 /= topo.num_cores; 1781 average.cores.mc6_us /= topo.num_cores; 1782 1783 if (DO_BIC(BIC_Totl_c0)) 1784 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1785 if (DO_BIC(BIC_Any_c0)) 1786 average.packages.pkg_any_core_c0 /= topo.num_packages; 1787 if (DO_BIC(BIC_GFX_c0)) 1788 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1789 if (DO_BIC(BIC_CPUGFX)) 1790 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1791 1792 average.packages.pc2 /= topo.num_packages; 1793 if (DO_BIC(BIC_Pkgpc3)) 1794 average.packages.pc3 /= topo.num_packages; 1795 if (DO_BIC(BIC_Pkgpc6)) 1796 average.packages.pc6 /= topo.num_packages; 1797 if (DO_BIC(BIC_Pkgpc7)) 1798 average.packages.pc7 /= topo.num_packages; 1799 1800 average.packages.pc8 /= topo.num_packages; 1801 average.packages.pc9 /= topo.num_packages; 1802 average.packages.pc10 /= topo.num_packages; 1803 1804 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1805 if (mp->format == FORMAT_RAW) 1806 continue; 1807 if (mp->type == COUNTER_ITEMS) { 1808 if (average.threads.counter[i] > 9999999) 1809 sums_need_wide_columns = 1; 1810 continue; 1811 } 1812 average.threads.counter[i] /= topo.num_cpus; 1813 } 1814 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1815 if (mp->format == FORMAT_RAW) 1816 continue; 1817 if (mp->type == COUNTER_ITEMS) { 1818 if (average.cores.counter[i] > 9999999) 1819 sums_need_wide_columns = 1; 1820 } 1821 average.cores.counter[i] /= topo.num_cores; 1822 } 1823 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1824 if (mp->format == FORMAT_RAW) 1825 continue; 1826 if (mp->type == COUNTER_ITEMS) { 1827 if (average.packages.counter[i] > 9999999) 1828 sums_need_wide_columns = 1; 1829 } 1830 average.packages.counter[i] /= topo.num_packages; 1831 } 1832 } 1833 1834 static unsigned long long rdtsc(void) 1835 { 1836 unsigned int low, high; 1837 1838 asm volatile ("rdtsc":"=a" (low), "=d"(high)); 1839 1840 return low | ((unsigned long long)high) << 32; 1841 } 1842 1843 /* 1844 * Open a file, and exit on failure 1845 */ 1846 FILE *fopen_or_die(const char *path, const char *mode) 1847 { 1848 FILE *filep = fopen(path, mode); 1849 1850 if (!filep) 1851 err(1, "%s: open failed", path); 1852 return filep; 1853 } 1854 1855 /* 1856 * snapshot_sysfs_counter() 1857 * 1858 * return snapshot of given counter 1859 */ 1860 unsigned long long snapshot_sysfs_counter(char *path) 1861 { 1862 FILE *fp; 1863 int retval; 1864 unsigned long long counter; 1865 1866 fp = fopen_or_die(path, "r"); 1867 1868 retval = fscanf(fp, "%lld", &counter); 1869 if (retval != 1) 1870 err(1, "snapshot_sysfs_counter(%s)", path); 1871 1872 fclose(fp); 1873 1874 return counter; 1875 } 1876 1877 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 1878 { 1879 if (mp->msr_num != 0) { 1880 if (get_msr(cpu, mp->msr_num, counterp)) 1881 return -1; 1882 } else { 1883 char path[128 + PATH_BYTES]; 1884 1885 if (mp->flags & SYSFS_PERCPU) { 1886 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", cpu, mp->path); 1887 1888 *counterp = snapshot_sysfs_counter(path); 1889 } else { 1890 *counterp = snapshot_sysfs_counter(mp->path); 1891 } 1892 } 1893 1894 return 0; 1895 } 1896 1897 int get_epb(int cpu) 1898 { 1899 char path[128 + PATH_BYTES]; 1900 unsigned long long msr; 1901 int ret, epb = -1; 1902 FILE *fp; 1903 1904 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu); 1905 1906 fp = fopen(path, "r"); 1907 if (!fp) 1908 goto msr_fallback; 1909 1910 ret = fscanf(fp, "%d", &epb); 1911 if (ret != 1) 1912 err(1, "%s(%s)", __func__, path); 1913 1914 fclose(fp); 1915 1916 return epb; 1917 1918 msr_fallback: 1919 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr); 1920 1921 return msr & 0xf; 1922 } 1923 1924 void get_apic_id(struct thread_data *t) 1925 { 1926 unsigned int eax, ebx, ecx, edx; 1927 1928 if (DO_BIC(BIC_APIC)) { 1929 eax = ebx = ecx = edx = 0; 1930 __cpuid(1, eax, ebx, ecx, edx); 1931 1932 t->apic_id = (ebx >> 24) & 0xff; 1933 } 1934 1935 if (!DO_BIC(BIC_X2APIC)) 1936 return; 1937 1938 if (authentic_amd || hygon_genuine) { 1939 unsigned int topology_extensions; 1940 1941 if (max_extended_level < 0x8000001e) 1942 return; 1943 1944 eax = ebx = ecx = edx = 0; 1945 __cpuid(0x80000001, eax, ebx, ecx, edx); 1946 topology_extensions = ecx & (1 << 22); 1947 1948 if (topology_extensions == 0) 1949 return; 1950 1951 eax = ebx = ecx = edx = 0; 1952 __cpuid(0x8000001e, eax, ebx, ecx, edx); 1953 1954 t->x2apic_id = eax; 1955 return; 1956 } 1957 1958 if (!genuine_intel) 1959 return; 1960 1961 if (max_level < 0xb) 1962 return; 1963 1964 ecx = 0; 1965 __cpuid(0xb, eax, ebx, ecx, edx); 1966 t->x2apic_id = edx; 1967 1968 if (debug && (t->apic_id != (t->x2apic_id & 0xff))) 1969 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id); 1970 } 1971 1972 /* 1973 * get_counters(...) 1974 * migrate to cpu 1975 * acquire and record local counters for that cpu 1976 */ 1977 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1978 { 1979 int cpu = t->cpu_id; 1980 unsigned long long msr; 1981 int aperf_mperf_retry_count = 0; 1982 struct msr_counter *mp; 1983 int i; 1984 1985 if (cpu_migrate(cpu)) { 1986 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu); 1987 return -1; 1988 } 1989 1990 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 1991 1992 if (first_counter_read) 1993 get_apic_id(t); 1994 retry: 1995 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1996 1997 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) { 1998 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1999 2000 /* 2001 * The TSC, APERF and MPERF must be read together for 2002 * APERF/MPERF and MPERF/TSC to give accurate results. 2003 * 2004 * Unfortunately, APERF and MPERF are read by 2005 * individual system call, so delays may occur 2006 * between them. If the time to read them 2007 * varies by a large amount, we re-read them. 2008 */ 2009 2010 /* 2011 * This initial dummy APERF read has been seen to 2012 * reduce jitter in the subsequent reads. 2013 */ 2014 2015 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 2016 return -3; 2017 2018 t->tsc = rdtsc(); /* re-read close to APERF */ 2019 2020 tsc_before = t->tsc; 2021 2022 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 2023 return -3; 2024 2025 tsc_between = rdtsc(); 2026 2027 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 2028 return -4; 2029 2030 tsc_after = rdtsc(); 2031 2032 aperf_time = tsc_between - tsc_before; 2033 mperf_time = tsc_after - tsc_between; 2034 2035 /* 2036 * If the system call latency to read APERF and MPERF 2037 * differ by more than 2x, then try again. 2038 */ 2039 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 2040 aperf_mperf_retry_count++; 2041 if (aperf_mperf_retry_count < 5) 2042 goto retry; 2043 else 2044 warnx("cpu%d jitter %lld %lld", cpu, aperf_time, mperf_time); 2045 } 2046 aperf_mperf_retry_count = 0; 2047 2048 t->aperf = t->aperf * aperf_mperf_multiplier; 2049 t->mperf = t->mperf * aperf_mperf_multiplier; 2050 } 2051 2052 if (DO_BIC(BIC_IPC)) 2053 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long)) 2054 return -4; 2055 2056 if (DO_BIC(BIC_IRQ)) 2057 t->irq_count = irqs_per_cpu[cpu]; 2058 if (DO_BIC(BIC_SMI)) { 2059 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 2060 return -5; 2061 t->smi_count = msr & 0xFFFFFFFF; 2062 } 2063 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 2064 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 2065 return -6; 2066 } 2067 2068 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 2069 if (get_mp(cpu, mp, &t->counter[i])) 2070 return -10; 2071 } 2072 2073 /* collect core counters only for 1st thread in core */ 2074 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 2075 goto done; 2076 2077 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) { 2078 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 2079 return -6; 2080 } 2081 2082 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) { 2083 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 2084 return -7; 2085 } else if (do_knl_cstates || soft_c1_residency_display(BIC_CPU_c6)) { 2086 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 2087 return -7; 2088 } 2089 2090 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) { 2091 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 2092 return -8; 2093 else if (t->is_atom) { 2094 /* 2095 * For Atom CPUs that has core cstate deeper than c6, 2096 * MSR_CORE_C6_RESIDENCY returns residency of cc6 and deeper. 2097 * Minus CC7 (and deeper cstates) residency to get 2098 * accturate cc6 residency. 2099 */ 2100 c->c6 -= c->c7; 2101 } 2102 } 2103 2104 if (DO_BIC(BIC_Mod_c6)) 2105 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 2106 return -8; 2107 2108 if (DO_BIC(BIC_CoreTmp)) { 2109 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 2110 return -9; 2111 c->core_temp_c = tj_max - ((msr >> 16) & 0x7F); 2112 } 2113 2114 if (do_rapl & RAPL_AMD_F17H) { 2115 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr)) 2116 return -14; 2117 c->core_energy = msr & 0xFFFFFFFF; 2118 } 2119 2120 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 2121 if (get_mp(cpu, mp, &c->counter[i])) 2122 return -10; 2123 } 2124 2125 /* collect package counters only for 1st core in package */ 2126 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2127 goto done; 2128 2129 if (DO_BIC(BIC_Totl_c0)) { 2130 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 2131 return -10; 2132 } 2133 if (DO_BIC(BIC_Any_c0)) { 2134 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 2135 return -11; 2136 } 2137 if (DO_BIC(BIC_GFX_c0)) { 2138 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 2139 return -12; 2140 } 2141 if (DO_BIC(BIC_CPUGFX)) { 2142 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 2143 return -13; 2144 } 2145 if (DO_BIC(BIC_Pkgpc3)) 2146 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 2147 return -9; 2148 if (DO_BIC(BIC_Pkgpc6)) { 2149 if (do_slm_cstates) { 2150 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 2151 return -10; 2152 } else { 2153 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 2154 return -10; 2155 } 2156 } 2157 2158 if (DO_BIC(BIC_Pkgpc2)) 2159 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 2160 return -11; 2161 if (DO_BIC(BIC_Pkgpc7)) 2162 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 2163 return -12; 2164 if (DO_BIC(BIC_Pkgpc8)) 2165 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 2166 return -13; 2167 if (DO_BIC(BIC_Pkgpc9)) 2168 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 2169 return -13; 2170 if (DO_BIC(BIC_Pkgpc10)) 2171 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 2172 return -13; 2173 2174 if (DO_BIC(BIC_CPU_LPI)) 2175 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 2176 if (DO_BIC(BIC_SYS_LPI)) 2177 p->sys_lpi = cpuidle_cur_sys_lpi_us; 2178 2179 if (do_rapl & RAPL_PKG) { 2180 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 2181 return -13; 2182 p->energy_pkg = msr; 2183 } 2184 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 2185 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 2186 return -14; 2187 p->energy_cores = msr; 2188 } 2189 if (do_rapl & RAPL_DRAM) { 2190 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 2191 return -15; 2192 p->energy_dram = msr; 2193 } 2194 if (do_rapl & RAPL_GFX) { 2195 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 2196 return -16; 2197 p->energy_gfx = msr; 2198 } 2199 if (do_rapl & RAPL_PKG_PERF_STATUS) { 2200 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr)) 2201 return -16; 2202 p->rapl_pkg_perf_status = msr; 2203 } 2204 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 2205 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr)) 2206 return -16; 2207 p->rapl_dram_perf_status = msr; 2208 } 2209 if (do_rapl & RAPL_AMD_F17H) { 2210 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr)) 2211 return -13; 2212 p->energy_pkg = msr; 2213 } 2214 if (DO_BIC(BIC_PkgTmp)) { 2215 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 2216 return -17; 2217 p->pkg_temp_c = tj_max - ((msr >> 16) & 0x7F); 2218 } 2219 2220 if (DO_BIC(BIC_GFX_rc6)) 2221 p->gfx_rc6_ms = gfx_cur_rc6_ms; 2222 2223 if (DO_BIC(BIC_GFXMHz)) 2224 p->gfx_mhz = gfx_cur_mhz; 2225 2226 if (DO_BIC(BIC_GFXACTMHz)) 2227 p->gfx_act_mhz = gfx_act_mhz; 2228 2229 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2230 if (get_mp(cpu, mp, &p->counter[i])) 2231 return -10; 2232 } 2233 done: 2234 gettimeofday(&t->tv_end, (struct timezone *)NULL); 2235 2236 return 0; 2237 } 2238 2239 /* 2240 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 2241 * If you change the values, note they are used both in comparisons 2242 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 2243 */ 2244 2245 #define PCLUKN 0 /* Unknown */ 2246 #define PCLRSV 1 /* Reserved */ 2247 #define PCL__0 2 /* PC0 */ 2248 #define PCL__1 3 /* PC1 */ 2249 #define PCL__2 4 /* PC2 */ 2250 #define PCL__3 5 /* PC3 */ 2251 #define PCL__4 6 /* PC4 */ 2252 #define PCL__6 7 /* PC6 */ 2253 #define PCL_6N 8 /* PC6 No Retention */ 2254 #define PCL_6R 9 /* PC6 Retention */ 2255 #define PCL__7 10 /* PC7 */ 2256 #define PCL_7S 11 /* PC7 Shrink */ 2257 #define PCL__8 12 /* PC8 */ 2258 #define PCL__9 13 /* PC9 */ 2259 #define PCL_10 14 /* PC10 */ 2260 #define PCLUNL 15 /* Unlimited */ 2261 2262 int pkg_cstate_limit = PCLUKN; 2263 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 2264 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited" 2265 }; 2266 2267 int nhm_pkg_cstate_limits[16] = 2268 { PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2269 PCLRSV, PCLRSV 2270 }; 2271 2272 int snb_pkg_cstate_limits[16] = 2273 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2274 PCLRSV, PCLRSV 2275 }; 2276 2277 int hsw_pkg_cstate_limits[16] = 2278 { PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2279 PCLRSV, PCLRSV 2280 }; 2281 2282 int slv_pkg_cstate_limits[16] = 2283 { PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2284 PCL__6, PCL__7 2285 }; 2286 2287 int amt_pkg_cstate_limits[16] = 2288 { PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2289 PCLRSV, PCLRSV 2290 }; 2291 2292 int phi_pkg_cstate_limits[16] = 2293 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2294 PCLRSV, PCLRSV 2295 }; 2296 2297 int glm_pkg_cstate_limits[16] = 2298 { PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2299 PCLRSV, PCLRSV 2300 }; 2301 2302 int skx_pkg_cstate_limits[16] = 2303 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2304 PCLRSV, PCLRSV 2305 }; 2306 2307 int icx_pkg_cstate_limits[16] = 2308 { PCL__0, PCL__2, PCL__6, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, 2309 PCLRSV, PCLRSV 2310 }; 2311 2312 static void calculate_tsc_tweak() 2313 { 2314 tsc_tweak = base_hz / tsc_hz; 2315 } 2316 2317 void prewake_cstate_probe(unsigned int family, unsigned int model); 2318 2319 static void dump_nhm_platform_info(void) 2320 { 2321 unsigned long long msr; 2322 unsigned int ratio; 2323 2324 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2325 2326 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 2327 2328 ratio = (msr >> 40) & 0xFF; 2329 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk); 2330 2331 ratio = (msr >> 8) & 0xFF; 2332 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk); 2333 2334 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 2335 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 2336 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 2337 2338 /* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */ 2339 if (dis_cstate_prewake) 2340 fprintf(outf, "C-state Pre-wake: %sabled\n", msr & 0x40000000 ? "DIS" : "EN"); 2341 2342 return; 2343 } 2344 2345 static void dump_hsw_turbo_ratio_limits(void) 2346 { 2347 unsigned long long msr; 2348 unsigned int ratio; 2349 2350 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 2351 2352 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 2353 2354 ratio = (msr >> 8) & 0xFF; 2355 if (ratio) 2356 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk); 2357 2358 ratio = (msr >> 0) & 0xFF; 2359 if (ratio) 2360 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk); 2361 return; 2362 } 2363 2364 static void dump_ivt_turbo_ratio_limits(void) 2365 { 2366 unsigned long long msr; 2367 unsigned int ratio; 2368 2369 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 2370 2371 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 2372 2373 ratio = (msr >> 56) & 0xFF; 2374 if (ratio) 2375 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk); 2376 2377 ratio = (msr >> 48) & 0xFF; 2378 if (ratio) 2379 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk); 2380 2381 ratio = (msr >> 40) & 0xFF; 2382 if (ratio) 2383 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk); 2384 2385 ratio = (msr >> 32) & 0xFF; 2386 if (ratio) 2387 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk); 2388 2389 ratio = (msr >> 24) & 0xFF; 2390 if (ratio) 2391 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk); 2392 2393 ratio = (msr >> 16) & 0xFF; 2394 if (ratio) 2395 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk); 2396 2397 ratio = (msr >> 8) & 0xFF; 2398 if (ratio) 2399 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk); 2400 2401 ratio = (msr >> 0) & 0xFF; 2402 if (ratio) 2403 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk); 2404 return; 2405 } 2406 2407 int has_turbo_ratio_group_limits(int family, int model) 2408 { 2409 2410 if (!genuine_intel) 2411 return 0; 2412 2413 switch (model) { 2414 case INTEL_FAM6_ATOM_GOLDMONT: 2415 case INTEL_FAM6_SKYLAKE_X: 2416 case INTEL_FAM6_ICELAKE_X: 2417 case INTEL_FAM6_ATOM_GOLDMONT_D: 2418 case INTEL_FAM6_ATOM_TREMONT_D: 2419 return 1; 2420 } 2421 return 0; 2422 } 2423 2424 static void dump_turbo_ratio_limits(int family, int model) 2425 { 2426 unsigned long long msr, core_counts; 2427 unsigned int ratio, group_size; 2428 2429 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2430 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2431 2432 if (has_turbo_ratio_group_limits(family, model)) { 2433 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 2434 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 2435 } else { 2436 core_counts = 0x0807060504030201; 2437 } 2438 2439 ratio = (msr >> 56) & 0xFF; 2440 group_size = (core_counts >> 56) & 0xFF; 2441 if (ratio) 2442 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2443 ratio, bclk, ratio * bclk, group_size); 2444 2445 ratio = (msr >> 48) & 0xFF; 2446 group_size = (core_counts >> 48) & 0xFF; 2447 if (ratio) 2448 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2449 ratio, bclk, ratio * bclk, group_size); 2450 2451 ratio = (msr >> 40) & 0xFF; 2452 group_size = (core_counts >> 40) & 0xFF; 2453 if (ratio) 2454 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2455 ratio, bclk, ratio * bclk, group_size); 2456 2457 ratio = (msr >> 32) & 0xFF; 2458 group_size = (core_counts >> 32) & 0xFF; 2459 if (ratio) 2460 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2461 ratio, bclk, ratio * bclk, group_size); 2462 2463 ratio = (msr >> 24) & 0xFF; 2464 group_size = (core_counts >> 24) & 0xFF; 2465 if (ratio) 2466 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2467 ratio, bclk, ratio * bclk, group_size); 2468 2469 ratio = (msr >> 16) & 0xFF; 2470 group_size = (core_counts >> 16) & 0xFF; 2471 if (ratio) 2472 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2473 ratio, bclk, ratio * bclk, group_size); 2474 2475 ratio = (msr >> 8) & 0xFF; 2476 group_size = (core_counts >> 8) & 0xFF; 2477 if (ratio) 2478 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2479 ratio, bclk, ratio * bclk, group_size); 2480 2481 ratio = (msr >> 0) & 0xFF; 2482 group_size = (core_counts >> 0) & 0xFF; 2483 if (ratio) 2484 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2485 ratio, bclk, ratio * bclk, group_size); 2486 return; 2487 } 2488 2489 static void dump_atom_turbo_ratio_limits(void) 2490 { 2491 unsigned long long msr; 2492 unsigned int ratio; 2493 2494 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 2495 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2496 2497 ratio = (msr >> 0) & 0x3F; 2498 if (ratio) 2499 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", ratio, bclk, ratio * bclk); 2500 2501 ratio = (msr >> 8) & 0x3F; 2502 if (ratio) 2503 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", ratio, bclk, ratio * bclk); 2504 2505 ratio = (msr >> 16) & 0x3F; 2506 if (ratio) 2507 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk); 2508 2509 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 2510 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2511 2512 ratio = (msr >> 24) & 0x3F; 2513 if (ratio) 2514 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk); 2515 2516 ratio = (msr >> 16) & 0x3F; 2517 if (ratio) 2518 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk); 2519 2520 ratio = (msr >> 8) & 0x3F; 2521 if (ratio) 2522 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk); 2523 2524 ratio = (msr >> 0) & 0x3F; 2525 if (ratio) 2526 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", ratio, bclk, ratio * bclk); 2527 } 2528 2529 static void dump_knl_turbo_ratio_limits(void) 2530 { 2531 const unsigned int buckets_no = 7; 2532 2533 unsigned long long msr; 2534 int delta_cores, delta_ratio; 2535 int i, b_nr; 2536 unsigned int cores[buckets_no]; 2537 unsigned int ratio[buckets_no]; 2538 2539 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2540 2541 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2542 2543 /* 2544 * Turbo encoding in KNL is as follows: 2545 * [0] -- Reserved 2546 * [7:1] -- Base value of number of active cores of bucket 1. 2547 * [15:8] -- Base value of freq ratio of bucket 1. 2548 * [20:16] -- +ve delta of number of active cores of bucket 2. 2549 * i.e. active cores of bucket 2 = 2550 * active cores of bucket 1 + delta 2551 * [23:21] -- Negative delta of freq ratio of bucket 2. 2552 * i.e. freq ratio of bucket 2 = 2553 * freq ratio of bucket 1 - delta 2554 * [28:24]-- +ve delta of number of active cores of bucket 3. 2555 * [31:29]-- -ve delta of freq ratio of bucket 3. 2556 * [36:32]-- +ve delta of number of active cores of bucket 4. 2557 * [39:37]-- -ve delta of freq ratio of bucket 4. 2558 * [44:40]-- +ve delta of number of active cores of bucket 5. 2559 * [47:45]-- -ve delta of freq ratio of bucket 5. 2560 * [52:48]-- +ve delta of number of active cores of bucket 6. 2561 * [55:53]-- -ve delta of freq ratio of bucket 6. 2562 * [60:56]-- +ve delta of number of active cores of bucket 7. 2563 * [63:61]-- -ve delta of freq ratio of bucket 7. 2564 */ 2565 2566 b_nr = 0; 2567 cores[b_nr] = (msr & 0xFF) >> 1; 2568 ratio[b_nr] = (msr >> 8) & 0xFF; 2569 2570 for (i = 16; i < 64; i += 8) { 2571 delta_cores = (msr >> i) & 0x1F; 2572 delta_ratio = (msr >> (i + 5)) & 0x7; 2573 2574 cores[b_nr + 1] = cores[b_nr] + delta_cores; 2575 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 2576 b_nr++; 2577 } 2578 2579 for (i = buckets_no - 1; i >= 0; i--) 2580 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 2581 fprintf(outf, 2582 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2583 ratio[i], bclk, ratio[i] * bclk, cores[i]); 2584 } 2585 2586 static void dump_nhm_cst_cfg(void) 2587 { 2588 unsigned long long msr; 2589 2590 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2591 2592 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 2593 2594 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 2595 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 2596 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 2597 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 2598 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 2599 (msr & (1 << 15)) ? "" : "UN", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]); 2600 2601 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 2602 if (has_automatic_cstate_conversion) { 2603 fprintf(outf, ", automatic c-state conversion=%s", (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 2604 } 2605 2606 fprintf(outf, ")\n"); 2607 2608 return; 2609 } 2610 2611 static void dump_config_tdp(void) 2612 { 2613 unsigned long long msr; 2614 2615 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 2616 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 2617 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 2618 2619 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 2620 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 2621 if (msr) { 2622 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2623 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2624 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2625 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 2626 } 2627 fprintf(outf, ")\n"); 2628 2629 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 2630 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 2631 if (msr) { 2632 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2633 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2634 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2635 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 2636 } 2637 fprintf(outf, ")\n"); 2638 2639 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 2640 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 2641 if ((msr) & 0x3) 2642 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 2643 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2644 fprintf(outf, ")\n"); 2645 2646 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 2647 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 2648 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 2649 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2650 fprintf(outf, ")\n"); 2651 } 2652 2653 unsigned int irtl_time_units[] = { 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 2654 2655 void print_irtl(void) 2656 { 2657 unsigned long long msr; 2658 2659 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 2660 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 2661 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2662 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2663 2664 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 2665 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 2666 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2667 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2668 2669 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 2670 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 2671 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2672 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2673 2674 if (!do_irtl_hsw) 2675 return; 2676 2677 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 2678 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 2679 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2680 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2681 2682 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 2683 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 2684 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2685 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2686 2687 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 2688 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 2689 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2690 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2691 2692 } 2693 2694 void free_fd_percpu(void) 2695 { 2696 int i; 2697 2698 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 2699 if (fd_percpu[i] != 0) 2700 close(fd_percpu[i]); 2701 } 2702 2703 free(fd_percpu); 2704 } 2705 2706 void free_all_buffers(void) 2707 { 2708 int i; 2709 2710 CPU_FREE(cpu_present_set); 2711 cpu_present_set = NULL; 2712 cpu_present_setsize = 0; 2713 2714 CPU_FREE(cpu_affinity_set); 2715 cpu_affinity_set = NULL; 2716 cpu_affinity_setsize = 0; 2717 2718 free(thread_even); 2719 free(core_even); 2720 free(package_even); 2721 2722 thread_even = NULL; 2723 core_even = NULL; 2724 package_even = NULL; 2725 2726 free(thread_odd); 2727 free(core_odd); 2728 free(package_odd); 2729 2730 thread_odd = NULL; 2731 core_odd = NULL; 2732 package_odd = NULL; 2733 2734 free(output_buffer); 2735 output_buffer = NULL; 2736 outp = NULL; 2737 2738 free_fd_percpu(); 2739 2740 free(irq_column_2_cpu); 2741 free(irqs_per_cpu); 2742 2743 for (i = 0; i <= topo.max_cpu_num; ++i) { 2744 if (cpus[i].put_ids) 2745 CPU_FREE(cpus[i].put_ids); 2746 } 2747 free(cpus); 2748 } 2749 2750 /* 2751 * Parse a file containing a single int. 2752 * Return 0 if file can not be opened 2753 * Exit if file can be opened, but can not be parsed 2754 */ 2755 int parse_int_file(const char *fmt, ...) 2756 { 2757 va_list args; 2758 char path[PATH_MAX]; 2759 FILE *filep; 2760 int value; 2761 2762 va_start(args, fmt); 2763 vsnprintf(path, sizeof(path), fmt, args); 2764 va_end(args); 2765 filep = fopen(path, "r"); 2766 if (!filep) 2767 return 0; 2768 if (fscanf(filep, "%d", &value) != 1) 2769 err(1, "%s: failed to parse number from file", path); 2770 fclose(filep); 2771 return value; 2772 } 2773 2774 /* 2775 * cpu_is_first_core_in_package(cpu) 2776 * return 1 if given CPU is 1st core in package 2777 */ 2778 int cpu_is_first_core_in_package(int cpu) 2779 { 2780 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2781 } 2782 2783 int get_physical_package_id(int cpu) 2784 { 2785 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2786 } 2787 2788 int get_die_id(int cpu) 2789 { 2790 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu); 2791 } 2792 2793 int get_core_id(int cpu) 2794 { 2795 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2796 } 2797 2798 void set_node_data(void) 2799 { 2800 int pkg, node, lnode, cpu, cpux; 2801 int cpu_count; 2802 2803 /* initialize logical_node_id */ 2804 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) 2805 cpus[cpu].logical_node_id = -1; 2806 2807 cpu_count = 0; 2808 for (pkg = 0; pkg < topo.num_packages; pkg++) { 2809 lnode = 0; 2810 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) { 2811 if (cpus[cpu].physical_package_id != pkg) 2812 continue; 2813 /* find a cpu with an unset logical_node_id */ 2814 if (cpus[cpu].logical_node_id != -1) 2815 continue; 2816 cpus[cpu].logical_node_id = lnode; 2817 node = cpus[cpu].physical_node_id; 2818 cpu_count++; 2819 /* 2820 * find all matching cpus on this pkg and set 2821 * the logical_node_id 2822 */ 2823 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) { 2824 if ((cpus[cpux].physical_package_id == pkg) && (cpus[cpux].physical_node_id == node)) { 2825 cpus[cpux].logical_node_id = lnode; 2826 cpu_count++; 2827 } 2828 } 2829 lnode++; 2830 if (lnode > topo.nodes_per_pkg) 2831 topo.nodes_per_pkg = lnode; 2832 } 2833 if (cpu_count >= topo.max_cpu_num) 2834 break; 2835 } 2836 } 2837 2838 int get_physical_node_id(struct cpu_topology *thiscpu) 2839 { 2840 char path[80]; 2841 FILE *filep; 2842 int i; 2843 int cpu = thiscpu->logical_cpu_id; 2844 2845 for (i = 0; i <= topo.max_cpu_num; i++) { 2846 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", cpu, i); 2847 filep = fopen(path, "r"); 2848 if (!filep) 2849 continue; 2850 fclose(filep); 2851 return i; 2852 } 2853 return -1; 2854 } 2855 2856 int get_thread_siblings(struct cpu_topology *thiscpu) 2857 { 2858 char path[80], character; 2859 FILE *filep; 2860 unsigned long map; 2861 int so, shift, sib_core; 2862 int cpu = thiscpu->logical_cpu_id; 2863 int offset = topo.max_cpu_num + 1; 2864 size_t size; 2865 int thread_id = 0; 2866 2867 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 2868 if (thiscpu->thread_id < 0) 2869 thiscpu->thread_id = thread_id++; 2870 if (!thiscpu->put_ids) 2871 return -1; 2872 2873 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 2874 CPU_ZERO_S(size, thiscpu->put_ids); 2875 2876 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 2877 filep = fopen(path, "r"); 2878 2879 if (!filep) { 2880 warnx("%s: open failed", path); 2881 return -1; 2882 } 2883 do { 2884 offset -= BITMASK_SIZE; 2885 if (fscanf(filep, "%lx%c", &map, &character) != 2) 2886 err(1, "%s: failed to parse file", path); 2887 for (shift = 0; shift < BITMASK_SIZE; shift++) { 2888 if ((map >> shift) & 0x1) { 2889 so = shift + offset; 2890 sib_core = get_core_id(so); 2891 if (sib_core == thiscpu->physical_core_id) { 2892 CPU_SET_S(so, size, thiscpu->put_ids); 2893 if ((so != cpu) && (cpus[so].thread_id < 0)) 2894 cpus[so].thread_id = thread_id++; 2895 } 2896 } 2897 } 2898 } while (!strncmp(&character, ",", 1)); 2899 fclose(filep); 2900 2901 return CPU_COUNT_S(size, thiscpu->put_ids); 2902 } 2903 2904 /* 2905 * run func(thread, core, package) in topology order 2906 * skip non-present cpus 2907 */ 2908 2909 int for_all_cpus_2(int (func) (struct thread_data *, struct core_data *, 2910 struct pkg_data *, struct thread_data *, struct core_data *, 2911 struct pkg_data *), struct thread_data *thread_base, 2912 struct core_data *core_base, struct pkg_data *pkg_base, 2913 struct thread_data *thread_base2, struct core_data *core_base2, struct pkg_data *pkg_base2) 2914 { 2915 int retval, pkg_no, node_no, core_no, thread_no; 2916 2917 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2918 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 2919 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 2920 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) { 2921 struct thread_data *t, *t2; 2922 struct core_data *c, *c2; 2923 struct pkg_data *p, *p2; 2924 2925 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no); 2926 2927 if (cpu_is_not_present(t->cpu_id)) 2928 continue; 2929 2930 t2 = GET_THREAD(thread_base2, thread_no, core_no, node_no, pkg_no); 2931 2932 c = GET_CORE(core_base, core_no, node_no, pkg_no); 2933 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no); 2934 2935 p = GET_PKG(pkg_base, pkg_no); 2936 p2 = GET_PKG(pkg_base2, pkg_no); 2937 2938 retval = func(t, c, p, t2, c2, p2); 2939 if (retval) 2940 return retval; 2941 } 2942 } 2943 } 2944 } 2945 return 0; 2946 } 2947 2948 /* 2949 * run func(cpu) on every cpu in /proc/stat 2950 * return max_cpu number 2951 */ 2952 int for_all_proc_cpus(int (func) (int)) 2953 { 2954 FILE *fp; 2955 int cpu_num; 2956 int retval; 2957 2958 fp = fopen_or_die(proc_stat, "r"); 2959 2960 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 2961 if (retval != 0) 2962 err(1, "%s: failed to parse format", proc_stat); 2963 2964 while (1) { 2965 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 2966 if (retval != 1) 2967 break; 2968 2969 retval = func(cpu_num); 2970 if (retval) { 2971 fclose(fp); 2972 return (retval); 2973 } 2974 } 2975 fclose(fp); 2976 return 0; 2977 } 2978 2979 void re_initialize(void) 2980 { 2981 free_all_buffers(); 2982 setup_all_buffers(); 2983 fprintf(outf, "turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2984 } 2985 2986 void set_max_cpu_num(void) 2987 { 2988 FILE *filep; 2989 int base_cpu; 2990 unsigned long dummy; 2991 char pathname[64]; 2992 2993 base_cpu = sched_getcpu(); 2994 if (base_cpu < 0) 2995 err(1, "cannot find calling cpu ID"); 2996 sprintf(pathname, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", base_cpu); 2997 2998 filep = fopen_or_die(pathname, "r"); 2999 topo.max_cpu_num = 0; 3000 while (fscanf(filep, "%lx,", &dummy) == 1) 3001 topo.max_cpu_num += BITMASK_SIZE; 3002 fclose(filep); 3003 topo.max_cpu_num--; /* 0 based */ 3004 } 3005 3006 /* 3007 * count_cpus() 3008 * remember the last one seen, it will be the max 3009 */ 3010 int count_cpus(int cpu) 3011 { 3012 topo.num_cpus++; 3013 return 0; 3014 } 3015 3016 int mark_cpu_present(int cpu) 3017 { 3018 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 3019 return 0; 3020 } 3021 3022 int init_thread_id(int cpu) 3023 { 3024 cpus[cpu].thread_id = -1; 3025 return 0; 3026 } 3027 3028 /* 3029 * snapshot_proc_interrupts() 3030 * 3031 * read and record summary of /proc/interrupts 3032 * 3033 * return 1 if config change requires a restart, else return 0 3034 */ 3035 int snapshot_proc_interrupts(void) 3036 { 3037 static FILE *fp; 3038 int column, retval; 3039 3040 if (fp == NULL) 3041 fp = fopen_or_die("/proc/interrupts", "r"); 3042 else 3043 rewind(fp); 3044 3045 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 3046 for (column = 0; column < topo.num_cpus; ++column) { 3047 int cpu_number; 3048 3049 retval = fscanf(fp, " CPU%d", &cpu_number); 3050 if (retval != 1) 3051 break; 3052 3053 if (cpu_number > topo.max_cpu_num) { 3054 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 3055 return 1; 3056 } 3057 3058 irq_column_2_cpu[column] = cpu_number; 3059 irqs_per_cpu[cpu_number] = 0; 3060 } 3061 3062 /* read /proc/interrupt count lines and sum up irqs per cpu */ 3063 while (1) { 3064 int column; 3065 char buf[64]; 3066 3067 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 3068 if (retval != 1) 3069 break; 3070 3071 /* read the count per cpu */ 3072 for (column = 0; column < topo.num_cpus; ++column) { 3073 3074 int cpu_number, irq_count; 3075 3076 retval = fscanf(fp, " %d", &irq_count); 3077 if (retval != 1) 3078 break; 3079 3080 cpu_number = irq_column_2_cpu[column]; 3081 irqs_per_cpu[cpu_number] += irq_count; 3082 3083 } 3084 3085 while (getc(fp) != '\n') ; /* flush interrupt description */ 3086 3087 } 3088 return 0; 3089 } 3090 3091 /* 3092 * snapshot_gfx_rc6_ms() 3093 * 3094 * record snapshot of 3095 * /sys/class/drm/card0/power/rc6_residency_ms 3096 * 3097 * return 1 if config change requires a restart, else return 0 3098 */ 3099 int snapshot_gfx_rc6_ms(void) 3100 { 3101 FILE *fp; 3102 int retval; 3103 3104 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 3105 3106 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 3107 if (retval != 1) 3108 err(1, "GFX rc6"); 3109 3110 fclose(fp); 3111 3112 return 0; 3113 } 3114 3115 /* 3116 * snapshot_gfx_mhz() 3117 * 3118 * record snapshot of 3119 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 3120 * 3121 * return 1 if config change requires a restart, else return 0 3122 */ 3123 int snapshot_gfx_mhz(void) 3124 { 3125 static FILE *fp; 3126 int retval; 3127 3128 if (fp == NULL) 3129 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 3130 else { 3131 rewind(fp); 3132 fflush(fp); 3133 } 3134 3135 retval = fscanf(fp, "%d", &gfx_cur_mhz); 3136 if (retval != 1) 3137 err(1, "GFX MHz"); 3138 3139 return 0; 3140 } 3141 3142 /* 3143 * snapshot_gfx_cur_mhz() 3144 * 3145 * record snapshot of 3146 * /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz 3147 * 3148 * return 1 if config change requires a restart, else return 0 3149 */ 3150 int snapshot_gfx_act_mhz(void) 3151 { 3152 static FILE *fp; 3153 int retval; 3154 3155 if (fp == NULL) 3156 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r"); 3157 else { 3158 rewind(fp); 3159 fflush(fp); 3160 } 3161 3162 retval = fscanf(fp, "%d", &gfx_act_mhz); 3163 if (retval != 1) 3164 err(1, "GFX ACT MHz"); 3165 3166 return 0; 3167 } 3168 3169 /* 3170 * snapshot_cpu_lpi() 3171 * 3172 * record snapshot of 3173 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 3174 */ 3175 int snapshot_cpu_lpi_us(void) 3176 { 3177 FILE *fp; 3178 int retval; 3179 3180 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 3181 3182 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 3183 if (retval != 1) { 3184 fprintf(stderr, "Disabling Low Power Idle CPU output\n"); 3185 BIC_NOT_PRESENT(BIC_CPU_LPI); 3186 fclose(fp); 3187 return -1; 3188 } 3189 3190 fclose(fp); 3191 3192 return 0; 3193 } 3194 3195 /* 3196 * snapshot_sys_lpi() 3197 * 3198 * record snapshot of sys_lpi_file 3199 */ 3200 int snapshot_sys_lpi_us(void) 3201 { 3202 FILE *fp; 3203 int retval; 3204 3205 fp = fopen_or_die(sys_lpi_file, "r"); 3206 3207 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 3208 if (retval != 1) { 3209 fprintf(stderr, "Disabling Low Power Idle System output\n"); 3210 BIC_NOT_PRESENT(BIC_SYS_LPI); 3211 fclose(fp); 3212 return -1; 3213 } 3214 fclose(fp); 3215 3216 return 0; 3217 } 3218 3219 /* 3220 * snapshot /proc and /sys files 3221 * 3222 * return 1 if configuration restart needed, else return 0 3223 */ 3224 int snapshot_proc_sysfs_files(void) 3225 { 3226 if (DO_BIC(BIC_IRQ)) 3227 if (snapshot_proc_interrupts()) 3228 return 1; 3229 3230 if (DO_BIC(BIC_GFX_rc6)) 3231 snapshot_gfx_rc6_ms(); 3232 3233 if (DO_BIC(BIC_GFXMHz)) 3234 snapshot_gfx_mhz(); 3235 3236 if (DO_BIC(BIC_GFXACTMHz)) 3237 snapshot_gfx_act_mhz(); 3238 3239 if (DO_BIC(BIC_CPU_LPI)) 3240 snapshot_cpu_lpi_us(); 3241 3242 if (DO_BIC(BIC_SYS_LPI)) 3243 snapshot_sys_lpi_us(); 3244 3245 return 0; 3246 } 3247 3248 int exit_requested; 3249 3250 static void signal_handler(int signal) 3251 { 3252 switch (signal) { 3253 case SIGINT: 3254 exit_requested = 1; 3255 if (debug) 3256 fprintf(stderr, " SIGINT\n"); 3257 break; 3258 case SIGUSR1: 3259 if (debug > 1) 3260 fprintf(stderr, "SIGUSR1\n"); 3261 break; 3262 } 3263 } 3264 3265 void setup_signal_handler(void) 3266 { 3267 struct sigaction sa; 3268 3269 memset(&sa, 0, sizeof(sa)); 3270 3271 sa.sa_handler = &signal_handler; 3272 3273 if (sigaction(SIGINT, &sa, NULL) < 0) 3274 err(1, "sigaction SIGINT"); 3275 if (sigaction(SIGUSR1, &sa, NULL) < 0) 3276 err(1, "sigaction SIGUSR1"); 3277 } 3278 3279 void do_sleep(void) 3280 { 3281 struct timeval tout; 3282 struct timespec rest; 3283 fd_set readfds; 3284 int retval; 3285 3286 FD_ZERO(&readfds); 3287 FD_SET(0, &readfds); 3288 3289 if (ignore_stdin) { 3290 nanosleep(&interval_ts, NULL); 3291 return; 3292 } 3293 3294 tout = interval_tv; 3295 retval = select(1, &readfds, NULL, NULL, &tout); 3296 3297 if (retval == 1) { 3298 switch (getc(stdin)) { 3299 case 'q': 3300 exit_requested = 1; 3301 break; 3302 case EOF: 3303 /* 3304 * 'stdin' is a pipe closed on the other end. There 3305 * won't be any further input. 3306 */ 3307 ignore_stdin = 1; 3308 /* Sleep the rest of the time */ 3309 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000); 3310 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000; 3311 nanosleep(&rest, NULL); 3312 } 3313 } 3314 } 3315 3316 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr) 3317 { 3318 int ret, idx; 3319 unsigned long long msr_cur, msr_last; 3320 3321 if (!per_cpu_msr_sum) 3322 return 1; 3323 3324 idx = offset_to_idx(offset); 3325 if (idx < 0) 3326 return idx; 3327 /* get_msr_sum() = sum + (get_msr() - last) */ 3328 ret = get_msr(cpu, offset, &msr_cur); 3329 if (ret) 3330 return ret; 3331 msr_last = per_cpu_msr_sum[cpu].entries[idx].last; 3332 DELTA_WRAP32(msr_cur, msr_last); 3333 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum; 3334 3335 return 0; 3336 } 3337 3338 timer_t timerid; 3339 3340 /* Timer callback, update the sum of MSRs periodically. */ 3341 static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3342 { 3343 int i, ret; 3344 int cpu = t->cpu_id; 3345 3346 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) { 3347 unsigned long long msr_cur, msr_last; 3348 off_t offset; 3349 3350 if (!idx_valid(i)) 3351 continue; 3352 offset = idx_to_offset(i); 3353 if (offset < 0) 3354 continue; 3355 ret = get_msr(cpu, offset, &msr_cur); 3356 if (ret) { 3357 fprintf(outf, "Can not update msr(0x%llx)\n", (unsigned long long)offset); 3358 continue; 3359 } 3360 3361 msr_last = per_cpu_msr_sum[cpu].entries[i].last; 3362 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff; 3363 3364 DELTA_WRAP32(msr_cur, msr_last); 3365 per_cpu_msr_sum[cpu].entries[i].sum += msr_last; 3366 } 3367 return 0; 3368 } 3369 3370 static void msr_record_handler(union sigval v) 3371 { 3372 for_all_cpus(update_msr_sum, EVEN_COUNTERS); 3373 } 3374 3375 void msr_sum_record(void) 3376 { 3377 struct itimerspec its; 3378 struct sigevent sev; 3379 3380 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array)); 3381 if (!per_cpu_msr_sum) { 3382 fprintf(outf, "Can not allocate memory for long time MSR.\n"); 3383 return; 3384 } 3385 /* 3386 * Signal handler might be restricted, so use thread notifier instead. 3387 */ 3388 memset(&sev, 0, sizeof(struct sigevent)); 3389 sev.sigev_notify = SIGEV_THREAD; 3390 sev.sigev_notify_function = msr_record_handler; 3391 3392 sev.sigev_value.sival_ptr = &timerid; 3393 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) { 3394 fprintf(outf, "Can not create timer.\n"); 3395 goto release_msr; 3396 } 3397 3398 its.it_value.tv_sec = 0; 3399 its.it_value.tv_nsec = 1; 3400 /* 3401 * A wraparound time has been calculated early. 3402 * Some sources state that the peak power for a 3403 * microprocessor is usually 1.5 times the TDP rating, 3404 * use 2 * TDP for safety. 3405 */ 3406 its.it_interval.tv_sec = rapl_joule_counter_range / 2; 3407 its.it_interval.tv_nsec = 0; 3408 3409 if (timer_settime(timerid, 0, &its, NULL) == -1) { 3410 fprintf(outf, "Can not set timer.\n"); 3411 goto release_timer; 3412 } 3413 return; 3414 3415 release_timer: 3416 timer_delete(timerid); 3417 release_msr: 3418 free(per_cpu_msr_sum); 3419 } 3420 3421 /* 3422 * set_my_sched_priority(pri) 3423 * return previous 3424 */ 3425 int set_my_sched_priority(int priority) 3426 { 3427 int retval; 3428 int original_priority; 3429 3430 errno = 0; 3431 original_priority = getpriority(PRIO_PROCESS, 0); 3432 if (errno && (original_priority == -1)) 3433 err(errno, "getpriority"); 3434 3435 retval = setpriority(PRIO_PROCESS, 0, priority); 3436 if (retval) 3437 err(retval, "setpriority(%d)", priority); 3438 3439 errno = 0; 3440 retval = getpriority(PRIO_PROCESS, 0); 3441 if (retval != priority) 3442 err(-1, "getpriority(%d) != setpriority(%d)", retval, priority); 3443 3444 return original_priority; 3445 } 3446 3447 void turbostat_loop() 3448 { 3449 int retval; 3450 int restarted = 0; 3451 int done_iters = 0; 3452 3453 setup_signal_handler(); 3454 3455 /* 3456 * elevate own priority for interval mode 3457 */ 3458 set_my_sched_priority(-20); 3459 3460 restart: 3461 restarted++; 3462 3463 snapshot_proc_sysfs_files(); 3464 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3465 first_counter_read = 0; 3466 if (retval < -1) { 3467 exit(retval); 3468 } else if (retval == -1) { 3469 if (restarted > 10) { 3470 exit(retval); 3471 } 3472 re_initialize(); 3473 goto restart; 3474 } 3475 restarted = 0; 3476 done_iters = 0; 3477 gettimeofday(&tv_even, (struct timezone *)NULL); 3478 3479 while (1) { 3480 if (for_all_proc_cpus(cpu_is_not_present)) { 3481 re_initialize(); 3482 goto restart; 3483 } 3484 do_sleep(); 3485 if (snapshot_proc_sysfs_files()) 3486 goto restart; 3487 retval = for_all_cpus(get_counters, ODD_COUNTERS); 3488 if (retval < -1) { 3489 exit(retval); 3490 } else if (retval == -1) { 3491 re_initialize(); 3492 goto restart; 3493 } 3494 gettimeofday(&tv_odd, (struct timezone *)NULL); 3495 timersub(&tv_odd, &tv_even, &tv_delta); 3496 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 3497 re_initialize(); 3498 goto restart; 3499 } 3500 compute_average(EVEN_COUNTERS); 3501 format_all_counters(EVEN_COUNTERS); 3502 flush_output_stdout(); 3503 if (exit_requested) 3504 break; 3505 if (num_iterations && ++done_iters >= num_iterations) 3506 break; 3507 do_sleep(); 3508 if (snapshot_proc_sysfs_files()) 3509 goto restart; 3510 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3511 if (retval < -1) { 3512 exit(retval); 3513 } else if (retval == -1) { 3514 re_initialize(); 3515 goto restart; 3516 } 3517 gettimeofday(&tv_even, (struct timezone *)NULL); 3518 timersub(&tv_even, &tv_odd, &tv_delta); 3519 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 3520 re_initialize(); 3521 goto restart; 3522 } 3523 compute_average(ODD_COUNTERS); 3524 format_all_counters(ODD_COUNTERS); 3525 flush_output_stdout(); 3526 if (exit_requested) 3527 break; 3528 if (num_iterations && ++done_iters >= num_iterations) 3529 break; 3530 } 3531 } 3532 3533 void check_dev_msr() 3534 { 3535 struct stat sb; 3536 char pathname[32]; 3537 3538 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3539 if (stat(pathname, &sb)) 3540 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 3541 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 3542 } 3543 3544 /* 3545 * check for CAP_SYS_RAWIO 3546 * return 0 on success 3547 * return 1 on fail 3548 */ 3549 int check_for_cap_sys_rawio(void) 3550 { 3551 cap_t caps; 3552 cap_flag_value_t cap_flag_value; 3553 3554 caps = cap_get_proc(); 3555 if (caps == NULL) 3556 err(-6, "cap_get_proc\n"); 3557 3558 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value)) 3559 err(-6, "cap_get\n"); 3560 3561 if (cap_flag_value != CAP_SET) { 3562 warnx("capget(CAP_SYS_RAWIO) failed," " try \"# setcap cap_sys_rawio=ep %s\"", progname); 3563 return 1; 3564 } 3565 3566 if (cap_free(caps) == -1) 3567 err(-6, "cap_free\n"); 3568 3569 return 0; 3570 } 3571 3572 void check_permissions(void) 3573 { 3574 int do_exit = 0; 3575 char pathname[32]; 3576 3577 /* check for CAP_SYS_RAWIO */ 3578 do_exit += check_for_cap_sys_rawio(); 3579 3580 /* test file permissions */ 3581 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3582 if (euidaccess(pathname, R_OK)) { 3583 do_exit++; 3584 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 3585 } 3586 3587 /* if all else fails, thell them to be root */ 3588 if (do_exit) 3589 if (getuid() != 0) 3590 warnx("... or simply run as root"); 3591 3592 if (do_exit) 3593 exit(-6); 3594 } 3595 3596 /* 3597 * NHM adds support for additional MSRs: 3598 * 3599 * MSR_SMI_COUNT 0x00000034 3600 * 3601 * MSR_PLATFORM_INFO 0x000000ce 3602 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 3603 * 3604 * MSR_MISC_PWR_MGMT 0x000001aa 3605 * 3606 * MSR_PKG_C3_RESIDENCY 0x000003f8 3607 * MSR_PKG_C6_RESIDENCY 0x000003f9 3608 * MSR_CORE_C3_RESIDENCY 0x000003fc 3609 * MSR_CORE_C6_RESIDENCY 0x000003fd 3610 * 3611 * Side effect: 3612 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 3613 * sets has_misc_feature_control 3614 */ 3615 int probe_nhm_msrs(unsigned int family, unsigned int model) 3616 { 3617 unsigned long long msr; 3618 unsigned int base_ratio; 3619 int *pkg_cstate_limits; 3620 3621 if (!genuine_intel) 3622 return 0; 3623 3624 if (family != 6) 3625 return 0; 3626 3627 bclk = discover_bclk(family, model); 3628 3629 switch (model) { 3630 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 3631 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3632 pkg_cstate_limits = nhm_pkg_cstate_limits; 3633 break; 3634 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 3635 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 3636 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3637 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3638 pkg_cstate_limits = snb_pkg_cstate_limits; 3639 has_misc_feature_control = 1; 3640 break; 3641 case INTEL_FAM6_HASWELL: /* HSW */ 3642 case INTEL_FAM6_HASWELL_G: /* HSW */ 3643 case INTEL_FAM6_HASWELL_X: /* HSX */ 3644 case INTEL_FAM6_HASWELL_L: /* HSW */ 3645 case INTEL_FAM6_BROADWELL: /* BDW */ 3646 case INTEL_FAM6_BROADWELL_G: /* BDW */ 3647 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3648 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 3649 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 3650 pkg_cstate_limits = hsw_pkg_cstate_limits; 3651 has_misc_feature_control = 1; 3652 break; 3653 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3654 pkg_cstate_limits = skx_pkg_cstate_limits; 3655 has_misc_feature_control = 1; 3656 break; 3657 case INTEL_FAM6_ICELAKE_X: /* ICX */ 3658 pkg_cstate_limits = icx_pkg_cstate_limits; 3659 has_misc_feature_control = 1; 3660 break; 3661 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3662 no_MSR_MISC_PWR_MGMT = 1; 3663 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 3664 pkg_cstate_limits = slv_pkg_cstate_limits; 3665 break; 3666 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 3667 pkg_cstate_limits = amt_pkg_cstate_limits; 3668 no_MSR_MISC_PWR_MGMT = 1; 3669 break; 3670 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 3671 pkg_cstate_limits = phi_pkg_cstate_limits; 3672 break; 3673 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3674 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3675 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 3676 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 3677 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 3678 pkg_cstate_limits = glm_pkg_cstate_limits; 3679 break; 3680 default: 3681 return 0; 3682 } 3683 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3684 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3685 3686 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3687 base_ratio = (msr >> 8) & 0xFF; 3688 3689 base_hz = base_ratio * bclk * 1000000; 3690 has_base_hz = 1; 3691 return 1; 3692 } 3693 3694 /* 3695 * SLV client has support for unique MSRs: 3696 * 3697 * MSR_CC6_DEMOTION_POLICY_CONFIG 3698 * MSR_MC6_DEMOTION_POLICY_CONFIG 3699 */ 3700 3701 int has_slv_msrs(unsigned int family, unsigned int model) 3702 { 3703 if (!genuine_intel) 3704 return 0; 3705 3706 switch (model) { 3707 case INTEL_FAM6_ATOM_SILVERMONT: 3708 case INTEL_FAM6_ATOM_SILVERMONT_MID: 3709 case INTEL_FAM6_ATOM_AIRMONT_MID: 3710 return 1; 3711 } 3712 return 0; 3713 } 3714 3715 int is_dnv(unsigned int family, unsigned int model) 3716 { 3717 3718 if (!genuine_intel) 3719 return 0; 3720 3721 switch (model) { 3722 case INTEL_FAM6_ATOM_GOLDMONT_D: 3723 return 1; 3724 } 3725 return 0; 3726 } 3727 3728 int is_bdx(unsigned int family, unsigned int model) 3729 { 3730 3731 if (!genuine_intel) 3732 return 0; 3733 3734 switch (model) { 3735 case INTEL_FAM6_BROADWELL_X: 3736 return 1; 3737 } 3738 return 0; 3739 } 3740 3741 int is_skx(unsigned int family, unsigned int model) 3742 { 3743 3744 if (!genuine_intel) 3745 return 0; 3746 3747 switch (model) { 3748 case INTEL_FAM6_SKYLAKE_X: 3749 return 1; 3750 } 3751 return 0; 3752 } 3753 3754 int is_icx(unsigned int family, unsigned int model) 3755 { 3756 3757 if (!genuine_intel) 3758 return 0; 3759 3760 switch (model) { 3761 case INTEL_FAM6_ICELAKE_X: 3762 return 1; 3763 } 3764 return 0; 3765 } 3766 3767 int is_ehl(unsigned int family, unsigned int model) 3768 { 3769 if (!genuine_intel) 3770 return 0; 3771 3772 switch (model) { 3773 case INTEL_FAM6_ATOM_TREMONT: 3774 return 1; 3775 } 3776 return 0; 3777 } 3778 3779 int is_jvl(unsigned int family, unsigned int model) 3780 { 3781 if (!genuine_intel) 3782 return 0; 3783 3784 switch (model) { 3785 case INTEL_FAM6_ATOM_TREMONT_D: 3786 return 1; 3787 } 3788 return 0; 3789 } 3790 3791 int has_turbo_ratio_limit(unsigned int family, unsigned int model) 3792 { 3793 if (has_slv_msrs(family, model)) 3794 return 0; 3795 3796 switch (model) { 3797 /* Nehalem compatible, but do not include turbo-ratio limit support */ 3798 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3799 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 3800 return 0; 3801 default: 3802 return 1; 3803 } 3804 } 3805 3806 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 3807 { 3808 if (has_slv_msrs(family, model)) 3809 return 1; 3810 3811 return 0; 3812 } 3813 3814 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 3815 { 3816 if (!genuine_intel) 3817 return 0; 3818 3819 if (family != 6) 3820 return 0; 3821 3822 switch (model) { 3823 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3824 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3825 return 1; 3826 default: 3827 return 0; 3828 } 3829 } 3830 3831 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 3832 { 3833 if (!genuine_intel) 3834 return 0; 3835 3836 if (family != 6) 3837 return 0; 3838 3839 switch (model) { 3840 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3841 return 1; 3842 default: 3843 return 0; 3844 } 3845 } 3846 3847 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 3848 { 3849 if (!genuine_intel) 3850 return 0; 3851 3852 if (family != 6) 3853 return 0; 3854 3855 switch (model) { 3856 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3857 return 1; 3858 default: 3859 return 0; 3860 } 3861 } 3862 3863 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) 3864 { 3865 if (!genuine_intel) 3866 return 0; 3867 3868 if (family != 6) 3869 return 0; 3870 3871 switch (model) { 3872 case INTEL_FAM6_ATOM_GOLDMONT: 3873 case INTEL_FAM6_SKYLAKE_X: 3874 case INTEL_FAM6_ICELAKE_X: 3875 return 1; 3876 default: 3877 return 0; 3878 } 3879 } 3880 3881 int has_config_tdp(unsigned int family, unsigned int model) 3882 { 3883 if (!genuine_intel) 3884 return 0; 3885 3886 if (family != 6) 3887 return 0; 3888 3889 switch (model) { 3890 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3891 case INTEL_FAM6_HASWELL: /* HSW */ 3892 case INTEL_FAM6_HASWELL_X: /* HSX */ 3893 case INTEL_FAM6_HASWELL_L: /* HSW */ 3894 case INTEL_FAM6_HASWELL_G: /* HSW */ 3895 case INTEL_FAM6_BROADWELL: /* BDW */ 3896 case INTEL_FAM6_BROADWELL_G: /* BDW */ 3897 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3898 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 3899 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 3900 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3901 case INTEL_FAM6_ICELAKE_X: /* ICX */ 3902 3903 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3904 return 1; 3905 default: 3906 return 0; 3907 } 3908 } 3909 3910 /* 3911 * tcc_offset_bits: 3912 * 0: Tcc Offset not supported (Default) 3913 * 6: Bit 29:24 of MSR_PLATFORM_INFO 3914 * 4: Bit 27:24 of MSR_PLATFORM_INFO 3915 */ 3916 void check_tcc_offset(int model) 3917 { 3918 unsigned long long msr; 3919 3920 if (!genuine_intel) 3921 return; 3922 3923 switch (model) { 3924 case INTEL_FAM6_SKYLAKE_L: 3925 case INTEL_FAM6_SKYLAKE: 3926 case INTEL_FAM6_KABYLAKE_L: 3927 case INTEL_FAM6_KABYLAKE: 3928 case INTEL_FAM6_ICELAKE_L: 3929 case INTEL_FAM6_ICELAKE: 3930 case INTEL_FAM6_TIGERLAKE_L: 3931 case INTEL_FAM6_TIGERLAKE: 3932 case INTEL_FAM6_COMETLAKE: 3933 if (!get_msr(base_cpu, MSR_PLATFORM_INFO, &msr)) { 3934 msr = (msr >> 30) & 1; 3935 if (msr) 3936 tcc_offset_bits = 6; 3937 } 3938 return; 3939 default: 3940 return; 3941 } 3942 } 3943 3944 static void remove_underbar(char *s) 3945 { 3946 char *to = s; 3947 3948 while (*s) { 3949 if (*s != '_') 3950 *to++ = *s; 3951 s++; 3952 } 3953 3954 *to = 0; 3955 } 3956 3957 static void dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 3958 { 3959 if (!do_nhm_platform_info) 3960 return; 3961 3962 dump_nhm_platform_info(); 3963 3964 if (has_hsw_turbo_ratio_limit(family, model)) 3965 dump_hsw_turbo_ratio_limits(); 3966 3967 if (has_ivt_turbo_ratio_limit(family, model)) 3968 dump_ivt_turbo_ratio_limits(); 3969 3970 if (has_turbo_ratio_limit(family, model)) 3971 dump_turbo_ratio_limits(family, model); 3972 3973 if (has_atom_turbo_ratio_limit(family, model)) 3974 dump_atom_turbo_ratio_limits(); 3975 3976 if (has_knl_turbo_ratio_limit(family, model)) 3977 dump_knl_turbo_ratio_limits(); 3978 3979 if (has_config_tdp(family, model)) 3980 dump_config_tdp(); 3981 3982 dump_nhm_cst_cfg(); 3983 } 3984 3985 static void dump_sysfs_file(char *path) 3986 { 3987 FILE *input; 3988 char cpuidle_buf[64]; 3989 3990 input = fopen(path, "r"); 3991 if (input == NULL) { 3992 if (debug) 3993 fprintf(outf, "NSFOD %s\n", path); 3994 return; 3995 } 3996 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input)) 3997 err(1, "%s: failed to read file", path); 3998 fclose(input); 3999 4000 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf); 4001 } 4002 4003 static void dump_sysfs_cstate_config(void) 4004 { 4005 char path[64]; 4006 char name_buf[16]; 4007 char desc[64]; 4008 FILE *input; 4009 int state; 4010 char *sp; 4011 4012 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) { 4013 fprintf(outf, "cpuidle not loaded\n"); 4014 return; 4015 } 4016 4017 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver"); 4018 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor"); 4019 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro"); 4020 4021 for (state = 0; state < 10; ++state) { 4022 4023 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 4024 input = fopen(path, "r"); 4025 if (input == NULL) 4026 continue; 4027 if (!fgets(name_buf, sizeof(name_buf), input)) 4028 err(1, "%s: failed to read file", path); 4029 4030 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 4031 sp = strchr(name_buf, '-'); 4032 if (!sp) 4033 sp = strchrnul(name_buf, '\n'); 4034 *sp = '\0'; 4035 fclose(input); 4036 4037 remove_underbar(name_buf); 4038 4039 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", base_cpu, state); 4040 input = fopen(path, "r"); 4041 if (input == NULL) 4042 continue; 4043 if (!fgets(desc, sizeof(desc), input)) 4044 err(1, "%s: failed to read file", path); 4045 4046 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 4047 fclose(input); 4048 } 4049 } 4050 4051 static void dump_sysfs_pstate_config(void) 4052 { 4053 char path[64]; 4054 char driver_buf[64]; 4055 char governor_buf[64]; 4056 FILE *input; 4057 int turbo; 4058 4059 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", base_cpu); 4060 input = fopen(path, "r"); 4061 if (input == NULL) { 4062 fprintf(outf, "NSFOD %s\n", path); 4063 return; 4064 } 4065 if (!fgets(driver_buf, sizeof(driver_buf), input)) 4066 err(1, "%s: failed to read file", path); 4067 fclose(input); 4068 4069 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", base_cpu); 4070 input = fopen(path, "r"); 4071 if (input == NULL) { 4072 fprintf(outf, "NSFOD %s\n", path); 4073 return; 4074 } 4075 if (!fgets(governor_buf, sizeof(governor_buf), input)) 4076 err(1, "%s: failed to read file", path); 4077 fclose(input); 4078 4079 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 4080 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 4081 4082 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 4083 input = fopen(path, "r"); 4084 if (input != NULL) { 4085 if (fscanf(input, "%d", &turbo) != 1) 4086 err(1, "%s: failed to parse number from file", path); 4087 fprintf(outf, "cpufreq boost: %d\n", turbo); 4088 fclose(input); 4089 } 4090 4091 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 4092 input = fopen(path, "r"); 4093 if (input != NULL) { 4094 if (fscanf(input, "%d", &turbo) != 1) 4095 err(1, "%s: failed to parse number from file", path); 4096 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 4097 fclose(input); 4098 } 4099 } 4100 4101 /* 4102 * print_epb() 4103 * Decode the ENERGY_PERF_BIAS MSR 4104 */ 4105 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4106 { 4107 char *epb_string; 4108 int cpu, epb; 4109 4110 if (!has_epb) 4111 return 0; 4112 4113 cpu = t->cpu_id; 4114 4115 /* EPB is per-package */ 4116 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4117 return 0; 4118 4119 if (cpu_migrate(cpu)) { 4120 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu); 4121 return -1; 4122 } 4123 4124 epb = get_epb(cpu); 4125 if (epb < 0) 4126 return 0; 4127 4128 switch (epb) { 4129 case ENERGY_PERF_BIAS_PERFORMANCE: 4130 epb_string = "performance"; 4131 break; 4132 case ENERGY_PERF_BIAS_NORMAL: 4133 epb_string = "balanced"; 4134 break; 4135 case ENERGY_PERF_BIAS_POWERSAVE: 4136 epb_string = "powersave"; 4137 break; 4138 default: 4139 epb_string = "custom"; 4140 break; 4141 } 4142 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string); 4143 4144 return 0; 4145 } 4146 4147 /* 4148 * print_hwp() 4149 * Decode the MSR_HWP_CAPABILITIES 4150 */ 4151 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4152 { 4153 unsigned long long msr; 4154 int cpu; 4155 4156 if (!has_hwp) 4157 return 0; 4158 4159 cpu = t->cpu_id; 4160 4161 /* MSR_HWP_CAPABILITIES is per-package */ 4162 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4163 return 0; 4164 4165 if (cpu_migrate(cpu)) { 4166 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu); 4167 return -1; 4168 } 4169 4170 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 4171 return 0; 4172 4173 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 4174 4175 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 4176 if ((msr & (1 << 0)) == 0) 4177 return 0; 4178 4179 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 4180 return 0; 4181 4182 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 4183 "(high %d guar %d eff %d low %d)\n", 4184 cpu, msr, 4185 (unsigned int)HWP_HIGHEST_PERF(msr), 4186 (unsigned int)HWP_GUARANTEED_PERF(msr), 4187 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), (unsigned int)HWP_LOWEST_PERF(msr)); 4188 4189 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 4190 return 0; 4191 4192 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 4193 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 4194 cpu, msr, 4195 (unsigned int)(((msr) >> 0) & 0xff), 4196 (unsigned int)(((msr) >> 8) & 0xff), 4197 (unsigned int)(((msr) >> 16) & 0xff), 4198 (unsigned int)(((msr) >> 24) & 0xff), 4199 (unsigned int)(((msr) >> 32) & 0xff3), (unsigned int)(((msr) >> 42) & 0x1)); 4200 4201 if (has_hwp_pkg) { 4202 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 4203 return 0; 4204 4205 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 4206 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 4207 cpu, msr, 4208 (unsigned int)(((msr) >> 0) & 0xff), 4209 (unsigned int)(((msr) >> 8) & 0xff), 4210 (unsigned int)(((msr) >> 16) & 0xff), 4211 (unsigned int)(((msr) >> 24) & 0xff), (unsigned int)(((msr) >> 32) & 0xff3)); 4212 } 4213 if (has_hwp_notify) { 4214 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 4215 return 0; 4216 4217 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 4218 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 4219 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis"); 4220 } 4221 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 4222 return 0; 4223 4224 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 4225 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 4226 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x2) ? "" : "No-"); 4227 4228 return 0; 4229 } 4230 4231 /* 4232 * print_perf_limit() 4233 */ 4234 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4235 { 4236 unsigned long long msr; 4237 int cpu; 4238 4239 cpu = t->cpu_id; 4240 4241 /* per-package */ 4242 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4243 return 0; 4244 4245 if (cpu_migrate(cpu)) { 4246 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu); 4247 return -1; 4248 } 4249 4250 if (do_core_perf_limit_reasons) { 4251 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 4252 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4253 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 4254 (msr & 1 << 15) ? "bit15, " : "", 4255 (msr & 1 << 14) ? "bit14, " : "", 4256 (msr & 1 << 13) ? "Transitions, " : "", 4257 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 4258 (msr & 1 << 11) ? "PkgPwrL2, " : "", 4259 (msr & 1 << 10) ? "PkgPwrL1, " : "", 4260 (msr & 1 << 9) ? "CorePwr, " : "", 4261 (msr & 1 << 8) ? "Amps, " : "", 4262 (msr & 1 << 6) ? "VR-Therm, " : "", 4263 (msr & 1 << 5) ? "Auto-HWP, " : "", 4264 (msr & 1 << 4) ? "Graphics, " : "", 4265 (msr & 1 << 2) ? "bit2, " : "", 4266 (msr & 1 << 1) ? "ThermStatus, " : "", (msr & 1 << 0) ? "PROCHOT, " : ""); 4267 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 4268 (msr & 1 << 31) ? "bit31, " : "", 4269 (msr & 1 << 30) ? "bit30, " : "", 4270 (msr & 1 << 29) ? "Transitions, " : "", 4271 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 4272 (msr & 1 << 27) ? "PkgPwrL2, " : "", 4273 (msr & 1 << 26) ? "PkgPwrL1, " : "", 4274 (msr & 1 << 25) ? "CorePwr, " : "", 4275 (msr & 1 << 24) ? "Amps, " : "", 4276 (msr & 1 << 22) ? "VR-Therm, " : "", 4277 (msr & 1 << 21) ? "Auto-HWP, " : "", 4278 (msr & 1 << 20) ? "Graphics, " : "", 4279 (msr & 1 << 18) ? "bit18, " : "", 4280 (msr & 1 << 17) ? "ThermStatus, " : "", (msr & 1 << 16) ? "PROCHOT, " : ""); 4281 4282 } 4283 if (do_gfx_perf_limit_reasons) { 4284 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 4285 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4286 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 4287 (msr & 1 << 0) ? "PROCHOT, " : "", 4288 (msr & 1 << 1) ? "ThermStatus, " : "", 4289 (msr & 1 << 4) ? "Graphics, " : "", 4290 (msr & 1 << 6) ? "VR-Therm, " : "", 4291 (msr & 1 << 8) ? "Amps, " : "", 4292 (msr & 1 << 9) ? "GFXPwr, " : "", 4293 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4294 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 4295 (msr & 1 << 16) ? "PROCHOT, " : "", 4296 (msr & 1 << 17) ? "ThermStatus, " : "", 4297 (msr & 1 << 20) ? "Graphics, " : "", 4298 (msr & 1 << 22) ? "VR-Therm, " : "", 4299 (msr & 1 << 24) ? "Amps, " : "", 4300 (msr & 1 << 25) ? "GFXPwr, " : "", 4301 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4302 } 4303 if (do_ring_perf_limit_reasons) { 4304 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 4305 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4306 fprintf(outf, " (Active: %s%s%s%s%s%s)", 4307 (msr & 1 << 0) ? "PROCHOT, " : "", 4308 (msr & 1 << 1) ? "ThermStatus, " : "", 4309 (msr & 1 << 6) ? "VR-Therm, " : "", 4310 (msr & 1 << 8) ? "Amps, " : "", 4311 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4312 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 4313 (msr & 1 << 16) ? "PROCHOT, " : "", 4314 (msr & 1 << 17) ? "ThermStatus, " : "", 4315 (msr & 1 << 22) ? "VR-Therm, " : "", 4316 (msr & 1 << 24) ? "Amps, " : "", 4317 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4318 } 4319 return 0; 4320 } 4321 4322 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 4323 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 4324 4325 double get_tdp_intel(unsigned int model) 4326 { 4327 unsigned long long msr; 4328 4329 if (do_rapl & RAPL_PKG_POWER_INFO) 4330 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 4331 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 4332 4333 switch (model) { 4334 case INTEL_FAM6_ATOM_SILVERMONT: 4335 case INTEL_FAM6_ATOM_SILVERMONT_D: 4336 return 30.0; 4337 default: 4338 return 135.0; 4339 } 4340 } 4341 4342 double get_tdp_amd(unsigned int family) 4343 { 4344 /* This is the max stock TDP of HEDT/Server Fam17h+ chips */ 4345 return 280.0; 4346 } 4347 4348 /* 4349 * rapl_dram_energy_units_probe() 4350 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 4351 */ 4352 static double rapl_dram_energy_units_probe(int model, double rapl_energy_units) 4353 { 4354 /* only called for genuine_intel, family 6 */ 4355 4356 switch (model) { 4357 case INTEL_FAM6_HASWELL_X: /* HSX */ 4358 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4359 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4360 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4361 return (rapl_dram_energy_units = 15.3 / 1000000); 4362 default: 4363 return (rapl_energy_units); 4364 } 4365 } 4366 4367 void rapl_probe_intel(unsigned int family, unsigned int model) 4368 { 4369 unsigned long long msr; 4370 unsigned int time_unit; 4371 double tdp; 4372 4373 if (family != 6) 4374 return; 4375 4376 switch (model) { 4377 case INTEL_FAM6_SANDYBRIDGE: 4378 case INTEL_FAM6_IVYBRIDGE: 4379 case INTEL_FAM6_HASWELL: /* HSW */ 4380 case INTEL_FAM6_HASWELL_L: /* HSW */ 4381 case INTEL_FAM6_HASWELL_G: /* HSW */ 4382 case INTEL_FAM6_BROADWELL: /* BDW */ 4383 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4384 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 4385 if (rapl_joules) { 4386 BIC_PRESENT(BIC_Pkg_J); 4387 BIC_PRESENT(BIC_Cor_J); 4388 BIC_PRESENT(BIC_GFX_J); 4389 } else { 4390 BIC_PRESENT(BIC_PkgWatt); 4391 BIC_PRESENT(BIC_CorWatt); 4392 BIC_PRESENT(BIC_GFXWatt); 4393 } 4394 break; 4395 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4396 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4397 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 4398 if (rapl_joules) 4399 BIC_PRESENT(BIC_Pkg_J); 4400 else 4401 BIC_PRESENT(BIC_PkgWatt); 4402 break; 4403 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4404 do_rapl = 4405 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS 4406 | RAPL_GFX | RAPL_PKG_POWER_INFO; 4407 if (rapl_joules) { 4408 BIC_PRESENT(BIC_Pkg_J); 4409 BIC_PRESENT(BIC_Cor_J); 4410 BIC_PRESENT(BIC_RAM_J); 4411 BIC_PRESENT(BIC_GFX_J); 4412 } else { 4413 BIC_PRESENT(BIC_PkgWatt); 4414 BIC_PRESENT(BIC_CorWatt); 4415 BIC_PRESENT(BIC_RAMWatt); 4416 BIC_PRESENT(BIC_GFXWatt); 4417 } 4418 break; 4419 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 4420 do_rapl = RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 4421 BIC_PRESENT(BIC_PKG__); 4422 if (rapl_joules) 4423 BIC_PRESENT(BIC_Pkg_J); 4424 else 4425 BIC_PRESENT(BIC_PkgWatt); 4426 break; 4427 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4428 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4429 do_rapl = 4430 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS 4431 | RAPL_GFX | RAPL_PKG_POWER_INFO; 4432 BIC_PRESENT(BIC_PKG__); 4433 BIC_PRESENT(BIC_RAM__); 4434 if (rapl_joules) { 4435 BIC_PRESENT(BIC_Pkg_J); 4436 BIC_PRESENT(BIC_Cor_J); 4437 BIC_PRESENT(BIC_RAM_J); 4438 BIC_PRESENT(BIC_GFX_J); 4439 } else { 4440 BIC_PRESENT(BIC_PkgWatt); 4441 BIC_PRESENT(BIC_CorWatt); 4442 BIC_PRESENT(BIC_RAMWatt); 4443 BIC_PRESENT(BIC_GFXWatt); 4444 } 4445 break; 4446 case INTEL_FAM6_HASWELL_X: /* HSX */ 4447 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4448 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4449 case INTEL_FAM6_ICELAKE_X: /* ICX */ 4450 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4451 do_rapl = 4452 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | 4453 RAPL_PKG_POWER_INFO; 4454 BIC_PRESENT(BIC_PKG__); 4455 BIC_PRESENT(BIC_RAM__); 4456 if (rapl_joules) { 4457 BIC_PRESENT(BIC_Pkg_J); 4458 BIC_PRESENT(BIC_RAM_J); 4459 } else { 4460 BIC_PRESENT(BIC_PkgWatt); 4461 BIC_PRESENT(BIC_RAMWatt); 4462 } 4463 break; 4464 case INTEL_FAM6_SANDYBRIDGE_X: 4465 case INTEL_FAM6_IVYBRIDGE_X: 4466 do_rapl = 4467 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | 4468 RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 4469 BIC_PRESENT(BIC_PKG__); 4470 BIC_PRESENT(BIC_RAM__); 4471 if (rapl_joules) { 4472 BIC_PRESENT(BIC_Pkg_J); 4473 BIC_PRESENT(BIC_Cor_J); 4474 BIC_PRESENT(BIC_RAM_J); 4475 } else { 4476 BIC_PRESENT(BIC_PkgWatt); 4477 BIC_PRESENT(BIC_CorWatt); 4478 BIC_PRESENT(BIC_RAMWatt); 4479 } 4480 break; 4481 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4482 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 4483 do_rapl = RAPL_PKG | RAPL_CORES; 4484 if (rapl_joules) { 4485 BIC_PRESENT(BIC_Pkg_J); 4486 BIC_PRESENT(BIC_Cor_J); 4487 } else { 4488 BIC_PRESENT(BIC_PkgWatt); 4489 BIC_PRESENT(BIC_CorWatt); 4490 } 4491 break; 4492 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 4493 do_rapl = 4494 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | 4495 RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 4496 BIC_PRESENT(BIC_PKG__); 4497 BIC_PRESENT(BIC_RAM__); 4498 if (rapl_joules) { 4499 BIC_PRESENT(BIC_Pkg_J); 4500 BIC_PRESENT(BIC_Cor_J); 4501 BIC_PRESENT(BIC_RAM_J); 4502 } else { 4503 BIC_PRESENT(BIC_PkgWatt); 4504 BIC_PRESENT(BIC_CorWatt); 4505 BIC_PRESENT(BIC_RAMWatt); 4506 } 4507 break; 4508 default: 4509 return; 4510 } 4511 4512 /* units on package 0, verify later other packages match */ 4513 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 4514 return; 4515 4516 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 4517 if (model == INTEL_FAM6_ATOM_SILVERMONT) 4518 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 4519 else 4520 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 4521 4522 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 4523 4524 time_unit = msr >> 16 & 0xF; 4525 if (time_unit == 0) 4526 time_unit = 0xA; 4527 4528 rapl_time_units = 1.0 / (1 << (time_unit)); 4529 4530 tdp = get_tdp_intel(model); 4531 4532 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4533 if (!quiet) 4534 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4535 } 4536 4537 void rapl_probe_amd(unsigned int family, unsigned int model) 4538 { 4539 unsigned long long msr; 4540 unsigned int eax, ebx, ecx, edx; 4541 unsigned int has_rapl = 0; 4542 double tdp; 4543 4544 if (max_extended_level >= 0x80000007) { 4545 __cpuid(0x80000007, eax, ebx, ecx, edx); 4546 /* RAPL (Fam 17h+) */ 4547 has_rapl = edx & (1 << 14); 4548 } 4549 4550 if (!has_rapl || family < 0x17) 4551 return; 4552 4553 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY; 4554 if (rapl_joules) { 4555 BIC_PRESENT(BIC_Pkg_J); 4556 BIC_PRESENT(BIC_Cor_J); 4557 } else { 4558 BIC_PRESENT(BIC_PkgWatt); 4559 BIC_PRESENT(BIC_CorWatt); 4560 } 4561 4562 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr)) 4563 return; 4564 4565 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf)); 4566 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f)); 4567 rapl_power_units = ldexp(1.0, -(msr & 0xf)); 4568 4569 tdp = get_tdp_amd(family); 4570 4571 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4572 if (!quiet) 4573 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4574 } 4575 4576 /* 4577 * rapl_probe() 4578 * 4579 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 4580 */ 4581 void rapl_probe(unsigned int family, unsigned int model) 4582 { 4583 if (genuine_intel) 4584 rapl_probe_intel(family, model); 4585 if (authentic_amd || hygon_genuine) 4586 rapl_probe_amd(family, model); 4587 } 4588 4589 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 4590 { 4591 if (!genuine_intel) 4592 return; 4593 4594 if (family != 6) 4595 return; 4596 4597 switch (model) { 4598 case INTEL_FAM6_HASWELL: /* HSW */ 4599 case INTEL_FAM6_HASWELL_L: /* HSW */ 4600 case INTEL_FAM6_HASWELL_G: /* HSW */ 4601 do_gfx_perf_limit_reasons = 1; 4602 case INTEL_FAM6_HASWELL_X: /* HSX */ 4603 do_core_perf_limit_reasons = 1; 4604 do_ring_perf_limit_reasons = 1; 4605 default: 4606 return; 4607 } 4608 } 4609 4610 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model) 4611 { 4612 if (is_skx(family, model) || is_bdx(family, model) || is_icx(family, model)) 4613 has_automatic_cstate_conversion = 1; 4614 } 4615 4616 void prewake_cstate_probe(unsigned int family, unsigned int model) 4617 { 4618 if (is_icx(family, model)) 4619 dis_cstate_prewake = 1; 4620 } 4621 4622 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4623 { 4624 unsigned long long msr; 4625 unsigned int dts, dts2; 4626 int cpu; 4627 4628 if (!(do_dts || do_ptm)) 4629 return 0; 4630 4631 cpu = t->cpu_id; 4632 4633 /* DTS is per-core, no need to print for each thread */ 4634 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 4635 return 0; 4636 4637 if (cpu_migrate(cpu)) { 4638 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu); 4639 return -1; 4640 } 4641 4642 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 4643 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 4644 return 0; 4645 4646 dts = (msr >> 16) & 0x7F; 4647 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", cpu, msr, tj_max - dts); 4648 4649 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 4650 return 0; 4651 4652 dts = (msr >> 16) & 0x7F; 4653 dts2 = (msr >> 8) & 0x7F; 4654 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4655 cpu, msr, tj_max - dts, tj_max - dts2); 4656 } 4657 4658 if (do_dts && debug) { 4659 unsigned int resolution; 4660 4661 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 4662 return 0; 4663 4664 dts = (msr >> 16) & 0x7F; 4665 resolution = (msr >> 27) & 0xF; 4666 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 4667 cpu, msr, tj_max - dts, resolution); 4668 4669 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 4670 return 0; 4671 4672 dts = (msr >> 16) & 0x7F; 4673 dts2 = (msr >> 8) & 0x7F; 4674 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4675 cpu, msr, tj_max - dts, tj_max - dts2); 4676 } 4677 4678 return 0; 4679 } 4680 4681 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 4682 { 4683 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 4684 cpu, label, 4685 ((msr >> 15) & 1) ? "EN" : "DIS", 4686 ((msr >> 0) & 0x7FFF) * rapl_power_units, 4687 (1.0 + (((msr >> 22) & 0x3) / 4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 4688 (((msr >> 16) & 1) ? "EN" : "DIS")); 4689 4690 return; 4691 } 4692 4693 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4694 { 4695 unsigned long long msr; 4696 const char *msr_name; 4697 int cpu; 4698 4699 if (!do_rapl) 4700 return 0; 4701 4702 /* RAPL counters are per package, so print only for 1st thread/package */ 4703 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4704 return 0; 4705 4706 cpu = t->cpu_id; 4707 if (cpu_migrate(cpu)) { 4708 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu); 4709 return -1; 4710 } 4711 4712 if (do_rapl & RAPL_AMD_F17H) { 4713 msr_name = "MSR_RAPL_PWR_UNIT"; 4714 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr)) 4715 return -1; 4716 } else { 4717 msr_name = "MSR_RAPL_POWER_UNIT"; 4718 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 4719 return -1; 4720 } 4721 4722 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr, 4723 rapl_power_units, rapl_energy_units, rapl_time_units); 4724 4725 if (do_rapl & RAPL_PKG_POWER_INFO) { 4726 4727 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 4728 return -5; 4729 4730 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4731 cpu, msr, 4732 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4733 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4734 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4735 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4736 4737 } 4738 if (do_rapl & RAPL_PKG) { 4739 4740 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 4741 return -9; 4742 4743 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 4744 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 4745 4746 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 4747 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 4748 cpu, 4749 ((msr >> 47) & 1) ? "EN" : "DIS", 4750 ((msr >> 32) & 0x7FFF) * rapl_power_units, 4751 (1.0 + (((msr >> 54) & 0x3) / 4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 4752 ((msr >> 48) & 1) ? "EN" : "DIS"); 4753 } 4754 4755 if (do_rapl & RAPL_DRAM_POWER_INFO) { 4756 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 4757 return -6; 4758 4759 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4760 cpu, msr, 4761 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4762 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4763 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4764 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4765 } 4766 if (do_rapl & RAPL_DRAM) { 4767 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 4768 return -9; 4769 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 4770 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4771 4772 print_power_limit_msr(cpu, msr, "DRAM Limit"); 4773 } 4774 if (do_rapl & RAPL_CORE_POLICY) { 4775 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 4776 return -7; 4777 4778 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 4779 } 4780 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 4781 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 4782 return -9; 4783 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 4784 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4785 print_power_limit_msr(cpu, msr, "Cores Limit"); 4786 } 4787 if (do_rapl & RAPL_GFX) { 4788 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 4789 return -8; 4790 4791 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 4792 4793 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 4794 return -9; 4795 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 4796 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4797 print_power_limit_msr(cpu, msr, "GFX Limit"); 4798 } 4799 return 0; 4800 } 4801 4802 /* 4803 * SNB adds support for additional MSRs: 4804 * 4805 * MSR_PKG_C7_RESIDENCY 0x000003fa 4806 * MSR_CORE_C7_RESIDENCY 0x000003fe 4807 * MSR_PKG_C2_RESIDENCY 0x0000060d 4808 */ 4809 4810 int has_snb_msrs(unsigned int family, unsigned int model) 4811 { 4812 if (!genuine_intel) 4813 return 0; 4814 4815 switch (model) { 4816 case INTEL_FAM6_SANDYBRIDGE: 4817 case INTEL_FAM6_SANDYBRIDGE_X: 4818 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 4819 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 4820 case INTEL_FAM6_HASWELL: /* HSW */ 4821 case INTEL_FAM6_HASWELL_X: /* HSW */ 4822 case INTEL_FAM6_HASWELL_L: /* HSW */ 4823 case INTEL_FAM6_HASWELL_G: /* HSW */ 4824 case INTEL_FAM6_BROADWELL: /* BDW */ 4825 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4826 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4827 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4828 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4829 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4830 case INTEL_FAM6_ICELAKE_X: /* ICX */ 4831 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4832 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4833 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 4834 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4835 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 4836 return 1; 4837 } 4838 return 0; 4839 } 4840 4841 /* 4842 * HSW ULT added support for C8/C9/C10 MSRs: 4843 * 4844 * MSR_PKG_C8_RESIDENCY 0x00000630 4845 * MSR_PKG_C9_RESIDENCY 0x00000631 4846 * MSR_PKG_C10_RESIDENCY 0x00000632 4847 * 4848 * MSR_PKGC8_IRTL 0x00000633 4849 * MSR_PKGC9_IRTL 0x00000634 4850 * MSR_PKGC10_IRTL 0x00000635 4851 * 4852 */ 4853 int has_c8910_msrs(unsigned int family, unsigned int model) 4854 { 4855 if (!genuine_intel) 4856 return 0; 4857 4858 switch (model) { 4859 case INTEL_FAM6_HASWELL_L: /* HSW */ 4860 case INTEL_FAM6_BROADWELL: /* BDW */ 4861 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4862 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4863 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4864 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4865 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4866 return 1; 4867 } 4868 return 0; 4869 } 4870 4871 /* 4872 * SKL adds support for additional MSRS: 4873 * 4874 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 4875 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 4876 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 4877 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 4878 */ 4879 int has_skl_msrs(unsigned int family, unsigned int model) 4880 { 4881 if (!genuine_intel) 4882 return 0; 4883 4884 switch (model) { 4885 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4886 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4887 return 1; 4888 } 4889 return 0; 4890 } 4891 4892 int is_slm(unsigned int family, unsigned int model) 4893 { 4894 if (!genuine_intel) 4895 return 0; 4896 switch (model) { 4897 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4898 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 4899 return 1; 4900 } 4901 return 0; 4902 } 4903 4904 int is_knl(unsigned int family, unsigned int model) 4905 { 4906 if (!genuine_intel) 4907 return 0; 4908 switch (model) { 4909 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4910 return 1; 4911 } 4912 return 0; 4913 } 4914 4915 int is_cnl(unsigned int family, unsigned int model) 4916 { 4917 if (!genuine_intel) 4918 return 0; 4919 4920 switch (model) { 4921 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4922 return 1; 4923 } 4924 4925 return 0; 4926 } 4927 4928 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 4929 { 4930 if (is_knl(family, model)) 4931 return 1024; 4932 return 1; 4933 } 4934 4935 #define SLM_BCLK_FREQS 5 4936 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0 }; 4937 4938 double slm_bclk(void) 4939 { 4940 unsigned long long msr = 3; 4941 unsigned int i; 4942 double freq; 4943 4944 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 4945 fprintf(outf, "SLM BCLK: unknown\n"); 4946 4947 i = msr & 0xf; 4948 if (i >= SLM_BCLK_FREQS) { 4949 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 4950 i = 3; 4951 } 4952 freq = slm_freq_table[i]; 4953 4954 if (!quiet) 4955 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 4956 4957 return freq; 4958 } 4959 4960 double discover_bclk(unsigned int family, unsigned int model) 4961 { 4962 if (has_snb_msrs(family, model) || is_knl(family, model)) 4963 return 100.00; 4964 else if (is_slm(family, model)) 4965 return slm_bclk(); 4966 else 4967 return 133.33; 4968 } 4969 4970 int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4971 { 4972 unsigned int eax, ebx, ecx, edx; 4973 4974 if (!genuine_intel) 4975 return 0; 4976 4977 if (cpu_migrate(t->cpu_id)) { 4978 fprintf(outf, "Could not migrate to CPU %d\n", t->cpu_id); 4979 return -1; 4980 } 4981 4982 if (max_level < 0x1a) 4983 return 0; 4984 4985 __cpuid(0x1a, eax, ebx, ecx, edx); 4986 eax = (eax >> 24) & 0xFF; 4987 if (eax == 0x20) 4988 t->is_atom = true; 4989 return 0; 4990 } 4991 4992 /* 4993 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 4994 * the Thermal Control Circuit (TCC) activates. 4995 * This is usually equal to tjMax. 4996 * 4997 * Older processors do not have this MSR, so there we guess, 4998 * but also allow cmdline over-ride with -T. 4999 * 5000 * Several MSR temperature values are in units of degrees-C 5001 * below this value, including the Digital Thermal Sensor (DTS), 5002 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 5003 */ 5004 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 5005 { 5006 unsigned long long msr; 5007 unsigned int tcc_default, tcc_offset; 5008 int cpu; 5009 5010 /* tj_max is used only for dts or ptm */ 5011 if (!(do_dts || do_ptm)) 5012 return 0; 5013 5014 /* this is a per-package concept */ 5015 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 5016 return 0; 5017 5018 cpu = t->cpu_id; 5019 if (cpu_migrate(cpu)) { 5020 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 5021 return -1; 5022 } 5023 5024 if (tj_max_override != 0) { 5025 tj_max = tj_max_override; 5026 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", cpu, tj_max); 5027 return 0; 5028 } 5029 5030 /* Temperature Target MSR is Nehalem and newer only */ 5031 if (!do_nhm_platform_info) 5032 goto guess; 5033 5034 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 5035 goto guess; 5036 5037 tcc_default = (msr >> 16) & 0xFF; 5038 5039 if (!quiet) { 5040 switch (tcc_offset_bits) { 5041 case 4: 5042 tcc_offset = (msr >> 24) & 0xF; 5043 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n", 5044 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset); 5045 break; 5046 case 6: 5047 tcc_offset = (msr >> 24) & 0x3F; 5048 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n", 5049 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset); 5050 break; 5051 default: 5052 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", cpu, msr, tcc_default); 5053 break; 5054 } 5055 } 5056 5057 if (!tcc_default) 5058 goto guess; 5059 5060 tj_max = tcc_default; 5061 5062 return 0; 5063 5064 guess: 5065 tj_max = TJMAX_DEFAULT; 5066 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", cpu, tj_max); 5067 5068 return 0; 5069 } 5070 5071 void decode_feature_control_msr(void) 5072 { 5073 unsigned long long msr; 5074 5075 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr)) 5076 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 5077 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : ""); 5078 } 5079 5080 void decode_misc_enable_msr(void) 5081 { 5082 unsigned long long msr; 5083 5084 if (!genuine_intel) 5085 return; 5086 5087 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 5088 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 5089 base_cpu, msr, 5090 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 5091 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 5092 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 5093 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 5094 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 5095 } 5096 5097 void decode_misc_feature_control(void) 5098 { 5099 unsigned long long msr; 5100 5101 if (!has_misc_feature_control) 5102 return; 5103 5104 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 5105 fprintf(outf, 5106 "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 5107 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "", 5108 msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : ""); 5109 } 5110 5111 /* 5112 * Decode MSR_MISC_PWR_MGMT 5113 * 5114 * Decode the bits according to the Nehalem documentation 5115 * bit[0] seems to continue to have same meaning going forward 5116 * bit[1] less so... 5117 */ 5118 void decode_misc_pwr_mgmt_msr(void) 5119 { 5120 unsigned long long msr; 5121 5122 if (!do_nhm_platform_info) 5123 return; 5124 5125 if (no_MSR_MISC_PWR_MGMT) 5126 return; 5127 5128 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 5129 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 5130 base_cpu, msr, 5131 msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS"); 5132 } 5133 5134 /* 5135 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 5136 * 5137 * This MSRs are present on Silvermont processors, 5138 * Intel Atom processor E3000 series (Baytrail), and friends. 5139 */ 5140 void decode_c6_demotion_policy_msr(void) 5141 { 5142 unsigned long long msr; 5143 5144 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 5145 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 5146 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 5147 5148 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 5149 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 5150 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 5151 } 5152 5153 /* 5154 * When models are the same, for the purpose of turbostat, reuse 5155 */ 5156 unsigned int intel_model_duplicates(unsigned int model) 5157 { 5158 5159 switch (model) { 5160 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 5161 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 5162 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 5163 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 5164 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 5165 return INTEL_FAM6_NEHALEM; 5166 5167 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 5168 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 5169 return INTEL_FAM6_NEHALEM_EX; 5170 5171 case INTEL_FAM6_XEON_PHI_KNM: 5172 return INTEL_FAM6_XEON_PHI_KNL; 5173 5174 case INTEL_FAM6_BROADWELL_X: 5175 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */ 5176 return INTEL_FAM6_BROADWELL_X; 5177 5178 case INTEL_FAM6_SKYLAKE_L: 5179 case INTEL_FAM6_SKYLAKE: 5180 case INTEL_FAM6_KABYLAKE_L: 5181 case INTEL_FAM6_KABYLAKE: 5182 case INTEL_FAM6_COMETLAKE_L: 5183 case INTEL_FAM6_COMETLAKE: 5184 return INTEL_FAM6_SKYLAKE_L; 5185 5186 case INTEL_FAM6_ICELAKE_L: 5187 case INTEL_FAM6_ICELAKE_NNPI: 5188 case INTEL_FAM6_TIGERLAKE_L: 5189 case INTEL_FAM6_TIGERLAKE: 5190 case INTEL_FAM6_ROCKETLAKE: 5191 case INTEL_FAM6_LAKEFIELD: 5192 case INTEL_FAM6_ALDERLAKE: 5193 case INTEL_FAM6_ALDERLAKE_L: 5194 return INTEL_FAM6_CANNONLAKE_L; 5195 5196 case INTEL_FAM6_ATOM_TREMONT_L: 5197 return INTEL_FAM6_ATOM_TREMONT; 5198 5199 case INTEL_FAM6_ICELAKE_D: 5200 case INTEL_FAM6_SAPPHIRERAPIDS_X: 5201 return INTEL_FAM6_ICELAKE_X; 5202 } 5203 return model; 5204 } 5205 5206 void print_dev_latency(void) 5207 { 5208 char *path = "/dev/cpu_dma_latency"; 5209 int fd; 5210 int value; 5211 int retval; 5212 5213 fd = open(path, O_RDONLY); 5214 if (fd < 0) { 5215 warn("fopen %s\n", path); 5216 return; 5217 } 5218 5219 retval = read(fd, (void *)&value, sizeof(int)); 5220 if (retval != sizeof(int)) { 5221 warn("read %s\n", path); 5222 close(fd); 5223 return; 5224 } 5225 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", value, value == 2000000000 ? "default" : "constrained"); 5226 5227 close(fd); 5228 } 5229 5230 /* 5231 * Linux-perf manages the the HW instructions-retired counter 5232 * by enabling when requested, and hiding rollover 5233 */ 5234 void linux_perf_init(void) 5235 { 5236 if (!BIC_IS_ENABLED(BIC_IPC)) 5237 return; 5238 5239 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK)) 5240 return; 5241 5242 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5243 if (fd_instr_count_percpu == NULL) 5244 err(-1, "calloc fd_instr_count_percpu"); 5245 5246 BIC_PRESENT(BIC_IPC); 5247 } 5248 5249 void process_cpuid() 5250 { 5251 unsigned int eax, ebx, ecx, edx; 5252 unsigned int fms, family, model, stepping, ecx_flags, edx_flags; 5253 unsigned int has_turbo; 5254 unsigned long long ucode_patch = 0; 5255 5256 eax = ebx = ecx = edx = 0; 5257 5258 __cpuid(0, max_level, ebx, ecx, edx); 5259 5260 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) 5261 genuine_intel = 1; 5262 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) 5263 authentic_amd = 1; 5264 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e) 5265 hygon_genuine = 1; 5266 5267 if (!quiet) 5268 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n", 5269 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level); 5270 5271 __cpuid(1, fms, ebx, ecx, edx); 5272 family = (fms >> 8) & 0xf; 5273 model = (fms >> 4) & 0xf; 5274 stepping = fms & 0xf; 5275 if (family == 0xf) 5276 family += (fms >> 20) & 0xff; 5277 if (family >= 6) 5278 model += ((fms >> 16) & 0xf) << 4; 5279 ecx_flags = ecx; 5280 edx_flags = edx; 5281 5282 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch)) 5283 warnx("get_msr(UCODE)\n"); 5284 5285 /* 5286 * check max extended function levels of CPUID. 5287 * This is needed to check for invariant TSC. 5288 * This check is valid for both Intel and AMD. 5289 */ 5290 ebx = ecx = edx = 0; 5291 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 5292 5293 if (!quiet) { 5294 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d) microcode 0x%x\n", 5295 family, model, stepping, family, model, stepping, 5296 (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF)); 5297 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level); 5298 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 5299 ecx_flags & (1 << 0) ? "SSE3" : "-", 5300 ecx_flags & (1 << 3) ? "MONITOR" : "-", 5301 ecx_flags & (1 << 6) ? "SMX" : "-", 5302 ecx_flags & (1 << 7) ? "EIST" : "-", 5303 ecx_flags & (1 << 8) ? "TM2" : "-", 5304 edx_flags & (1 << 4) ? "TSC" : "-", 5305 edx_flags & (1 << 5) ? "MSR" : "-", 5306 edx_flags & (1 << 22) ? "ACPI-TM" : "-", 5307 edx_flags & (1 << 28) ? "HT" : "-", edx_flags & (1 << 29) ? "TM" : "-"); 5308 } 5309 if (genuine_intel) { 5310 model_orig = model; 5311 model = intel_model_duplicates(model); 5312 } 5313 5314 if (!(edx_flags & (1 << 5))) 5315 errx(1, "CPUID: no MSR"); 5316 5317 if (max_extended_level >= 0x80000007) { 5318 5319 /* 5320 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 5321 * this check is valid for both Intel and AMD 5322 */ 5323 __cpuid(0x80000007, eax, ebx, ecx, edx); 5324 has_invariant_tsc = edx & (1 << 8); 5325 } 5326 5327 /* 5328 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 5329 * this check is valid for both Intel and AMD 5330 */ 5331 5332 __cpuid(0x6, eax, ebx, ecx, edx); 5333 has_aperf = ecx & (1 << 0); 5334 if (has_aperf) { 5335 BIC_PRESENT(BIC_Avg_MHz); 5336 BIC_PRESENT(BIC_Busy); 5337 BIC_PRESENT(BIC_Bzy_MHz); 5338 } 5339 do_dts = eax & (1 << 0); 5340 if (do_dts) 5341 BIC_PRESENT(BIC_CoreTmp); 5342 has_turbo = eax & (1 << 1); 5343 do_ptm = eax & (1 << 6); 5344 if (do_ptm) 5345 BIC_PRESENT(BIC_PkgTmp); 5346 has_hwp = eax & (1 << 7); 5347 has_hwp_notify = eax & (1 << 8); 5348 has_hwp_activity_window = eax & (1 << 9); 5349 has_hwp_epp = eax & (1 << 10); 5350 has_hwp_pkg = eax & (1 << 11); 5351 has_epb = ecx & (1 << 3); 5352 5353 if (!quiet) 5354 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 5355 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 5356 has_aperf ? "" : "No-", 5357 has_turbo ? "" : "No-", 5358 do_dts ? "" : "No-", 5359 do_ptm ? "" : "No-", 5360 has_hwp ? "" : "No-", 5361 has_hwp_notify ? "" : "No-", 5362 has_hwp_activity_window ? "" : "No-", 5363 has_hwp_epp ? "" : "No-", has_hwp_pkg ? "" : "No-", has_epb ? "" : "No-"); 5364 5365 if (!quiet) 5366 decode_misc_enable_msr(); 5367 5368 if (max_level >= 0x7 && !quiet) { 5369 int has_sgx; 5370 5371 ecx = 0; 5372 5373 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 5374 5375 has_sgx = ebx & (1 << 2); 5376 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 5377 5378 if (has_sgx) 5379 decode_feature_control_msr(); 5380 } 5381 5382 if (max_level >= 0x15) { 5383 unsigned int eax_crystal; 5384 unsigned int ebx_tsc; 5385 5386 /* 5387 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 5388 */ 5389 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 5390 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 5391 5392 if (ebx_tsc != 0) { 5393 5394 if (!quiet && (ebx != 0)) 5395 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 5396 eax_crystal, ebx_tsc, crystal_hz); 5397 5398 if (crystal_hz == 0) 5399 switch (model) { 5400 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5401 crystal_hz = 24000000; /* 24.0 MHz */ 5402 break; 5403 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 5404 crystal_hz = 25000000; /* 25.0 MHz */ 5405 break; 5406 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 5407 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5408 crystal_hz = 19200000; /* 19.2 MHz */ 5409 break; 5410 default: 5411 crystal_hz = 0; 5412 } 5413 5414 if (crystal_hz) { 5415 tsc_hz = (unsigned long long)crystal_hz *ebx_tsc / eax_crystal; 5416 if (!quiet) 5417 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 5418 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 5419 } 5420 } 5421 } 5422 if (max_level >= 0x16) { 5423 unsigned int base_mhz, max_mhz, bus_mhz, edx; 5424 5425 /* 5426 * CPUID 16H Base MHz, Max MHz, Bus MHz 5427 */ 5428 base_mhz = max_mhz = bus_mhz = edx = 0; 5429 5430 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 5431 if (!quiet) 5432 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 5433 base_mhz, max_mhz, bus_mhz); 5434 } 5435 5436 if (has_aperf) 5437 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 5438 5439 BIC_PRESENT(BIC_IRQ); 5440 BIC_PRESENT(BIC_TSC_MHz); 5441 5442 if (probe_nhm_msrs(family, model)) { 5443 do_nhm_platform_info = 1; 5444 BIC_PRESENT(BIC_CPU_c1); 5445 BIC_PRESENT(BIC_CPU_c3); 5446 BIC_PRESENT(BIC_CPU_c6); 5447 BIC_PRESENT(BIC_SMI); 5448 } 5449 do_snb_cstates = has_snb_msrs(family, model); 5450 5451 if (do_snb_cstates) 5452 BIC_PRESENT(BIC_CPU_c7); 5453 5454 do_irtl_snb = has_snb_msrs(family, model); 5455 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 5456 BIC_PRESENT(BIC_Pkgpc2); 5457 if (pkg_cstate_limit >= PCL__3) 5458 BIC_PRESENT(BIC_Pkgpc3); 5459 if (pkg_cstate_limit >= PCL__6) 5460 BIC_PRESENT(BIC_Pkgpc6); 5461 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 5462 BIC_PRESENT(BIC_Pkgpc7); 5463 if (has_slv_msrs(family, model)) { 5464 BIC_NOT_PRESENT(BIC_Pkgpc2); 5465 BIC_NOT_PRESENT(BIC_Pkgpc3); 5466 BIC_PRESENT(BIC_Pkgpc6); 5467 BIC_NOT_PRESENT(BIC_Pkgpc7); 5468 BIC_PRESENT(BIC_Mod_c6); 5469 use_c1_residency_msr = 1; 5470 } 5471 if (is_jvl(family, model)) { 5472 BIC_NOT_PRESENT(BIC_CPU_c3); 5473 BIC_NOT_PRESENT(BIC_CPU_c7); 5474 BIC_NOT_PRESENT(BIC_Pkgpc2); 5475 BIC_NOT_PRESENT(BIC_Pkgpc3); 5476 BIC_NOT_PRESENT(BIC_Pkgpc6); 5477 BIC_NOT_PRESENT(BIC_Pkgpc7); 5478 } 5479 if (is_dnv(family, model)) { 5480 BIC_PRESENT(BIC_CPU_c1); 5481 BIC_NOT_PRESENT(BIC_CPU_c3); 5482 BIC_NOT_PRESENT(BIC_Pkgpc3); 5483 BIC_NOT_PRESENT(BIC_CPU_c7); 5484 BIC_NOT_PRESENT(BIC_Pkgpc7); 5485 use_c1_residency_msr = 1; 5486 } 5487 if (is_skx(family, model) || is_icx(family, model)) { 5488 BIC_NOT_PRESENT(BIC_CPU_c3); 5489 BIC_NOT_PRESENT(BIC_Pkgpc3); 5490 BIC_NOT_PRESENT(BIC_CPU_c7); 5491 BIC_NOT_PRESENT(BIC_Pkgpc7); 5492 } 5493 if (is_bdx(family, model)) { 5494 BIC_NOT_PRESENT(BIC_CPU_c7); 5495 BIC_NOT_PRESENT(BIC_Pkgpc7); 5496 } 5497 if (has_c8910_msrs(family, model)) { 5498 if (pkg_cstate_limit >= PCL__8) 5499 BIC_PRESENT(BIC_Pkgpc8); 5500 if (pkg_cstate_limit >= PCL__9) 5501 BIC_PRESENT(BIC_Pkgpc9); 5502 if (pkg_cstate_limit >= PCL_10) 5503 BIC_PRESENT(BIC_Pkgpc10); 5504 } 5505 do_irtl_hsw = has_c8910_msrs(family, model); 5506 if (has_skl_msrs(family, model)) { 5507 BIC_PRESENT(BIC_Totl_c0); 5508 BIC_PRESENT(BIC_Any_c0); 5509 BIC_PRESENT(BIC_GFX_c0); 5510 BIC_PRESENT(BIC_CPUGFX); 5511 } 5512 do_slm_cstates = is_slm(family, model); 5513 do_knl_cstates = is_knl(family, model); 5514 5515 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || is_ehl(family, model)) 5516 BIC_NOT_PRESENT(BIC_CPU_c3); 5517 5518 if (!quiet) 5519 decode_misc_pwr_mgmt_msr(); 5520 5521 if (!quiet && has_slv_msrs(family, model)) 5522 decode_c6_demotion_policy_msr(); 5523 5524 rapl_probe(family, model); 5525 perf_limit_reasons_probe(family, model); 5526 automatic_cstate_conversion_probe(family, model); 5527 5528 check_tcc_offset(model_orig); 5529 5530 if (!quiet) 5531 dump_cstate_pstate_config_info(family, model); 5532 5533 if (!quiet) 5534 print_dev_latency(); 5535 if (!quiet) 5536 dump_sysfs_cstate_config(); 5537 if (!quiet) 5538 dump_sysfs_pstate_config(); 5539 5540 if (has_skl_msrs(family, model) || is_ehl(family, model)) 5541 calculate_tsc_tweak(); 5542 5543 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 5544 BIC_PRESENT(BIC_GFX_rc6); 5545 5546 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 5547 BIC_PRESENT(BIC_GFXMHz); 5548 5549 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK)) 5550 BIC_PRESENT(BIC_GFXACTMHz); 5551 5552 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 5553 BIC_PRESENT(BIC_CPU_LPI); 5554 else 5555 BIC_NOT_PRESENT(BIC_CPU_LPI); 5556 5557 if (!access(sys_lpi_file_sysfs, R_OK)) { 5558 sys_lpi_file = sys_lpi_file_sysfs; 5559 BIC_PRESENT(BIC_SYS_LPI); 5560 } else if (!access(sys_lpi_file_debugfs, R_OK)) { 5561 sys_lpi_file = sys_lpi_file_debugfs; 5562 BIC_PRESENT(BIC_SYS_LPI); 5563 } else { 5564 sys_lpi_file_sysfs = NULL; 5565 BIC_NOT_PRESENT(BIC_SYS_LPI); 5566 } 5567 5568 if (!quiet) 5569 decode_misc_feature_control(); 5570 5571 return; 5572 } 5573 5574 /* 5575 * in /dev/cpu/ return success for names that are numbers 5576 * ie. filter out ".", "..", "microcode". 5577 */ 5578 int dir_filter(const struct dirent *dirp) 5579 { 5580 if (isdigit(dirp->d_name[0])) 5581 return 1; 5582 else 5583 return 0; 5584 } 5585 5586 int open_dev_cpu_msr(int dummy1) 5587 { 5588 return 0; 5589 } 5590 5591 void topology_probe() 5592 { 5593 int i; 5594 int max_core_id = 0; 5595 int max_package_id = 0; 5596 int max_die_id = 0; 5597 int max_siblings = 0; 5598 5599 /* Initialize num_cpus, max_cpu_num */ 5600 set_max_cpu_num(); 5601 topo.num_cpus = 0; 5602 for_all_proc_cpus(count_cpus); 5603 if (!summary_only && topo.num_cpus > 1) 5604 BIC_PRESENT(BIC_CPU); 5605 5606 if (debug > 1) 5607 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 5608 5609 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 5610 if (cpus == NULL) 5611 err(1, "calloc cpus"); 5612 5613 /* 5614 * Allocate and initialize cpu_present_set 5615 */ 5616 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5617 if (cpu_present_set == NULL) 5618 err(3, "CPU_ALLOC"); 5619 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5620 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 5621 for_all_proc_cpus(mark_cpu_present); 5622 5623 /* 5624 * Validate that all cpus in cpu_subset are also in cpu_present_set 5625 */ 5626 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 5627 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 5628 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) 5629 err(1, "cpu%d not present", i); 5630 } 5631 5632 /* 5633 * Allocate and initialize cpu_affinity_set 5634 */ 5635 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5636 if (cpu_affinity_set == NULL) 5637 err(3, "CPU_ALLOC"); 5638 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5639 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 5640 5641 for_all_proc_cpus(init_thread_id); 5642 5643 /* 5644 * For online cpus 5645 * find max_core_id, max_package_id 5646 */ 5647 for (i = 0; i <= topo.max_cpu_num; ++i) { 5648 int siblings; 5649 5650 if (cpu_is_not_present(i)) { 5651 if (debug > 1) 5652 fprintf(outf, "cpu%d NOT PRESENT\n", i); 5653 continue; 5654 } 5655 5656 cpus[i].logical_cpu_id = i; 5657 5658 /* get package information */ 5659 cpus[i].physical_package_id = get_physical_package_id(i); 5660 if (cpus[i].physical_package_id > max_package_id) 5661 max_package_id = cpus[i].physical_package_id; 5662 5663 /* get die information */ 5664 cpus[i].die_id = get_die_id(i); 5665 if (cpus[i].die_id > max_die_id) 5666 max_die_id = cpus[i].die_id; 5667 5668 /* get numa node information */ 5669 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 5670 if (cpus[i].physical_node_id > topo.max_node_num) 5671 topo.max_node_num = cpus[i].physical_node_id; 5672 5673 /* get core information */ 5674 cpus[i].physical_core_id = get_core_id(i); 5675 if (cpus[i].physical_core_id > max_core_id) 5676 max_core_id = cpus[i].physical_core_id; 5677 5678 /* get thread information */ 5679 siblings = get_thread_siblings(&cpus[i]); 5680 if (siblings > max_siblings) 5681 max_siblings = siblings; 5682 if (cpus[i].thread_id == 0) 5683 topo.num_cores++; 5684 } 5685 5686 topo.cores_per_node = max_core_id + 1; 5687 if (debug > 1) 5688 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", max_core_id, topo.cores_per_node); 5689 if (!summary_only && topo.cores_per_node > 1) 5690 BIC_PRESENT(BIC_Core); 5691 5692 topo.num_die = max_die_id + 1; 5693 if (debug > 1) 5694 fprintf(outf, "max_die_id %d, sizing for %d die\n", max_die_id, topo.num_die); 5695 if (!summary_only && topo.num_die > 1) 5696 BIC_PRESENT(BIC_Die); 5697 5698 topo.num_packages = max_package_id + 1; 5699 if (debug > 1) 5700 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages); 5701 if (!summary_only && topo.num_packages > 1) 5702 BIC_PRESENT(BIC_Package); 5703 5704 set_node_data(); 5705 if (debug > 1) 5706 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 5707 if (!summary_only && topo.nodes_per_pkg > 1) 5708 BIC_PRESENT(BIC_Node); 5709 5710 topo.threads_per_core = max_siblings; 5711 if (debug > 1) 5712 fprintf(outf, "max_siblings %d\n", max_siblings); 5713 5714 if (debug < 1) 5715 return; 5716 5717 for (i = 0; i <= topo.max_cpu_num; ++i) { 5718 if (cpu_is_not_present(i)) 5719 continue; 5720 fprintf(outf, 5721 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n", 5722 i, cpus[i].physical_package_id, cpus[i].die_id, 5723 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id); 5724 } 5725 5726 } 5727 5728 void allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) 5729 { 5730 int i; 5731 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * topo.num_packages; 5732 int num_threads = topo.threads_per_core * num_cores; 5733 5734 *t = calloc(num_threads, sizeof(struct thread_data)); 5735 if (*t == NULL) 5736 goto error; 5737 5738 for (i = 0; i < num_threads; i++) 5739 (*t)[i].cpu_id = -1; 5740 5741 *c = calloc(num_cores, sizeof(struct core_data)); 5742 if (*c == NULL) 5743 goto error; 5744 5745 for (i = 0; i < num_cores; i++) 5746 (*c)[i].core_id = -1; 5747 5748 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 5749 if (*p == NULL) 5750 goto error; 5751 5752 for (i = 0; i < topo.num_packages; i++) 5753 (*p)[i].package_id = i; 5754 5755 return; 5756 error: 5757 err(1, "calloc counters"); 5758 } 5759 5760 /* 5761 * init_counter() 5762 * 5763 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 5764 */ 5765 void init_counter(struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base, int cpu_id) 5766 { 5767 int pkg_id = cpus[cpu_id].physical_package_id; 5768 int node_id = cpus[cpu_id].logical_node_id; 5769 int core_id = cpus[cpu_id].physical_core_id; 5770 int thread_id = cpus[cpu_id].thread_id; 5771 struct thread_data *t; 5772 struct core_data *c; 5773 struct pkg_data *p; 5774 5775 /* Workaround for systems where physical_node_id==-1 5776 * and logical_node_id==(-1 - topo.num_cpus) 5777 */ 5778 if (node_id < 0) 5779 node_id = 0; 5780 5781 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 5782 c = GET_CORE(core_base, core_id, node_id, pkg_id); 5783 p = GET_PKG(pkg_base, pkg_id); 5784 5785 t->cpu_id = cpu_id; 5786 if (thread_id == 0) { 5787 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 5788 if (cpu_is_first_core_in_package(cpu_id)) 5789 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 5790 } 5791 5792 c->core_id = core_id; 5793 p->package_id = pkg_id; 5794 } 5795 5796 int initialize_counters(int cpu_id) 5797 { 5798 init_counter(EVEN_COUNTERS, cpu_id); 5799 init_counter(ODD_COUNTERS, cpu_id); 5800 return 0; 5801 } 5802 5803 void allocate_output_buffer() 5804 { 5805 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048); 5806 outp = output_buffer; 5807 if (outp == NULL) 5808 err(-1, "calloc output buffer"); 5809 } 5810 5811 void allocate_fd_percpu(void) 5812 { 5813 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5814 if (fd_percpu == NULL) 5815 err(-1, "calloc fd_percpu"); 5816 } 5817 5818 void allocate_irq_buffers(void) 5819 { 5820 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 5821 if (irq_column_2_cpu == NULL) 5822 err(-1, "calloc %d", topo.num_cpus); 5823 5824 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5825 if (irqs_per_cpu == NULL) 5826 err(-1, "calloc %d", topo.max_cpu_num + 1); 5827 } 5828 5829 void setup_all_buffers(void) 5830 { 5831 topology_probe(); 5832 allocate_irq_buffers(); 5833 allocate_fd_percpu(); 5834 allocate_counters(&thread_even, &core_even, &package_even); 5835 allocate_counters(&thread_odd, &core_odd, &package_odd); 5836 allocate_output_buffer(); 5837 for_all_proc_cpus(initialize_counters); 5838 } 5839 5840 void set_base_cpu(void) 5841 { 5842 base_cpu = sched_getcpu(); 5843 if (base_cpu < 0) 5844 err(-ENODEV, "No valid cpus found"); 5845 5846 if (debug > 1) 5847 fprintf(outf, "base_cpu = %d\n", base_cpu); 5848 } 5849 5850 void turbostat_init() 5851 { 5852 setup_all_buffers(); 5853 set_base_cpu(); 5854 check_dev_msr(); 5855 check_permissions(); 5856 process_cpuid(); 5857 linux_perf_init(); 5858 5859 if (!quiet) 5860 for_all_cpus(print_hwp, ODD_COUNTERS); 5861 5862 if (!quiet) 5863 for_all_cpus(print_epb, ODD_COUNTERS); 5864 5865 if (!quiet) 5866 for_all_cpus(print_perf_limit, ODD_COUNTERS); 5867 5868 if (!quiet) 5869 for_all_cpus(print_rapl, ODD_COUNTERS); 5870 5871 for_all_cpus(set_temperature_target, ODD_COUNTERS); 5872 5873 for_all_cpus(get_cpu_type, ODD_COUNTERS); 5874 for_all_cpus(get_cpu_type, EVEN_COUNTERS); 5875 5876 if (!quiet) 5877 for_all_cpus(print_thermal, ODD_COUNTERS); 5878 5879 if (!quiet && do_irtl_snb) 5880 print_irtl(); 5881 } 5882 5883 int fork_it(char **argv) 5884 { 5885 pid_t child_pid; 5886 int status; 5887 5888 snapshot_proc_sysfs_files(); 5889 status = for_all_cpus(get_counters, EVEN_COUNTERS); 5890 first_counter_read = 0; 5891 if (status) 5892 exit(status); 5893 /* clear affinity side-effect of get_counters() */ 5894 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 5895 gettimeofday(&tv_even, (struct timezone *)NULL); 5896 5897 child_pid = fork(); 5898 if (!child_pid) { 5899 /* child */ 5900 execvp(argv[0], argv); 5901 err(errno, "exec %s", argv[0]); 5902 } else { 5903 5904 /* parent */ 5905 if (child_pid == -1) 5906 err(1, "fork"); 5907 5908 signal(SIGINT, SIG_IGN); 5909 signal(SIGQUIT, SIG_IGN); 5910 if (waitpid(child_pid, &status, 0) == -1) 5911 err(status, "waitpid"); 5912 5913 if (WIFEXITED(status)) 5914 status = WEXITSTATUS(status); 5915 } 5916 /* 5917 * n.b. fork_it() does not check for errors from for_all_cpus() 5918 * because re-starting is problematic when forking 5919 */ 5920 snapshot_proc_sysfs_files(); 5921 for_all_cpus(get_counters, ODD_COUNTERS); 5922 gettimeofday(&tv_odd, (struct timezone *)NULL); 5923 timersub(&tv_odd, &tv_even, &tv_delta); 5924 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 5925 fprintf(outf, "%s: Counter reset detected\n", progname); 5926 else { 5927 compute_average(EVEN_COUNTERS); 5928 format_all_counters(EVEN_COUNTERS); 5929 } 5930 5931 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec / 1000000.0); 5932 5933 flush_output_stderr(); 5934 5935 return status; 5936 } 5937 5938 int get_and_dump_counters(void) 5939 { 5940 int status; 5941 5942 snapshot_proc_sysfs_files(); 5943 status = for_all_cpus(get_counters, ODD_COUNTERS); 5944 if (status) 5945 return status; 5946 5947 status = for_all_cpus(dump_counters, ODD_COUNTERS); 5948 if (status) 5949 return status; 5950 5951 flush_output_stdout(); 5952 5953 return status; 5954 } 5955 5956 void print_version() 5957 { 5958 fprintf(outf, "turbostat version 21.03.12" " - Len Brown <lenb@kernel.org>\n"); 5959 } 5960 5961 int add_counter(unsigned int msr_num, char *path, char *name, 5962 unsigned int width, enum counter_scope scope, 5963 enum counter_type type, enum counter_format format, int flags) 5964 { 5965 struct msr_counter *msrp; 5966 5967 msrp = calloc(1, sizeof(struct msr_counter)); 5968 if (msrp == NULL) { 5969 perror("calloc"); 5970 exit(1); 5971 } 5972 5973 msrp->msr_num = msr_num; 5974 strncpy(msrp->name, name, NAME_BYTES - 1); 5975 if (path) 5976 strncpy(msrp->path, path, PATH_BYTES - 1); 5977 msrp->width = width; 5978 msrp->type = type; 5979 msrp->format = format; 5980 msrp->flags = flags; 5981 5982 switch (scope) { 5983 5984 case SCOPE_CPU: 5985 msrp->next = sys.tp; 5986 sys.tp = msrp; 5987 sys.added_thread_counters++; 5988 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 5989 fprintf(stderr, "exceeded max %d added thread counters\n", MAX_ADDED_COUNTERS); 5990 exit(-1); 5991 } 5992 break; 5993 5994 case SCOPE_CORE: 5995 msrp->next = sys.cp; 5996 sys.cp = msrp; 5997 sys.added_core_counters++; 5998 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 5999 fprintf(stderr, "exceeded max %d added core counters\n", MAX_ADDED_COUNTERS); 6000 exit(-1); 6001 } 6002 break; 6003 6004 case SCOPE_PACKAGE: 6005 msrp->next = sys.pp; 6006 sys.pp = msrp; 6007 sys.added_package_counters++; 6008 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 6009 fprintf(stderr, "exceeded max %d added package counters\n", MAX_ADDED_COUNTERS); 6010 exit(-1); 6011 } 6012 break; 6013 } 6014 6015 return 0; 6016 } 6017 6018 void parse_add_command(char *add_command) 6019 { 6020 int msr_num = 0; 6021 char *path = NULL; 6022 char name_buffer[NAME_BYTES] = ""; 6023 int width = 64; 6024 int fail = 0; 6025 enum counter_scope scope = SCOPE_CPU; 6026 enum counter_type type = COUNTER_CYCLES; 6027 enum counter_format format = FORMAT_DELTA; 6028 6029 while (add_command) { 6030 6031 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 6032 goto next; 6033 6034 if (sscanf(add_command, "msr%d", &msr_num) == 1) 6035 goto next; 6036 6037 if (*add_command == '/') { 6038 path = add_command; 6039 goto next; 6040 } 6041 6042 if (sscanf(add_command, "u%d", &width) == 1) { 6043 if ((width == 32) || (width == 64)) 6044 goto next; 6045 width = 64; 6046 } 6047 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 6048 scope = SCOPE_CPU; 6049 goto next; 6050 } 6051 if (!strncmp(add_command, "core", strlen("core"))) { 6052 scope = SCOPE_CORE; 6053 goto next; 6054 } 6055 if (!strncmp(add_command, "package", strlen("package"))) { 6056 scope = SCOPE_PACKAGE; 6057 goto next; 6058 } 6059 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 6060 type = COUNTER_CYCLES; 6061 goto next; 6062 } 6063 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 6064 type = COUNTER_SECONDS; 6065 goto next; 6066 } 6067 if (!strncmp(add_command, "usec", strlen("usec"))) { 6068 type = COUNTER_USEC; 6069 goto next; 6070 } 6071 if (!strncmp(add_command, "raw", strlen("raw"))) { 6072 format = FORMAT_RAW; 6073 goto next; 6074 } 6075 if (!strncmp(add_command, "delta", strlen("delta"))) { 6076 format = FORMAT_DELTA; 6077 goto next; 6078 } 6079 if (!strncmp(add_command, "percent", strlen("percent"))) { 6080 format = FORMAT_PERCENT; 6081 goto next; 6082 } 6083 6084 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 6085 char *eos; 6086 6087 eos = strchr(name_buffer, ','); 6088 if (eos) 6089 *eos = '\0'; 6090 goto next; 6091 } 6092 6093 next: 6094 add_command = strchr(add_command, ','); 6095 if (add_command) { 6096 *add_command = '\0'; 6097 add_command++; 6098 } 6099 6100 } 6101 if ((msr_num == 0) && (path == NULL)) { 6102 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 6103 fail++; 6104 } 6105 6106 /* generate default column header */ 6107 if (*name_buffer == '\0') { 6108 if (width == 32) 6109 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 6110 else 6111 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 6112 } 6113 6114 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 6115 fail++; 6116 6117 if (fail) { 6118 help(); 6119 exit(1); 6120 } 6121 } 6122 6123 int is_deferred_skip(char *name) 6124 { 6125 int i; 6126 6127 for (i = 0; i < deferred_skip_index; ++i) 6128 if (!strcmp(name, deferred_skip_names[i])) 6129 return 1; 6130 return 0; 6131 } 6132 6133 void probe_sysfs(void) 6134 { 6135 char path[64]; 6136 char name_buf[16]; 6137 FILE *input; 6138 int state; 6139 char *sp; 6140 6141 if (!DO_BIC(BIC_sysfs)) 6142 return; 6143 6144 for (state = 10; state >= 0; --state) { 6145 6146 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 6147 input = fopen(path, "r"); 6148 if (input == NULL) 6149 continue; 6150 if (!fgets(name_buf, sizeof(name_buf), input)) 6151 err(1, "%s: failed to read file", path); 6152 6153 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 6154 sp = strchr(name_buf, '-'); 6155 if (!sp) 6156 sp = strchrnul(name_buf, '\n'); 6157 *sp = '%'; 6158 *(sp + 1) = '\0'; 6159 6160 remove_underbar(name_buf); 6161 6162 fclose(input); 6163 6164 sprintf(path, "cpuidle/state%d/time", state); 6165 6166 if (is_deferred_skip(name_buf)) 6167 continue; 6168 6169 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, FORMAT_PERCENT, SYSFS_PERCPU); 6170 } 6171 6172 for (state = 10; state >= 0; --state) { 6173 6174 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state); 6175 input = fopen(path, "r"); 6176 if (input == NULL) 6177 continue; 6178 if (!fgets(name_buf, sizeof(name_buf), input)) 6179 err(1, "%s: failed to read file", path); 6180 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 6181 sp = strchr(name_buf, '-'); 6182 if (!sp) 6183 sp = strchrnul(name_buf, '\n'); 6184 *sp = '\0'; 6185 fclose(input); 6186 6187 remove_underbar(name_buf); 6188 6189 sprintf(path, "cpuidle/state%d/usage", state); 6190 6191 if (is_deferred_skip(name_buf)) 6192 continue; 6193 6194 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, FORMAT_DELTA, SYSFS_PERCPU); 6195 } 6196 6197 } 6198 6199 /* 6200 * parse cpuset with following syntax 6201 * 1,2,4..6,8-10 and set bits in cpu_subset 6202 */ 6203 void parse_cpu_command(char *optarg) 6204 { 6205 unsigned int start, end; 6206 char *next; 6207 6208 if (!strcmp(optarg, "core")) { 6209 if (cpu_subset) 6210 goto error; 6211 show_core_only++; 6212 return; 6213 } 6214 if (!strcmp(optarg, "package")) { 6215 if (cpu_subset) 6216 goto error; 6217 show_pkg_only++; 6218 return; 6219 } 6220 if (show_core_only || show_pkg_only) 6221 goto error; 6222 6223 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 6224 if (cpu_subset == NULL) 6225 err(3, "CPU_ALLOC"); 6226 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 6227 6228 CPU_ZERO_S(cpu_subset_size, cpu_subset); 6229 6230 next = optarg; 6231 6232 while (next && *next) { 6233 6234 if (*next == '-') /* no negative cpu numbers */ 6235 goto error; 6236 6237 start = strtoul(next, &next, 10); 6238 6239 if (start >= CPU_SUBSET_MAXCPUS) 6240 goto error; 6241 CPU_SET_S(start, cpu_subset_size, cpu_subset); 6242 6243 if (*next == '\0') 6244 break; 6245 6246 if (*next == ',') { 6247 next += 1; 6248 continue; 6249 } 6250 6251 if (*next == '-') { 6252 next += 1; /* start range */ 6253 } else if (*next == '.') { 6254 next += 1; 6255 if (*next == '.') 6256 next += 1; /* start range */ 6257 else 6258 goto error; 6259 } 6260 6261 end = strtoul(next, &next, 10); 6262 if (end <= start) 6263 goto error; 6264 6265 while (++start <= end) { 6266 if (start >= CPU_SUBSET_MAXCPUS) 6267 goto error; 6268 CPU_SET_S(start, cpu_subset_size, cpu_subset); 6269 } 6270 6271 if (*next == ',') 6272 next += 1; 6273 else if (*next != '\0') 6274 goto error; 6275 } 6276 6277 return; 6278 6279 error: 6280 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 6281 help(); 6282 exit(-1); 6283 } 6284 6285 void cmdline(int argc, char **argv) 6286 { 6287 int opt; 6288 int option_index = 0; 6289 static struct option long_options[] = { 6290 { "add", required_argument, 0, 'a' }, 6291 { "cpu", required_argument, 0, 'c' }, 6292 { "Dump", no_argument, 0, 'D' }, 6293 { "debug", no_argument, 0, 'd' }, /* internal, not documented */ 6294 { "enable", required_argument, 0, 'e' }, 6295 { "interval", required_argument, 0, 'i' }, 6296 { "IPC", no_argument, 0, 'I' }, 6297 { "num_iterations", required_argument, 0, 'n' }, 6298 { "help", no_argument, 0, 'h' }, 6299 { "hide", required_argument, 0, 'H' }, // meh, -h taken by --help 6300 { "Joules", no_argument, 0, 'J' }, 6301 { "list", no_argument, 0, 'l' }, 6302 { "out", required_argument, 0, 'o' }, 6303 { "quiet", no_argument, 0, 'q' }, 6304 { "show", required_argument, 0, 's' }, 6305 { "Summary", no_argument, 0, 'S' }, 6306 { "TCC", required_argument, 0, 'T' }, 6307 { "version", no_argument, 0, 'v' }, 6308 { 0, 0, 0, 0 } 6309 }; 6310 6311 progname = argv[0]; 6312 6313 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", long_options, &option_index)) != -1) { 6314 switch (opt) { 6315 case 'a': 6316 parse_add_command(optarg); 6317 break; 6318 case 'c': 6319 parse_cpu_command(optarg); 6320 break; 6321 case 'D': 6322 dump_only++; 6323 break; 6324 case 'e': 6325 /* --enable specified counter */ 6326 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 6327 break; 6328 case 'd': 6329 debug++; 6330 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6331 break; 6332 case 'H': 6333 /* 6334 * --hide: do not show those specified 6335 * multiple invocations simply clear more bits in enabled mask 6336 */ 6337 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 6338 break; 6339 case 'h': 6340 default: 6341 help(); 6342 exit(1); 6343 case 'i': 6344 { 6345 double interval = strtod(optarg, NULL); 6346 6347 if (interval < 0.001) { 6348 fprintf(outf, "interval %f seconds is too small\n", interval); 6349 exit(2); 6350 } 6351 6352 interval_tv.tv_sec = interval_ts.tv_sec = interval; 6353 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 6354 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 6355 } 6356 break; 6357 case 'J': 6358 rapl_joules++; 6359 break; 6360 case 'l': 6361 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6362 list_header_only++; 6363 quiet++; 6364 break; 6365 case 'o': 6366 outf = fopen_or_die(optarg, "w"); 6367 break; 6368 case 'q': 6369 quiet = 1; 6370 break; 6371 case 'n': 6372 num_iterations = strtod(optarg, NULL); 6373 6374 if (num_iterations <= 0) { 6375 fprintf(outf, "iterations %d should be positive number\n", num_iterations); 6376 exit(2); 6377 } 6378 break; 6379 case 's': 6380 /* 6381 * --show: show only those specified 6382 * The 1st invocation will clear and replace the enabled mask 6383 * subsequent invocations can add to it. 6384 */ 6385 if (shown == 0) 6386 bic_enabled = bic_lookup(optarg, SHOW_LIST); 6387 else 6388 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 6389 shown = 1; 6390 break; 6391 case 'S': 6392 summary_only++; 6393 break; 6394 case 'T': 6395 tj_max_override = atoi(optarg); 6396 break; 6397 case 'v': 6398 print_version(); 6399 exit(0); 6400 break; 6401 } 6402 } 6403 } 6404 6405 int main(int argc, char **argv) 6406 { 6407 outf = stderr; 6408 cmdline(argc, argv); 6409 6410 if (!quiet) 6411 print_version(); 6412 6413 probe_sysfs(); 6414 6415 turbostat_init(); 6416 6417 /* dump counters and exit */ 6418 if (dump_only) 6419 return get_and_dump_counters(); 6420 6421 /* list header and exit */ 6422 if (list_header_only) { 6423 print_header(","); 6424 flush_output_stdout(); 6425 return 0; 6426 } 6427 6428 msr_sum_record(); 6429 /* 6430 * if any params left, it must be a command to fork 6431 */ 6432 if (argc - optind) 6433 return fork_it(argv + optind); 6434 else 6435 turbostat_loop(); 6436 6437 return 0; 6438 } 6439