1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * turbostat -- show CPU frequency and C-state residency 4 * on modern Intel and AMD processors. 5 * 6 * Copyright (c) 2013 Intel Corporation. 7 * Len Brown <len.brown@intel.com> 8 */ 9 10 #define _GNU_SOURCE 11 #include MSRHEADER 12 #include INTEL_FAMILY_HEADER 13 #include <stdarg.h> 14 #include <stdio.h> 15 #include <err.h> 16 #include <unistd.h> 17 #include <sys/types.h> 18 #include <sys/wait.h> 19 #include <sys/stat.h> 20 #include <sys/select.h> 21 #include <sys/resource.h> 22 #include <fcntl.h> 23 #include <signal.h> 24 #include <sys/time.h> 25 #include <stdlib.h> 26 #include <getopt.h> 27 #include <dirent.h> 28 #include <string.h> 29 #include <ctype.h> 30 #include <sched.h> 31 #include <time.h> 32 #include <cpuid.h> 33 #include <sys/capability.h> 34 #include <errno.h> 35 #include <math.h> 36 37 char *proc_stat = "/proc/stat"; 38 FILE *outf; 39 int *fd_percpu; 40 struct timeval interval_tv = {5, 0}; 41 struct timespec interval_ts = {5, 0}; 42 unsigned int num_iterations; 43 unsigned int debug; 44 unsigned int quiet; 45 unsigned int shown; 46 unsigned int sums_need_wide_columns; 47 unsigned int rapl_joules; 48 unsigned int summary_only; 49 unsigned int list_header_only; 50 unsigned int dump_only; 51 unsigned int do_snb_cstates; 52 unsigned int do_knl_cstates; 53 unsigned int do_slm_cstates; 54 unsigned int use_c1_residency_msr; 55 unsigned int has_aperf; 56 unsigned int has_epb; 57 unsigned int do_irtl_snb; 58 unsigned int do_irtl_hsw; 59 unsigned int units = 1000000; /* MHz etc */ 60 unsigned int genuine_intel; 61 unsigned int authentic_amd; 62 unsigned int hygon_genuine; 63 unsigned int max_level, max_extended_level; 64 unsigned int has_invariant_tsc; 65 unsigned int do_nhm_platform_info; 66 unsigned int no_MSR_MISC_PWR_MGMT; 67 unsigned int aperf_mperf_multiplier = 1; 68 double bclk; 69 double base_hz; 70 unsigned int has_base_hz; 71 double tsc_tweak = 1.0; 72 unsigned int show_pkg_only; 73 unsigned int show_core_only; 74 char *output_buffer, *outp; 75 unsigned int do_rapl; 76 unsigned int do_dts; 77 unsigned int do_ptm; 78 unsigned long long gfx_cur_rc6_ms; 79 unsigned long long cpuidle_cur_cpu_lpi_us; 80 unsigned long long cpuidle_cur_sys_lpi_us; 81 unsigned int gfx_cur_mhz; 82 unsigned int gfx_act_mhz; 83 unsigned int tcc_activation_temp; 84 unsigned int tcc_activation_temp_override; 85 double rapl_power_units, rapl_time_units; 86 double rapl_dram_energy_units, rapl_energy_units; 87 double rapl_joule_counter_range; 88 unsigned int do_core_perf_limit_reasons; 89 unsigned int has_automatic_cstate_conversion; 90 unsigned int do_gfx_perf_limit_reasons; 91 unsigned int do_ring_perf_limit_reasons; 92 unsigned int crystal_hz; 93 unsigned long long tsc_hz; 94 int base_cpu; 95 double discover_bclk(unsigned int family, unsigned int model); 96 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 97 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 98 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 99 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 100 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 101 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 102 unsigned int has_misc_feature_control; 103 unsigned int first_counter_read = 1; 104 int ignore_stdin; 105 106 #define RAPL_PKG (1 << 0) 107 /* 0x610 MSR_PKG_POWER_LIMIT */ 108 /* 0x611 MSR_PKG_ENERGY_STATUS */ 109 #define RAPL_PKG_PERF_STATUS (1 << 1) 110 /* 0x613 MSR_PKG_PERF_STATUS */ 111 #define RAPL_PKG_POWER_INFO (1 << 2) 112 /* 0x614 MSR_PKG_POWER_INFO */ 113 114 #define RAPL_DRAM (1 << 3) 115 /* 0x618 MSR_DRAM_POWER_LIMIT */ 116 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 117 #define RAPL_DRAM_PERF_STATUS (1 << 4) 118 /* 0x61b MSR_DRAM_PERF_STATUS */ 119 #define RAPL_DRAM_POWER_INFO (1 << 5) 120 /* 0x61c MSR_DRAM_POWER_INFO */ 121 122 #define RAPL_CORES_POWER_LIMIT (1 << 6) 123 /* 0x638 MSR_PP0_POWER_LIMIT */ 124 #define RAPL_CORE_POLICY (1 << 7) 125 /* 0x63a MSR_PP0_POLICY */ 126 127 #define RAPL_GFX (1 << 8) 128 /* 0x640 MSR_PP1_POWER_LIMIT */ 129 /* 0x641 MSR_PP1_ENERGY_STATUS */ 130 /* 0x642 MSR_PP1_POLICY */ 131 132 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 133 /* 0x639 MSR_PP0_ENERGY_STATUS */ 134 #define RAPL_PER_CORE_ENERGY (1 << 10) 135 /* Indicates cores energy collection is per-core, 136 * not per-package. */ 137 #define RAPL_AMD_F17H (1 << 11) 138 /* 0xc0010299 MSR_RAPL_PWR_UNIT */ 139 /* 0xc001029a MSR_CORE_ENERGY_STAT */ 140 /* 0xc001029b MSR_PKG_ENERGY_STAT */ 141 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 142 #define TJMAX_DEFAULT 100 143 144 /* MSRs that are not yet in the kernel-provided header. */ 145 #define MSR_RAPL_PWR_UNIT 0xc0010299 146 #define MSR_CORE_ENERGY_STAT 0xc001029a 147 #define MSR_PKG_ENERGY_STAT 0xc001029b 148 149 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 150 151 /* 152 * buffer size used by sscanf() for added column names 153 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 154 */ 155 #define NAME_BYTES 20 156 #define PATH_BYTES 128 157 158 int backwards_count; 159 char *progname; 160 161 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 162 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset; 163 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size; 164 #define MAX_ADDED_COUNTERS 8 165 #define MAX_ADDED_THREAD_COUNTERS 24 166 #define BITMASK_SIZE 32 167 168 struct thread_data { 169 struct timeval tv_begin; 170 struct timeval tv_end; 171 struct timeval tv_delta; 172 unsigned long long tsc; 173 unsigned long long aperf; 174 unsigned long long mperf; 175 unsigned long long c1; 176 unsigned long long irq_count; 177 unsigned int smi_count; 178 unsigned int cpu_id; 179 unsigned int apic_id; 180 unsigned int x2apic_id; 181 unsigned int flags; 182 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 183 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 184 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 185 } *thread_even, *thread_odd; 186 187 struct core_data { 188 unsigned long long c3; 189 unsigned long long c6; 190 unsigned long long c7; 191 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 192 unsigned int core_temp_c; 193 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */ 194 unsigned int core_id; 195 unsigned long long counter[MAX_ADDED_COUNTERS]; 196 } *core_even, *core_odd; 197 198 struct pkg_data { 199 unsigned long long pc2; 200 unsigned long long pc3; 201 unsigned long long pc6; 202 unsigned long long pc7; 203 unsigned long long pc8; 204 unsigned long long pc9; 205 unsigned long long pc10; 206 unsigned long long cpu_lpi; 207 unsigned long long sys_lpi; 208 unsigned long long pkg_wtd_core_c0; 209 unsigned long long pkg_any_core_c0; 210 unsigned long long pkg_any_gfxe_c0; 211 unsigned long long pkg_both_core_gfxe_c0; 212 long long gfx_rc6_ms; 213 unsigned int gfx_mhz; 214 unsigned int gfx_act_mhz; 215 unsigned int package_id; 216 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 217 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 218 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */ 219 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 220 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 221 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 222 unsigned int pkg_temp_c; 223 unsigned long long counter[MAX_ADDED_COUNTERS]; 224 } *package_even, *package_odd; 225 226 #define ODD_COUNTERS thread_odd, core_odd, package_odd 227 #define EVEN_COUNTERS thread_even, core_even, package_even 228 229 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 230 ((thread_base) + \ 231 ((pkg_no) * \ 232 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 233 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 234 ((core_no) * topo.threads_per_core) + \ 235 (thread_no)) 236 237 #define GET_CORE(core_base, core_no, node_no, pkg_no) \ 238 ((core_base) + \ 239 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 240 ((node_no) * topo.cores_per_node) + \ 241 (core_no)) 242 243 244 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 245 246 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; 247 enum counter_type {COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC}; 248 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; 249 250 struct msr_counter { 251 unsigned int msr_num; 252 char name[NAME_BYTES]; 253 char path[PATH_BYTES]; 254 unsigned int width; 255 enum counter_type type; 256 enum counter_format format; 257 struct msr_counter *next; 258 unsigned int flags; 259 #define FLAGS_HIDE (1 << 0) 260 #define FLAGS_SHOW (1 << 1) 261 #define SYSFS_PERCPU (1 << 1) 262 }; 263 264 /* 265 * The accumulated sum of MSR is defined as a monotonic 266 * increasing MSR, it will be accumulated periodically, 267 * despite its register's bit width. 268 */ 269 enum { 270 IDX_PKG_ENERGY, 271 IDX_DRAM_ENERGY, 272 IDX_PP0_ENERGY, 273 IDX_PP1_ENERGY, 274 IDX_PKG_PERF, 275 IDX_DRAM_PERF, 276 IDX_COUNT, 277 }; 278 279 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr); 280 281 struct msr_sum_array { 282 /* get_msr_sum() = sum + (get_msr() - last) */ 283 struct { 284 /*The accumulated MSR value is updated by the timer*/ 285 unsigned long long sum; 286 /*The MSR footprint recorded in last timer*/ 287 unsigned long long last; 288 } entries[IDX_COUNT]; 289 }; 290 291 /* The percpu MSR sum array.*/ 292 struct msr_sum_array *per_cpu_msr_sum; 293 294 int idx_to_offset(int idx) 295 { 296 int offset; 297 298 switch (idx) { 299 case IDX_PKG_ENERGY: 300 offset = MSR_PKG_ENERGY_STATUS; 301 break; 302 case IDX_DRAM_ENERGY: 303 offset = MSR_DRAM_ENERGY_STATUS; 304 break; 305 case IDX_PP0_ENERGY: 306 offset = MSR_PP0_ENERGY_STATUS; 307 break; 308 case IDX_PP1_ENERGY: 309 offset = MSR_PP1_ENERGY_STATUS; 310 break; 311 case IDX_PKG_PERF: 312 offset = MSR_PKG_PERF_STATUS; 313 break; 314 case IDX_DRAM_PERF: 315 offset = MSR_DRAM_PERF_STATUS; 316 break; 317 default: 318 offset = -1; 319 } 320 return offset; 321 } 322 323 int offset_to_idx(int offset) 324 { 325 int idx; 326 327 switch (offset) { 328 case MSR_PKG_ENERGY_STATUS: 329 idx = IDX_PKG_ENERGY; 330 break; 331 case MSR_DRAM_ENERGY_STATUS: 332 idx = IDX_DRAM_ENERGY; 333 break; 334 case MSR_PP0_ENERGY_STATUS: 335 idx = IDX_PP0_ENERGY; 336 break; 337 case MSR_PP1_ENERGY_STATUS: 338 idx = IDX_PP1_ENERGY; 339 break; 340 case MSR_PKG_PERF_STATUS: 341 idx = IDX_PKG_PERF; 342 break; 343 case MSR_DRAM_PERF_STATUS: 344 idx = IDX_DRAM_PERF; 345 break; 346 default: 347 idx = -1; 348 } 349 return idx; 350 } 351 352 int idx_valid(int idx) 353 { 354 switch (idx) { 355 case IDX_PKG_ENERGY: 356 return do_rapl & RAPL_PKG; 357 case IDX_DRAM_ENERGY: 358 return do_rapl & RAPL_DRAM; 359 case IDX_PP0_ENERGY: 360 return do_rapl & RAPL_CORES_ENERGY_STATUS; 361 case IDX_PP1_ENERGY: 362 return do_rapl & RAPL_GFX; 363 case IDX_PKG_PERF: 364 return do_rapl & RAPL_PKG_PERF_STATUS; 365 case IDX_DRAM_PERF: 366 return do_rapl & RAPL_DRAM_PERF_STATUS; 367 default: 368 return 0; 369 } 370 } 371 struct sys_counters { 372 unsigned int added_thread_counters; 373 unsigned int added_core_counters; 374 unsigned int added_package_counters; 375 struct msr_counter *tp; 376 struct msr_counter *cp; 377 struct msr_counter *pp; 378 } sys; 379 380 struct system_summary { 381 struct thread_data threads; 382 struct core_data cores; 383 struct pkg_data packages; 384 } average; 385 386 struct cpu_topology { 387 int physical_package_id; 388 int die_id; 389 int logical_cpu_id; 390 int physical_node_id; 391 int logical_node_id; /* 0-based count within the package */ 392 int physical_core_id; 393 int thread_id; 394 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 395 } *cpus; 396 397 struct topo_params { 398 int num_packages; 399 int num_die; 400 int num_cpus; 401 int num_cores; 402 int max_cpu_num; 403 int max_node_num; 404 int nodes_per_pkg; 405 int cores_per_node; 406 int threads_per_core; 407 } topo; 408 409 struct timeval tv_even, tv_odd, tv_delta; 410 411 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 412 int *irqs_per_cpu; /* indexed by cpu_num */ 413 414 void setup_all_buffers(void); 415 416 char *sys_lpi_file; 417 char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us"; 418 char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec"; 419 420 int cpu_is_not_present(int cpu) 421 { 422 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 423 } 424 /* 425 * run func(thread, core, package) in topology order 426 * skip non-present cpus 427 */ 428 429 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 430 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 431 { 432 int retval, pkg_no, core_no, thread_no, node_no; 433 434 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 435 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) { 436 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 437 for (thread_no = 0; thread_no < 438 topo.threads_per_core; ++thread_no) { 439 struct thread_data *t; 440 struct core_data *c; 441 struct pkg_data *p; 442 443 t = GET_THREAD(thread_base, thread_no, 444 core_no, node_no, 445 pkg_no); 446 447 if (cpu_is_not_present(t->cpu_id)) 448 continue; 449 450 c = GET_CORE(core_base, core_no, 451 node_no, pkg_no); 452 p = GET_PKG(pkg_base, pkg_no); 453 454 retval = func(t, c, p); 455 if (retval) 456 return retval; 457 } 458 } 459 } 460 } 461 return 0; 462 } 463 464 int cpu_migrate(int cpu) 465 { 466 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 467 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 468 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 469 return -1; 470 else 471 return 0; 472 } 473 int get_msr_fd(int cpu) 474 { 475 char pathname[32]; 476 int fd; 477 478 fd = fd_percpu[cpu]; 479 480 if (fd) 481 return fd; 482 483 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 484 fd = open(pathname, O_RDONLY); 485 if (fd < 0) 486 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 487 488 fd_percpu[cpu] = fd; 489 490 return fd; 491 } 492 493 int get_msr(int cpu, off_t offset, unsigned long long *msr) 494 { 495 ssize_t retval; 496 497 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 498 499 if (retval != sizeof *msr) 500 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 501 502 return 0; 503 } 504 505 /* 506 * This list matches the column headers, except 507 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 508 * 2. Core and CPU are moved to the end, we can't have strings that contain them 509 * matching on them for --show and --hide. 510 */ 511 struct msr_counter bic[] = { 512 { 0x0, "usec" }, 513 { 0x0, "Time_Of_Day_Seconds" }, 514 { 0x0, "Package" }, 515 { 0x0, "Node" }, 516 { 0x0, "Avg_MHz" }, 517 { 0x0, "Busy%" }, 518 { 0x0, "Bzy_MHz" }, 519 { 0x0, "TSC_MHz" }, 520 { 0x0, "IRQ" }, 521 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL}, 522 { 0x0, "sysfs" }, 523 { 0x0, "CPU%c1" }, 524 { 0x0, "CPU%c3" }, 525 { 0x0, "CPU%c6" }, 526 { 0x0, "CPU%c7" }, 527 { 0x0, "ThreadC" }, 528 { 0x0, "CoreTmp" }, 529 { 0x0, "CoreCnt" }, 530 { 0x0, "PkgTmp" }, 531 { 0x0, "GFX%rc6" }, 532 { 0x0, "GFXMHz" }, 533 { 0x0, "Pkg%pc2" }, 534 { 0x0, "Pkg%pc3" }, 535 { 0x0, "Pkg%pc6" }, 536 { 0x0, "Pkg%pc7" }, 537 { 0x0, "Pkg%pc8" }, 538 { 0x0, "Pkg%pc9" }, 539 { 0x0, "Pk%pc10" }, 540 { 0x0, "CPU%LPI" }, 541 { 0x0, "SYS%LPI" }, 542 { 0x0, "PkgWatt" }, 543 { 0x0, "CorWatt" }, 544 { 0x0, "GFXWatt" }, 545 { 0x0, "PkgCnt" }, 546 { 0x0, "RAMWatt" }, 547 { 0x0, "PKG_%" }, 548 { 0x0, "RAM_%" }, 549 { 0x0, "Pkg_J" }, 550 { 0x0, "Cor_J" }, 551 { 0x0, "GFX_J" }, 552 { 0x0, "RAM_J" }, 553 { 0x0, "Mod%c6" }, 554 { 0x0, "Totl%C0" }, 555 { 0x0, "Any%C0" }, 556 { 0x0, "GFX%C0" }, 557 { 0x0, "CPUGFX%" }, 558 { 0x0, "Core" }, 559 { 0x0, "CPU" }, 560 { 0x0, "APIC" }, 561 { 0x0, "X2APIC" }, 562 { 0x0, "Die" }, 563 { 0x0, "GFXAMHz" }, 564 }; 565 566 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 567 #define BIC_USEC (1ULL << 0) 568 #define BIC_TOD (1ULL << 1) 569 #define BIC_Package (1ULL << 2) 570 #define BIC_Node (1ULL << 3) 571 #define BIC_Avg_MHz (1ULL << 4) 572 #define BIC_Busy (1ULL << 5) 573 #define BIC_Bzy_MHz (1ULL << 6) 574 #define BIC_TSC_MHz (1ULL << 7) 575 #define BIC_IRQ (1ULL << 8) 576 #define BIC_SMI (1ULL << 9) 577 #define BIC_sysfs (1ULL << 10) 578 #define BIC_CPU_c1 (1ULL << 11) 579 #define BIC_CPU_c3 (1ULL << 12) 580 #define BIC_CPU_c6 (1ULL << 13) 581 #define BIC_CPU_c7 (1ULL << 14) 582 #define BIC_ThreadC (1ULL << 15) 583 #define BIC_CoreTmp (1ULL << 16) 584 #define BIC_CoreCnt (1ULL << 17) 585 #define BIC_PkgTmp (1ULL << 18) 586 #define BIC_GFX_rc6 (1ULL << 19) 587 #define BIC_GFXMHz (1ULL << 20) 588 #define BIC_Pkgpc2 (1ULL << 21) 589 #define BIC_Pkgpc3 (1ULL << 22) 590 #define BIC_Pkgpc6 (1ULL << 23) 591 #define BIC_Pkgpc7 (1ULL << 24) 592 #define BIC_Pkgpc8 (1ULL << 25) 593 #define BIC_Pkgpc9 (1ULL << 26) 594 #define BIC_Pkgpc10 (1ULL << 27) 595 #define BIC_CPU_LPI (1ULL << 28) 596 #define BIC_SYS_LPI (1ULL << 29) 597 #define BIC_PkgWatt (1ULL << 30) 598 #define BIC_CorWatt (1ULL << 31) 599 #define BIC_GFXWatt (1ULL << 32) 600 #define BIC_PkgCnt (1ULL << 33) 601 #define BIC_RAMWatt (1ULL << 34) 602 #define BIC_PKG__ (1ULL << 35) 603 #define BIC_RAM__ (1ULL << 36) 604 #define BIC_Pkg_J (1ULL << 37) 605 #define BIC_Cor_J (1ULL << 38) 606 #define BIC_GFX_J (1ULL << 39) 607 #define BIC_RAM_J (1ULL << 40) 608 #define BIC_Mod_c6 (1ULL << 41) 609 #define BIC_Totl_c0 (1ULL << 42) 610 #define BIC_Any_c0 (1ULL << 43) 611 #define BIC_GFX_c0 (1ULL << 44) 612 #define BIC_CPUGFX (1ULL << 45) 613 #define BIC_Core (1ULL << 46) 614 #define BIC_CPU (1ULL << 47) 615 #define BIC_APIC (1ULL << 48) 616 #define BIC_X2APIC (1ULL << 49) 617 #define BIC_Die (1ULL << 50) 618 #define BIC_GFXACTMHz (1ULL << 51) 619 620 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 621 622 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 623 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 624 625 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 626 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME) 627 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 628 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 629 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 630 631 632 #define MAX_DEFERRED 16 633 char *deferred_skip_names[MAX_DEFERRED]; 634 int deferred_skip_index; 635 636 /* 637 * HIDE_LIST - hide this list of counters, show the rest [default] 638 * SHOW_LIST - show this list of counters, hide the rest 639 */ 640 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 641 642 void help(void) 643 { 644 fprintf(outf, 645 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 646 "\n" 647 "Turbostat forks the specified COMMAND and prints statistics\n" 648 "when COMMAND completes.\n" 649 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 650 "to print statistics, until interrupted.\n" 651 " -a, --add add a counter\n" 652 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 653 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n" 654 " {core | package | j,k,l..m,n-p }\n" 655 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n" 656 " -D, --Dump displays the raw counter values\n" 657 " -e, --enable [all | column]\n" 658 " shows all or the specified disabled column\n" 659 " -H, --hide [column|column,column,...]\n" 660 " hide the specified column(s)\n" 661 " -i, --interval sec.subsec\n" 662 " Override default 5-second measurement interval\n" 663 " -J, --Joules displays energy in Joules instead of Watts\n" 664 " -l, --list list column headers only\n" 665 " -n, --num_iterations num\n" 666 " number of the measurement iterations\n" 667 " -o, --out file\n" 668 " create or truncate \"file\" for all output\n" 669 " -q, --quiet skip decoding system configuration header\n" 670 " -s, --show [column|column,column,...]\n" 671 " show only the specified column(s)\n" 672 " -S, --Summary\n" 673 " limits output to 1-line system summary per interval\n" 674 " -T, --TCC temperature\n" 675 " sets the Thermal Control Circuit temperature in\n" 676 " degrees Celsius\n" 677 " -h, --help print this help message\n" 678 " -v, --version print version information\n" 679 "\n" 680 "For more help, run \"man turbostat\"\n"); 681 } 682 683 /* 684 * bic_lookup 685 * for all the strings in comma separate name_list, 686 * set the approprate bit in return value. 687 */ 688 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 689 { 690 int i; 691 unsigned long long retval = 0; 692 693 while (name_list) { 694 char *comma; 695 696 comma = strchr(name_list, ','); 697 698 if (comma) 699 *comma = '\0'; 700 701 if (!strcmp(name_list, "all")) 702 return ~0; 703 704 for (i = 0; i < MAX_BIC; ++i) { 705 if (!strcmp(name_list, bic[i].name)) { 706 retval |= (1ULL << i); 707 break; 708 } 709 } 710 if (i == MAX_BIC) { 711 if (mode == SHOW_LIST) { 712 fprintf(stderr, "Invalid counter name: %s\n", name_list); 713 exit(-1); 714 } 715 deferred_skip_names[deferred_skip_index++] = name_list; 716 if (debug) 717 fprintf(stderr, "deferred \"%s\"\n", name_list); 718 if (deferred_skip_index >= MAX_DEFERRED) { 719 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 720 MAX_DEFERRED, name_list); 721 help(); 722 exit(1); 723 } 724 } 725 726 name_list = comma; 727 if (name_list) 728 name_list++; 729 730 } 731 return retval; 732 } 733 734 735 void print_header(char *delim) 736 { 737 struct msr_counter *mp; 738 int printed = 0; 739 740 if (DO_BIC(BIC_USEC)) 741 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 742 if (DO_BIC(BIC_TOD)) 743 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 744 if (DO_BIC(BIC_Package)) 745 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 746 if (DO_BIC(BIC_Die)) 747 outp += sprintf(outp, "%sDie", (printed++ ? delim : "")); 748 if (DO_BIC(BIC_Node)) 749 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 750 if (DO_BIC(BIC_Core)) 751 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 752 if (DO_BIC(BIC_CPU)) 753 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 754 if (DO_BIC(BIC_APIC)) 755 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 756 if (DO_BIC(BIC_X2APIC)) 757 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 758 if (DO_BIC(BIC_Avg_MHz)) 759 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 760 if (DO_BIC(BIC_Busy)) 761 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 762 if (DO_BIC(BIC_Bzy_MHz)) 763 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 764 if (DO_BIC(BIC_TSC_MHz)) 765 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 766 767 if (DO_BIC(BIC_IRQ)) { 768 if (sums_need_wide_columns) 769 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 770 else 771 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 772 } 773 774 if (DO_BIC(BIC_SMI)) 775 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 776 777 for (mp = sys.tp; mp; mp = mp->next) { 778 779 if (mp->format == FORMAT_RAW) { 780 if (mp->width == 64) 781 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 782 else 783 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 784 } else { 785 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 786 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 787 else 788 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 789 } 790 } 791 792 if (DO_BIC(BIC_CPU_c1)) 793 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 794 if (DO_BIC(BIC_CPU_c3)) 795 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 796 if (DO_BIC(BIC_CPU_c6)) 797 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 798 if (DO_BIC(BIC_CPU_c7)) 799 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 800 801 if (DO_BIC(BIC_Mod_c6)) 802 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 803 804 if (DO_BIC(BIC_CoreTmp)) 805 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 806 807 if (do_rapl && !rapl_joules) { 808 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 809 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 810 } else if (do_rapl && rapl_joules) { 811 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 812 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 813 } 814 815 for (mp = sys.cp; mp; mp = mp->next) { 816 if (mp->format == FORMAT_RAW) { 817 if (mp->width == 64) 818 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 819 else 820 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 821 } else { 822 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 823 outp += sprintf(outp, "%s%8s", delim, mp->name); 824 else 825 outp += sprintf(outp, "%s%s", delim, mp->name); 826 } 827 } 828 829 if (DO_BIC(BIC_PkgTmp)) 830 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 831 832 if (DO_BIC(BIC_GFX_rc6)) 833 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 834 835 if (DO_BIC(BIC_GFXMHz)) 836 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 837 838 if (DO_BIC(BIC_GFXACTMHz)) 839 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : "")); 840 841 if (DO_BIC(BIC_Totl_c0)) 842 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 843 if (DO_BIC(BIC_Any_c0)) 844 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 845 if (DO_BIC(BIC_GFX_c0)) 846 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 847 if (DO_BIC(BIC_CPUGFX)) 848 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 849 850 if (DO_BIC(BIC_Pkgpc2)) 851 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 852 if (DO_BIC(BIC_Pkgpc3)) 853 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 854 if (DO_BIC(BIC_Pkgpc6)) 855 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 856 if (DO_BIC(BIC_Pkgpc7)) 857 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 858 if (DO_BIC(BIC_Pkgpc8)) 859 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 860 if (DO_BIC(BIC_Pkgpc9)) 861 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 862 if (DO_BIC(BIC_Pkgpc10)) 863 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 864 if (DO_BIC(BIC_CPU_LPI)) 865 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 866 if (DO_BIC(BIC_SYS_LPI)) 867 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 868 869 if (do_rapl && !rapl_joules) { 870 if (DO_BIC(BIC_PkgWatt)) 871 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 872 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 873 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 874 if (DO_BIC(BIC_GFXWatt)) 875 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 876 if (DO_BIC(BIC_RAMWatt)) 877 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 878 if (DO_BIC(BIC_PKG__)) 879 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 880 if (DO_BIC(BIC_RAM__)) 881 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 882 } else if (do_rapl && rapl_joules) { 883 if (DO_BIC(BIC_Pkg_J)) 884 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 885 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 886 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 887 if (DO_BIC(BIC_GFX_J)) 888 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 889 if (DO_BIC(BIC_RAM_J)) 890 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 891 if (DO_BIC(BIC_PKG__)) 892 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 893 if (DO_BIC(BIC_RAM__)) 894 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 895 } 896 for (mp = sys.pp; mp; mp = mp->next) { 897 if (mp->format == FORMAT_RAW) { 898 if (mp->width == 64) 899 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 900 else 901 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 902 } else { 903 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 904 outp += sprintf(outp, "%s%8s", delim, mp->name); 905 else 906 outp += sprintf(outp, "%s%s", delim, mp->name); 907 } 908 } 909 910 outp += sprintf(outp, "\n"); 911 } 912 913 int dump_counters(struct thread_data *t, struct core_data *c, 914 struct pkg_data *p) 915 { 916 int i; 917 struct msr_counter *mp; 918 919 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 920 921 if (t) { 922 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 923 t->cpu_id, t->flags); 924 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 925 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 926 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 927 outp += sprintf(outp, "c1: %016llX\n", t->c1); 928 929 if (DO_BIC(BIC_IRQ)) 930 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 931 if (DO_BIC(BIC_SMI)) 932 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 933 934 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 935 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", 936 i, mp->msr_num, t->counter[i]); 937 } 938 } 939 940 if (c) { 941 outp += sprintf(outp, "core: %d\n", c->core_id); 942 outp += sprintf(outp, "c3: %016llX\n", c->c3); 943 outp += sprintf(outp, "c6: %016llX\n", c->c6); 944 outp += sprintf(outp, "c7: %016llX\n", c->c7); 945 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 946 outp += sprintf(outp, "Joules: %0X\n", c->core_energy); 947 948 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 949 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", 950 i, mp->msr_num, c->counter[i]); 951 } 952 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 953 } 954 955 if (p) { 956 outp += sprintf(outp, "package: %d\n", p->package_id); 957 958 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 959 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 960 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 961 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 962 963 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 964 if (DO_BIC(BIC_Pkgpc3)) 965 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 966 if (DO_BIC(BIC_Pkgpc6)) 967 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 968 if (DO_BIC(BIC_Pkgpc7)) 969 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 970 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 971 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 972 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 973 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 974 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 975 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg); 976 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores); 977 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx); 978 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram); 979 outp += sprintf(outp, "Throttle PKG: %0llX\n", 980 p->rapl_pkg_perf_status); 981 outp += sprintf(outp, "Throttle RAM: %0llX\n", 982 p->rapl_dram_perf_status); 983 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 984 985 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 986 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", 987 i, mp->msr_num, p->counter[i]); 988 } 989 } 990 991 outp += sprintf(outp, "\n"); 992 993 return 0; 994 } 995 996 /* 997 * column formatting convention & formats 998 */ 999 int format_counters(struct thread_data *t, struct core_data *c, 1000 struct pkg_data *p) 1001 { 1002 double interval_float, tsc; 1003 char *fmt8; 1004 int i; 1005 struct msr_counter *mp; 1006 char *delim = "\t"; 1007 int printed = 0; 1008 1009 /* if showing only 1st thread in core and this isn't one, bail out */ 1010 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1011 return 0; 1012 1013 /* if showing only 1st thread in pkg and this isn't one, bail out */ 1014 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1015 return 0; 1016 1017 /*if not summary line and --cpu is used */ 1018 if ((t != &average.threads) && 1019 (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 1020 return 0; 1021 1022 if (DO_BIC(BIC_USEC)) { 1023 /* on each row, print how many usec each timestamp took to gather */ 1024 struct timeval tv; 1025 1026 timersub(&t->tv_end, &t->tv_begin, &tv); 1027 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 1028 } 1029 1030 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 1031 if (DO_BIC(BIC_TOD)) 1032 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 1033 1034 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec/1000000.0; 1035 1036 tsc = t->tsc * tsc_tweak; 1037 1038 /* topo columns, print blanks on 1st (average) line */ 1039 if (t == &average.threads) { 1040 if (DO_BIC(BIC_Package)) 1041 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1042 if (DO_BIC(BIC_Die)) 1043 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1044 if (DO_BIC(BIC_Node)) 1045 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1046 if (DO_BIC(BIC_Core)) 1047 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1048 if (DO_BIC(BIC_CPU)) 1049 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1050 if (DO_BIC(BIC_APIC)) 1051 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1052 if (DO_BIC(BIC_X2APIC)) 1053 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1054 } else { 1055 if (DO_BIC(BIC_Package)) { 1056 if (p) 1057 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 1058 else 1059 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1060 } 1061 if (DO_BIC(BIC_Die)) { 1062 if (c) 1063 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id); 1064 else 1065 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1066 } 1067 if (DO_BIC(BIC_Node)) { 1068 if (t) 1069 outp += sprintf(outp, "%s%d", 1070 (printed++ ? delim : ""), 1071 cpus[t->cpu_id].physical_node_id); 1072 else 1073 outp += sprintf(outp, "%s-", 1074 (printed++ ? delim : "")); 1075 } 1076 if (DO_BIC(BIC_Core)) { 1077 if (c) 1078 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 1079 else 1080 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1081 } 1082 if (DO_BIC(BIC_CPU)) 1083 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 1084 if (DO_BIC(BIC_APIC)) 1085 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 1086 if (DO_BIC(BIC_X2APIC)) 1087 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 1088 } 1089 1090 if (DO_BIC(BIC_Avg_MHz)) 1091 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1092 1.0 / units * t->aperf / interval_float); 1093 1094 if (DO_BIC(BIC_Busy)) 1095 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf/tsc); 1096 1097 if (DO_BIC(BIC_Bzy_MHz)) { 1098 if (has_base_hz) 1099 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 1100 else 1101 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1102 tsc / units * t->aperf / t->mperf / interval_float); 1103 } 1104 1105 if (DO_BIC(BIC_TSC_MHz)) 1106 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc/units/interval_float); 1107 1108 /* IRQ */ 1109 if (DO_BIC(BIC_IRQ)) { 1110 if (sums_need_wide_columns) 1111 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 1112 else 1113 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 1114 } 1115 1116 /* SMI */ 1117 if (DO_BIC(BIC_SMI)) 1118 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 1119 1120 /* Added counters */ 1121 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1122 if (mp->format == FORMAT_RAW) { 1123 if (mp->width == 32) 1124 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) t->counter[i]); 1125 else 1126 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 1127 } else if (mp->format == FORMAT_DELTA) { 1128 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1129 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 1130 else 1131 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 1132 } else if (mp->format == FORMAT_PERCENT) { 1133 if (mp->type == COUNTER_USEC) 1134 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), t->counter[i]/interval_float/10000); 1135 else 1136 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i]/tsc); 1137 } 1138 } 1139 1140 /* C1 */ 1141 if (DO_BIC(BIC_CPU_c1)) 1142 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1/tsc); 1143 1144 1145 /* print per-core data only for 1st thread in core */ 1146 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1147 goto done; 1148 1149 if (DO_BIC(BIC_CPU_c3)) 1150 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3/tsc); 1151 if (DO_BIC(BIC_CPU_c6)) 1152 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6/tsc); 1153 if (DO_BIC(BIC_CPU_c7)) 1154 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7/tsc); 1155 1156 /* Mod%c6 */ 1157 if (DO_BIC(BIC_Mod_c6)) 1158 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 1159 1160 if (DO_BIC(BIC_CoreTmp)) 1161 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1162 1163 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1164 if (mp->format == FORMAT_RAW) { 1165 if (mp->width == 32) 1166 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) c->counter[i]); 1167 else 1168 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1169 } else if (mp->format == FORMAT_DELTA) { 1170 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1171 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1172 else 1173 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1174 } else if (mp->format == FORMAT_PERCENT) { 1175 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i]/tsc); 1176 } 1177 } 1178 1179 fmt8 = "%s%.2f"; 1180 1181 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1182 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float); 1183 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1184 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units); 1185 1186 /* print per-package data only for 1st core in package */ 1187 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1188 goto done; 1189 1190 /* PkgTmp */ 1191 if (DO_BIC(BIC_PkgTmp)) 1192 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1193 1194 /* GFXrc6 */ 1195 if (DO_BIC(BIC_GFX_rc6)) { 1196 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1197 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1198 } else { 1199 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1200 p->gfx_rc6_ms / 10.0 / interval_float); 1201 } 1202 } 1203 1204 /* GFXMHz */ 1205 if (DO_BIC(BIC_GFXMHz)) 1206 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1207 1208 /* GFXACTMHz */ 1209 if (DO_BIC(BIC_GFXACTMHz)) 1210 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz); 1211 1212 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1213 if (DO_BIC(BIC_Totl_c0)) 1214 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0/tsc); 1215 if (DO_BIC(BIC_Any_c0)) 1216 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0/tsc); 1217 if (DO_BIC(BIC_GFX_c0)) 1218 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0/tsc); 1219 if (DO_BIC(BIC_CPUGFX)) 1220 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0/tsc); 1221 1222 if (DO_BIC(BIC_Pkgpc2)) 1223 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2/tsc); 1224 if (DO_BIC(BIC_Pkgpc3)) 1225 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3/tsc); 1226 if (DO_BIC(BIC_Pkgpc6)) 1227 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6/tsc); 1228 if (DO_BIC(BIC_Pkgpc7)) 1229 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7/tsc); 1230 if (DO_BIC(BIC_Pkgpc8)) 1231 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8/tsc); 1232 if (DO_BIC(BIC_Pkgpc9)) 1233 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9/tsc); 1234 if (DO_BIC(BIC_Pkgpc10)) 1235 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10/tsc); 1236 1237 if (DO_BIC(BIC_CPU_LPI)) 1238 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1239 if (DO_BIC(BIC_SYS_LPI)) 1240 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1241 1242 if (DO_BIC(BIC_PkgWatt)) 1243 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1244 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1245 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1246 if (DO_BIC(BIC_GFXWatt)) 1247 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1248 if (DO_BIC(BIC_RAMWatt)) 1249 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units / interval_float); 1250 if (DO_BIC(BIC_Pkg_J)) 1251 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 1252 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1253 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 1254 if (DO_BIC(BIC_GFX_J)) 1255 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 1256 if (DO_BIC(BIC_RAM_J)) 1257 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 1258 if (DO_BIC(BIC_PKG__)) 1259 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 1260 if (DO_BIC(BIC_RAM__)) 1261 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 1262 1263 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1264 if (mp->format == FORMAT_RAW) { 1265 if (mp->width == 32) 1266 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) p->counter[i]); 1267 else 1268 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 1269 } else if (mp->format == FORMAT_DELTA) { 1270 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1271 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 1272 else 1273 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 1274 } else if (mp->format == FORMAT_PERCENT) { 1275 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i]/tsc); 1276 } 1277 } 1278 1279 done: 1280 if (*(outp - 1) != '\n') 1281 outp += sprintf(outp, "\n"); 1282 1283 return 0; 1284 } 1285 1286 void flush_output_stdout(void) 1287 { 1288 FILE *filep; 1289 1290 if (outf == stderr) 1291 filep = stdout; 1292 else 1293 filep = outf; 1294 1295 fputs(output_buffer, filep); 1296 fflush(filep); 1297 1298 outp = output_buffer; 1299 } 1300 void flush_output_stderr(void) 1301 { 1302 fputs(output_buffer, outf); 1303 fflush(outf); 1304 outp = output_buffer; 1305 } 1306 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1307 { 1308 static int printed; 1309 1310 if (!printed || !summary_only) 1311 print_header("\t"); 1312 1313 format_counters(&average.threads, &average.cores, &average.packages); 1314 1315 printed = 1; 1316 1317 if (summary_only) 1318 return; 1319 1320 for_all_cpus(format_counters, t, c, p); 1321 } 1322 1323 #define DELTA_WRAP32(new, old) \ 1324 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32); 1325 1326 int 1327 delta_package(struct pkg_data *new, struct pkg_data *old) 1328 { 1329 int i; 1330 struct msr_counter *mp; 1331 1332 1333 if (DO_BIC(BIC_Totl_c0)) 1334 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 1335 if (DO_BIC(BIC_Any_c0)) 1336 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 1337 if (DO_BIC(BIC_GFX_c0)) 1338 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 1339 if (DO_BIC(BIC_CPUGFX)) 1340 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 1341 1342 old->pc2 = new->pc2 - old->pc2; 1343 if (DO_BIC(BIC_Pkgpc3)) 1344 old->pc3 = new->pc3 - old->pc3; 1345 if (DO_BIC(BIC_Pkgpc6)) 1346 old->pc6 = new->pc6 - old->pc6; 1347 if (DO_BIC(BIC_Pkgpc7)) 1348 old->pc7 = new->pc7 - old->pc7; 1349 old->pc8 = new->pc8 - old->pc8; 1350 old->pc9 = new->pc9 - old->pc9; 1351 old->pc10 = new->pc10 - old->pc10; 1352 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 1353 old->sys_lpi = new->sys_lpi - old->sys_lpi; 1354 old->pkg_temp_c = new->pkg_temp_c; 1355 1356 /* flag an error when rc6 counter resets/wraps */ 1357 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 1358 old->gfx_rc6_ms = -1; 1359 else 1360 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 1361 1362 old->gfx_mhz = new->gfx_mhz; 1363 old->gfx_act_mhz = new->gfx_act_mhz; 1364 1365 old->energy_pkg = new->energy_pkg - old->energy_pkg; 1366 old->energy_cores = new->energy_cores - old->energy_cores; 1367 old->energy_gfx = new->energy_gfx - old->energy_gfx; 1368 old->energy_dram = new->energy_dram - old->energy_dram; 1369 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status; 1370 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status; 1371 1372 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1373 if (mp->format == FORMAT_RAW) 1374 old->counter[i] = new->counter[i]; 1375 else 1376 old->counter[i] = new->counter[i] - old->counter[i]; 1377 } 1378 1379 return 0; 1380 } 1381 1382 void 1383 delta_core(struct core_data *new, struct core_data *old) 1384 { 1385 int i; 1386 struct msr_counter *mp; 1387 1388 old->c3 = new->c3 - old->c3; 1389 old->c6 = new->c6 - old->c6; 1390 old->c7 = new->c7 - old->c7; 1391 old->core_temp_c = new->core_temp_c; 1392 old->mc6_us = new->mc6_us - old->mc6_us; 1393 1394 DELTA_WRAP32(new->core_energy, old->core_energy); 1395 1396 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1397 if (mp->format == FORMAT_RAW) 1398 old->counter[i] = new->counter[i]; 1399 else 1400 old->counter[i] = new->counter[i] - old->counter[i]; 1401 } 1402 } 1403 1404 int soft_c1_residency_display(int bic) 1405 { 1406 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr) 1407 return 0; 1408 1409 return DO_BIC_READ(bic); 1410 } 1411 1412 /* 1413 * old = new - old 1414 */ 1415 int 1416 delta_thread(struct thread_data *new, struct thread_data *old, 1417 struct core_data *core_delta) 1418 { 1419 int i; 1420 struct msr_counter *mp; 1421 1422 /* we run cpuid just the 1st time, copy the results */ 1423 if (DO_BIC(BIC_APIC)) 1424 new->apic_id = old->apic_id; 1425 if (DO_BIC(BIC_X2APIC)) 1426 new->x2apic_id = old->x2apic_id; 1427 1428 /* 1429 * the timestamps from start of measurement interval are in "old" 1430 * the timestamp from end of measurement interval are in "new" 1431 * over-write old w/ new so we can print end of interval values 1432 */ 1433 1434 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta); 1435 old->tv_begin = new->tv_begin; 1436 old->tv_end = new->tv_end; 1437 1438 old->tsc = new->tsc - old->tsc; 1439 1440 /* check for TSC < 1 Mcycles over interval */ 1441 if (old->tsc < (1000 * 1000)) 1442 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1443 "You can disable all c-states by booting with \"idle=poll\"\n" 1444 "or just the deep ones with \"processor.max_cstate=1\""); 1445 1446 old->c1 = new->c1 - old->c1; 1447 1448 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || 1449 soft_c1_residency_display(BIC_Avg_MHz)) { 1450 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1451 old->aperf = new->aperf - old->aperf; 1452 old->mperf = new->mperf - old->mperf; 1453 } else { 1454 return -1; 1455 } 1456 } 1457 1458 1459 if (use_c1_residency_msr) { 1460 /* 1461 * Some models have a dedicated C1 residency MSR, 1462 * which should be more accurate than the derivation below. 1463 */ 1464 } else { 1465 /* 1466 * As counter collection is not atomic, 1467 * it is possible for mperf's non-halted cycles + idle states 1468 * to exceed TSC's all cycles: show c1 = 0% in that case. 1469 */ 1470 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 1471 old->c1 = 0; 1472 else { 1473 /* normal case, derive c1 */ 1474 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1475 - core_delta->c6 - core_delta->c7; 1476 } 1477 } 1478 1479 if (old->mperf == 0) { 1480 if (debug > 1) 1481 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1482 old->mperf = 1; /* divide by 0 protection */ 1483 } 1484 1485 if (DO_BIC(BIC_IRQ)) 1486 old->irq_count = new->irq_count - old->irq_count; 1487 1488 if (DO_BIC(BIC_SMI)) 1489 old->smi_count = new->smi_count - old->smi_count; 1490 1491 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1492 if (mp->format == FORMAT_RAW) 1493 old->counter[i] = new->counter[i]; 1494 else 1495 old->counter[i] = new->counter[i] - old->counter[i]; 1496 } 1497 return 0; 1498 } 1499 1500 int delta_cpu(struct thread_data *t, struct core_data *c, 1501 struct pkg_data *p, struct thread_data *t2, 1502 struct core_data *c2, struct pkg_data *p2) 1503 { 1504 int retval = 0; 1505 1506 /* calculate core delta only for 1st thread in core */ 1507 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1508 delta_core(c, c2); 1509 1510 /* always calculate thread delta */ 1511 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1512 if (retval) 1513 return retval; 1514 1515 /* calculate package delta only for 1st core in package */ 1516 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1517 retval = delta_package(p, p2); 1518 1519 return retval; 1520 } 1521 1522 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1523 { 1524 int i; 1525 struct msr_counter *mp; 1526 1527 t->tv_begin.tv_sec = 0; 1528 t->tv_begin.tv_usec = 0; 1529 t->tv_end.tv_sec = 0; 1530 t->tv_end.tv_usec = 0; 1531 t->tv_delta.tv_sec = 0; 1532 t->tv_delta.tv_usec = 0; 1533 1534 t->tsc = 0; 1535 t->aperf = 0; 1536 t->mperf = 0; 1537 t->c1 = 0; 1538 1539 t->irq_count = 0; 1540 t->smi_count = 0; 1541 1542 /* tells format_counters to dump all fields from this set */ 1543 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1544 1545 c->c3 = 0; 1546 c->c6 = 0; 1547 c->c7 = 0; 1548 c->mc6_us = 0; 1549 c->core_temp_c = 0; 1550 c->core_energy = 0; 1551 1552 p->pkg_wtd_core_c0 = 0; 1553 p->pkg_any_core_c0 = 0; 1554 p->pkg_any_gfxe_c0 = 0; 1555 p->pkg_both_core_gfxe_c0 = 0; 1556 1557 p->pc2 = 0; 1558 if (DO_BIC(BIC_Pkgpc3)) 1559 p->pc3 = 0; 1560 if (DO_BIC(BIC_Pkgpc6)) 1561 p->pc6 = 0; 1562 if (DO_BIC(BIC_Pkgpc7)) 1563 p->pc7 = 0; 1564 p->pc8 = 0; 1565 p->pc9 = 0; 1566 p->pc10 = 0; 1567 p->cpu_lpi = 0; 1568 p->sys_lpi = 0; 1569 1570 p->energy_pkg = 0; 1571 p->energy_dram = 0; 1572 p->energy_cores = 0; 1573 p->energy_gfx = 0; 1574 p->rapl_pkg_perf_status = 0; 1575 p->rapl_dram_perf_status = 0; 1576 p->pkg_temp_c = 0; 1577 1578 p->gfx_rc6_ms = 0; 1579 p->gfx_mhz = 0; 1580 p->gfx_act_mhz = 0; 1581 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1582 t->counter[i] = 0; 1583 1584 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1585 c->counter[i] = 0; 1586 1587 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1588 p->counter[i] = 0; 1589 } 1590 int sum_counters(struct thread_data *t, struct core_data *c, 1591 struct pkg_data *p) 1592 { 1593 int i; 1594 struct msr_counter *mp; 1595 1596 /* copy un-changing apic_id's */ 1597 if (DO_BIC(BIC_APIC)) 1598 average.threads.apic_id = t->apic_id; 1599 if (DO_BIC(BIC_X2APIC)) 1600 average.threads.x2apic_id = t->x2apic_id; 1601 1602 /* remember first tv_begin */ 1603 if (average.threads.tv_begin.tv_sec == 0) 1604 average.threads.tv_begin = t->tv_begin; 1605 1606 /* remember last tv_end */ 1607 average.threads.tv_end = t->tv_end; 1608 1609 average.threads.tsc += t->tsc; 1610 average.threads.aperf += t->aperf; 1611 average.threads.mperf += t->mperf; 1612 average.threads.c1 += t->c1; 1613 1614 average.threads.irq_count += t->irq_count; 1615 average.threads.smi_count += t->smi_count; 1616 1617 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1618 if (mp->format == FORMAT_RAW) 1619 continue; 1620 average.threads.counter[i] += t->counter[i]; 1621 } 1622 1623 /* sum per-core values only for 1st thread in core */ 1624 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1625 return 0; 1626 1627 average.cores.c3 += c->c3; 1628 average.cores.c6 += c->c6; 1629 average.cores.c7 += c->c7; 1630 average.cores.mc6_us += c->mc6_us; 1631 1632 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1633 1634 average.cores.core_energy += c->core_energy; 1635 1636 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1637 if (mp->format == FORMAT_RAW) 1638 continue; 1639 average.cores.counter[i] += c->counter[i]; 1640 } 1641 1642 /* sum per-pkg values only for 1st core in pkg */ 1643 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1644 return 0; 1645 1646 if (DO_BIC(BIC_Totl_c0)) 1647 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1648 if (DO_BIC(BIC_Any_c0)) 1649 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1650 if (DO_BIC(BIC_GFX_c0)) 1651 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1652 if (DO_BIC(BIC_CPUGFX)) 1653 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1654 1655 average.packages.pc2 += p->pc2; 1656 if (DO_BIC(BIC_Pkgpc3)) 1657 average.packages.pc3 += p->pc3; 1658 if (DO_BIC(BIC_Pkgpc6)) 1659 average.packages.pc6 += p->pc6; 1660 if (DO_BIC(BIC_Pkgpc7)) 1661 average.packages.pc7 += p->pc7; 1662 average.packages.pc8 += p->pc8; 1663 average.packages.pc9 += p->pc9; 1664 average.packages.pc10 += p->pc10; 1665 1666 average.packages.cpu_lpi = p->cpu_lpi; 1667 average.packages.sys_lpi = p->sys_lpi; 1668 1669 average.packages.energy_pkg += p->energy_pkg; 1670 average.packages.energy_dram += p->energy_dram; 1671 average.packages.energy_cores += p->energy_cores; 1672 average.packages.energy_gfx += p->energy_gfx; 1673 1674 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1675 average.packages.gfx_mhz = p->gfx_mhz; 1676 average.packages.gfx_act_mhz = p->gfx_act_mhz; 1677 1678 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1679 1680 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1681 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1682 1683 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1684 if (mp->format == FORMAT_RAW) 1685 continue; 1686 average.packages.counter[i] += p->counter[i]; 1687 } 1688 return 0; 1689 } 1690 /* 1691 * sum the counters for all cpus in the system 1692 * compute the weighted average 1693 */ 1694 void compute_average(struct thread_data *t, struct core_data *c, 1695 struct pkg_data *p) 1696 { 1697 int i; 1698 struct msr_counter *mp; 1699 1700 clear_counters(&average.threads, &average.cores, &average.packages); 1701 1702 for_all_cpus(sum_counters, t, c, p); 1703 1704 /* Use the global time delta for the average. */ 1705 average.threads.tv_delta = tv_delta; 1706 1707 average.threads.tsc /= topo.num_cpus; 1708 average.threads.aperf /= topo.num_cpus; 1709 average.threads.mperf /= topo.num_cpus; 1710 average.threads.c1 /= topo.num_cpus; 1711 1712 if (average.threads.irq_count > 9999999) 1713 sums_need_wide_columns = 1; 1714 1715 average.cores.c3 /= topo.num_cores; 1716 average.cores.c6 /= topo.num_cores; 1717 average.cores.c7 /= topo.num_cores; 1718 average.cores.mc6_us /= topo.num_cores; 1719 1720 if (DO_BIC(BIC_Totl_c0)) 1721 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1722 if (DO_BIC(BIC_Any_c0)) 1723 average.packages.pkg_any_core_c0 /= topo.num_packages; 1724 if (DO_BIC(BIC_GFX_c0)) 1725 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1726 if (DO_BIC(BIC_CPUGFX)) 1727 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1728 1729 average.packages.pc2 /= topo.num_packages; 1730 if (DO_BIC(BIC_Pkgpc3)) 1731 average.packages.pc3 /= topo.num_packages; 1732 if (DO_BIC(BIC_Pkgpc6)) 1733 average.packages.pc6 /= topo.num_packages; 1734 if (DO_BIC(BIC_Pkgpc7)) 1735 average.packages.pc7 /= topo.num_packages; 1736 1737 average.packages.pc8 /= topo.num_packages; 1738 average.packages.pc9 /= topo.num_packages; 1739 average.packages.pc10 /= topo.num_packages; 1740 1741 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1742 if (mp->format == FORMAT_RAW) 1743 continue; 1744 if (mp->type == COUNTER_ITEMS) { 1745 if (average.threads.counter[i] > 9999999) 1746 sums_need_wide_columns = 1; 1747 continue; 1748 } 1749 average.threads.counter[i] /= topo.num_cpus; 1750 } 1751 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1752 if (mp->format == FORMAT_RAW) 1753 continue; 1754 if (mp->type == COUNTER_ITEMS) { 1755 if (average.cores.counter[i] > 9999999) 1756 sums_need_wide_columns = 1; 1757 } 1758 average.cores.counter[i] /= topo.num_cores; 1759 } 1760 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1761 if (mp->format == FORMAT_RAW) 1762 continue; 1763 if (mp->type == COUNTER_ITEMS) { 1764 if (average.packages.counter[i] > 9999999) 1765 sums_need_wide_columns = 1; 1766 } 1767 average.packages.counter[i] /= topo.num_packages; 1768 } 1769 } 1770 1771 static unsigned long long rdtsc(void) 1772 { 1773 unsigned int low, high; 1774 1775 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1776 1777 return low | ((unsigned long long)high) << 32; 1778 } 1779 1780 /* 1781 * Open a file, and exit on failure 1782 */ 1783 FILE *fopen_or_die(const char *path, const char *mode) 1784 { 1785 FILE *filep = fopen(path, mode); 1786 1787 if (!filep) 1788 err(1, "%s: open failed", path); 1789 return filep; 1790 } 1791 /* 1792 * snapshot_sysfs_counter() 1793 * 1794 * return snapshot of given counter 1795 */ 1796 unsigned long long snapshot_sysfs_counter(char *path) 1797 { 1798 FILE *fp; 1799 int retval; 1800 unsigned long long counter; 1801 1802 fp = fopen_or_die(path, "r"); 1803 1804 retval = fscanf(fp, "%lld", &counter); 1805 if (retval != 1) 1806 err(1, "snapshot_sysfs_counter(%s)", path); 1807 1808 fclose(fp); 1809 1810 return counter; 1811 } 1812 1813 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 1814 { 1815 if (mp->msr_num != 0) { 1816 if (get_msr(cpu, mp->msr_num, counterp)) 1817 return -1; 1818 } else { 1819 char path[128 + PATH_BYTES]; 1820 1821 if (mp->flags & SYSFS_PERCPU) { 1822 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", 1823 cpu, mp->path); 1824 1825 *counterp = snapshot_sysfs_counter(path); 1826 } else { 1827 *counterp = snapshot_sysfs_counter(mp->path); 1828 } 1829 } 1830 1831 return 0; 1832 } 1833 1834 int get_epb(int cpu) 1835 { 1836 char path[128 + PATH_BYTES]; 1837 unsigned long long msr; 1838 int ret, epb = -1; 1839 FILE *fp; 1840 1841 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu); 1842 1843 fp = fopen(path, "r"); 1844 if (!fp) 1845 goto msr_fallback; 1846 1847 ret = fscanf(fp, "%d", &epb); 1848 if (ret != 1) 1849 err(1, "%s(%s)", __func__, path); 1850 1851 fclose(fp); 1852 1853 return epb; 1854 1855 msr_fallback: 1856 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr); 1857 1858 return msr & 0xf; 1859 } 1860 1861 void get_apic_id(struct thread_data *t) 1862 { 1863 unsigned int eax, ebx, ecx, edx; 1864 1865 if (DO_BIC(BIC_APIC)) { 1866 eax = ebx = ecx = edx = 0; 1867 __cpuid(1, eax, ebx, ecx, edx); 1868 1869 t->apic_id = (ebx >> 24) & 0xff; 1870 } 1871 1872 if (!DO_BIC(BIC_X2APIC)) 1873 return; 1874 1875 if (authentic_amd || hygon_genuine) { 1876 unsigned int topology_extensions; 1877 1878 if (max_extended_level < 0x8000001e) 1879 return; 1880 1881 eax = ebx = ecx = edx = 0; 1882 __cpuid(0x80000001, eax, ebx, ecx, edx); 1883 topology_extensions = ecx & (1 << 22); 1884 1885 if (topology_extensions == 0) 1886 return; 1887 1888 eax = ebx = ecx = edx = 0; 1889 __cpuid(0x8000001e, eax, ebx, ecx, edx); 1890 1891 t->x2apic_id = eax; 1892 return; 1893 } 1894 1895 if (!genuine_intel) 1896 return; 1897 1898 if (max_level < 0xb) 1899 return; 1900 1901 ecx = 0; 1902 __cpuid(0xb, eax, ebx, ecx, edx); 1903 t->x2apic_id = edx; 1904 1905 if (debug && (t->apic_id != (t->x2apic_id & 0xff))) 1906 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", 1907 t->cpu_id, t->apic_id, t->x2apic_id); 1908 } 1909 1910 /* 1911 * get_counters(...) 1912 * migrate to cpu 1913 * acquire and record local counters for that cpu 1914 */ 1915 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1916 { 1917 int cpu = t->cpu_id; 1918 unsigned long long msr; 1919 int aperf_mperf_retry_count = 0; 1920 struct msr_counter *mp; 1921 int i; 1922 1923 if (cpu_migrate(cpu)) { 1924 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu); 1925 return -1; 1926 } 1927 1928 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 1929 1930 if (first_counter_read) 1931 get_apic_id(t); 1932 retry: 1933 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1934 1935 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || 1936 soft_c1_residency_display(BIC_Avg_MHz)) { 1937 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1938 1939 /* 1940 * The TSC, APERF and MPERF must be read together for 1941 * APERF/MPERF and MPERF/TSC to give accurate results. 1942 * 1943 * Unfortunately, APERF and MPERF are read by 1944 * individual system call, so delays may occur 1945 * between them. If the time to read them 1946 * varies by a large amount, we re-read them. 1947 */ 1948 1949 /* 1950 * This initial dummy APERF read has been seen to 1951 * reduce jitter in the subsequent reads. 1952 */ 1953 1954 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1955 return -3; 1956 1957 t->tsc = rdtsc(); /* re-read close to APERF */ 1958 1959 tsc_before = t->tsc; 1960 1961 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1962 return -3; 1963 1964 tsc_between = rdtsc(); 1965 1966 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1967 return -4; 1968 1969 tsc_after = rdtsc(); 1970 1971 aperf_time = tsc_between - tsc_before; 1972 mperf_time = tsc_after - tsc_between; 1973 1974 /* 1975 * If the system call latency to read APERF and MPERF 1976 * differ by more than 2x, then try again. 1977 */ 1978 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1979 aperf_mperf_retry_count++; 1980 if (aperf_mperf_retry_count < 5) 1981 goto retry; 1982 else 1983 warnx("cpu%d jitter %lld %lld", 1984 cpu, aperf_time, mperf_time); 1985 } 1986 aperf_mperf_retry_count = 0; 1987 1988 t->aperf = t->aperf * aperf_mperf_multiplier; 1989 t->mperf = t->mperf * aperf_mperf_multiplier; 1990 } 1991 1992 if (DO_BIC(BIC_IRQ)) 1993 t->irq_count = irqs_per_cpu[cpu]; 1994 if (DO_BIC(BIC_SMI)) { 1995 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1996 return -5; 1997 t->smi_count = msr & 0xFFFFFFFF; 1998 } 1999 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 2000 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 2001 return -6; 2002 } 2003 2004 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 2005 if (get_mp(cpu, mp, &t->counter[i])) 2006 return -10; 2007 } 2008 2009 /* collect core counters only for 1st thread in core */ 2010 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 2011 goto done; 2012 2013 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) { 2014 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 2015 return -6; 2016 } 2017 2018 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) { 2019 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 2020 return -7; 2021 } else if (do_knl_cstates || soft_c1_residency_display(BIC_CPU_c6)) { 2022 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 2023 return -7; 2024 } 2025 2026 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) 2027 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 2028 return -8; 2029 2030 if (DO_BIC(BIC_Mod_c6)) 2031 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 2032 return -8; 2033 2034 if (DO_BIC(BIC_CoreTmp)) { 2035 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 2036 return -9; 2037 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 2038 } 2039 2040 if (do_rapl & RAPL_AMD_F17H) { 2041 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr)) 2042 return -14; 2043 c->core_energy = msr & 0xFFFFFFFF; 2044 } 2045 2046 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 2047 if (get_mp(cpu, mp, &c->counter[i])) 2048 return -10; 2049 } 2050 2051 /* collect package counters only for 1st core in package */ 2052 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2053 goto done; 2054 2055 if (DO_BIC(BIC_Totl_c0)) { 2056 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 2057 return -10; 2058 } 2059 if (DO_BIC(BIC_Any_c0)) { 2060 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 2061 return -11; 2062 } 2063 if (DO_BIC(BIC_GFX_c0)) { 2064 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 2065 return -12; 2066 } 2067 if (DO_BIC(BIC_CPUGFX)) { 2068 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 2069 return -13; 2070 } 2071 if (DO_BIC(BIC_Pkgpc3)) 2072 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 2073 return -9; 2074 if (DO_BIC(BIC_Pkgpc6)) { 2075 if (do_slm_cstates) { 2076 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 2077 return -10; 2078 } else { 2079 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 2080 return -10; 2081 } 2082 } 2083 2084 if (DO_BIC(BIC_Pkgpc2)) 2085 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 2086 return -11; 2087 if (DO_BIC(BIC_Pkgpc7)) 2088 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 2089 return -12; 2090 if (DO_BIC(BIC_Pkgpc8)) 2091 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 2092 return -13; 2093 if (DO_BIC(BIC_Pkgpc9)) 2094 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 2095 return -13; 2096 if (DO_BIC(BIC_Pkgpc10)) 2097 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 2098 return -13; 2099 2100 if (DO_BIC(BIC_CPU_LPI)) 2101 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 2102 if (DO_BIC(BIC_SYS_LPI)) 2103 p->sys_lpi = cpuidle_cur_sys_lpi_us; 2104 2105 if (do_rapl & RAPL_PKG) { 2106 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 2107 return -13; 2108 p->energy_pkg = msr; 2109 } 2110 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 2111 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 2112 return -14; 2113 p->energy_cores = msr; 2114 } 2115 if (do_rapl & RAPL_DRAM) { 2116 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 2117 return -15; 2118 p->energy_dram = msr; 2119 } 2120 if (do_rapl & RAPL_GFX) { 2121 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 2122 return -16; 2123 p->energy_gfx = msr; 2124 } 2125 if (do_rapl & RAPL_PKG_PERF_STATUS) { 2126 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr)) 2127 return -16; 2128 p->rapl_pkg_perf_status = msr; 2129 } 2130 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 2131 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr)) 2132 return -16; 2133 p->rapl_dram_perf_status = msr; 2134 } 2135 if (do_rapl & RAPL_AMD_F17H) { 2136 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr)) 2137 return -13; 2138 p->energy_pkg = msr; 2139 } 2140 if (DO_BIC(BIC_PkgTmp)) { 2141 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 2142 return -17; 2143 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 2144 } 2145 2146 if (DO_BIC(BIC_GFX_rc6)) 2147 p->gfx_rc6_ms = gfx_cur_rc6_ms; 2148 2149 if (DO_BIC(BIC_GFXMHz)) 2150 p->gfx_mhz = gfx_cur_mhz; 2151 2152 if (DO_BIC(BIC_GFXACTMHz)) 2153 p->gfx_act_mhz = gfx_act_mhz; 2154 2155 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2156 if (get_mp(cpu, mp, &p->counter[i])) 2157 return -10; 2158 } 2159 done: 2160 gettimeofday(&t->tv_end, (struct timezone *)NULL); 2161 2162 return 0; 2163 } 2164 2165 /* 2166 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 2167 * If you change the values, note they are used both in comparisons 2168 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 2169 */ 2170 2171 #define PCLUKN 0 /* Unknown */ 2172 #define PCLRSV 1 /* Reserved */ 2173 #define PCL__0 2 /* PC0 */ 2174 #define PCL__1 3 /* PC1 */ 2175 #define PCL__2 4 /* PC2 */ 2176 #define PCL__3 5 /* PC3 */ 2177 #define PCL__4 6 /* PC4 */ 2178 #define PCL__6 7 /* PC6 */ 2179 #define PCL_6N 8 /* PC6 No Retention */ 2180 #define PCL_6R 9 /* PC6 Retention */ 2181 #define PCL__7 10 /* PC7 */ 2182 #define PCL_7S 11 /* PC7 Shrink */ 2183 #define PCL__8 12 /* PC8 */ 2184 #define PCL__9 13 /* PC9 */ 2185 #define PCL_10 14 /* PC10 */ 2186 #define PCLUNL 15 /* Unlimited */ 2187 2188 int pkg_cstate_limit = PCLUKN; 2189 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 2190 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"}; 2191 2192 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2193 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2194 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2195 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7}; 2196 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2197 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2198 int glm_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2199 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2200 2201 2202 static void 2203 calculate_tsc_tweak() 2204 { 2205 tsc_tweak = base_hz / tsc_hz; 2206 } 2207 2208 static void 2209 dump_nhm_platform_info(void) 2210 { 2211 unsigned long long msr; 2212 unsigned int ratio; 2213 2214 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2215 2216 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 2217 2218 ratio = (msr >> 40) & 0xFF; 2219 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", 2220 ratio, bclk, ratio * bclk); 2221 2222 ratio = (msr >> 8) & 0xFF; 2223 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2224 ratio, bclk, ratio * bclk); 2225 2226 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 2227 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 2228 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 2229 2230 return; 2231 } 2232 2233 static void 2234 dump_hsw_turbo_ratio_limits(void) 2235 { 2236 unsigned long long msr; 2237 unsigned int ratio; 2238 2239 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 2240 2241 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 2242 2243 ratio = (msr >> 8) & 0xFF; 2244 if (ratio) 2245 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", 2246 ratio, bclk, ratio * bclk); 2247 2248 ratio = (msr >> 0) & 0xFF; 2249 if (ratio) 2250 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", 2251 ratio, bclk, ratio * bclk); 2252 return; 2253 } 2254 2255 static void 2256 dump_ivt_turbo_ratio_limits(void) 2257 { 2258 unsigned long long msr; 2259 unsigned int ratio; 2260 2261 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 2262 2263 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 2264 2265 ratio = (msr >> 56) & 0xFF; 2266 if (ratio) 2267 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", 2268 ratio, bclk, ratio * bclk); 2269 2270 ratio = (msr >> 48) & 0xFF; 2271 if (ratio) 2272 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", 2273 ratio, bclk, ratio * bclk); 2274 2275 ratio = (msr >> 40) & 0xFF; 2276 if (ratio) 2277 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", 2278 ratio, bclk, ratio * bclk); 2279 2280 ratio = (msr >> 32) & 0xFF; 2281 if (ratio) 2282 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", 2283 ratio, bclk, ratio * bclk); 2284 2285 ratio = (msr >> 24) & 0xFF; 2286 if (ratio) 2287 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", 2288 ratio, bclk, ratio * bclk); 2289 2290 ratio = (msr >> 16) & 0xFF; 2291 if (ratio) 2292 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", 2293 ratio, bclk, ratio * bclk); 2294 2295 ratio = (msr >> 8) & 0xFF; 2296 if (ratio) 2297 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", 2298 ratio, bclk, ratio * bclk); 2299 2300 ratio = (msr >> 0) & 0xFF; 2301 if (ratio) 2302 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", 2303 ratio, bclk, ratio * bclk); 2304 return; 2305 } 2306 int has_turbo_ratio_group_limits(int family, int model) 2307 { 2308 2309 if (!genuine_intel) 2310 return 0; 2311 2312 switch (model) { 2313 case INTEL_FAM6_ATOM_GOLDMONT: 2314 case INTEL_FAM6_SKYLAKE_X: 2315 case INTEL_FAM6_ATOM_GOLDMONT_D: 2316 case INTEL_FAM6_ATOM_TREMONT_D: 2317 return 1; 2318 } 2319 return 0; 2320 } 2321 2322 static void 2323 dump_turbo_ratio_limits(int family, int model) 2324 { 2325 unsigned long long msr, core_counts; 2326 unsigned int ratio, group_size; 2327 2328 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2329 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2330 2331 if (has_turbo_ratio_group_limits(family, model)) { 2332 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 2333 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 2334 } else { 2335 core_counts = 0x0807060504030201; 2336 } 2337 2338 ratio = (msr >> 56) & 0xFF; 2339 group_size = (core_counts >> 56) & 0xFF; 2340 if (ratio) 2341 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2342 ratio, bclk, ratio * bclk, group_size); 2343 2344 ratio = (msr >> 48) & 0xFF; 2345 group_size = (core_counts >> 48) & 0xFF; 2346 if (ratio) 2347 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2348 ratio, bclk, ratio * bclk, group_size); 2349 2350 ratio = (msr >> 40) & 0xFF; 2351 group_size = (core_counts >> 40) & 0xFF; 2352 if (ratio) 2353 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2354 ratio, bclk, ratio * bclk, group_size); 2355 2356 ratio = (msr >> 32) & 0xFF; 2357 group_size = (core_counts >> 32) & 0xFF; 2358 if (ratio) 2359 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2360 ratio, bclk, ratio * bclk, group_size); 2361 2362 ratio = (msr >> 24) & 0xFF; 2363 group_size = (core_counts >> 24) & 0xFF; 2364 if (ratio) 2365 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2366 ratio, bclk, ratio * bclk, group_size); 2367 2368 ratio = (msr >> 16) & 0xFF; 2369 group_size = (core_counts >> 16) & 0xFF; 2370 if (ratio) 2371 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2372 ratio, bclk, ratio * bclk, group_size); 2373 2374 ratio = (msr >> 8) & 0xFF; 2375 group_size = (core_counts >> 8) & 0xFF; 2376 if (ratio) 2377 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2378 ratio, bclk, ratio * bclk, group_size); 2379 2380 ratio = (msr >> 0) & 0xFF; 2381 group_size = (core_counts >> 0) & 0xFF; 2382 if (ratio) 2383 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2384 ratio, bclk, ratio * bclk, group_size); 2385 return; 2386 } 2387 2388 static void 2389 dump_atom_turbo_ratio_limits(void) 2390 { 2391 unsigned long long msr; 2392 unsigned int ratio; 2393 2394 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 2395 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2396 2397 ratio = (msr >> 0) & 0x3F; 2398 if (ratio) 2399 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", 2400 ratio, bclk, ratio * bclk); 2401 2402 ratio = (msr >> 8) & 0x3F; 2403 if (ratio) 2404 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", 2405 ratio, bclk, ratio * bclk); 2406 2407 ratio = (msr >> 16) & 0x3F; 2408 if (ratio) 2409 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2410 ratio, bclk, ratio * bclk); 2411 2412 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 2413 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2414 2415 ratio = (msr >> 24) & 0x3F; 2416 if (ratio) 2417 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", 2418 ratio, bclk, ratio * bclk); 2419 2420 ratio = (msr >> 16) & 0x3F; 2421 if (ratio) 2422 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", 2423 ratio, bclk, ratio * bclk); 2424 2425 ratio = (msr >> 8) & 0x3F; 2426 if (ratio) 2427 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", 2428 ratio, bclk, ratio * bclk); 2429 2430 ratio = (msr >> 0) & 0x3F; 2431 if (ratio) 2432 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", 2433 ratio, bclk, ratio * bclk); 2434 } 2435 2436 static void 2437 dump_knl_turbo_ratio_limits(void) 2438 { 2439 const unsigned int buckets_no = 7; 2440 2441 unsigned long long msr; 2442 int delta_cores, delta_ratio; 2443 int i, b_nr; 2444 unsigned int cores[buckets_no]; 2445 unsigned int ratio[buckets_no]; 2446 2447 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2448 2449 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 2450 base_cpu, msr); 2451 2452 /** 2453 * Turbo encoding in KNL is as follows: 2454 * [0] -- Reserved 2455 * [7:1] -- Base value of number of active cores of bucket 1. 2456 * [15:8] -- Base value of freq ratio of bucket 1. 2457 * [20:16] -- +ve delta of number of active cores of bucket 2. 2458 * i.e. active cores of bucket 2 = 2459 * active cores of bucket 1 + delta 2460 * [23:21] -- Negative delta of freq ratio of bucket 2. 2461 * i.e. freq ratio of bucket 2 = 2462 * freq ratio of bucket 1 - delta 2463 * [28:24]-- +ve delta of number of active cores of bucket 3. 2464 * [31:29]-- -ve delta of freq ratio of bucket 3. 2465 * [36:32]-- +ve delta of number of active cores of bucket 4. 2466 * [39:37]-- -ve delta of freq ratio of bucket 4. 2467 * [44:40]-- +ve delta of number of active cores of bucket 5. 2468 * [47:45]-- -ve delta of freq ratio of bucket 5. 2469 * [52:48]-- +ve delta of number of active cores of bucket 6. 2470 * [55:53]-- -ve delta of freq ratio of bucket 6. 2471 * [60:56]-- +ve delta of number of active cores of bucket 7. 2472 * [63:61]-- -ve delta of freq ratio of bucket 7. 2473 */ 2474 2475 b_nr = 0; 2476 cores[b_nr] = (msr & 0xFF) >> 1; 2477 ratio[b_nr] = (msr >> 8) & 0xFF; 2478 2479 for (i = 16; i < 64; i += 8) { 2480 delta_cores = (msr >> i) & 0x1F; 2481 delta_ratio = (msr >> (i + 5)) & 0x7; 2482 2483 cores[b_nr + 1] = cores[b_nr] + delta_cores; 2484 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 2485 b_nr++; 2486 } 2487 2488 for (i = buckets_no - 1; i >= 0; i--) 2489 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 2490 fprintf(outf, 2491 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2492 ratio[i], bclk, ratio[i] * bclk, cores[i]); 2493 } 2494 2495 static void 2496 dump_nhm_cst_cfg(void) 2497 { 2498 unsigned long long msr; 2499 2500 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2501 2502 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 2503 2504 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 2505 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 2506 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 2507 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 2508 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 2509 (msr & (1 << 15)) ? "" : "UN", 2510 (unsigned int)msr & 0xF, 2511 pkg_cstate_limit_strings[pkg_cstate_limit]); 2512 2513 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 2514 if (has_automatic_cstate_conversion) { 2515 fprintf(outf, ", automatic c-state conversion=%s", 2516 (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 2517 } 2518 2519 fprintf(outf, ")\n"); 2520 2521 return; 2522 } 2523 2524 static void 2525 dump_config_tdp(void) 2526 { 2527 unsigned long long msr; 2528 2529 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 2530 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 2531 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 2532 2533 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 2534 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 2535 if (msr) { 2536 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2537 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2538 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2539 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 2540 } 2541 fprintf(outf, ")\n"); 2542 2543 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 2544 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 2545 if (msr) { 2546 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2547 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2548 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2549 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 2550 } 2551 fprintf(outf, ")\n"); 2552 2553 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 2554 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 2555 if ((msr) & 0x3) 2556 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 2557 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2558 fprintf(outf, ")\n"); 2559 2560 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 2561 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 2562 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 2563 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2564 fprintf(outf, ")\n"); 2565 } 2566 2567 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 2568 2569 void print_irtl(void) 2570 { 2571 unsigned long long msr; 2572 2573 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 2574 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 2575 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2576 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2577 2578 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 2579 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 2580 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2581 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2582 2583 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 2584 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 2585 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2586 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2587 2588 if (!do_irtl_hsw) 2589 return; 2590 2591 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 2592 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 2593 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2594 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2595 2596 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 2597 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 2598 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2599 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2600 2601 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 2602 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 2603 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2604 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2605 2606 } 2607 void free_fd_percpu(void) 2608 { 2609 int i; 2610 2611 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 2612 if (fd_percpu[i] != 0) 2613 close(fd_percpu[i]); 2614 } 2615 2616 free(fd_percpu); 2617 } 2618 2619 void free_all_buffers(void) 2620 { 2621 int i; 2622 2623 CPU_FREE(cpu_present_set); 2624 cpu_present_set = NULL; 2625 cpu_present_setsize = 0; 2626 2627 CPU_FREE(cpu_affinity_set); 2628 cpu_affinity_set = NULL; 2629 cpu_affinity_setsize = 0; 2630 2631 free(thread_even); 2632 free(core_even); 2633 free(package_even); 2634 2635 thread_even = NULL; 2636 core_even = NULL; 2637 package_even = NULL; 2638 2639 free(thread_odd); 2640 free(core_odd); 2641 free(package_odd); 2642 2643 thread_odd = NULL; 2644 core_odd = NULL; 2645 package_odd = NULL; 2646 2647 free(output_buffer); 2648 output_buffer = NULL; 2649 outp = NULL; 2650 2651 free_fd_percpu(); 2652 2653 free(irq_column_2_cpu); 2654 free(irqs_per_cpu); 2655 2656 for (i = 0; i <= topo.max_cpu_num; ++i) { 2657 if (cpus[i].put_ids) 2658 CPU_FREE(cpus[i].put_ids); 2659 } 2660 free(cpus); 2661 } 2662 2663 2664 /* 2665 * Parse a file containing a single int. 2666 * Return 0 if file can not be opened 2667 * Exit if file can be opened, but can not be parsed 2668 */ 2669 int parse_int_file(const char *fmt, ...) 2670 { 2671 va_list args; 2672 char path[PATH_MAX]; 2673 FILE *filep; 2674 int value; 2675 2676 va_start(args, fmt); 2677 vsnprintf(path, sizeof(path), fmt, args); 2678 va_end(args); 2679 filep = fopen(path, "r"); 2680 if (!filep) 2681 return 0; 2682 if (fscanf(filep, "%d", &value) != 1) 2683 err(1, "%s: failed to parse number from file", path); 2684 fclose(filep); 2685 return value; 2686 } 2687 2688 /* 2689 * cpu_is_first_core_in_package(cpu) 2690 * return 1 if given CPU is 1st core in package 2691 */ 2692 int cpu_is_first_core_in_package(int cpu) 2693 { 2694 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2695 } 2696 2697 int get_physical_package_id(int cpu) 2698 { 2699 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2700 } 2701 2702 int get_die_id(int cpu) 2703 { 2704 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu); 2705 } 2706 2707 int get_core_id(int cpu) 2708 { 2709 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2710 } 2711 2712 void set_node_data(void) 2713 { 2714 int pkg, node, lnode, cpu, cpux; 2715 int cpu_count; 2716 2717 /* initialize logical_node_id */ 2718 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) 2719 cpus[cpu].logical_node_id = -1; 2720 2721 cpu_count = 0; 2722 for (pkg = 0; pkg < topo.num_packages; pkg++) { 2723 lnode = 0; 2724 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) { 2725 if (cpus[cpu].physical_package_id != pkg) 2726 continue; 2727 /* find a cpu with an unset logical_node_id */ 2728 if (cpus[cpu].logical_node_id != -1) 2729 continue; 2730 cpus[cpu].logical_node_id = lnode; 2731 node = cpus[cpu].physical_node_id; 2732 cpu_count++; 2733 /* 2734 * find all matching cpus on this pkg and set 2735 * the logical_node_id 2736 */ 2737 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) { 2738 if ((cpus[cpux].physical_package_id == pkg) && 2739 (cpus[cpux].physical_node_id == node)) { 2740 cpus[cpux].logical_node_id = lnode; 2741 cpu_count++; 2742 } 2743 } 2744 lnode++; 2745 if (lnode > topo.nodes_per_pkg) 2746 topo.nodes_per_pkg = lnode; 2747 } 2748 if (cpu_count >= topo.max_cpu_num) 2749 break; 2750 } 2751 } 2752 2753 int get_physical_node_id(struct cpu_topology *thiscpu) 2754 { 2755 char path[80]; 2756 FILE *filep; 2757 int i; 2758 int cpu = thiscpu->logical_cpu_id; 2759 2760 for (i = 0; i <= topo.max_cpu_num; i++) { 2761 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", 2762 cpu, i); 2763 filep = fopen(path, "r"); 2764 if (!filep) 2765 continue; 2766 fclose(filep); 2767 return i; 2768 } 2769 return -1; 2770 } 2771 2772 int get_thread_siblings(struct cpu_topology *thiscpu) 2773 { 2774 char path[80], character; 2775 FILE *filep; 2776 unsigned long map; 2777 int so, shift, sib_core; 2778 int cpu = thiscpu->logical_cpu_id; 2779 int offset = topo.max_cpu_num + 1; 2780 size_t size; 2781 int thread_id = 0; 2782 2783 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 2784 if (thiscpu->thread_id < 0) 2785 thiscpu->thread_id = thread_id++; 2786 if (!thiscpu->put_ids) 2787 return -1; 2788 2789 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 2790 CPU_ZERO_S(size, thiscpu->put_ids); 2791 2792 sprintf(path, 2793 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 2794 filep = fopen(path, "r"); 2795 2796 if (!filep) { 2797 warnx("%s: open failed", path); 2798 return -1; 2799 } 2800 do { 2801 offset -= BITMASK_SIZE; 2802 if (fscanf(filep, "%lx%c", &map, &character) != 2) 2803 err(1, "%s: failed to parse file", path); 2804 for (shift = 0; shift < BITMASK_SIZE; shift++) { 2805 if ((map >> shift) & 0x1) { 2806 so = shift + offset; 2807 sib_core = get_core_id(so); 2808 if (sib_core == thiscpu->physical_core_id) { 2809 CPU_SET_S(so, size, thiscpu->put_ids); 2810 if ((so != cpu) && 2811 (cpus[so].thread_id < 0)) 2812 cpus[so].thread_id = 2813 thread_id++; 2814 } 2815 } 2816 } 2817 } while (!strncmp(&character, ",", 1)); 2818 fclose(filep); 2819 2820 return CPU_COUNT_S(size, thiscpu->put_ids); 2821 } 2822 2823 /* 2824 * run func(thread, core, package) in topology order 2825 * skip non-present cpus 2826 */ 2827 2828 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 2829 struct pkg_data *, struct thread_data *, struct core_data *, 2830 struct pkg_data *), struct thread_data *thread_base, 2831 struct core_data *core_base, struct pkg_data *pkg_base, 2832 struct thread_data *thread_base2, struct core_data *core_base2, 2833 struct pkg_data *pkg_base2) 2834 { 2835 int retval, pkg_no, node_no, core_no, thread_no; 2836 2837 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2838 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 2839 for (core_no = 0; core_no < topo.cores_per_node; 2840 ++core_no) { 2841 for (thread_no = 0; thread_no < 2842 topo.threads_per_core; ++thread_no) { 2843 struct thread_data *t, *t2; 2844 struct core_data *c, *c2; 2845 struct pkg_data *p, *p2; 2846 2847 t = GET_THREAD(thread_base, thread_no, 2848 core_no, node_no, 2849 pkg_no); 2850 2851 if (cpu_is_not_present(t->cpu_id)) 2852 continue; 2853 2854 t2 = GET_THREAD(thread_base2, thread_no, 2855 core_no, node_no, 2856 pkg_no); 2857 2858 c = GET_CORE(core_base, core_no, 2859 node_no, pkg_no); 2860 c2 = GET_CORE(core_base2, core_no, 2861 node_no, 2862 pkg_no); 2863 2864 p = GET_PKG(pkg_base, pkg_no); 2865 p2 = GET_PKG(pkg_base2, pkg_no); 2866 2867 retval = func(t, c, p, t2, c2, p2); 2868 if (retval) 2869 return retval; 2870 } 2871 } 2872 } 2873 } 2874 return 0; 2875 } 2876 2877 /* 2878 * run func(cpu) on every cpu in /proc/stat 2879 * return max_cpu number 2880 */ 2881 int for_all_proc_cpus(int (func)(int)) 2882 { 2883 FILE *fp; 2884 int cpu_num; 2885 int retval; 2886 2887 fp = fopen_or_die(proc_stat, "r"); 2888 2889 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 2890 if (retval != 0) 2891 err(1, "%s: failed to parse format", proc_stat); 2892 2893 while (1) { 2894 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 2895 if (retval != 1) 2896 break; 2897 2898 retval = func(cpu_num); 2899 if (retval) { 2900 fclose(fp); 2901 return(retval); 2902 } 2903 } 2904 fclose(fp); 2905 return 0; 2906 } 2907 2908 void re_initialize(void) 2909 { 2910 free_all_buffers(); 2911 setup_all_buffers(); 2912 fprintf(outf, "turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2913 } 2914 2915 void set_max_cpu_num(void) 2916 { 2917 FILE *filep; 2918 int base_cpu; 2919 unsigned long dummy; 2920 char pathname[64]; 2921 2922 base_cpu = sched_getcpu(); 2923 if (base_cpu < 0) 2924 err(1, "cannot find calling cpu ID"); 2925 sprintf(pathname, 2926 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", 2927 base_cpu); 2928 2929 filep = fopen_or_die(pathname, "r"); 2930 topo.max_cpu_num = 0; 2931 while (fscanf(filep, "%lx,", &dummy) == 1) 2932 topo.max_cpu_num += BITMASK_SIZE; 2933 fclose(filep); 2934 topo.max_cpu_num--; /* 0 based */ 2935 } 2936 2937 /* 2938 * count_cpus() 2939 * remember the last one seen, it will be the max 2940 */ 2941 int count_cpus(int cpu) 2942 { 2943 topo.num_cpus++; 2944 return 0; 2945 } 2946 int mark_cpu_present(int cpu) 2947 { 2948 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 2949 return 0; 2950 } 2951 2952 int init_thread_id(int cpu) 2953 { 2954 cpus[cpu].thread_id = -1; 2955 return 0; 2956 } 2957 2958 /* 2959 * snapshot_proc_interrupts() 2960 * 2961 * read and record summary of /proc/interrupts 2962 * 2963 * return 1 if config change requires a restart, else return 0 2964 */ 2965 int snapshot_proc_interrupts(void) 2966 { 2967 static FILE *fp; 2968 int column, retval; 2969 2970 if (fp == NULL) 2971 fp = fopen_or_die("/proc/interrupts", "r"); 2972 else 2973 rewind(fp); 2974 2975 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 2976 for (column = 0; column < topo.num_cpus; ++column) { 2977 int cpu_number; 2978 2979 retval = fscanf(fp, " CPU%d", &cpu_number); 2980 if (retval != 1) 2981 break; 2982 2983 if (cpu_number > topo.max_cpu_num) { 2984 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 2985 return 1; 2986 } 2987 2988 irq_column_2_cpu[column] = cpu_number; 2989 irqs_per_cpu[cpu_number] = 0; 2990 } 2991 2992 /* read /proc/interrupt count lines and sum up irqs per cpu */ 2993 while (1) { 2994 int column; 2995 char buf[64]; 2996 2997 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 2998 if (retval != 1) 2999 break; 3000 3001 /* read the count per cpu */ 3002 for (column = 0; column < topo.num_cpus; ++column) { 3003 3004 int cpu_number, irq_count; 3005 3006 retval = fscanf(fp, " %d", &irq_count); 3007 if (retval != 1) 3008 break; 3009 3010 cpu_number = irq_column_2_cpu[column]; 3011 irqs_per_cpu[cpu_number] += irq_count; 3012 3013 } 3014 3015 while (getc(fp) != '\n') 3016 ; /* flush interrupt description */ 3017 3018 } 3019 return 0; 3020 } 3021 /* 3022 * snapshot_gfx_rc6_ms() 3023 * 3024 * record snapshot of 3025 * /sys/class/drm/card0/power/rc6_residency_ms 3026 * 3027 * return 1 if config change requires a restart, else return 0 3028 */ 3029 int snapshot_gfx_rc6_ms(void) 3030 { 3031 FILE *fp; 3032 int retval; 3033 3034 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 3035 3036 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 3037 if (retval != 1) 3038 err(1, "GFX rc6"); 3039 3040 fclose(fp); 3041 3042 return 0; 3043 } 3044 /* 3045 * snapshot_gfx_mhz() 3046 * 3047 * record snapshot of 3048 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 3049 * 3050 * return 1 if config change requires a restart, else return 0 3051 */ 3052 int snapshot_gfx_mhz(void) 3053 { 3054 static FILE *fp; 3055 int retval; 3056 3057 if (fp == NULL) 3058 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 3059 else { 3060 rewind(fp); 3061 fflush(fp); 3062 } 3063 3064 retval = fscanf(fp, "%d", &gfx_cur_mhz); 3065 if (retval != 1) 3066 err(1, "GFX MHz"); 3067 3068 return 0; 3069 } 3070 3071 /* 3072 * snapshot_gfx_cur_mhz() 3073 * 3074 * record snapshot of 3075 * /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz 3076 * 3077 * return 1 if config change requires a restart, else return 0 3078 */ 3079 int snapshot_gfx_act_mhz(void) 3080 { 3081 static FILE *fp; 3082 int retval; 3083 3084 if (fp == NULL) 3085 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r"); 3086 else { 3087 rewind(fp); 3088 fflush(fp); 3089 } 3090 3091 retval = fscanf(fp, "%d", &gfx_act_mhz); 3092 if (retval != 1) 3093 err(1, "GFX ACT MHz"); 3094 3095 return 0; 3096 } 3097 3098 /* 3099 * snapshot_cpu_lpi() 3100 * 3101 * record snapshot of 3102 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 3103 */ 3104 int snapshot_cpu_lpi_us(void) 3105 { 3106 FILE *fp; 3107 int retval; 3108 3109 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 3110 3111 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 3112 if (retval != 1) { 3113 fprintf(stderr, "Disabling Low Power Idle CPU output\n"); 3114 BIC_NOT_PRESENT(BIC_CPU_LPI); 3115 fclose(fp); 3116 return -1; 3117 } 3118 3119 fclose(fp); 3120 3121 return 0; 3122 } 3123 /* 3124 * snapshot_sys_lpi() 3125 * 3126 * record snapshot of sys_lpi_file 3127 */ 3128 int snapshot_sys_lpi_us(void) 3129 { 3130 FILE *fp; 3131 int retval; 3132 3133 fp = fopen_or_die(sys_lpi_file, "r"); 3134 3135 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 3136 if (retval != 1) { 3137 fprintf(stderr, "Disabling Low Power Idle System output\n"); 3138 BIC_NOT_PRESENT(BIC_SYS_LPI); 3139 fclose(fp); 3140 return -1; 3141 } 3142 fclose(fp); 3143 3144 return 0; 3145 } 3146 /* 3147 * snapshot /proc and /sys files 3148 * 3149 * return 1 if configuration restart needed, else return 0 3150 */ 3151 int snapshot_proc_sysfs_files(void) 3152 { 3153 if (DO_BIC(BIC_IRQ)) 3154 if (snapshot_proc_interrupts()) 3155 return 1; 3156 3157 if (DO_BIC(BIC_GFX_rc6)) 3158 snapshot_gfx_rc6_ms(); 3159 3160 if (DO_BIC(BIC_GFXMHz)) 3161 snapshot_gfx_mhz(); 3162 3163 if (DO_BIC(BIC_GFXACTMHz)) 3164 snapshot_gfx_act_mhz(); 3165 3166 if (DO_BIC(BIC_CPU_LPI)) 3167 snapshot_cpu_lpi_us(); 3168 3169 if (DO_BIC(BIC_SYS_LPI)) 3170 snapshot_sys_lpi_us(); 3171 3172 return 0; 3173 } 3174 3175 int exit_requested; 3176 3177 static void signal_handler (int signal) 3178 { 3179 switch (signal) { 3180 case SIGINT: 3181 exit_requested = 1; 3182 if (debug) 3183 fprintf(stderr, " SIGINT\n"); 3184 break; 3185 case SIGUSR1: 3186 if (debug > 1) 3187 fprintf(stderr, "SIGUSR1\n"); 3188 break; 3189 } 3190 } 3191 3192 void setup_signal_handler(void) 3193 { 3194 struct sigaction sa; 3195 3196 memset(&sa, 0, sizeof(sa)); 3197 3198 sa.sa_handler = &signal_handler; 3199 3200 if (sigaction(SIGINT, &sa, NULL) < 0) 3201 err(1, "sigaction SIGINT"); 3202 if (sigaction(SIGUSR1, &sa, NULL) < 0) 3203 err(1, "sigaction SIGUSR1"); 3204 } 3205 3206 void do_sleep(void) 3207 { 3208 struct timeval tout; 3209 struct timespec rest; 3210 fd_set readfds; 3211 int retval; 3212 3213 FD_ZERO(&readfds); 3214 FD_SET(0, &readfds); 3215 3216 if (ignore_stdin) { 3217 nanosleep(&interval_ts, NULL); 3218 return; 3219 } 3220 3221 tout = interval_tv; 3222 retval = select(1, &readfds, NULL, NULL, &tout); 3223 3224 if (retval == 1) { 3225 switch (getc(stdin)) { 3226 case 'q': 3227 exit_requested = 1; 3228 break; 3229 case EOF: 3230 /* 3231 * 'stdin' is a pipe closed on the other end. There 3232 * won't be any further input. 3233 */ 3234 ignore_stdin = 1; 3235 /* Sleep the rest of the time */ 3236 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000); 3237 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000; 3238 nanosleep(&rest, NULL); 3239 } 3240 } 3241 } 3242 3243 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr) 3244 { 3245 int ret, idx; 3246 unsigned long long msr_cur, msr_last; 3247 3248 if (!per_cpu_msr_sum) 3249 return 1; 3250 3251 idx = offset_to_idx(offset); 3252 if (idx < 0) 3253 return idx; 3254 /* get_msr_sum() = sum + (get_msr() - last) */ 3255 ret = get_msr(cpu, offset, &msr_cur); 3256 if (ret) 3257 return ret; 3258 msr_last = per_cpu_msr_sum[cpu].entries[idx].last; 3259 DELTA_WRAP32(msr_cur, msr_last); 3260 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum; 3261 3262 return 0; 3263 } 3264 3265 timer_t timerid; 3266 3267 /* Timer callback, update the sum of MSRs periodically. */ 3268 static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3269 { 3270 int i, ret; 3271 int cpu = t->cpu_id; 3272 3273 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) { 3274 unsigned long long msr_cur, msr_last; 3275 int offset; 3276 3277 if (!idx_valid(i)) 3278 continue; 3279 offset = idx_to_offset(i); 3280 if (offset < 0) 3281 continue; 3282 ret = get_msr(cpu, offset, &msr_cur); 3283 if (ret) { 3284 fprintf(outf, "Can not update msr(0x%x)\n", offset); 3285 continue; 3286 } 3287 3288 msr_last = per_cpu_msr_sum[cpu].entries[i].last; 3289 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff; 3290 3291 DELTA_WRAP32(msr_cur, msr_last); 3292 per_cpu_msr_sum[cpu].entries[i].sum += msr_last; 3293 } 3294 return 0; 3295 } 3296 3297 static void 3298 msr_record_handler(union sigval v) 3299 { 3300 for_all_cpus(update_msr_sum, EVEN_COUNTERS); 3301 } 3302 3303 void msr_sum_record(void) 3304 { 3305 struct itimerspec its; 3306 struct sigevent sev; 3307 3308 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array)); 3309 if (!per_cpu_msr_sum) { 3310 fprintf(outf, "Can not allocate memory for long time MSR.\n"); 3311 return; 3312 } 3313 /* 3314 * Signal handler might be restricted, so use thread notifier instead. 3315 */ 3316 memset(&sev, 0, sizeof(struct sigevent)); 3317 sev.sigev_notify = SIGEV_THREAD; 3318 sev.sigev_notify_function = msr_record_handler; 3319 3320 sev.sigev_value.sival_ptr = &timerid; 3321 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) { 3322 fprintf(outf, "Can not create timer.\n"); 3323 goto release_msr; 3324 } 3325 3326 its.it_value.tv_sec = 0; 3327 its.it_value.tv_nsec = 1; 3328 /* 3329 * A wraparound time has been calculated early. 3330 * Some sources state that the peak power for a 3331 * microprocessor is usually 1.5 times the TDP rating, 3332 * use 2 * TDP for safety. 3333 */ 3334 its.it_interval.tv_sec = rapl_joule_counter_range / 2; 3335 its.it_interval.tv_nsec = 0; 3336 3337 if (timer_settime(timerid, 0, &its, NULL) == -1) { 3338 fprintf(outf, "Can not set timer.\n"); 3339 goto release_timer; 3340 } 3341 return; 3342 3343 release_timer: 3344 timer_delete(timerid); 3345 release_msr: 3346 free(per_cpu_msr_sum); 3347 } 3348 3349 void turbostat_loop() 3350 { 3351 int retval; 3352 int restarted = 0; 3353 int done_iters = 0; 3354 3355 setup_signal_handler(); 3356 3357 restart: 3358 restarted++; 3359 3360 snapshot_proc_sysfs_files(); 3361 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3362 first_counter_read = 0; 3363 if (retval < -1) { 3364 exit(retval); 3365 } else if (retval == -1) { 3366 if (restarted > 10) { 3367 exit(retval); 3368 } 3369 re_initialize(); 3370 goto restart; 3371 } 3372 restarted = 0; 3373 done_iters = 0; 3374 gettimeofday(&tv_even, (struct timezone *)NULL); 3375 3376 while (1) { 3377 if (for_all_proc_cpus(cpu_is_not_present)) { 3378 re_initialize(); 3379 goto restart; 3380 } 3381 do_sleep(); 3382 if (snapshot_proc_sysfs_files()) 3383 goto restart; 3384 retval = for_all_cpus(get_counters, ODD_COUNTERS); 3385 if (retval < -1) { 3386 exit(retval); 3387 } else if (retval == -1) { 3388 re_initialize(); 3389 goto restart; 3390 } 3391 gettimeofday(&tv_odd, (struct timezone *)NULL); 3392 timersub(&tv_odd, &tv_even, &tv_delta); 3393 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 3394 re_initialize(); 3395 goto restart; 3396 } 3397 compute_average(EVEN_COUNTERS); 3398 format_all_counters(EVEN_COUNTERS); 3399 flush_output_stdout(); 3400 if (exit_requested) 3401 break; 3402 if (num_iterations && ++done_iters >= num_iterations) 3403 break; 3404 do_sleep(); 3405 if (snapshot_proc_sysfs_files()) 3406 goto restart; 3407 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3408 if (retval < -1) { 3409 exit(retval); 3410 } else if (retval == -1) { 3411 re_initialize(); 3412 goto restart; 3413 } 3414 gettimeofday(&tv_even, (struct timezone *)NULL); 3415 timersub(&tv_even, &tv_odd, &tv_delta); 3416 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 3417 re_initialize(); 3418 goto restart; 3419 } 3420 compute_average(ODD_COUNTERS); 3421 format_all_counters(ODD_COUNTERS); 3422 flush_output_stdout(); 3423 if (exit_requested) 3424 break; 3425 if (num_iterations && ++done_iters >= num_iterations) 3426 break; 3427 } 3428 } 3429 3430 void check_dev_msr() 3431 { 3432 struct stat sb; 3433 char pathname[32]; 3434 3435 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3436 if (stat(pathname, &sb)) 3437 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 3438 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 3439 } 3440 3441 /* 3442 * check for CAP_SYS_RAWIO 3443 * return 0 on success 3444 * return 1 on fail 3445 */ 3446 int check_for_cap_sys_rawio(void) 3447 { 3448 cap_t caps; 3449 cap_flag_value_t cap_flag_value; 3450 3451 caps = cap_get_proc(); 3452 if (caps == NULL) 3453 err(-6, "cap_get_proc\n"); 3454 3455 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value)) 3456 err(-6, "cap_get\n"); 3457 3458 if (cap_flag_value != CAP_SET) { 3459 warnx("capget(CAP_SYS_RAWIO) failed," 3460 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 3461 return 1; 3462 } 3463 3464 if (cap_free(caps) == -1) 3465 err(-6, "cap_free\n"); 3466 3467 return 0; 3468 } 3469 void check_permissions(void) 3470 { 3471 int do_exit = 0; 3472 char pathname[32]; 3473 3474 /* check for CAP_SYS_RAWIO */ 3475 do_exit += check_for_cap_sys_rawio(); 3476 3477 /* test file permissions */ 3478 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3479 if (euidaccess(pathname, R_OK)) { 3480 do_exit++; 3481 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 3482 } 3483 3484 /* if all else fails, thell them to be root */ 3485 if (do_exit) 3486 if (getuid() != 0) 3487 warnx("... or simply run as root"); 3488 3489 if (do_exit) 3490 exit(-6); 3491 } 3492 3493 /* 3494 * NHM adds support for additional MSRs: 3495 * 3496 * MSR_SMI_COUNT 0x00000034 3497 * 3498 * MSR_PLATFORM_INFO 0x000000ce 3499 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 3500 * 3501 * MSR_MISC_PWR_MGMT 0x000001aa 3502 * 3503 * MSR_PKG_C3_RESIDENCY 0x000003f8 3504 * MSR_PKG_C6_RESIDENCY 0x000003f9 3505 * MSR_CORE_C3_RESIDENCY 0x000003fc 3506 * MSR_CORE_C6_RESIDENCY 0x000003fd 3507 * 3508 * Side effect: 3509 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 3510 * sets has_misc_feature_control 3511 */ 3512 int probe_nhm_msrs(unsigned int family, unsigned int model) 3513 { 3514 unsigned long long msr; 3515 unsigned int base_ratio; 3516 int *pkg_cstate_limits; 3517 3518 if (!genuine_intel) 3519 return 0; 3520 3521 if (family != 6) 3522 return 0; 3523 3524 bclk = discover_bclk(family, model); 3525 3526 switch (model) { 3527 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 3528 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3529 pkg_cstate_limits = nhm_pkg_cstate_limits; 3530 break; 3531 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 3532 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 3533 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3534 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3535 pkg_cstate_limits = snb_pkg_cstate_limits; 3536 has_misc_feature_control = 1; 3537 break; 3538 case INTEL_FAM6_HASWELL: /* HSW */ 3539 case INTEL_FAM6_HASWELL_G: /* HSW */ 3540 case INTEL_FAM6_HASWELL_X: /* HSX */ 3541 case INTEL_FAM6_HASWELL_L: /* HSW */ 3542 case INTEL_FAM6_BROADWELL: /* BDW */ 3543 case INTEL_FAM6_BROADWELL_G: /* BDW */ 3544 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3545 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 3546 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 3547 pkg_cstate_limits = hsw_pkg_cstate_limits; 3548 has_misc_feature_control = 1; 3549 break; 3550 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3551 pkg_cstate_limits = skx_pkg_cstate_limits; 3552 has_misc_feature_control = 1; 3553 break; 3554 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3555 no_MSR_MISC_PWR_MGMT = 1; 3556 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 3557 pkg_cstate_limits = slv_pkg_cstate_limits; 3558 break; 3559 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 3560 pkg_cstate_limits = amt_pkg_cstate_limits; 3561 no_MSR_MISC_PWR_MGMT = 1; 3562 break; 3563 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 3564 pkg_cstate_limits = phi_pkg_cstate_limits; 3565 break; 3566 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3567 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3568 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 3569 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 3570 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 3571 pkg_cstate_limits = glm_pkg_cstate_limits; 3572 break; 3573 default: 3574 return 0; 3575 } 3576 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3577 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3578 3579 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3580 base_ratio = (msr >> 8) & 0xFF; 3581 3582 base_hz = base_ratio * bclk * 1000000; 3583 has_base_hz = 1; 3584 return 1; 3585 } 3586 /* 3587 * SLV client has support for unique MSRs: 3588 * 3589 * MSR_CC6_DEMOTION_POLICY_CONFIG 3590 * MSR_MC6_DEMOTION_POLICY_CONFIG 3591 */ 3592 3593 int has_slv_msrs(unsigned int family, unsigned int model) 3594 { 3595 if (!genuine_intel) 3596 return 0; 3597 3598 switch (model) { 3599 case INTEL_FAM6_ATOM_SILVERMONT: 3600 case INTEL_FAM6_ATOM_SILVERMONT_MID: 3601 case INTEL_FAM6_ATOM_AIRMONT_MID: 3602 return 1; 3603 } 3604 return 0; 3605 } 3606 int is_dnv(unsigned int family, unsigned int model) 3607 { 3608 3609 if (!genuine_intel) 3610 return 0; 3611 3612 switch (model) { 3613 case INTEL_FAM6_ATOM_GOLDMONT_D: 3614 return 1; 3615 } 3616 return 0; 3617 } 3618 int is_bdx(unsigned int family, unsigned int model) 3619 { 3620 3621 if (!genuine_intel) 3622 return 0; 3623 3624 switch (model) { 3625 case INTEL_FAM6_BROADWELL_X: 3626 return 1; 3627 } 3628 return 0; 3629 } 3630 int is_skx(unsigned int family, unsigned int model) 3631 { 3632 3633 if (!genuine_intel) 3634 return 0; 3635 3636 switch (model) { 3637 case INTEL_FAM6_SKYLAKE_X: 3638 return 1; 3639 } 3640 return 0; 3641 } 3642 int is_ehl(unsigned int family, unsigned int model) 3643 { 3644 if (!genuine_intel) 3645 return 0; 3646 3647 switch (model) { 3648 case INTEL_FAM6_ATOM_TREMONT: 3649 return 1; 3650 } 3651 return 0; 3652 } 3653 int is_jvl(unsigned int family, unsigned int model) 3654 { 3655 if (!genuine_intel) 3656 return 0; 3657 3658 switch (model) { 3659 case INTEL_FAM6_ATOM_TREMONT_D: 3660 return 1; 3661 } 3662 return 0; 3663 } 3664 3665 int has_turbo_ratio_limit(unsigned int family, unsigned int model) 3666 { 3667 if (has_slv_msrs(family, model)) 3668 return 0; 3669 3670 switch (model) { 3671 /* Nehalem compatible, but do not include turbo-ratio limit support */ 3672 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3673 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 3674 return 0; 3675 default: 3676 return 1; 3677 } 3678 } 3679 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 3680 { 3681 if (has_slv_msrs(family, model)) 3682 return 1; 3683 3684 return 0; 3685 } 3686 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 3687 { 3688 if (!genuine_intel) 3689 return 0; 3690 3691 if (family != 6) 3692 return 0; 3693 3694 switch (model) { 3695 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3696 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3697 return 1; 3698 default: 3699 return 0; 3700 } 3701 } 3702 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 3703 { 3704 if (!genuine_intel) 3705 return 0; 3706 3707 if (family != 6) 3708 return 0; 3709 3710 switch (model) { 3711 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3712 return 1; 3713 default: 3714 return 0; 3715 } 3716 } 3717 3718 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 3719 { 3720 if (!genuine_intel) 3721 return 0; 3722 3723 if (family != 6) 3724 return 0; 3725 3726 switch (model) { 3727 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3728 return 1; 3729 default: 3730 return 0; 3731 } 3732 } 3733 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) 3734 { 3735 if (!genuine_intel) 3736 return 0; 3737 3738 if (family != 6) 3739 return 0; 3740 3741 switch (model) { 3742 case INTEL_FAM6_ATOM_GOLDMONT: 3743 case INTEL_FAM6_SKYLAKE_X: 3744 return 1; 3745 default: 3746 return 0; 3747 } 3748 } 3749 int has_config_tdp(unsigned int family, unsigned int model) 3750 { 3751 if (!genuine_intel) 3752 return 0; 3753 3754 if (family != 6) 3755 return 0; 3756 3757 switch (model) { 3758 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3759 case INTEL_FAM6_HASWELL: /* HSW */ 3760 case INTEL_FAM6_HASWELL_X: /* HSX */ 3761 case INTEL_FAM6_HASWELL_L: /* HSW */ 3762 case INTEL_FAM6_HASWELL_G: /* HSW */ 3763 case INTEL_FAM6_BROADWELL: /* BDW */ 3764 case INTEL_FAM6_BROADWELL_G: /* BDW */ 3765 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3766 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 3767 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 3768 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3769 3770 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3771 return 1; 3772 default: 3773 return 0; 3774 } 3775 } 3776 3777 static void 3778 remove_underbar(char *s) 3779 { 3780 char *to = s; 3781 3782 while (*s) { 3783 if (*s != '_') 3784 *to++ = *s; 3785 s++; 3786 } 3787 3788 *to = 0; 3789 } 3790 3791 static void 3792 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 3793 { 3794 if (!do_nhm_platform_info) 3795 return; 3796 3797 dump_nhm_platform_info(); 3798 3799 if (has_hsw_turbo_ratio_limit(family, model)) 3800 dump_hsw_turbo_ratio_limits(); 3801 3802 if (has_ivt_turbo_ratio_limit(family, model)) 3803 dump_ivt_turbo_ratio_limits(); 3804 3805 if (has_turbo_ratio_limit(family, model)) 3806 dump_turbo_ratio_limits(family, model); 3807 3808 if (has_atom_turbo_ratio_limit(family, model)) 3809 dump_atom_turbo_ratio_limits(); 3810 3811 if (has_knl_turbo_ratio_limit(family, model)) 3812 dump_knl_turbo_ratio_limits(); 3813 3814 if (has_config_tdp(family, model)) 3815 dump_config_tdp(); 3816 3817 dump_nhm_cst_cfg(); 3818 } 3819 3820 static void dump_sysfs_file(char *path) 3821 { 3822 FILE *input; 3823 char cpuidle_buf[64]; 3824 3825 input = fopen(path, "r"); 3826 if (input == NULL) { 3827 if (debug) 3828 fprintf(outf, "NSFOD %s\n", path); 3829 return; 3830 } 3831 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input)) 3832 err(1, "%s: failed to read file", path); 3833 fclose(input); 3834 3835 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf); 3836 } 3837 static void 3838 dump_sysfs_cstate_config(void) 3839 { 3840 char path[64]; 3841 char name_buf[16]; 3842 char desc[64]; 3843 FILE *input; 3844 int state; 3845 char *sp; 3846 3847 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) { 3848 fprintf(outf, "cpuidle not loaded\n"); 3849 return; 3850 } 3851 3852 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver"); 3853 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor"); 3854 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro"); 3855 3856 for (state = 0; state < 10; ++state) { 3857 3858 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 3859 base_cpu, state); 3860 input = fopen(path, "r"); 3861 if (input == NULL) 3862 continue; 3863 if (!fgets(name_buf, sizeof(name_buf), input)) 3864 err(1, "%s: failed to read file", path); 3865 3866 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 3867 sp = strchr(name_buf, '-'); 3868 if (!sp) 3869 sp = strchrnul(name_buf, '\n'); 3870 *sp = '\0'; 3871 fclose(input); 3872 3873 remove_underbar(name_buf); 3874 3875 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", 3876 base_cpu, state); 3877 input = fopen(path, "r"); 3878 if (input == NULL) 3879 continue; 3880 if (!fgets(desc, sizeof(desc), input)) 3881 err(1, "%s: failed to read file", path); 3882 3883 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 3884 fclose(input); 3885 } 3886 } 3887 static void 3888 dump_sysfs_pstate_config(void) 3889 { 3890 char path[64]; 3891 char driver_buf[64]; 3892 char governor_buf[64]; 3893 FILE *input; 3894 int turbo; 3895 3896 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", 3897 base_cpu); 3898 input = fopen(path, "r"); 3899 if (input == NULL) { 3900 fprintf(outf, "NSFOD %s\n", path); 3901 return; 3902 } 3903 if (!fgets(driver_buf, sizeof(driver_buf), input)) 3904 err(1, "%s: failed to read file", path); 3905 fclose(input); 3906 3907 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", 3908 base_cpu); 3909 input = fopen(path, "r"); 3910 if (input == NULL) { 3911 fprintf(outf, "NSFOD %s\n", path); 3912 return; 3913 } 3914 if (!fgets(governor_buf, sizeof(governor_buf), input)) 3915 err(1, "%s: failed to read file", path); 3916 fclose(input); 3917 3918 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 3919 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 3920 3921 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 3922 input = fopen(path, "r"); 3923 if (input != NULL) { 3924 if (fscanf(input, "%d", &turbo) != 1) 3925 err(1, "%s: failed to parse number from file", path); 3926 fprintf(outf, "cpufreq boost: %d\n", turbo); 3927 fclose(input); 3928 } 3929 3930 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 3931 input = fopen(path, "r"); 3932 if (input != NULL) { 3933 if (fscanf(input, "%d", &turbo) != 1) 3934 err(1, "%s: failed to parse number from file", path); 3935 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 3936 fclose(input); 3937 } 3938 } 3939 3940 3941 /* 3942 * print_epb() 3943 * Decode the ENERGY_PERF_BIAS MSR 3944 */ 3945 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3946 { 3947 char *epb_string; 3948 int cpu, epb; 3949 3950 if (!has_epb) 3951 return 0; 3952 3953 cpu = t->cpu_id; 3954 3955 /* EPB is per-package */ 3956 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3957 return 0; 3958 3959 if (cpu_migrate(cpu)) { 3960 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu); 3961 return -1; 3962 } 3963 3964 epb = get_epb(cpu); 3965 if (epb < 0) 3966 return 0; 3967 3968 switch (epb) { 3969 case ENERGY_PERF_BIAS_PERFORMANCE: 3970 epb_string = "performance"; 3971 break; 3972 case ENERGY_PERF_BIAS_NORMAL: 3973 epb_string = "balanced"; 3974 break; 3975 case ENERGY_PERF_BIAS_POWERSAVE: 3976 epb_string = "powersave"; 3977 break; 3978 default: 3979 epb_string = "custom"; 3980 break; 3981 } 3982 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string); 3983 3984 return 0; 3985 } 3986 /* 3987 * print_hwp() 3988 * Decode the MSR_HWP_CAPABILITIES 3989 */ 3990 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3991 { 3992 unsigned long long msr; 3993 int cpu; 3994 3995 if (!has_hwp) 3996 return 0; 3997 3998 cpu = t->cpu_id; 3999 4000 /* MSR_HWP_CAPABILITIES is per-package */ 4001 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4002 return 0; 4003 4004 if (cpu_migrate(cpu)) { 4005 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu); 4006 return -1; 4007 } 4008 4009 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 4010 return 0; 4011 4012 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 4013 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 4014 4015 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 4016 if ((msr & (1 << 0)) == 0) 4017 return 0; 4018 4019 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 4020 return 0; 4021 4022 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 4023 "(high %d guar %d eff %d low %d)\n", 4024 cpu, msr, 4025 (unsigned int)HWP_HIGHEST_PERF(msr), 4026 (unsigned int)HWP_GUARANTEED_PERF(msr), 4027 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 4028 (unsigned int)HWP_LOWEST_PERF(msr)); 4029 4030 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 4031 return 0; 4032 4033 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 4034 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 4035 cpu, msr, 4036 (unsigned int)(((msr) >> 0) & 0xff), 4037 (unsigned int)(((msr) >> 8) & 0xff), 4038 (unsigned int)(((msr) >> 16) & 0xff), 4039 (unsigned int)(((msr) >> 24) & 0xff), 4040 (unsigned int)(((msr) >> 32) & 0xff3), 4041 (unsigned int)(((msr) >> 42) & 0x1)); 4042 4043 if (has_hwp_pkg) { 4044 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 4045 return 0; 4046 4047 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 4048 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 4049 cpu, msr, 4050 (unsigned int)(((msr) >> 0) & 0xff), 4051 (unsigned int)(((msr) >> 8) & 0xff), 4052 (unsigned int)(((msr) >> 16) & 0xff), 4053 (unsigned int)(((msr) >> 24) & 0xff), 4054 (unsigned int)(((msr) >> 32) & 0xff3)); 4055 } 4056 if (has_hwp_notify) { 4057 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 4058 return 0; 4059 4060 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 4061 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 4062 cpu, msr, 4063 ((msr) & 0x1) ? "EN" : "Dis", 4064 ((msr) & 0x2) ? "EN" : "Dis"); 4065 } 4066 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 4067 return 0; 4068 4069 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 4070 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 4071 cpu, msr, 4072 ((msr) & 0x1) ? "" : "No-", 4073 ((msr) & 0x2) ? "" : "No-"); 4074 4075 return 0; 4076 } 4077 4078 /* 4079 * print_perf_limit() 4080 */ 4081 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4082 { 4083 unsigned long long msr; 4084 int cpu; 4085 4086 cpu = t->cpu_id; 4087 4088 /* per-package */ 4089 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4090 return 0; 4091 4092 if (cpu_migrate(cpu)) { 4093 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu); 4094 return -1; 4095 } 4096 4097 if (do_core_perf_limit_reasons) { 4098 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 4099 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4100 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 4101 (msr & 1 << 15) ? "bit15, " : "", 4102 (msr & 1 << 14) ? "bit14, " : "", 4103 (msr & 1 << 13) ? "Transitions, " : "", 4104 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 4105 (msr & 1 << 11) ? "PkgPwrL2, " : "", 4106 (msr & 1 << 10) ? "PkgPwrL1, " : "", 4107 (msr & 1 << 9) ? "CorePwr, " : "", 4108 (msr & 1 << 8) ? "Amps, " : "", 4109 (msr & 1 << 6) ? "VR-Therm, " : "", 4110 (msr & 1 << 5) ? "Auto-HWP, " : "", 4111 (msr & 1 << 4) ? "Graphics, " : "", 4112 (msr & 1 << 2) ? "bit2, " : "", 4113 (msr & 1 << 1) ? "ThermStatus, " : "", 4114 (msr & 1 << 0) ? "PROCHOT, " : ""); 4115 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 4116 (msr & 1 << 31) ? "bit31, " : "", 4117 (msr & 1 << 30) ? "bit30, " : "", 4118 (msr & 1 << 29) ? "Transitions, " : "", 4119 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 4120 (msr & 1 << 27) ? "PkgPwrL2, " : "", 4121 (msr & 1 << 26) ? "PkgPwrL1, " : "", 4122 (msr & 1 << 25) ? "CorePwr, " : "", 4123 (msr & 1 << 24) ? "Amps, " : "", 4124 (msr & 1 << 22) ? "VR-Therm, " : "", 4125 (msr & 1 << 21) ? "Auto-HWP, " : "", 4126 (msr & 1 << 20) ? "Graphics, " : "", 4127 (msr & 1 << 18) ? "bit18, " : "", 4128 (msr & 1 << 17) ? "ThermStatus, " : "", 4129 (msr & 1 << 16) ? "PROCHOT, " : ""); 4130 4131 } 4132 if (do_gfx_perf_limit_reasons) { 4133 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 4134 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4135 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 4136 (msr & 1 << 0) ? "PROCHOT, " : "", 4137 (msr & 1 << 1) ? "ThermStatus, " : "", 4138 (msr & 1 << 4) ? "Graphics, " : "", 4139 (msr & 1 << 6) ? "VR-Therm, " : "", 4140 (msr & 1 << 8) ? "Amps, " : "", 4141 (msr & 1 << 9) ? "GFXPwr, " : "", 4142 (msr & 1 << 10) ? "PkgPwrL1, " : "", 4143 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4144 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 4145 (msr & 1 << 16) ? "PROCHOT, " : "", 4146 (msr & 1 << 17) ? "ThermStatus, " : "", 4147 (msr & 1 << 20) ? "Graphics, " : "", 4148 (msr & 1 << 22) ? "VR-Therm, " : "", 4149 (msr & 1 << 24) ? "Amps, " : "", 4150 (msr & 1 << 25) ? "GFXPwr, " : "", 4151 (msr & 1 << 26) ? "PkgPwrL1, " : "", 4152 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4153 } 4154 if (do_ring_perf_limit_reasons) { 4155 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 4156 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4157 fprintf(outf, " (Active: %s%s%s%s%s%s)", 4158 (msr & 1 << 0) ? "PROCHOT, " : "", 4159 (msr & 1 << 1) ? "ThermStatus, " : "", 4160 (msr & 1 << 6) ? "VR-Therm, " : "", 4161 (msr & 1 << 8) ? "Amps, " : "", 4162 (msr & 1 << 10) ? "PkgPwrL1, " : "", 4163 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4164 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 4165 (msr & 1 << 16) ? "PROCHOT, " : "", 4166 (msr & 1 << 17) ? "ThermStatus, " : "", 4167 (msr & 1 << 22) ? "VR-Therm, " : "", 4168 (msr & 1 << 24) ? "Amps, " : "", 4169 (msr & 1 << 26) ? "PkgPwrL1, " : "", 4170 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4171 } 4172 return 0; 4173 } 4174 4175 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 4176 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 4177 4178 double get_tdp_intel(unsigned int model) 4179 { 4180 unsigned long long msr; 4181 4182 if (do_rapl & RAPL_PKG_POWER_INFO) 4183 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 4184 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 4185 4186 switch (model) { 4187 case INTEL_FAM6_ATOM_SILVERMONT: 4188 case INTEL_FAM6_ATOM_SILVERMONT_D: 4189 return 30.0; 4190 default: 4191 return 135.0; 4192 } 4193 } 4194 4195 double get_tdp_amd(unsigned int family) 4196 { 4197 /* This is the max stock TDP of HEDT/Server Fam17h+ chips */ 4198 return 280.0; 4199 } 4200 4201 /* 4202 * rapl_dram_energy_units_probe() 4203 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 4204 */ 4205 static double 4206 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 4207 { 4208 /* only called for genuine_intel, family 6 */ 4209 4210 switch (model) { 4211 case INTEL_FAM6_HASWELL_X: /* HSX */ 4212 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4213 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4214 return (rapl_dram_energy_units = 15.3 / 1000000); 4215 default: 4216 return (rapl_energy_units); 4217 } 4218 } 4219 4220 void rapl_probe_intel(unsigned int family, unsigned int model) 4221 { 4222 unsigned long long msr; 4223 unsigned int time_unit; 4224 double tdp; 4225 4226 if (family != 6) 4227 return; 4228 4229 switch (model) { 4230 case INTEL_FAM6_SANDYBRIDGE: 4231 case INTEL_FAM6_IVYBRIDGE: 4232 case INTEL_FAM6_HASWELL: /* HSW */ 4233 case INTEL_FAM6_HASWELL_L: /* HSW */ 4234 case INTEL_FAM6_HASWELL_G: /* HSW */ 4235 case INTEL_FAM6_BROADWELL: /* BDW */ 4236 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4237 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 4238 if (rapl_joules) { 4239 BIC_PRESENT(BIC_Pkg_J); 4240 BIC_PRESENT(BIC_Cor_J); 4241 BIC_PRESENT(BIC_GFX_J); 4242 } else { 4243 BIC_PRESENT(BIC_PkgWatt); 4244 BIC_PRESENT(BIC_CorWatt); 4245 BIC_PRESENT(BIC_GFXWatt); 4246 } 4247 break; 4248 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4249 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4250 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 4251 if (rapl_joules) 4252 BIC_PRESENT(BIC_Pkg_J); 4253 else 4254 BIC_PRESENT(BIC_PkgWatt); 4255 break; 4256 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4257 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO; 4258 if (rapl_joules) { 4259 BIC_PRESENT(BIC_Pkg_J); 4260 BIC_PRESENT(BIC_Cor_J); 4261 BIC_PRESENT(BIC_RAM_J); 4262 BIC_PRESENT(BIC_GFX_J); 4263 } else { 4264 BIC_PRESENT(BIC_PkgWatt); 4265 BIC_PRESENT(BIC_CorWatt); 4266 BIC_PRESENT(BIC_RAMWatt); 4267 BIC_PRESENT(BIC_GFXWatt); 4268 } 4269 break; 4270 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 4271 do_rapl = RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 4272 BIC_PRESENT(BIC_PKG__); 4273 if (rapl_joules) 4274 BIC_PRESENT(BIC_Pkg_J); 4275 else 4276 BIC_PRESENT(BIC_PkgWatt); 4277 break; 4278 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4279 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4280 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO; 4281 BIC_PRESENT(BIC_PKG__); 4282 BIC_PRESENT(BIC_RAM__); 4283 if (rapl_joules) { 4284 BIC_PRESENT(BIC_Pkg_J); 4285 BIC_PRESENT(BIC_Cor_J); 4286 BIC_PRESENT(BIC_RAM_J); 4287 BIC_PRESENT(BIC_GFX_J); 4288 } else { 4289 BIC_PRESENT(BIC_PkgWatt); 4290 BIC_PRESENT(BIC_CorWatt); 4291 BIC_PRESENT(BIC_RAMWatt); 4292 BIC_PRESENT(BIC_GFXWatt); 4293 } 4294 break; 4295 case INTEL_FAM6_HASWELL_X: /* HSX */ 4296 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4297 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4298 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4299 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 4300 BIC_PRESENT(BIC_PKG__); 4301 BIC_PRESENT(BIC_RAM__); 4302 if (rapl_joules) { 4303 BIC_PRESENT(BIC_Pkg_J); 4304 BIC_PRESENT(BIC_RAM_J); 4305 } else { 4306 BIC_PRESENT(BIC_PkgWatt); 4307 BIC_PRESENT(BIC_RAMWatt); 4308 } 4309 break; 4310 case INTEL_FAM6_SANDYBRIDGE_X: 4311 case INTEL_FAM6_IVYBRIDGE_X: 4312 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 4313 BIC_PRESENT(BIC_PKG__); 4314 BIC_PRESENT(BIC_RAM__); 4315 if (rapl_joules) { 4316 BIC_PRESENT(BIC_Pkg_J); 4317 BIC_PRESENT(BIC_Cor_J); 4318 BIC_PRESENT(BIC_RAM_J); 4319 } else { 4320 BIC_PRESENT(BIC_PkgWatt); 4321 BIC_PRESENT(BIC_CorWatt); 4322 BIC_PRESENT(BIC_RAMWatt); 4323 } 4324 break; 4325 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4326 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 4327 do_rapl = RAPL_PKG | RAPL_CORES; 4328 if (rapl_joules) { 4329 BIC_PRESENT(BIC_Pkg_J); 4330 BIC_PRESENT(BIC_Cor_J); 4331 } else { 4332 BIC_PRESENT(BIC_PkgWatt); 4333 BIC_PRESENT(BIC_CorWatt); 4334 } 4335 break; 4336 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 4337 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 4338 BIC_PRESENT(BIC_PKG__); 4339 BIC_PRESENT(BIC_RAM__); 4340 if (rapl_joules) { 4341 BIC_PRESENT(BIC_Pkg_J); 4342 BIC_PRESENT(BIC_Cor_J); 4343 BIC_PRESENT(BIC_RAM_J); 4344 } else { 4345 BIC_PRESENT(BIC_PkgWatt); 4346 BIC_PRESENT(BIC_CorWatt); 4347 BIC_PRESENT(BIC_RAMWatt); 4348 } 4349 break; 4350 default: 4351 return; 4352 } 4353 4354 /* units on package 0, verify later other packages match */ 4355 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 4356 return; 4357 4358 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 4359 if (model == INTEL_FAM6_ATOM_SILVERMONT) 4360 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 4361 else 4362 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 4363 4364 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 4365 4366 time_unit = msr >> 16 & 0xF; 4367 if (time_unit == 0) 4368 time_unit = 0xA; 4369 4370 rapl_time_units = 1.0 / (1 << (time_unit)); 4371 4372 tdp = get_tdp_intel(model); 4373 4374 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4375 if (!quiet) 4376 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4377 } 4378 4379 void rapl_probe_amd(unsigned int family, unsigned int model) 4380 { 4381 unsigned long long msr; 4382 unsigned int eax, ebx, ecx, edx; 4383 unsigned int has_rapl = 0; 4384 double tdp; 4385 4386 if (max_extended_level >= 0x80000007) { 4387 __cpuid(0x80000007, eax, ebx, ecx, edx); 4388 /* RAPL (Fam 17h+) */ 4389 has_rapl = edx & (1 << 14); 4390 } 4391 4392 if (!has_rapl || family < 0x17) 4393 return; 4394 4395 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY; 4396 if (rapl_joules) { 4397 BIC_PRESENT(BIC_Pkg_J); 4398 BIC_PRESENT(BIC_Cor_J); 4399 } else { 4400 BIC_PRESENT(BIC_PkgWatt); 4401 BIC_PRESENT(BIC_CorWatt); 4402 } 4403 4404 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr)) 4405 return; 4406 4407 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf)); 4408 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f)); 4409 rapl_power_units = ldexp(1.0, -(msr & 0xf)); 4410 4411 tdp = get_tdp_amd(family); 4412 4413 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4414 if (!quiet) 4415 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4416 } 4417 4418 /* 4419 * rapl_probe() 4420 * 4421 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 4422 */ 4423 void rapl_probe(unsigned int family, unsigned int model) 4424 { 4425 if (genuine_intel) 4426 rapl_probe_intel(family, model); 4427 if (authentic_amd || hygon_genuine) 4428 rapl_probe_amd(family, model); 4429 } 4430 4431 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 4432 { 4433 if (!genuine_intel) 4434 return; 4435 4436 if (family != 6) 4437 return; 4438 4439 switch (model) { 4440 case INTEL_FAM6_HASWELL: /* HSW */ 4441 case INTEL_FAM6_HASWELL_L: /* HSW */ 4442 case INTEL_FAM6_HASWELL_G: /* HSW */ 4443 do_gfx_perf_limit_reasons = 1; 4444 case INTEL_FAM6_HASWELL_X: /* HSX */ 4445 do_core_perf_limit_reasons = 1; 4446 do_ring_perf_limit_reasons = 1; 4447 default: 4448 return; 4449 } 4450 } 4451 4452 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model) 4453 { 4454 if (is_skx(family, model) || is_bdx(family, model)) 4455 has_automatic_cstate_conversion = 1; 4456 } 4457 4458 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4459 { 4460 unsigned long long msr; 4461 unsigned int dts, dts2; 4462 int cpu; 4463 4464 if (!(do_dts || do_ptm)) 4465 return 0; 4466 4467 cpu = t->cpu_id; 4468 4469 /* DTS is per-core, no need to print for each thread */ 4470 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 4471 return 0; 4472 4473 if (cpu_migrate(cpu)) { 4474 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu); 4475 return -1; 4476 } 4477 4478 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 4479 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 4480 return 0; 4481 4482 dts = (msr >> 16) & 0x7F; 4483 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 4484 cpu, msr, tcc_activation_temp - dts); 4485 4486 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 4487 return 0; 4488 4489 dts = (msr >> 16) & 0x7F; 4490 dts2 = (msr >> 8) & 0x7F; 4491 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4492 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 4493 } 4494 4495 4496 if (do_dts && debug) { 4497 unsigned int resolution; 4498 4499 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 4500 return 0; 4501 4502 dts = (msr >> 16) & 0x7F; 4503 resolution = (msr >> 27) & 0xF; 4504 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 4505 cpu, msr, tcc_activation_temp - dts, resolution); 4506 4507 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 4508 return 0; 4509 4510 dts = (msr >> 16) & 0x7F; 4511 dts2 = (msr >> 8) & 0x7F; 4512 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4513 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 4514 } 4515 4516 return 0; 4517 } 4518 4519 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 4520 { 4521 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 4522 cpu, label, 4523 ((msr >> 15) & 1) ? "EN" : "DIS", 4524 ((msr >> 0) & 0x7FFF) * rapl_power_units, 4525 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 4526 (((msr >> 16) & 1) ? "EN" : "DIS")); 4527 4528 return; 4529 } 4530 4531 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4532 { 4533 unsigned long long msr; 4534 const char *msr_name; 4535 int cpu; 4536 4537 if (!do_rapl) 4538 return 0; 4539 4540 /* RAPL counters are per package, so print only for 1st thread/package */ 4541 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4542 return 0; 4543 4544 cpu = t->cpu_id; 4545 if (cpu_migrate(cpu)) { 4546 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu); 4547 return -1; 4548 } 4549 4550 if (do_rapl & RAPL_AMD_F17H) { 4551 msr_name = "MSR_RAPL_PWR_UNIT"; 4552 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr)) 4553 return -1; 4554 } else { 4555 msr_name = "MSR_RAPL_POWER_UNIT"; 4556 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 4557 return -1; 4558 } 4559 4560 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr, 4561 rapl_power_units, rapl_energy_units, rapl_time_units); 4562 4563 if (do_rapl & RAPL_PKG_POWER_INFO) { 4564 4565 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 4566 return -5; 4567 4568 4569 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4570 cpu, msr, 4571 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4572 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4573 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4574 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4575 4576 } 4577 if (do_rapl & RAPL_PKG) { 4578 4579 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 4580 return -9; 4581 4582 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 4583 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 4584 4585 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 4586 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 4587 cpu, 4588 ((msr >> 47) & 1) ? "EN" : "DIS", 4589 ((msr >> 32) & 0x7FFF) * rapl_power_units, 4590 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 4591 ((msr >> 48) & 1) ? "EN" : "DIS"); 4592 } 4593 4594 if (do_rapl & RAPL_DRAM_POWER_INFO) { 4595 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 4596 return -6; 4597 4598 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4599 cpu, msr, 4600 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4601 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4602 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4603 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4604 } 4605 if (do_rapl & RAPL_DRAM) { 4606 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 4607 return -9; 4608 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 4609 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4610 4611 print_power_limit_msr(cpu, msr, "DRAM Limit"); 4612 } 4613 if (do_rapl & RAPL_CORE_POLICY) { 4614 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 4615 return -7; 4616 4617 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 4618 } 4619 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 4620 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 4621 return -9; 4622 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 4623 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4624 print_power_limit_msr(cpu, msr, "Cores Limit"); 4625 } 4626 if (do_rapl & RAPL_GFX) { 4627 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 4628 return -8; 4629 4630 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 4631 4632 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 4633 return -9; 4634 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 4635 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4636 print_power_limit_msr(cpu, msr, "GFX Limit"); 4637 } 4638 return 0; 4639 } 4640 4641 /* 4642 * SNB adds support for additional MSRs: 4643 * 4644 * MSR_PKG_C7_RESIDENCY 0x000003fa 4645 * MSR_CORE_C7_RESIDENCY 0x000003fe 4646 * MSR_PKG_C2_RESIDENCY 0x0000060d 4647 */ 4648 4649 int has_snb_msrs(unsigned int family, unsigned int model) 4650 { 4651 if (!genuine_intel) 4652 return 0; 4653 4654 switch (model) { 4655 case INTEL_FAM6_SANDYBRIDGE: 4656 case INTEL_FAM6_SANDYBRIDGE_X: 4657 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 4658 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 4659 case INTEL_FAM6_HASWELL: /* HSW */ 4660 case INTEL_FAM6_HASWELL_X: /* HSW */ 4661 case INTEL_FAM6_HASWELL_L: /* HSW */ 4662 case INTEL_FAM6_HASWELL_G: /* HSW */ 4663 case INTEL_FAM6_BROADWELL: /* BDW */ 4664 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4665 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4666 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4667 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4668 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4669 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4670 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4671 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 4672 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4673 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 4674 return 1; 4675 } 4676 return 0; 4677 } 4678 4679 /* 4680 * HSW ULT added support for C8/C9/C10 MSRs: 4681 * 4682 * MSR_PKG_C8_RESIDENCY 0x00000630 4683 * MSR_PKG_C9_RESIDENCY 0x00000631 4684 * MSR_PKG_C10_RESIDENCY 0x00000632 4685 * 4686 * MSR_PKGC8_IRTL 0x00000633 4687 * MSR_PKGC9_IRTL 0x00000634 4688 * MSR_PKGC10_IRTL 0x00000635 4689 * 4690 */ 4691 int has_c8910_msrs(unsigned int family, unsigned int model) 4692 { 4693 if (!genuine_intel) 4694 return 0; 4695 4696 switch (model) { 4697 case INTEL_FAM6_HASWELL_L: /* HSW */ 4698 case INTEL_FAM6_BROADWELL: /* BDW */ 4699 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4700 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4701 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4702 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4703 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4704 return 1; 4705 } 4706 return 0; 4707 } 4708 4709 /* 4710 * SKL adds support for additional MSRS: 4711 * 4712 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 4713 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 4714 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 4715 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 4716 */ 4717 int has_skl_msrs(unsigned int family, unsigned int model) 4718 { 4719 if (!genuine_intel) 4720 return 0; 4721 4722 switch (model) { 4723 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4724 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4725 return 1; 4726 } 4727 return 0; 4728 } 4729 4730 int is_slm(unsigned int family, unsigned int model) 4731 { 4732 if (!genuine_intel) 4733 return 0; 4734 switch (model) { 4735 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4736 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 4737 return 1; 4738 } 4739 return 0; 4740 } 4741 4742 int is_knl(unsigned int family, unsigned int model) 4743 { 4744 if (!genuine_intel) 4745 return 0; 4746 switch (model) { 4747 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4748 return 1; 4749 } 4750 return 0; 4751 } 4752 4753 int is_cnl(unsigned int family, unsigned int model) 4754 { 4755 if (!genuine_intel) 4756 return 0; 4757 4758 switch (model) { 4759 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4760 return 1; 4761 } 4762 4763 return 0; 4764 } 4765 4766 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 4767 { 4768 if (is_knl(family, model)) 4769 return 1024; 4770 return 1; 4771 } 4772 4773 #define SLM_BCLK_FREQS 5 4774 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 4775 4776 double slm_bclk(void) 4777 { 4778 unsigned long long msr = 3; 4779 unsigned int i; 4780 double freq; 4781 4782 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 4783 fprintf(outf, "SLM BCLK: unknown\n"); 4784 4785 i = msr & 0xf; 4786 if (i >= SLM_BCLK_FREQS) { 4787 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 4788 i = 3; 4789 } 4790 freq = slm_freq_table[i]; 4791 4792 if (!quiet) 4793 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 4794 4795 return freq; 4796 } 4797 4798 double discover_bclk(unsigned int family, unsigned int model) 4799 { 4800 if (has_snb_msrs(family, model) || is_knl(family, model)) 4801 return 100.00; 4802 else if (is_slm(family, model)) 4803 return slm_bclk(); 4804 else 4805 return 133.33; 4806 } 4807 4808 /* 4809 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 4810 * the Thermal Control Circuit (TCC) activates. 4811 * This is usually equal to tjMax. 4812 * 4813 * Older processors do not have this MSR, so there we guess, 4814 * but also allow cmdline over-ride with -T. 4815 * 4816 * Several MSR temperature values are in units of degrees-C 4817 * below this value, including the Digital Thermal Sensor (DTS), 4818 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 4819 */ 4820 int read_tcc_activation_temp() 4821 { 4822 unsigned long long msr; 4823 unsigned int tcc, target_c, offset_c; 4824 4825 /* Temperature Target MSR is Nehalem and newer only */ 4826 if (!do_nhm_platform_info) 4827 return 0; 4828 4829 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 4830 return 0; 4831 4832 target_c = (msr >> 16) & 0xFF; 4833 4834 offset_c = (msr >> 24) & 0xF; 4835 4836 tcc = target_c - offset_c; 4837 4838 if (!quiet) 4839 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n", 4840 base_cpu, msr, tcc, target_c, offset_c); 4841 4842 return tcc; 4843 } 4844 4845 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4846 { 4847 /* tcc_activation_temp is used only for dts or ptm */ 4848 if (!(do_dts || do_ptm)) 4849 return 0; 4850 4851 /* this is a per-package concept */ 4852 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4853 return 0; 4854 4855 if (tcc_activation_temp_override != 0) { 4856 tcc_activation_temp = tcc_activation_temp_override; 4857 fprintf(outf, "Using cmdline TCC Target (%d C)\n", tcc_activation_temp); 4858 return 0; 4859 } 4860 4861 tcc_activation_temp = read_tcc_activation_temp(); 4862 if (tcc_activation_temp) 4863 return 0; 4864 4865 tcc_activation_temp = TJMAX_DEFAULT; 4866 fprintf(outf, "Guessing tjMax %d C, Please use -T to specify\n", tcc_activation_temp); 4867 4868 return 0; 4869 } 4870 4871 void decode_feature_control_msr(void) 4872 { 4873 unsigned long long msr; 4874 4875 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr)) 4876 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 4877 base_cpu, msr, 4878 msr & FEAT_CTL_LOCKED ? "" : "UN-", 4879 msr & (1 << 18) ? "SGX" : ""); 4880 } 4881 4882 void decode_misc_enable_msr(void) 4883 { 4884 unsigned long long msr; 4885 4886 if (!genuine_intel) 4887 return; 4888 4889 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 4890 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 4891 base_cpu, msr, 4892 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 4893 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 4894 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 4895 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 4896 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 4897 } 4898 4899 void decode_misc_feature_control(void) 4900 { 4901 unsigned long long msr; 4902 4903 if (!has_misc_feature_control) 4904 return; 4905 4906 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 4907 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 4908 base_cpu, msr, 4909 msr & (0 << 0) ? "No-" : "", 4910 msr & (1 << 0) ? "No-" : "", 4911 msr & (2 << 0) ? "No-" : "", 4912 msr & (3 << 0) ? "No-" : ""); 4913 } 4914 /* 4915 * Decode MSR_MISC_PWR_MGMT 4916 * 4917 * Decode the bits according to the Nehalem documentation 4918 * bit[0] seems to continue to have same meaning going forward 4919 * bit[1] less so... 4920 */ 4921 void decode_misc_pwr_mgmt_msr(void) 4922 { 4923 unsigned long long msr; 4924 4925 if (!do_nhm_platform_info) 4926 return; 4927 4928 if (no_MSR_MISC_PWR_MGMT) 4929 return; 4930 4931 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 4932 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 4933 base_cpu, msr, 4934 msr & (1 << 0) ? "DIS" : "EN", 4935 msr & (1 << 1) ? "EN" : "DIS", 4936 msr & (1 << 8) ? "EN" : "DIS"); 4937 } 4938 /* 4939 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 4940 * 4941 * This MSRs are present on Silvermont processors, 4942 * Intel Atom processor E3000 series (Baytrail), and friends. 4943 */ 4944 void decode_c6_demotion_policy_msr(void) 4945 { 4946 unsigned long long msr; 4947 4948 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 4949 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 4950 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4951 4952 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 4953 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 4954 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4955 } 4956 4957 /* 4958 * When models are the same, for the purpose of turbostat, reuse 4959 */ 4960 unsigned int intel_model_duplicates(unsigned int model) 4961 { 4962 4963 switch(model) { 4964 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 4965 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 4966 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 4967 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 4968 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 4969 return INTEL_FAM6_NEHALEM; 4970 4971 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 4972 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 4973 return INTEL_FAM6_NEHALEM_EX; 4974 4975 case INTEL_FAM6_XEON_PHI_KNM: 4976 return INTEL_FAM6_XEON_PHI_KNL; 4977 4978 case INTEL_FAM6_BROADWELL_X: 4979 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */ 4980 return INTEL_FAM6_BROADWELL_X; 4981 4982 case INTEL_FAM6_SKYLAKE_L: 4983 case INTEL_FAM6_SKYLAKE: 4984 case INTEL_FAM6_KABYLAKE_L: 4985 case INTEL_FAM6_KABYLAKE: 4986 case INTEL_FAM6_COMETLAKE_L: 4987 case INTEL_FAM6_COMETLAKE: 4988 return INTEL_FAM6_SKYLAKE_L; 4989 4990 case INTEL_FAM6_ICELAKE_L: 4991 case INTEL_FAM6_ICELAKE_NNPI: 4992 case INTEL_FAM6_TIGERLAKE_L: 4993 case INTEL_FAM6_TIGERLAKE: 4994 case INTEL_FAM6_ROCKETLAKE: 4995 case INTEL_FAM6_LAKEFIELD: 4996 case INTEL_FAM6_ALDERLAKE: 4997 return INTEL_FAM6_CANNONLAKE_L; 4998 4999 case INTEL_FAM6_ATOM_TREMONT_L: 5000 return INTEL_FAM6_ATOM_TREMONT; 5001 5002 case INTEL_FAM6_ICELAKE_X: 5003 case INTEL_FAM6_SAPPHIRERAPIDS_X: 5004 return INTEL_FAM6_SKYLAKE_X; 5005 } 5006 return model; 5007 } 5008 5009 void print_dev_latency(void) 5010 { 5011 char *path = "/dev/cpu_dma_latency"; 5012 int fd; 5013 int value; 5014 int retval; 5015 5016 fd = open(path, O_RDONLY); 5017 if (fd < 0) { 5018 warn("fopen %s\n", path); 5019 return; 5020 } 5021 5022 retval = read(fd, (void *)&value, sizeof(int)); 5023 if (retval != sizeof(int)) { 5024 warn("read %s\n", path); 5025 close(fd); 5026 return; 5027 } 5028 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", 5029 value, value == 2000000000 ? "default" : "constrained"); 5030 5031 close(fd); 5032 } 5033 5034 void process_cpuid() 5035 { 5036 unsigned int eax, ebx, ecx, edx; 5037 unsigned int fms, family, model, stepping, ecx_flags, edx_flags; 5038 unsigned int has_turbo; 5039 5040 eax = ebx = ecx = edx = 0; 5041 5042 __cpuid(0, max_level, ebx, ecx, edx); 5043 5044 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) 5045 genuine_intel = 1; 5046 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) 5047 authentic_amd = 1; 5048 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e) 5049 hygon_genuine = 1; 5050 5051 if (!quiet) 5052 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 5053 (char *)&ebx, (char *)&edx, (char *)&ecx); 5054 5055 __cpuid(1, fms, ebx, ecx, edx); 5056 family = (fms >> 8) & 0xf; 5057 model = (fms >> 4) & 0xf; 5058 stepping = fms & 0xf; 5059 if (family == 0xf) 5060 family += (fms >> 20) & 0xff; 5061 if (family >= 6) 5062 model += ((fms >> 16) & 0xf) << 4; 5063 ecx_flags = ecx; 5064 edx_flags = edx; 5065 5066 /* 5067 * check max extended function levels of CPUID. 5068 * This is needed to check for invariant TSC. 5069 * This check is valid for both Intel and AMD. 5070 */ 5071 ebx = ecx = edx = 0; 5072 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 5073 5074 if (!quiet) { 5075 fprintf(outf, "0x%x CPUID levels; 0x%x xlevels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 5076 max_level, max_extended_level, family, model, stepping, family, model, stepping); 5077 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 5078 ecx_flags & (1 << 0) ? "SSE3" : "-", 5079 ecx_flags & (1 << 3) ? "MONITOR" : "-", 5080 ecx_flags & (1 << 6) ? "SMX" : "-", 5081 ecx_flags & (1 << 7) ? "EIST" : "-", 5082 ecx_flags & (1 << 8) ? "TM2" : "-", 5083 edx_flags & (1 << 4) ? "TSC" : "-", 5084 edx_flags & (1 << 5) ? "MSR" : "-", 5085 edx_flags & (1 << 22) ? "ACPI-TM" : "-", 5086 edx_flags & (1 << 28) ? "HT" : "-", 5087 edx_flags & (1 << 29) ? "TM" : "-"); 5088 } 5089 if (genuine_intel) 5090 model = intel_model_duplicates(model); 5091 5092 if (!(edx_flags & (1 << 5))) 5093 errx(1, "CPUID: no MSR"); 5094 5095 if (max_extended_level >= 0x80000007) { 5096 5097 /* 5098 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 5099 * this check is valid for both Intel and AMD 5100 */ 5101 __cpuid(0x80000007, eax, ebx, ecx, edx); 5102 has_invariant_tsc = edx & (1 << 8); 5103 } 5104 5105 /* 5106 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 5107 * this check is valid for both Intel and AMD 5108 */ 5109 5110 __cpuid(0x6, eax, ebx, ecx, edx); 5111 has_aperf = ecx & (1 << 0); 5112 if (has_aperf) { 5113 BIC_PRESENT(BIC_Avg_MHz); 5114 BIC_PRESENT(BIC_Busy); 5115 BIC_PRESENT(BIC_Bzy_MHz); 5116 } 5117 do_dts = eax & (1 << 0); 5118 if (do_dts) 5119 BIC_PRESENT(BIC_CoreTmp); 5120 has_turbo = eax & (1 << 1); 5121 do_ptm = eax & (1 << 6); 5122 if (do_ptm) 5123 BIC_PRESENT(BIC_PkgTmp); 5124 has_hwp = eax & (1 << 7); 5125 has_hwp_notify = eax & (1 << 8); 5126 has_hwp_activity_window = eax & (1 << 9); 5127 has_hwp_epp = eax & (1 << 10); 5128 has_hwp_pkg = eax & (1 << 11); 5129 has_epb = ecx & (1 << 3); 5130 5131 if (!quiet) 5132 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 5133 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 5134 has_aperf ? "" : "No-", 5135 has_turbo ? "" : "No-", 5136 do_dts ? "" : "No-", 5137 do_ptm ? "" : "No-", 5138 has_hwp ? "" : "No-", 5139 has_hwp_notify ? "" : "No-", 5140 has_hwp_activity_window ? "" : "No-", 5141 has_hwp_epp ? "" : "No-", 5142 has_hwp_pkg ? "" : "No-", 5143 has_epb ? "" : "No-"); 5144 5145 if (!quiet) 5146 decode_misc_enable_msr(); 5147 5148 5149 if (max_level >= 0x7 && !quiet) { 5150 int has_sgx; 5151 5152 ecx = 0; 5153 5154 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 5155 5156 has_sgx = ebx & (1 << 2); 5157 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 5158 5159 if (has_sgx) 5160 decode_feature_control_msr(); 5161 } 5162 5163 if (max_level >= 0x15) { 5164 unsigned int eax_crystal; 5165 unsigned int ebx_tsc; 5166 5167 /* 5168 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 5169 */ 5170 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 5171 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 5172 5173 if (ebx_tsc != 0) { 5174 5175 if (!quiet && (ebx != 0)) 5176 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 5177 eax_crystal, ebx_tsc, crystal_hz); 5178 5179 if (crystal_hz == 0) 5180 switch(model) { 5181 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5182 crystal_hz = 24000000; /* 24.0 MHz */ 5183 break; 5184 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 5185 crystal_hz = 25000000; /* 25.0 MHz */ 5186 break; 5187 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 5188 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5189 crystal_hz = 19200000; /* 19.2 MHz */ 5190 break; 5191 default: 5192 crystal_hz = 0; 5193 } 5194 5195 if (crystal_hz) { 5196 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 5197 if (!quiet) 5198 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 5199 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 5200 } 5201 } 5202 } 5203 if (max_level >= 0x16) { 5204 unsigned int base_mhz, max_mhz, bus_mhz, edx; 5205 5206 /* 5207 * CPUID 16H Base MHz, Max MHz, Bus MHz 5208 */ 5209 base_mhz = max_mhz = bus_mhz = edx = 0; 5210 5211 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 5212 if (!quiet) 5213 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 5214 base_mhz, max_mhz, bus_mhz); 5215 } 5216 5217 if (has_aperf) 5218 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 5219 5220 BIC_PRESENT(BIC_IRQ); 5221 BIC_PRESENT(BIC_TSC_MHz); 5222 5223 if (probe_nhm_msrs(family, model)) { 5224 do_nhm_platform_info = 1; 5225 BIC_PRESENT(BIC_CPU_c1); 5226 BIC_PRESENT(BIC_CPU_c3); 5227 BIC_PRESENT(BIC_CPU_c6); 5228 BIC_PRESENT(BIC_SMI); 5229 } 5230 do_snb_cstates = has_snb_msrs(family, model); 5231 5232 if (do_snb_cstates) 5233 BIC_PRESENT(BIC_CPU_c7); 5234 5235 do_irtl_snb = has_snb_msrs(family, model); 5236 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 5237 BIC_PRESENT(BIC_Pkgpc2); 5238 if (pkg_cstate_limit >= PCL__3) 5239 BIC_PRESENT(BIC_Pkgpc3); 5240 if (pkg_cstate_limit >= PCL__6) 5241 BIC_PRESENT(BIC_Pkgpc6); 5242 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 5243 BIC_PRESENT(BIC_Pkgpc7); 5244 if (has_slv_msrs(family, model)) { 5245 BIC_NOT_PRESENT(BIC_Pkgpc2); 5246 BIC_NOT_PRESENT(BIC_Pkgpc3); 5247 BIC_PRESENT(BIC_Pkgpc6); 5248 BIC_NOT_PRESENT(BIC_Pkgpc7); 5249 BIC_PRESENT(BIC_Mod_c6); 5250 use_c1_residency_msr = 1; 5251 } 5252 if (is_jvl(family, model)) { 5253 BIC_NOT_PRESENT(BIC_CPU_c3); 5254 BIC_NOT_PRESENT(BIC_CPU_c7); 5255 BIC_NOT_PRESENT(BIC_Pkgpc2); 5256 BIC_NOT_PRESENT(BIC_Pkgpc3); 5257 BIC_NOT_PRESENT(BIC_Pkgpc6); 5258 BIC_NOT_PRESENT(BIC_Pkgpc7); 5259 } 5260 if (is_dnv(family, model)) { 5261 BIC_PRESENT(BIC_CPU_c1); 5262 BIC_NOT_PRESENT(BIC_CPU_c3); 5263 BIC_NOT_PRESENT(BIC_Pkgpc3); 5264 BIC_NOT_PRESENT(BIC_CPU_c7); 5265 BIC_NOT_PRESENT(BIC_Pkgpc7); 5266 use_c1_residency_msr = 1; 5267 } 5268 if (is_skx(family, model)) { 5269 BIC_NOT_PRESENT(BIC_CPU_c3); 5270 BIC_NOT_PRESENT(BIC_Pkgpc3); 5271 BIC_NOT_PRESENT(BIC_CPU_c7); 5272 BIC_NOT_PRESENT(BIC_Pkgpc7); 5273 } 5274 if (is_bdx(family, model)) { 5275 BIC_NOT_PRESENT(BIC_CPU_c7); 5276 BIC_NOT_PRESENT(BIC_Pkgpc7); 5277 } 5278 if (has_c8910_msrs(family, model)) { 5279 if (pkg_cstate_limit >= PCL__8) 5280 BIC_PRESENT(BIC_Pkgpc8); 5281 if (pkg_cstate_limit >= PCL__9) 5282 BIC_PRESENT(BIC_Pkgpc9); 5283 if (pkg_cstate_limit >= PCL_10) 5284 BIC_PRESENT(BIC_Pkgpc10); 5285 } 5286 do_irtl_hsw = has_c8910_msrs(family, model); 5287 if (has_skl_msrs(family, model)) { 5288 BIC_PRESENT(BIC_Totl_c0); 5289 BIC_PRESENT(BIC_Any_c0); 5290 BIC_PRESENT(BIC_GFX_c0); 5291 BIC_PRESENT(BIC_CPUGFX); 5292 } 5293 do_slm_cstates = is_slm(family, model); 5294 do_knl_cstates = is_knl(family, model); 5295 5296 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || 5297 is_ehl(family, model)) 5298 BIC_NOT_PRESENT(BIC_CPU_c3); 5299 5300 if (!quiet) 5301 decode_misc_pwr_mgmt_msr(); 5302 5303 if (!quiet && has_slv_msrs(family, model)) 5304 decode_c6_demotion_policy_msr(); 5305 5306 rapl_probe(family, model); 5307 perf_limit_reasons_probe(family, model); 5308 automatic_cstate_conversion_probe(family, model); 5309 5310 if (!quiet) 5311 dump_cstate_pstate_config_info(family, model); 5312 5313 if (!quiet) 5314 print_dev_latency(); 5315 if (!quiet) 5316 dump_sysfs_cstate_config(); 5317 if (!quiet) 5318 dump_sysfs_pstate_config(); 5319 5320 if (has_skl_msrs(family, model)) 5321 calculate_tsc_tweak(); 5322 5323 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 5324 BIC_PRESENT(BIC_GFX_rc6); 5325 5326 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 5327 BIC_PRESENT(BIC_GFXMHz); 5328 5329 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK)) 5330 BIC_PRESENT(BIC_GFXACTMHz); 5331 5332 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 5333 BIC_PRESENT(BIC_CPU_LPI); 5334 else 5335 BIC_NOT_PRESENT(BIC_CPU_LPI); 5336 5337 if (!access(sys_lpi_file_sysfs, R_OK)) { 5338 sys_lpi_file = sys_lpi_file_sysfs; 5339 BIC_PRESENT(BIC_SYS_LPI); 5340 } else if (!access(sys_lpi_file_debugfs, R_OK)) { 5341 sys_lpi_file = sys_lpi_file_debugfs; 5342 BIC_PRESENT(BIC_SYS_LPI); 5343 } else { 5344 sys_lpi_file_sysfs = NULL; 5345 BIC_NOT_PRESENT(BIC_SYS_LPI); 5346 } 5347 5348 if (!quiet) 5349 decode_misc_feature_control(); 5350 5351 return; 5352 } 5353 5354 /* 5355 * in /dev/cpu/ return success for names that are numbers 5356 * ie. filter out ".", "..", "microcode". 5357 */ 5358 int dir_filter(const struct dirent *dirp) 5359 { 5360 if (isdigit(dirp->d_name[0])) 5361 return 1; 5362 else 5363 return 0; 5364 } 5365 5366 int open_dev_cpu_msr(int dummy1) 5367 { 5368 return 0; 5369 } 5370 5371 void topology_probe() 5372 { 5373 int i; 5374 int max_core_id = 0; 5375 int max_package_id = 0; 5376 int max_die_id = 0; 5377 int max_siblings = 0; 5378 5379 /* Initialize num_cpus, max_cpu_num */ 5380 set_max_cpu_num(); 5381 topo.num_cpus = 0; 5382 for_all_proc_cpus(count_cpus); 5383 if (!summary_only && topo.num_cpus > 1) 5384 BIC_PRESENT(BIC_CPU); 5385 5386 if (debug > 1) 5387 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 5388 5389 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 5390 if (cpus == NULL) 5391 err(1, "calloc cpus"); 5392 5393 /* 5394 * Allocate and initialize cpu_present_set 5395 */ 5396 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5397 if (cpu_present_set == NULL) 5398 err(3, "CPU_ALLOC"); 5399 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5400 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 5401 for_all_proc_cpus(mark_cpu_present); 5402 5403 /* 5404 * Validate that all cpus in cpu_subset are also in cpu_present_set 5405 */ 5406 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 5407 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 5408 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) 5409 err(1, "cpu%d not present", i); 5410 } 5411 5412 /* 5413 * Allocate and initialize cpu_affinity_set 5414 */ 5415 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5416 if (cpu_affinity_set == NULL) 5417 err(3, "CPU_ALLOC"); 5418 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5419 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 5420 5421 for_all_proc_cpus(init_thread_id); 5422 5423 /* 5424 * For online cpus 5425 * find max_core_id, max_package_id 5426 */ 5427 for (i = 0; i <= topo.max_cpu_num; ++i) { 5428 int siblings; 5429 5430 if (cpu_is_not_present(i)) { 5431 if (debug > 1) 5432 fprintf(outf, "cpu%d NOT PRESENT\n", i); 5433 continue; 5434 } 5435 5436 cpus[i].logical_cpu_id = i; 5437 5438 /* get package information */ 5439 cpus[i].physical_package_id = get_physical_package_id(i); 5440 if (cpus[i].physical_package_id > max_package_id) 5441 max_package_id = cpus[i].physical_package_id; 5442 5443 /* get die information */ 5444 cpus[i].die_id = get_die_id(i); 5445 if (cpus[i].die_id > max_die_id) 5446 max_die_id = cpus[i].die_id; 5447 5448 /* get numa node information */ 5449 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 5450 if (cpus[i].physical_node_id > topo.max_node_num) 5451 topo.max_node_num = cpus[i].physical_node_id; 5452 5453 /* get core information */ 5454 cpus[i].physical_core_id = get_core_id(i); 5455 if (cpus[i].physical_core_id > max_core_id) 5456 max_core_id = cpus[i].physical_core_id; 5457 5458 /* get thread information */ 5459 siblings = get_thread_siblings(&cpus[i]); 5460 if (siblings > max_siblings) 5461 max_siblings = siblings; 5462 if (cpus[i].thread_id == 0) 5463 topo.num_cores++; 5464 } 5465 5466 topo.cores_per_node = max_core_id + 1; 5467 if (debug > 1) 5468 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 5469 max_core_id, topo.cores_per_node); 5470 if (!summary_only && topo.cores_per_node > 1) 5471 BIC_PRESENT(BIC_Core); 5472 5473 topo.num_die = max_die_id + 1; 5474 if (debug > 1) 5475 fprintf(outf, "max_die_id %d, sizing for %d die\n", 5476 max_die_id, topo.num_die); 5477 if (!summary_only && topo.num_die > 1) 5478 BIC_PRESENT(BIC_Die); 5479 5480 topo.num_packages = max_package_id + 1; 5481 if (debug > 1) 5482 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 5483 max_package_id, topo.num_packages); 5484 if (!summary_only && topo.num_packages > 1) 5485 BIC_PRESENT(BIC_Package); 5486 5487 set_node_data(); 5488 if (debug > 1) 5489 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 5490 if (!summary_only && topo.nodes_per_pkg > 1) 5491 BIC_PRESENT(BIC_Node); 5492 5493 topo.threads_per_core = max_siblings; 5494 if (debug > 1) 5495 fprintf(outf, "max_siblings %d\n", max_siblings); 5496 5497 if (debug < 1) 5498 return; 5499 5500 for (i = 0; i <= topo.max_cpu_num; ++i) { 5501 if (cpu_is_not_present(i)) 5502 continue; 5503 fprintf(outf, 5504 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n", 5505 i, cpus[i].physical_package_id, cpus[i].die_id, 5506 cpus[i].physical_node_id, 5507 cpus[i].logical_node_id, 5508 cpus[i].physical_core_id, 5509 cpus[i].thread_id); 5510 } 5511 5512 } 5513 5514 void 5515 allocate_counters(struct thread_data **t, struct core_data **c, 5516 struct pkg_data **p) 5517 { 5518 int i; 5519 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * 5520 topo.num_packages; 5521 int num_threads = topo.threads_per_core * num_cores; 5522 5523 *t = calloc(num_threads, sizeof(struct thread_data)); 5524 if (*t == NULL) 5525 goto error; 5526 5527 for (i = 0; i < num_threads; i++) 5528 (*t)[i].cpu_id = -1; 5529 5530 *c = calloc(num_cores, sizeof(struct core_data)); 5531 if (*c == NULL) 5532 goto error; 5533 5534 for (i = 0; i < num_cores; i++) 5535 (*c)[i].core_id = -1; 5536 5537 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 5538 if (*p == NULL) 5539 goto error; 5540 5541 for (i = 0; i < topo.num_packages; i++) 5542 (*p)[i].package_id = i; 5543 5544 return; 5545 error: 5546 err(1, "calloc counters"); 5547 } 5548 /* 5549 * init_counter() 5550 * 5551 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 5552 */ 5553 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 5554 struct pkg_data *pkg_base, int cpu_id) 5555 { 5556 int pkg_id = cpus[cpu_id].physical_package_id; 5557 int node_id = cpus[cpu_id].logical_node_id; 5558 int core_id = cpus[cpu_id].physical_core_id; 5559 int thread_id = cpus[cpu_id].thread_id; 5560 struct thread_data *t; 5561 struct core_data *c; 5562 struct pkg_data *p; 5563 5564 5565 /* Workaround for systems where physical_node_id==-1 5566 * and logical_node_id==(-1 - topo.num_cpus) 5567 */ 5568 if (node_id < 0) 5569 node_id = 0; 5570 5571 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 5572 c = GET_CORE(core_base, core_id, node_id, pkg_id); 5573 p = GET_PKG(pkg_base, pkg_id); 5574 5575 t->cpu_id = cpu_id; 5576 if (thread_id == 0) { 5577 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 5578 if (cpu_is_first_core_in_package(cpu_id)) 5579 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 5580 } 5581 5582 c->core_id = core_id; 5583 p->package_id = pkg_id; 5584 } 5585 5586 5587 int initialize_counters(int cpu_id) 5588 { 5589 init_counter(EVEN_COUNTERS, cpu_id); 5590 init_counter(ODD_COUNTERS, cpu_id); 5591 return 0; 5592 } 5593 5594 void allocate_output_buffer() 5595 { 5596 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048); 5597 outp = output_buffer; 5598 if (outp == NULL) 5599 err(-1, "calloc output buffer"); 5600 } 5601 void allocate_fd_percpu(void) 5602 { 5603 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5604 if (fd_percpu == NULL) 5605 err(-1, "calloc fd_percpu"); 5606 } 5607 void allocate_irq_buffers(void) 5608 { 5609 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 5610 if (irq_column_2_cpu == NULL) 5611 err(-1, "calloc %d", topo.num_cpus); 5612 5613 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5614 if (irqs_per_cpu == NULL) 5615 err(-1, "calloc %d", topo.max_cpu_num + 1); 5616 } 5617 void setup_all_buffers(void) 5618 { 5619 topology_probe(); 5620 allocate_irq_buffers(); 5621 allocate_fd_percpu(); 5622 allocate_counters(&thread_even, &core_even, &package_even); 5623 allocate_counters(&thread_odd, &core_odd, &package_odd); 5624 allocate_output_buffer(); 5625 for_all_proc_cpus(initialize_counters); 5626 } 5627 5628 void set_base_cpu(void) 5629 { 5630 base_cpu = sched_getcpu(); 5631 if (base_cpu < 0) 5632 err(-ENODEV, "No valid cpus found"); 5633 5634 if (debug > 1) 5635 fprintf(outf, "base_cpu = %d\n", base_cpu); 5636 } 5637 5638 void turbostat_init() 5639 { 5640 setup_all_buffers(); 5641 set_base_cpu(); 5642 check_dev_msr(); 5643 check_permissions(); 5644 process_cpuid(); 5645 5646 5647 if (!quiet) 5648 for_all_cpus(print_hwp, ODD_COUNTERS); 5649 5650 if (!quiet) 5651 for_all_cpus(print_epb, ODD_COUNTERS); 5652 5653 if (!quiet) 5654 for_all_cpus(print_perf_limit, ODD_COUNTERS); 5655 5656 if (!quiet) 5657 for_all_cpus(print_rapl, ODD_COUNTERS); 5658 5659 for_all_cpus(set_temperature_target, ODD_COUNTERS); 5660 5661 if (!quiet) 5662 for_all_cpus(print_thermal, ODD_COUNTERS); 5663 5664 if (!quiet && do_irtl_snb) 5665 print_irtl(); 5666 } 5667 5668 int fork_it(char **argv) 5669 { 5670 pid_t child_pid; 5671 int status; 5672 5673 snapshot_proc_sysfs_files(); 5674 status = for_all_cpus(get_counters, EVEN_COUNTERS); 5675 first_counter_read = 0; 5676 if (status) 5677 exit(status); 5678 /* clear affinity side-effect of get_counters() */ 5679 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 5680 gettimeofday(&tv_even, (struct timezone *)NULL); 5681 5682 child_pid = fork(); 5683 if (!child_pid) { 5684 /* child */ 5685 execvp(argv[0], argv); 5686 err(errno, "exec %s", argv[0]); 5687 } else { 5688 5689 /* parent */ 5690 if (child_pid == -1) 5691 err(1, "fork"); 5692 5693 signal(SIGINT, SIG_IGN); 5694 signal(SIGQUIT, SIG_IGN); 5695 if (waitpid(child_pid, &status, 0) == -1) 5696 err(status, "waitpid"); 5697 5698 if (WIFEXITED(status)) 5699 status = WEXITSTATUS(status); 5700 } 5701 /* 5702 * n.b. fork_it() does not check for errors from for_all_cpus() 5703 * because re-starting is problematic when forking 5704 */ 5705 snapshot_proc_sysfs_files(); 5706 for_all_cpus(get_counters, ODD_COUNTERS); 5707 gettimeofday(&tv_odd, (struct timezone *)NULL); 5708 timersub(&tv_odd, &tv_even, &tv_delta); 5709 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 5710 fprintf(outf, "%s: Counter reset detected\n", progname); 5711 else { 5712 compute_average(EVEN_COUNTERS); 5713 format_all_counters(EVEN_COUNTERS); 5714 } 5715 5716 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 5717 5718 flush_output_stderr(); 5719 5720 return status; 5721 } 5722 5723 int get_and_dump_counters(void) 5724 { 5725 int status; 5726 5727 snapshot_proc_sysfs_files(); 5728 status = for_all_cpus(get_counters, ODD_COUNTERS); 5729 if (status) 5730 return status; 5731 5732 status = for_all_cpus(dump_counters, ODD_COUNTERS); 5733 if (status) 5734 return status; 5735 5736 flush_output_stdout(); 5737 5738 return status; 5739 } 5740 5741 void print_version() { 5742 fprintf(outf, "turbostat version 20.09.30" 5743 " - Len Brown <lenb@kernel.org>\n"); 5744 } 5745 5746 int add_counter(unsigned int msr_num, char *path, char *name, 5747 unsigned int width, enum counter_scope scope, 5748 enum counter_type type, enum counter_format format, int flags) 5749 { 5750 struct msr_counter *msrp; 5751 5752 msrp = calloc(1, sizeof(struct msr_counter)); 5753 if (msrp == NULL) { 5754 perror("calloc"); 5755 exit(1); 5756 } 5757 5758 msrp->msr_num = msr_num; 5759 strncpy(msrp->name, name, NAME_BYTES - 1); 5760 if (path) 5761 strncpy(msrp->path, path, PATH_BYTES - 1); 5762 msrp->width = width; 5763 msrp->type = type; 5764 msrp->format = format; 5765 msrp->flags = flags; 5766 5767 switch (scope) { 5768 5769 case SCOPE_CPU: 5770 msrp->next = sys.tp; 5771 sys.tp = msrp; 5772 sys.added_thread_counters++; 5773 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 5774 fprintf(stderr, "exceeded max %d added thread counters\n", 5775 MAX_ADDED_COUNTERS); 5776 exit(-1); 5777 } 5778 break; 5779 5780 case SCOPE_CORE: 5781 msrp->next = sys.cp; 5782 sys.cp = msrp; 5783 sys.added_core_counters++; 5784 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 5785 fprintf(stderr, "exceeded max %d added core counters\n", 5786 MAX_ADDED_COUNTERS); 5787 exit(-1); 5788 } 5789 break; 5790 5791 case SCOPE_PACKAGE: 5792 msrp->next = sys.pp; 5793 sys.pp = msrp; 5794 sys.added_package_counters++; 5795 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 5796 fprintf(stderr, "exceeded max %d added package counters\n", 5797 MAX_ADDED_COUNTERS); 5798 exit(-1); 5799 } 5800 break; 5801 } 5802 5803 return 0; 5804 } 5805 5806 void parse_add_command(char *add_command) 5807 { 5808 int msr_num = 0; 5809 char *path = NULL; 5810 char name_buffer[NAME_BYTES] = ""; 5811 int width = 64; 5812 int fail = 0; 5813 enum counter_scope scope = SCOPE_CPU; 5814 enum counter_type type = COUNTER_CYCLES; 5815 enum counter_format format = FORMAT_DELTA; 5816 5817 while (add_command) { 5818 5819 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 5820 goto next; 5821 5822 if (sscanf(add_command, "msr%d", &msr_num) == 1) 5823 goto next; 5824 5825 if (*add_command == '/') { 5826 path = add_command; 5827 goto next; 5828 } 5829 5830 if (sscanf(add_command, "u%d", &width) == 1) { 5831 if ((width == 32) || (width == 64)) 5832 goto next; 5833 width = 64; 5834 } 5835 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 5836 scope = SCOPE_CPU; 5837 goto next; 5838 } 5839 if (!strncmp(add_command, "core", strlen("core"))) { 5840 scope = SCOPE_CORE; 5841 goto next; 5842 } 5843 if (!strncmp(add_command, "package", strlen("package"))) { 5844 scope = SCOPE_PACKAGE; 5845 goto next; 5846 } 5847 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 5848 type = COUNTER_CYCLES; 5849 goto next; 5850 } 5851 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 5852 type = COUNTER_SECONDS; 5853 goto next; 5854 } 5855 if (!strncmp(add_command, "usec", strlen("usec"))) { 5856 type = COUNTER_USEC; 5857 goto next; 5858 } 5859 if (!strncmp(add_command, "raw", strlen("raw"))) { 5860 format = FORMAT_RAW; 5861 goto next; 5862 } 5863 if (!strncmp(add_command, "delta", strlen("delta"))) { 5864 format = FORMAT_DELTA; 5865 goto next; 5866 } 5867 if (!strncmp(add_command, "percent", strlen("percent"))) { 5868 format = FORMAT_PERCENT; 5869 goto next; 5870 } 5871 5872 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 5873 char *eos; 5874 5875 eos = strchr(name_buffer, ','); 5876 if (eos) 5877 *eos = '\0'; 5878 goto next; 5879 } 5880 5881 next: 5882 add_command = strchr(add_command, ','); 5883 if (add_command) { 5884 *add_command = '\0'; 5885 add_command++; 5886 } 5887 5888 } 5889 if ((msr_num == 0) && (path == NULL)) { 5890 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 5891 fail++; 5892 } 5893 5894 /* generate default column header */ 5895 if (*name_buffer == '\0') { 5896 if (width == 32) 5897 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5898 else 5899 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5900 } 5901 5902 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 5903 fail++; 5904 5905 if (fail) { 5906 help(); 5907 exit(1); 5908 } 5909 } 5910 5911 int is_deferred_skip(char *name) 5912 { 5913 int i; 5914 5915 for (i = 0; i < deferred_skip_index; ++i) 5916 if (!strcmp(name, deferred_skip_names[i])) 5917 return 1; 5918 return 0; 5919 } 5920 5921 void probe_sysfs(void) 5922 { 5923 char path[64]; 5924 char name_buf[16]; 5925 FILE *input; 5926 int state; 5927 char *sp; 5928 5929 if (!DO_BIC(BIC_sysfs)) 5930 return; 5931 5932 for (state = 10; state >= 0; --state) { 5933 5934 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5935 base_cpu, state); 5936 input = fopen(path, "r"); 5937 if (input == NULL) 5938 continue; 5939 if (!fgets(name_buf, sizeof(name_buf), input)) 5940 err(1, "%s: failed to read file", path); 5941 5942 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5943 sp = strchr(name_buf, '-'); 5944 if (!sp) 5945 sp = strchrnul(name_buf, '\n'); 5946 *sp = '%'; 5947 *(sp + 1) = '\0'; 5948 5949 remove_underbar(name_buf); 5950 5951 fclose(input); 5952 5953 sprintf(path, "cpuidle/state%d/time", state); 5954 5955 if (is_deferred_skip(name_buf)) 5956 continue; 5957 5958 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, 5959 FORMAT_PERCENT, SYSFS_PERCPU); 5960 } 5961 5962 for (state = 10; state >= 0; --state) { 5963 5964 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5965 base_cpu, state); 5966 input = fopen(path, "r"); 5967 if (input == NULL) 5968 continue; 5969 if (!fgets(name_buf, sizeof(name_buf), input)) 5970 err(1, "%s: failed to read file", path); 5971 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5972 sp = strchr(name_buf, '-'); 5973 if (!sp) 5974 sp = strchrnul(name_buf, '\n'); 5975 *sp = '\0'; 5976 fclose(input); 5977 5978 remove_underbar(name_buf); 5979 5980 sprintf(path, "cpuidle/state%d/usage", state); 5981 5982 if (is_deferred_skip(name_buf)) 5983 continue; 5984 5985 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, 5986 FORMAT_DELTA, SYSFS_PERCPU); 5987 } 5988 5989 } 5990 5991 5992 /* 5993 * parse cpuset with following syntax 5994 * 1,2,4..6,8-10 and set bits in cpu_subset 5995 */ 5996 void parse_cpu_command(char *optarg) 5997 { 5998 unsigned int start, end; 5999 char *next; 6000 6001 if (!strcmp(optarg, "core")) { 6002 if (cpu_subset) 6003 goto error; 6004 show_core_only++; 6005 return; 6006 } 6007 if (!strcmp(optarg, "package")) { 6008 if (cpu_subset) 6009 goto error; 6010 show_pkg_only++; 6011 return; 6012 } 6013 if (show_core_only || show_pkg_only) 6014 goto error; 6015 6016 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 6017 if (cpu_subset == NULL) 6018 err(3, "CPU_ALLOC"); 6019 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 6020 6021 CPU_ZERO_S(cpu_subset_size, cpu_subset); 6022 6023 next = optarg; 6024 6025 while (next && *next) { 6026 6027 if (*next == '-') /* no negative cpu numbers */ 6028 goto error; 6029 6030 start = strtoul(next, &next, 10); 6031 6032 if (start >= CPU_SUBSET_MAXCPUS) 6033 goto error; 6034 CPU_SET_S(start, cpu_subset_size, cpu_subset); 6035 6036 if (*next == '\0') 6037 break; 6038 6039 if (*next == ',') { 6040 next += 1; 6041 continue; 6042 } 6043 6044 if (*next == '-') { 6045 next += 1; /* start range */ 6046 } else if (*next == '.') { 6047 next += 1; 6048 if (*next == '.') 6049 next += 1; /* start range */ 6050 else 6051 goto error; 6052 } 6053 6054 end = strtoul(next, &next, 10); 6055 if (end <= start) 6056 goto error; 6057 6058 while (++start <= end) { 6059 if (start >= CPU_SUBSET_MAXCPUS) 6060 goto error; 6061 CPU_SET_S(start, cpu_subset_size, cpu_subset); 6062 } 6063 6064 if (*next == ',') 6065 next += 1; 6066 else if (*next != '\0') 6067 goto error; 6068 } 6069 6070 return; 6071 6072 error: 6073 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 6074 help(); 6075 exit(-1); 6076 } 6077 6078 6079 void cmdline(int argc, char **argv) 6080 { 6081 int opt; 6082 int option_index = 0; 6083 static struct option long_options[] = { 6084 {"add", required_argument, 0, 'a'}, 6085 {"cpu", required_argument, 0, 'c'}, 6086 {"Dump", no_argument, 0, 'D'}, 6087 {"debug", no_argument, 0, 'd'}, /* internal, not documented */ 6088 {"enable", required_argument, 0, 'e'}, 6089 {"interval", required_argument, 0, 'i'}, 6090 {"num_iterations", required_argument, 0, 'n'}, 6091 {"help", no_argument, 0, 'h'}, 6092 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help 6093 {"Joules", no_argument, 0, 'J'}, 6094 {"list", no_argument, 0, 'l'}, 6095 {"out", required_argument, 0, 'o'}, 6096 {"quiet", no_argument, 0, 'q'}, 6097 {"show", required_argument, 0, 's'}, 6098 {"Summary", no_argument, 0, 'S'}, 6099 {"TCC", required_argument, 0, 'T'}, 6100 {"version", no_argument, 0, 'v' }, 6101 {0, 0, 0, 0 } 6102 }; 6103 6104 progname = argv[0]; 6105 6106 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", 6107 long_options, &option_index)) != -1) { 6108 switch (opt) { 6109 case 'a': 6110 parse_add_command(optarg); 6111 break; 6112 case 'c': 6113 parse_cpu_command(optarg); 6114 break; 6115 case 'D': 6116 dump_only++; 6117 break; 6118 case 'e': 6119 /* --enable specified counter */ 6120 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 6121 break; 6122 case 'd': 6123 debug++; 6124 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6125 break; 6126 case 'H': 6127 /* 6128 * --hide: do not show those specified 6129 * multiple invocations simply clear more bits in enabled mask 6130 */ 6131 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 6132 break; 6133 case 'h': 6134 default: 6135 help(); 6136 exit(1); 6137 case 'i': 6138 { 6139 double interval = strtod(optarg, NULL); 6140 6141 if (interval < 0.001) { 6142 fprintf(outf, "interval %f seconds is too small\n", 6143 interval); 6144 exit(2); 6145 } 6146 6147 interval_tv.tv_sec = interval_ts.tv_sec = interval; 6148 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 6149 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 6150 } 6151 break; 6152 case 'J': 6153 rapl_joules++; 6154 break; 6155 case 'l': 6156 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6157 list_header_only++; 6158 quiet++; 6159 break; 6160 case 'o': 6161 outf = fopen_or_die(optarg, "w"); 6162 break; 6163 case 'q': 6164 quiet = 1; 6165 break; 6166 case 'n': 6167 num_iterations = strtod(optarg, NULL); 6168 6169 if (num_iterations <= 0) { 6170 fprintf(outf, "iterations %d should be positive number\n", 6171 num_iterations); 6172 exit(2); 6173 } 6174 break; 6175 case 's': 6176 /* 6177 * --show: show only those specified 6178 * The 1st invocation will clear and replace the enabled mask 6179 * subsequent invocations can add to it. 6180 */ 6181 if (shown == 0) 6182 bic_enabled = bic_lookup(optarg, SHOW_LIST); 6183 else 6184 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 6185 shown = 1; 6186 break; 6187 case 'S': 6188 summary_only++; 6189 break; 6190 case 'T': 6191 tcc_activation_temp_override = atoi(optarg); 6192 break; 6193 case 'v': 6194 print_version(); 6195 exit(0); 6196 break; 6197 } 6198 } 6199 } 6200 6201 int main(int argc, char **argv) 6202 { 6203 outf = stderr; 6204 cmdline(argc, argv); 6205 6206 if (!quiet) 6207 print_version(); 6208 6209 probe_sysfs(); 6210 6211 turbostat_init(); 6212 6213 /* dump counters and exit */ 6214 if (dump_only) 6215 return get_and_dump_counters(); 6216 6217 /* list header and exit */ 6218 if (list_header_only) { 6219 print_header(","); 6220 flush_output_stdout(); 6221 return 0; 6222 } 6223 6224 msr_sum_record(); 6225 /* 6226 * if any params left, it must be a command to fork 6227 */ 6228 if (argc - optind) 6229 return fork_it(argv + optind); 6230 else 6231 turbostat_loop(); 6232 6233 return 0; 6234 } 6235