1dfc83cc8SIan Rogers[ 2dfc83cc8SIan Rogers { 3dfc83cc8SIan Rogers "BriefDescription": "This event counts the cycles the floating point divider is busy.", 4dfc83cc8SIan Rogers "CounterMask": "1", 5dfc83cc8SIan Rogers "EventCode": "0xb0", 6dfc83cc8SIan Rogers "EventName": "ARITH.FPDIV_ACTIVE", 7dfc83cc8SIan Rogers "SampleAfterValue": "1000003", 8dfc83cc8SIan Rogers "UMask": "0x1", 9dfc83cc8SIan Rogers "Unit": "cpu_core" 10dfc83cc8SIan Rogers }, 11dfc83cc8SIan Rogers { 12dfc83cc8SIan Rogers "BriefDescription": "Counts all microcode FP assists.", 13dfc83cc8SIan Rogers "EventCode": "0xc1", 14dfc83cc8SIan Rogers "EventName": "ASSISTS.FP", 15dfc83cc8SIan Rogers "PublicDescription": "Counts all microcode Floating Point assists.", 16dfc83cc8SIan Rogers "SampleAfterValue": "100003", 17dfc83cc8SIan Rogers "UMask": "0x2", 18dfc83cc8SIan Rogers "Unit": "cpu_core" 19dfc83cc8SIan Rogers }, 20dfc83cc8SIan Rogers { 21dfc83cc8SIan Rogers "BriefDescription": "ASSISTS.SSE_AVX_MIX", 22dfc83cc8SIan Rogers "EventCode": "0xc1", 23dfc83cc8SIan Rogers "EventName": "ASSISTS.SSE_AVX_MIX", 24dfc83cc8SIan Rogers "SampleAfterValue": "1000003", 25dfc83cc8SIan Rogers "UMask": "0x10", 26dfc83cc8SIan Rogers "Unit": "cpu_core" 27dfc83cc8SIan Rogers }, 28dfc83cc8SIan Rogers { 29dfc83cc8SIan Rogers "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0", 30dfc83cc8SIan Rogers "EventCode": "0xb3", 31dfc83cc8SIan Rogers "EventName": "FP_ARITH_DISPATCHED.PORT_0", 32dfc83cc8SIan Rogers "SampleAfterValue": "2000003", 33dfc83cc8SIan Rogers "UMask": "0x1", 34dfc83cc8SIan Rogers "Unit": "cpu_core" 35dfc83cc8SIan Rogers }, 36dfc83cc8SIan Rogers { 37dfc83cc8SIan Rogers "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1", 38dfc83cc8SIan Rogers "EventCode": "0xb3", 39dfc83cc8SIan Rogers "EventName": "FP_ARITH_DISPATCHED.PORT_1", 40dfc83cc8SIan Rogers "SampleAfterValue": "2000003", 41dfc83cc8SIan Rogers "UMask": "0x2", 42dfc83cc8SIan Rogers "Unit": "cpu_core" 43dfc83cc8SIan Rogers }, 44dfc83cc8SIan Rogers { 45*ab0cfb79SIan Rogers "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5", 46*ab0cfb79SIan Rogers "EventCode": "0xb3", 47*ab0cfb79SIan Rogers "EventName": "FP_ARITH_DISPATCHED.PORT_5", 48*ab0cfb79SIan Rogers "SampleAfterValue": "2000003", 49*ab0cfb79SIan Rogers "UMask": "0x4", 50*ab0cfb79SIan Rogers "Unit": "cpu_core" 51*ab0cfb79SIan Rogers }, 52*ab0cfb79SIan Rogers { 53dfc83cc8SIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 54dfc83cc8SIan Rogers "EventCode": "0xc7", 55dfc83cc8SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 56dfc83cc8SIan Rogers "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 57dfc83cc8SIan Rogers "SampleAfterValue": "100003", 58dfc83cc8SIan Rogers "UMask": "0x4", 59dfc83cc8SIan Rogers "Unit": "cpu_core" 60dfc83cc8SIan Rogers }, 61dfc83cc8SIan Rogers { 62dfc83cc8SIan Rogers "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 63dfc83cc8SIan Rogers "EventCode": "0xc7", 64dfc83cc8SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 65dfc83cc8SIan Rogers "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 66dfc83cc8SIan Rogers "SampleAfterValue": "100003", 67dfc83cc8SIan Rogers "UMask": "0x8", 68dfc83cc8SIan Rogers "Unit": "cpu_core" 69dfc83cc8SIan Rogers }, 70dfc83cc8SIan Rogers { 71dfc83cc8SIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 72dfc83cc8SIan Rogers "EventCode": "0xc7", 73dfc83cc8SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 74dfc83cc8SIan Rogers "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 75dfc83cc8SIan Rogers "SampleAfterValue": "100003", 76dfc83cc8SIan Rogers "UMask": "0x10", 77dfc83cc8SIan Rogers "Unit": "cpu_core" 78dfc83cc8SIan Rogers }, 79dfc83cc8SIan Rogers { 80dfc83cc8SIan Rogers "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 81dfc83cc8SIan Rogers "EventCode": "0xc7", 82dfc83cc8SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 83dfc83cc8SIan Rogers "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 84dfc83cc8SIan Rogers "SampleAfterValue": "100003", 85dfc83cc8SIan Rogers "UMask": "0x20", 86dfc83cc8SIan Rogers "Unit": "cpu_core" 87dfc83cc8SIan Rogers }, 88dfc83cc8SIan Rogers { 89dfc83cc8SIan Rogers "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 90dfc83cc8SIan Rogers "EventCode": "0xc7", 91dfc83cc8SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 92dfc83cc8SIan Rogers "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 93dfc83cc8SIan Rogers "SampleAfterValue": "100003", 94dfc83cc8SIan Rogers "UMask": "0x18", 95dfc83cc8SIan Rogers "Unit": "cpu_core" 96dfc83cc8SIan Rogers }, 97dfc83cc8SIan Rogers { 98dfc83cc8SIan Rogers "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 99dfc83cc8SIan Rogers "EventCode": "0xc7", 100dfc83cc8SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 101dfc83cc8SIan Rogers "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 102dfc83cc8SIan Rogers "SampleAfterValue": "1000003", 103dfc83cc8SIan Rogers "UMask": "0x3", 104dfc83cc8SIan Rogers "Unit": "cpu_core" 105dfc83cc8SIan Rogers }, 106dfc83cc8SIan Rogers { 107dfc83cc8SIan Rogers "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 108dfc83cc8SIan Rogers "EventCode": "0xc7", 109dfc83cc8SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 110dfc83cc8SIan Rogers "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 111dfc83cc8SIan Rogers "SampleAfterValue": "100003", 112dfc83cc8SIan Rogers "UMask": "0x1", 113dfc83cc8SIan Rogers "Unit": "cpu_core" 114dfc83cc8SIan Rogers }, 115dfc83cc8SIan Rogers { 116dfc83cc8SIan Rogers "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 117dfc83cc8SIan Rogers "EventCode": "0xc7", 118dfc83cc8SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 119dfc83cc8SIan Rogers "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 120dfc83cc8SIan Rogers "SampleAfterValue": "100003", 121dfc83cc8SIan Rogers "UMask": "0x2", 122dfc83cc8SIan Rogers "Unit": "cpu_core" 123dfc83cc8SIan Rogers }, 124dfc83cc8SIan Rogers { 125dfc83cc8SIan Rogers "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 126dfc83cc8SIan Rogers "EventCode": "0xc7", 127dfc83cc8SIan Rogers "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 128dfc83cc8SIan Rogers "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 129dfc83cc8SIan Rogers "SampleAfterValue": "1000003", 130dfc83cc8SIan Rogers "UMask": "0xfc", 131dfc83cc8SIan Rogers "Unit": "cpu_core" 132dfc83cc8SIan Rogers }, 133dfc83cc8SIan Rogers { 134dfc83cc8SIan Rogers "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 135dfc83cc8SIan Rogers "EventCode": "0xc3", 136dfc83cc8SIan Rogers "EventName": "MACHINE_CLEARS.FP_ASSIST", 137dfc83cc8SIan Rogers "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", 138dfc83cc8SIan Rogers "SampleAfterValue": "20003", 139dfc83cc8SIan Rogers "UMask": "0x4", 140dfc83cc8SIan Rogers "Unit": "cpu_atom" 141dfc83cc8SIan Rogers }, 142dfc83cc8SIan Rogers { 143dfc83cc8SIan Rogers "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).", 144dfc83cc8SIan Rogers "EventCode": "0xc2", 145dfc83cc8SIan Rogers "EventName": "UOPS_RETIRED.FPDIV", 146dfc83cc8SIan Rogers "PEBS": "1", 147dfc83cc8SIan Rogers "SampleAfterValue": "2000003", 148dfc83cc8SIan Rogers "UMask": "0x8", 149dfc83cc8SIan Rogers "Unit": "cpu_atom" 150dfc83cc8SIan Rogers } 151dfc83cc8SIan Rogers] 152