1[
2    {
3        "BriefDescription": "This event counts the cycles the floating point divider is busy.",
4        "CounterMask": "1",
5        "EventCode": "0xb0",
6        "EventName": "ARITH.FPDIV_ACTIVE",
7        "SampleAfterValue": "1000003",
8        "UMask": "0x1",
9        "Unit": "cpu_core"
10    },
11    {
12        "BriefDescription": "Counts all microcode FP assists.",
13        "EventCode": "0xc1",
14        "EventName": "ASSISTS.FP",
15        "PublicDescription": "Counts all microcode Floating Point assists.",
16        "SampleAfterValue": "100003",
17        "UMask": "0x2",
18        "Unit": "cpu_core"
19    },
20    {
21        "BriefDescription": "ASSISTS.SSE_AVX_MIX",
22        "EventCode": "0xc1",
23        "EventName": "ASSISTS.SSE_AVX_MIX",
24        "SampleAfterValue": "1000003",
25        "UMask": "0x10",
26        "Unit": "cpu_core"
27    },
28    {
29        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
30        "EventCode": "0xb3",
31        "EventName": "FP_ARITH_DISPATCHED.PORT_0",
32        "SampleAfterValue": "2000003",
33        "UMask": "0x1",
34        "Unit": "cpu_core"
35    },
36    {
37        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
38        "EventCode": "0xb3",
39        "EventName": "FP_ARITH_DISPATCHED.PORT_1",
40        "SampleAfterValue": "2000003",
41        "UMask": "0x2",
42        "Unit": "cpu_core"
43    },
44    {
45        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
46        "EventCode": "0xb3",
47        "EventName": "FP_ARITH_DISPATCHED.PORT_5",
48        "SampleAfterValue": "2000003",
49        "UMask": "0x4",
50        "Unit": "cpu_core"
51    },
52    {
53        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
54        "EventCode": "0xc7",
55        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
56        "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
57        "SampleAfterValue": "100003",
58        "UMask": "0x4",
59        "Unit": "cpu_core"
60    },
61    {
62        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
63        "EventCode": "0xc7",
64        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
65        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
66        "SampleAfterValue": "100003",
67        "UMask": "0x8",
68        "Unit": "cpu_core"
69    },
70    {
71        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
72        "EventCode": "0xc7",
73        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
74        "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
75        "SampleAfterValue": "100003",
76        "UMask": "0x10",
77        "Unit": "cpu_core"
78    },
79    {
80        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
81        "EventCode": "0xc7",
82        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
83        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
84        "SampleAfterValue": "100003",
85        "UMask": "0x20",
86        "Unit": "cpu_core"
87    },
88    {
89        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
90        "EventCode": "0xc7",
91        "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
92        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
93        "SampleAfterValue": "100003",
94        "UMask": "0x18",
95        "Unit": "cpu_core"
96    },
97    {
98        "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
99        "EventCode": "0xc7",
100        "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
101        "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
102        "SampleAfterValue": "1000003",
103        "UMask": "0x3",
104        "Unit": "cpu_core"
105    },
106    {
107        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
108        "EventCode": "0xc7",
109        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
110        "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
111        "SampleAfterValue": "100003",
112        "UMask": "0x1",
113        "Unit": "cpu_core"
114    },
115    {
116        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
117        "EventCode": "0xc7",
118        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
119        "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
120        "SampleAfterValue": "100003",
121        "UMask": "0x2",
122        "Unit": "cpu_core"
123    },
124    {
125        "BriefDescription": "Number of any Vector retired FP arithmetic instructions",
126        "EventCode": "0xc7",
127        "EventName": "FP_ARITH_INST_RETIRED.VECTOR",
128        "PublicDescription": "Number of any Vector retired FP arithmetic instructions.  The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
129        "SampleAfterValue": "1000003",
130        "UMask": "0xfc",
131        "Unit": "cpu_core"
132    },
133    {
134        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
135        "EventCode": "0xc3",
136        "EventName": "MACHINE_CLEARS.FP_ASSIST",
137        "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
138        "SampleAfterValue": "20003",
139        "UMask": "0x4",
140        "Unit": "cpu_atom"
141    },
142    {
143        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).",
144        "EventCode": "0xc2",
145        "EventName": "UOPS_RETIRED.FPDIV",
146        "PEBS": "1",
147        "SampleAfterValue": "2000003",
148        "UMask": "0x8",
149        "Unit": "cpu_atom"
150    }
151]
152