1826db0f1SSukadev Bhattiprolu[ 2826db0f1SSukadev Bhattiprolu {, 3826db0f1SSukadev Bhattiprolu "EventCode": "0x1001C", 4826db0f1SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_THRD", 5826db0f1SSukadev Bhattiprolu "BriefDescription": "Completion Stalled because the thread was blocked", 6826db0f1SSukadev Bhattiprolu "PublicDescription": "" 7826db0f1SSukadev Bhattiprolu }, 8826db0f1SSukadev Bhattiprolu {, 9826db0f1SSukadev Bhattiprolu "EventCode": "0x1002E", 10826db0f1SSukadev Bhattiprolu "EventName": "PM_LMQ_MERGE", 11826db0f1SSukadev Bhattiprolu "BriefDescription": "A demand miss collides with a prefetch for the same line", 12826db0f1SSukadev Bhattiprolu "PublicDescription": "" 13826db0f1SSukadev Bhattiprolu }, 14826db0f1SSukadev Bhattiprolu {, 15826db0f1SSukadev Bhattiprolu "EventCode": "0x10134", 16826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_ST_DONE_L2", 17826db0f1SSukadev Bhattiprolu "BriefDescription": "marked store completed in L2 ( RC machine done)", 18826db0f1SSukadev Bhattiprolu "PublicDescription": "" 19826db0f1SSukadev Bhattiprolu }, 20826db0f1SSukadev Bhattiprolu {, 21826db0f1SSukadev Bhattiprolu "EventCode": "0x10138", 22826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_BR_2PATH", 23826db0f1SSukadev Bhattiprolu "BriefDescription": "marked branches which are not strongly biased", 24826db0f1SSukadev Bhattiprolu "PublicDescription": "" 25826db0f1SSukadev Bhattiprolu }, 26826db0f1SSukadev Bhattiprolu {, 27826db0f1SSukadev Bhattiprolu "EventCode": "0x1C04A", 28826db0f1SSukadev Bhattiprolu "EventName": "PM_DATA_FROM_RL2L3_SHR", 29826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load", 30826db0f1SSukadev Bhattiprolu "PublicDescription": "" 31826db0f1SSukadev Bhattiprolu }, 32826db0f1SSukadev Bhattiprolu {, 33826db0f1SSukadev Bhattiprolu "EventCode": "0x1C04C", 34826db0f1SSukadev Bhattiprolu "EventName": "PM_DATA_FROM_LL4", 35826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load", 36826db0f1SSukadev Bhattiprolu "PublicDescription": "" 37826db0f1SSukadev Bhattiprolu }, 38826db0f1SSukadev Bhattiprolu {, 39826db0f1SSukadev Bhattiprolu "EventCode": "0x1D140", 40826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3.1_MOD_CYC", 41826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load", 42826db0f1SSukadev Bhattiprolu "PublicDescription": "" 43826db0f1SSukadev Bhattiprolu }, 44826db0f1SSukadev Bhattiprolu {, 45826db0f1SSukadev Bhattiprolu "EventCode": "0x1D144", 46826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT", 47826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load", 48826db0f1SSukadev Bhattiprolu "PublicDescription": "" 49826db0f1SSukadev Bhattiprolu }, 50826db0f1SSukadev Bhattiprolu {, 51826db0f1SSukadev Bhattiprolu "EventCode": "0x1D146", 52826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_MEMORY_CYC", 53826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load", 54826db0f1SSukadev Bhattiprolu "PublicDescription": "" 55826db0f1SSukadev Bhattiprolu }, 56826db0f1SSukadev Bhattiprolu {, 57826db0f1SSukadev Bhattiprolu "EventCode": "0x1D148", 58826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_RMEM", 59826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load", 60826db0f1SSukadev Bhattiprolu "PublicDescription": "" 61826db0f1SSukadev Bhattiprolu }, 62826db0f1SSukadev Bhattiprolu {, 63826db0f1SSukadev Bhattiprolu "EventCode": "0x1D14E", 64826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC", 65826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", 66826db0f1SSukadev Bhattiprolu "PublicDescription": "" 67826db0f1SSukadev Bhattiprolu }, 68826db0f1SSukadev Bhattiprolu {, 69826db0f1SSukadev Bhattiprolu "EventCode": "0x15040", 70826db0f1SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_L2_NO_CONFLICT", 71826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request", 72826db0f1SSukadev Bhattiprolu "PublicDescription": "" 73826db0f1SSukadev Bhattiprolu }, 74826db0f1SSukadev Bhattiprolu {, 75826db0f1SSukadev Bhattiprolu "EventCode": "0x1504C", 76826db0f1SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_LL4", 77826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request", 78826db0f1SSukadev Bhattiprolu "PublicDescription": "" 79826db0f1SSukadev Bhattiprolu }, 80826db0f1SSukadev Bhattiprolu {, 81826db0f1SSukadev Bhattiprolu "EventCode": "0x1E048", 82826db0f1SSukadev Bhattiprolu "EventName": "PM_DPTEG_FROM_ON_CHIP_CACHE", 83826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", 84826db0f1SSukadev Bhattiprolu "PublicDescription": "" 85826db0f1SSukadev Bhattiprolu }, 86826db0f1SSukadev Bhattiprolu {, 87826db0f1SSukadev Bhattiprolu "EventCode": "0x1E04E", 88826db0f1SSukadev Bhattiprolu "EventName": "PM_DPTEG_FROM_L2MISS", 89826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", 90826db0f1SSukadev Bhattiprolu "PublicDescription": "" 91826db0f1SSukadev Bhattiprolu }, 92826db0f1SSukadev Bhattiprolu {, 93826db0f1SSukadev Bhattiprolu "EventCode": "0x1F146", 94826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DPTEG_FROM_L3.1_SHR", 95826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", 96826db0f1SSukadev Bhattiprolu "PublicDescription": "" 97826db0f1SSukadev Bhattiprolu }, 98826db0f1SSukadev Bhattiprolu {, 99826db0f1SSukadev Bhattiprolu "EventCode": "0x10052", 100826db0f1SSukadev Bhattiprolu "EventName": "PM_GRP_PUMP_MPRED_RTY", 101826db0f1SSukadev Bhattiprolu "BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)", 102826db0f1SSukadev Bhattiprolu "PublicDescription": "" 103826db0f1SSukadev Bhattiprolu }, 104826db0f1SSukadev Bhattiprolu {, 105826db0f1SSukadev Bhattiprolu "EventCode": "0x1C05C", 106826db0f1SSukadev Bhattiprolu "EventName": "PM_DTLB_MISS_2M", 107826db0f1SSukadev Bhattiprolu "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used", 108826db0f1SSukadev Bhattiprolu "PublicDescription": "" 109826db0f1SSukadev Bhattiprolu }, 110826db0f1SSukadev Bhattiprolu {, 111826db0f1SSukadev Bhattiprolu "EventCode": "0x14156", 112826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2_CYC", 113826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load", 114826db0f1SSukadev Bhattiprolu "PublicDescription": "" 115826db0f1SSukadev Bhattiprolu }, 116826db0f1SSukadev Bhattiprolu {, 117826db0f1SSukadev Bhattiprolu "EventCode": "0x14158", 118826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC", 119826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L2 without conflict due to a marked load", 120826db0f1SSukadev Bhattiprolu "PublicDescription": "" 121826db0f1SSukadev Bhattiprolu }, 122826db0f1SSukadev Bhattiprolu {, 123826db0f1SSukadev Bhattiprolu "EventCode": "0x1415C", 124826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_MEPF_CYC", 125826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load", 126826db0f1SSukadev Bhattiprolu "PublicDescription": "" 127826db0f1SSukadev Bhattiprolu }, 128826db0f1SSukadev Bhattiprolu {, 129826db0f1SSukadev Bhattiprolu "EventCode": "0x1D150", 130826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR", 131826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 132826db0f1SSukadev Bhattiprolu "PublicDescription": "" 133826db0f1SSukadev Bhattiprolu }, 134826db0f1SSukadev Bhattiprolu {, 135826db0f1SSukadev Bhattiprolu "EventCode": "0x1D152", 136826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DL4", 137826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load", 138826db0f1SSukadev Bhattiprolu "PublicDescription": "" 139826db0f1SSukadev Bhattiprolu }, 140826db0f1SSukadev Bhattiprolu {, 141826db0f1SSukadev Bhattiprolu "EventCode": "0x1D156", 142826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_LD_MISS_L1_CYC", 143826db0f1SSukadev Bhattiprolu "BriefDescription": "Marked ld latency", 144826db0f1SSukadev Bhattiprolu "PublicDescription": "" 145826db0f1SSukadev Bhattiprolu }, 146826db0f1SSukadev Bhattiprolu {, 147826db0f1SSukadev Bhattiprolu "EventCode": "0x15154", 148826db0f1SSukadev Bhattiprolu "EventName": "PM_SYNC_MRK_L3MISS", 149826db0f1SSukadev Bhattiprolu "BriefDescription": "Marked L3 misses that can throw a synchronous interrupt", 150826db0f1SSukadev Bhattiprolu "PublicDescription": "" 151826db0f1SSukadev Bhattiprolu }, 152826db0f1SSukadev Bhattiprolu {, 153826db0f1SSukadev Bhattiprolu "EventCode": "0x1515A", 154826db0f1SSukadev Bhattiprolu "EventName": "PM_SYNC_MRK_L2MISS", 155826db0f1SSukadev Bhattiprolu "BriefDescription": "Marked L2 Miss that can throw a synchronous interrupt", 156826db0f1SSukadev Bhattiprolu "PublicDescription": "" 157826db0f1SSukadev Bhattiprolu }, 158826db0f1SSukadev Bhattiprolu {, 159826db0f1SSukadev Bhattiprolu "EventCode": "0x1E05A", 160826db0f1SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_ANY_SYNC", 161826db0f1SSukadev Bhattiprolu "BriefDescription": "Cycles in which the NTC sync instruction (isync, lwsync or hwsync) is not allowed to complete ", 162826db0f1SSukadev Bhattiprolu "PublicDescription": "" 163826db0f1SSukadev Bhattiprolu }, 164826db0f1SSukadev Bhattiprolu {, 165826db0f1SSukadev Bhattiprolu "EventCode": "0x1E05C", 166826db0f1SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_NESTED_TBEGIN", 167826db0f1SSukadev Bhattiprolu "BriefDescription": "Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin. This is a short delay, and it includes ROT", 168826db0f1SSukadev Bhattiprolu "PublicDescription": "" 169826db0f1SSukadev Bhattiprolu }, 170826db0f1SSukadev Bhattiprolu {, 171826db0f1SSukadev Bhattiprolu "EventCode": "0x1F152", 172826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_FAB_RSP_BKILL_CYC", 173826db0f1SSukadev Bhattiprolu "BriefDescription": "cycles L2 RC took for a bkill", 174826db0f1SSukadev Bhattiprolu "PublicDescription": "" 175826db0f1SSukadev Bhattiprolu }, 176826db0f1SSukadev Bhattiprolu {, 177826db0f1SSukadev Bhattiprolu "EventCode": "0x1F056", 178826db0f1SSukadev Bhattiprolu "EventName": "PM_RADIX_PWC_L1_HIT", 179826db0f1SSukadev Bhattiprolu "BriefDescription": "A radix translation attempt missed in the TLB and only the first level page walk cache was a hit.", 180826db0f1SSukadev Bhattiprolu "PublicDescription": "" 181826db0f1SSukadev Bhattiprolu }, 182826db0f1SSukadev Bhattiprolu {, 183826db0f1SSukadev Bhattiprolu "EventCode": "0x101E4", 184826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_L1_ICACHE_MISS", 185826db0f1SSukadev Bhattiprolu "BriefDescription": "sampled Instruction suffered an icache Miss", 186826db0f1SSukadev Bhattiprolu "PublicDescription": "" 187826db0f1SSukadev Bhattiprolu }, 188826db0f1SSukadev Bhattiprolu {, 189826db0f1SSukadev Bhattiprolu "EventCode": "0x101EA", 190826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_L1_RELOAD_VALID", 191826db0f1SSukadev Bhattiprolu "BriefDescription": "Marked demand reload", 192826db0f1SSukadev Bhattiprolu "PublicDescription": "" 193826db0f1SSukadev Bhattiprolu }, 194826db0f1SSukadev Bhattiprolu {, 195826db0f1SSukadev Bhattiprolu "EventCode": "0x100FA", 196826db0f1SSukadev Bhattiprolu "EventName": "PM_ANY_THRD_RUN_CYC", 197826db0f1SSukadev Bhattiprolu "BriefDescription": "Cycles in which at least one thread has the run latch set", 198826db0f1SSukadev Bhattiprolu "PublicDescription": "" 199826db0f1SSukadev Bhattiprolu }, 200826db0f1SSukadev Bhattiprolu {, 201826db0f1SSukadev Bhattiprolu "EventCode": "0x100FC", 202826db0f1SSukadev Bhattiprolu "EventName": "PM_LD_REF_L1", 203826db0f1SSukadev Bhattiprolu "BriefDescription": "All L1 D cache load references counted at finish, gated by reject", 204826db0f1SSukadev Bhattiprolu "PublicDescription": "" 205826db0f1SSukadev Bhattiprolu }, 206826db0f1SSukadev Bhattiprolu {, 207826db0f1SSukadev Bhattiprolu "EventCode": "0x20006", 208826db0f1SSukadev Bhattiprolu "EventName": "PM_DISP_HELD_ISSQ_FULL", 209826db0f1SSukadev Bhattiprolu "BriefDescription": "Dispatch held due to Issue q full. Includes issue queue and branch queue", 210826db0f1SSukadev Bhattiprolu "PublicDescription": "" 211826db0f1SSukadev Bhattiprolu }, 212826db0f1SSukadev Bhattiprolu {, 213826db0f1SSukadev Bhattiprolu "EventCode": "0x2000C", 214826db0f1SSukadev Bhattiprolu "EventName": "PM_THRD_ALL_RUN_CYC", 215826db0f1SSukadev Bhattiprolu "BriefDescription": "Cycles in which all the threads have the run latch set", 216826db0f1SSukadev Bhattiprolu "PublicDescription": "" 217826db0f1SSukadev Bhattiprolu }, 218826db0f1SSukadev Bhattiprolu {, 219826db0f1SSukadev Bhattiprolu "EventCode": "0x2001A", 220826db0f1SSukadev Bhattiprolu "EventName": "PM_NTC_ALL_FIN", 221826db0f1SSukadev Bhattiprolu "BriefDescription": "Cycles after all instructions have finished to group completed", 222826db0f1SSukadev Bhattiprolu "PublicDescription": "" 223826db0f1SSukadev Bhattiprolu }, 224826db0f1SSukadev Bhattiprolu {, 225826db0f1SSukadev Bhattiprolu "EventCode": "0x2D014", 226826db0f1SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_LRQ_FULL", 227826db0f1SSukadev Bhattiprolu "BriefDescription": "Finish stall because the NTF instruction was a load that was held in LSAQ (load-store address queue) because the LRQ (load-reorder queue) was full", 228826db0f1SSukadev Bhattiprolu "PublicDescription": "" 229826db0f1SSukadev Bhattiprolu }, 230826db0f1SSukadev Bhattiprolu {, 231826db0f1SSukadev Bhattiprolu "EventCode": "0x2D018", 232826db0f1SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_EXEC_UNIT", 233826db0f1SSukadev Bhattiprolu "BriefDescription": "Completion stall due to execution units (FXU/VSU/CRU)", 234826db0f1SSukadev Bhattiprolu "PublicDescription": "" 235826db0f1SSukadev Bhattiprolu }, 236826db0f1SSukadev Bhattiprolu {, 237826db0f1SSukadev Bhattiprolu "EventCode": "0x2D01E", 238826db0f1SSukadev Bhattiprolu "EventName": "PM_ICT_NOSLOT_DISP_HELD_ISSQ", 239826db0f1SSukadev Bhattiprolu "BriefDescription": "Ict empty for this thread due to dispatch hold on this thread due to Issue q full, BRQ full, XVCF Full, Count cache, Link, Tar full", 240826db0f1SSukadev Bhattiprolu "PublicDescription": "" 241826db0f1SSukadev Bhattiprolu }, 242826db0f1SSukadev Bhattiprolu {, 243826db0f1SSukadev Bhattiprolu "EventCode": "0x2E014", 244826db0f1SSukadev Bhattiprolu "EventName": "PM_STCX_FIN", 245826db0f1SSukadev Bhattiprolu "BriefDescription": "Number of stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed", 246826db0f1SSukadev Bhattiprolu "PublicDescription": "" 247826db0f1SSukadev Bhattiprolu }, 248826db0f1SSukadev Bhattiprolu {, 249826db0f1SSukadev Bhattiprolu "EventCode": "0x2C120", 250826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT", 251826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load", 252826db0f1SSukadev Bhattiprolu "PublicDescription": "" 253826db0f1SSukadev Bhattiprolu }, 254826db0f1SSukadev Bhattiprolu {, 255826db0f1SSukadev Bhattiprolu "EventCode": "0x2C122", 256826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC", 257826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load", 258826db0f1SSukadev Bhattiprolu "PublicDescription": "" 259826db0f1SSukadev Bhattiprolu }, 260826db0f1SSukadev Bhattiprolu {, 261826db0f1SSukadev Bhattiprolu "EventCode": "0x2C126", 262826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2", 263826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load", 264826db0f1SSukadev Bhattiprolu "PublicDescription": "" 265826db0f1SSukadev Bhattiprolu }, 266826db0f1SSukadev Bhattiprolu {, 267826db0f1SSukadev Bhattiprolu "EventCode": "0x2C12A", 268826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_RMEM_CYC", 269826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load", 270826db0f1SSukadev Bhattiprolu "PublicDescription": "" 271826db0f1SSukadev Bhattiprolu }, 272826db0f1SSukadev Bhattiprolu {, 273826db0f1SSukadev Bhattiprolu "EventCode": "0x2C12C", 274826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DL4_CYC", 275826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load", 276826db0f1SSukadev Bhattiprolu "PublicDescription": "" 277826db0f1SSukadev Bhattiprolu }, 278826db0f1SSukadev Bhattiprolu {, 279826db0f1SSukadev Bhattiprolu "EventCode": "0x2D120", 280826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE", 281826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load", 282826db0f1SSukadev Bhattiprolu "PublicDescription": "" 283826db0f1SSukadev Bhattiprolu }, 284826db0f1SSukadev Bhattiprolu {, 285826db0f1SSukadev Bhattiprolu "EventCode": "0x2D026", 286826db0f1SSukadev Bhattiprolu "EventName": "PM_RADIX_PWC_L1_PDE_FROM_L2", 287826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L2 data cache", 288826db0f1SSukadev Bhattiprolu "PublicDescription": "" 289826db0f1SSukadev Bhattiprolu }, 290826db0f1SSukadev Bhattiprolu {, 291826db0f1SSukadev Bhattiprolu "EventCode": "0x20132", 292826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DFU_FIN", 293826db0f1SSukadev Bhattiprolu "BriefDescription": "Decimal Unit marked Instruction Finish", 294826db0f1SSukadev Bhattiprolu "PublicDescription": "" 295826db0f1SSukadev Bhattiprolu }, 296826db0f1SSukadev Bhattiprolu {, 297826db0f1SSukadev Bhattiprolu "EventCode": "0x20134", 298826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_FXU_FIN", 299826db0f1SSukadev Bhattiprolu "BriefDescription": "fxu marked instr finish", 300826db0f1SSukadev Bhattiprolu "PublicDescription": "" 301826db0f1SSukadev Bhattiprolu }, 302826db0f1SSukadev Bhattiprolu {, 303826db0f1SSukadev Bhattiprolu "EventCode": "0x2C04E", 304826db0f1SSukadev Bhattiprolu "EventName": "PM_LD_MISS_L1_FIN", 305826db0f1SSukadev Bhattiprolu "BriefDescription": "Number of load instructions that finished with an L1 miss. Note that even if a load spans multiple slices this event will increment only once per load op.", 306826db0f1SSukadev Bhattiprolu "PublicDescription": "" 307826db0f1SSukadev Bhattiprolu }, 308826db0f1SSukadev Bhattiprolu {, 309826db0f1SSukadev Bhattiprolu "EventCode": "0x24040", 310826db0f1SSukadev Bhattiprolu "EventName": "PM_INST_FROM_L2_MEPF", 311826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch)", 312826db0f1SSukadev Bhattiprolu "PublicDescription": "" 313826db0f1SSukadev Bhattiprolu }, 314826db0f1SSukadev Bhattiprolu {, 315826db0f1SSukadev Bhattiprolu "EventCode": "0x24048", 316826db0f1SSukadev Bhattiprolu "EventName": "PM_INST_FROM_LMEM", 317826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)", 318826db0f1SSukadev Bhattiprolu "PublicDescription": "" 319826db0f1SSukadev Bhattiprolu }, 320826db0f1SSukadev Bhattiprolu {, 321826db0f1SSukadev Bhattiprolu "EventCode": "0x2D142", 322826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_MEPF", 323826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load", 324826db0f1SSukadev Bhattiprolu "PublicDescription": "" 325826db0f1SSukadev Bhattiprolu }, 326826db0f1SSukadev Bhattiprolu {, 327826db0f1SSukadev Bhattiprolu "EventCode": "0x2D144", 328826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3.1_MOD", 329826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load", 330826db0f1SSukadev Bhattiprolu "PublicDescription": "" 331826db0f1SSukadev Bhattiprolu }, 332826db0f1SSukadev Bhattiprolu {, 333826db0f1SSukadev Bhattiprolu "EventCode": "0x2D148", 334826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST", 335826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load", 336826db0f1SSukadev Bhattiprolu "PublicDescription": "" 337826db0f1SSukadev Bhattiprolu }, 338826db0f1SSukadev Bhattiprolu {, 339826db0f1SSukadev Bhattiprolu "EventCode": "0x25048", 340826db0f1SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_LMEM", 341826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request", 342826db0f1SSukadev Bhattiprolu "PublicDescription": "" 343826db0f1SSukadev Bhattiprolu }, 344826db0f1SSukadev Bhattiprolu {, 345826db0f1SSukadev Bhattiprolu "EventCode": "0x2E040", 346826db0f1SSukadev Bhattiprolu "EventName": "PM_DPTEG_FROM_L2_MEPF", 347826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", 348826db0f1SSukadev Bhattiprolu "PublicDescription": "" 349826db0f1SSukadev Bhattiprolu }, 350826db0f1SSukadev Bhattiprolu {, 351826db0f1SSukadev Bhattiprolu "EventCode": "0x2E04A", 352826db0f1SSukadev Bhattiprolu "EventName": "PM_DPTEG_FROM_RL4", 353826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", 354826db0f1SSukadev Bhattiprolu "PublicDescription": "" 355826db0f1SSukadev Bhattiprolu }, 356826db0f1SSukadev Bhattiprolu {, 357826db0f1SSukadev Bhattiprolu "EventCode": "0x2F14A", 358826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DPTEG_FROM_RL4", 359826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", 360826db0f1SSukadev Bhattiprolu "PublicDescription": "" 361826db0f1SSukadev Bhattiprolu }, 362826db0f1SSukadev Bhattiprolu {, 363826db0f1SSukadev Bhattiprolu "EventCode": "0x20054", 364826db0f1SSukadev Bhattiprolu "EventName": "PM_L1_PREF", 365826db0f1SSukadev Bhattiprolu "BriefDescription": "A data line was written to the L1 due to a hardware or software prefetch", 366826db0f1SSukadev Bhattiprolu "PublicDescription": "" 367826db0f1SSukadev Bhattiprolu }, 368826db0f1SSukadev Bhattiprolu {, 369826db0f1SSukadev Bhattiprolu "EventCode": "0x20056", 370826db0f1SSukadev Bhattiprolu "EventName": "PM_TAKEN_BR_MPRED_CMPL", 371826db0f1SSukadev Bhattiprolu "BriefDescription": "Total number of taken branches that were incorrectly predicted as not-taken. This event counts branches completed and does not include speculative instructions", 372826db0f1SSukadev Bhattiprolu "PublicDescription": "" 373826db0f1SSukadev Bhattiprolu }, 374826db0f1SSukadev Bhattiprolu {, 375826db0f1SSukadev Bhattiprolu "EventCode": "0x20058", 376826db0f1SSukadev Bhattiprolu "EventName": "PM_DARQ1_10_12_ENTRIES", 377826db0f1SSukadev Bhattiprolu "BriefDescription": "Cycles in which 10 or more DARQ1 entries (out of 12) are in use", 378826db0f1SSukadev Bhattiprolu "PublicDescription": "" 379826db0f1SSukadev Bhattiprolu }, 380826db0f1SSukadev Bhattiprolu {, 381826db0f1SSukadev Bhattiprolu "EventCode": "0x2C050", 382826db0f1SSukadev Bhattiprolu "EventName": "PM_DATA_GRP_PUMP_CPRED", 383826db0f1SSukadev Bhattiprolu "BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load", 384826db0f1SSukadev Bhattiprolu "PublicDescription": "" 385826db0f1SSukadev Bhattiprolu }, 386826db0f1SSukadev Bhattiprolu {, 387826db0f1SSukadev Bhattiprolu "EventCode": "0x2C05E", 388826db0f1SSukadev Bhattiprolu "EventName": "PM_INST_GRP_PUMP_MPRED", 389826db0f1SSukadev Bhattiprolu "BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only)", 390826db0f1SSukadev Bhattiprolu "PublicDescription": "" 391826db0f1SSukadev Bhattiprolu }, 392826db0f1SSukadev Bhattiprolu {, 393826db0f1SSukadev Bhattiprolu "EventCode": "0x2505C", 394826db0f1SSukadev Bhattiprolu "EventName": "PM_VSU_FIN", 395826db0f1SSukadev Bhattiprolu "BriefDescription": "VSU instruction finished. Up to 4 per cycle", 396826db0f1SSukadev Bhattiprolu "PublicDescription": "" 397826db0f1SSukadev Bhattiprolu }, 398826db0f1SSukadev Bhattiprolu {, 399826db0f1SSukadev Bhattiprolu "EventCode": "0x2505E", 400826db0f1SSukadev Bhattiprolu "EventName": "PM_BACK_BR_CMPL", 401826db0f1SSukadev Bhattiprolu "BriefDescription": "Branch instruction completed with a target address less than current instruction address", 402826db0f1SSukadev Bhattiprolu "PublicDescription": "" 403826db0f1SSukadev Bhattiprolu }, 404826db0f1SSukadev Bhattiprolu {, 405826db0f1SSukadev Bhattiprolu "EventCode": "0x2E052", 406826db0f1SSukadev Bhattiprolu "EventName": "PM_TM_PASSED", 407826db0f1SSukadev Bhattiprolu "BriefDescription": "Number of TM transactions that passed", 408826db0f1SSukadev Bhattiprolu "PublicDescription": "" 409826db0f1SSukadev Bhattiprolu }, 410826db0f1SSukadev Bhattiprolu {, 411826db0f1SSukadev Bhattiprolu "EventCode": "0x20064", 412826db0f1SSukadev Bhattiprolu "EventName": "PM_IERAT_RELOAD_4K", 413826db0f1SSukadev Bhattiprolu "BriefDescription": "IERAT reloaded (after a miss) for 4K pages", 414826db0f1SSukadev Bhattiprolu "PublicDescription": "" 415826db0f1SSukadev Bhattiprolu }, 416826db0f1SSukadev Bhattiprolu {, 417826db0f1SSukadev Bhattiprolu "EventCode": "0x2006C", 418826db0f1SSukadev Bhattiprolu "EventName": "PM_RUN_CYC_SMT4_MODE", 419826db0f1SSukadev Bhattiprolu "BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT4 mode", 420826db0f1SSukadev Bhattiprolu "PublicDescription": "" 421826db0f1SSukadev Bhattiprolu }, 422826db0f1SSukadev Bhattiprolu {, 423826db0f1SSukadev Bhattiprolu "EventCode": "0x201E0", 424826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_MEMORY", 425826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load", 426826db0f1SSukadev Bhattiprolu "PublicDescription": "" 427826db0f1SSukadev Bhattiprolu }, 428826db0f1SSukadev Bhattiprolu {, 429826db0f1SSukadev Bhattiprolu "EventCode": "0x201E4", 430826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3MISS", 431826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load", 432826db0f1SSukadev Bhattiprolu "PublicDescription": "" 433826db0f1SSukadev Bhattiprolu }, 434826db0f1SSukadev Bhattiprolu {, 435826db0f1SSukadev Bhattiprolu "EventCode": "0x201E8", 436826db0f1SSukadev Bhattiprolu "EventName": "PM_THRESH_EXC_512", 437826db0f1SSukadev Bhattiprolu "BriefDescription": "Threshold counter exceeded a value of 512", 438826db0f1SSukadev Bhattiprolu "PublicDescription": "" 439826db0f1SSukadev Bhattiprolu }, 440826db0f1SSukadev Bhattiprolu {, 441826db0f1SSukadev Bhattiprolu "EventCode": "0x200F2", 442826db0f1SSukadev Bhattiprolu "EventName": "PM_INST_DISP", 443826db0f1SSukadev Bhattiprolu "BriefDescription": "# PPC Dispatched", 444826db0f1SSukadev Bhattiprolu "PublicDescription": "" 445826db0f1SSukadev Bhattiprolu }, 446826db0f1SSukadev Bhattiprolu {, 447826db0f1SSukadev Bhattiprolu "EventCode": "0x30016", 448826db0f1SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_SRQ_FULL", 449826db0f1SSukadev Bhattiprolu "BriefDescription": "Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full", 450826db0f1SSukadev Bhattiprolu "PublicDescription": "" 451826db0f1SSukadev Bhattiprolu }, 452826db0f1SSukadev Bhattiprolu {, 453826db0f1SSukadev Bhattiprolu "EventCode": "0x30018", 454826db0f1SSukadev Bhattiprolu "EventName": "PM_ICT_NOSLOT_DISP_HELD_HB_FULL", 455826db0f1SSukadev Bhattiprolu "BriefDescription": "Ict empty for this thread due to dispatch holds because the History Buffer was full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)", 456826db0f1SSukadev Bhattiprolu "PublicDescription": "" 457826db0f1SSukadev Bhattiprolu }, 458826db0f1SSukadev Bhattiprolu {, 459826db0f1SSukadev Bhattiprolu "EventCode": "0x3001A", 460826db0f1SSukadev Bhattiprolu "EventName": "PM_DATA_TABLEWALK_CYC", 461826db0f1SSukadev Bhattiprolu "BriefDescription": "Data Tablewalk Cycles. Could be 1 or 2 active tablewalks. Includes data prefetches.", 462826db0f1SSukadev Bhattiprolu "PublicDescription": "" 463826db0f1SSukadev Bhattiprolu }, 464826db0f1SSukadev Bhattiprolu {, 465826db0f1SSukadev Bhattiprolu "EventCode": "0x30132", 466826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_VSU_FIN", 467826db0f1SSukadev Bhattiprolu "BriefDescription": "VSU marked instr finish", 468826db0f1SSukadev Bhattiprolu "PublicDescription": "" 469826db0f1SSukadev Bhattiprolu }, 470826db0f1SSukadev Bhattiprolu {, 471826db0f1SSukadev Bhattiprolu "EventCode": "0x30134", 472826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_ST_CMPL_INT", 473826db0f1SSukadev Bhattiprolu "BriefDescription": "marked store finished with intervention", 474826db0f1SSukadev Bhattiprolu "PublicDescription": "" 475826db0f1SSukadev Bhattiprolu }, 476826db0f1SSukadev Bhattiprolu {, 477826db0f1SSukadev Bhattiprolu "EventCode": "0x30038", 478826db0f1SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_DMISS_LMEM", 479826db0f1SSukadev Bhattiprolu "BriefDescription": "Completion stall due to cache miss that resolves in local memory", 480826db0f1SSukadev Bhattiprolu "PublicDescription": "" 481826db0f1SSukadev Bhattiprolu }, 482826db0f1SSukadev Bhattiprolu {, 483826db0f1SSukadev Bhattiprolu "EventCode": "0x3C040", 484826db0f1SSukadev Bhattiprolu "EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST", 485826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load", 486826db0f1SSukadev Bhattiprolu "PublicDescription": "" 487826db0f1SSukadev Bhattiprolu }, 488826db0f1SSukadev Bhattiprolu {, 489826db0f1SSukadev Bhattiprolu "EventCode": "0x3C042", 490826db0f1SSukadev Bhattiprolu "EventName": "PM_DATA_FROM_L3_DISP_CONFLICT", 491826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load", 492826db0f1SSukadev Bhattiprolu "PublicDescription": "" 493826db0f1SSukadev Bhattiprolu }, 494826db0f1SSukadev Bhattiprolu {, 495826db0f1SSukadev Bhattiprolu "EventCode": "0x3D140", 496826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC", 497826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load", 498826db0f1SSukadev Bhattiprolu "PublicDescription": "" 499826db0f1SSukadev Bhattiprolu }, 500826db0f1SSukadev Bhattiprolu {, 501826db0f1SSukadev Bhattiprolu "EventCode": "0x3D144", 502826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2_MEPF_CYC", 503826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load", 504826db0f1SSukadev Bhattiprolu "PublicDescription": "" 505826db0f1SSukadev Bhattiprolu }, 506826db0f1SSukadev Bhattiprolu {, 507826db0f1SSukadev Bhattiprolu "EventCode": "0x3D146", 508826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT", 509826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load", 510826db0f1SSukadev Bhattiprolu "PublicDescription": "" 511826db0f1SSukadev Bhattiprolu }, 512826db0f1SSukadev Bhattiprolu {, 513826db0f1SSukadev Bhattiprolu "EventCode": "0x3D14C", 514826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DMEM", 515826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load", 516826db0f1SSukadev Bhattiprolu "PublicDescription": "" 517826db0f1SSukadev Bhattiprolu }, 518826db0f1SSukadev Bhattiprolu {, 519826db0f1SSukadev Bhattiprolu "EventCode": "0x3D14E", 520826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD", 521826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 522826db0f1SSukadev Bhattiprolu "PublicDescription": "" 523826db0f1SSukadev Bhattiprolu }, 524826db0f1SSukadev Bhattiprolu {, 525826db0f1SSukadev Bhattiprolu "EventCode": "0x35042", 526826db0f1SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_L3_DISP_CONFLICT", 527826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request", 528826db0f1SSukadev Bhattiprolu "PublicDescription": "" 529826db0f1SSukadev Bhattiprolu }, 530826db0f1SSukadev Bhattiprolu {, 531826db0f1SSukadev Bhattiprolu "EventCode": "0x35048", 532826db0f1SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_DL2L3_SHR", 533826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", 534826db0f1SSukadev Bhattiprolu "PublicDescription": "" 535826db0f1SSukadev Bhattiprolu }, 536826db0f1SSukadev Bhattiprolu {, 537826db0f1SSukadev Bhattiprolu "EventCode": "0x3504C", 538826db0f1SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_DL4", 539826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request", 540826db0f1SSukadev Bhattiprolu "PublicDescription": "" 541826db0f1SSukadev Bhattiprolu }, 542826db0f1SSukadev Bhattiprolu {, 543826db0f1SSukadev Bhattiprolu "EventCode": "0x3F146", 544826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DPTEG_FROM_L2.1_SHR", 545826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", 546826db0f1SSukadev Bhattiprolu "PublicDescription": "" 547826db0f1SSukadev Bhattiprolu }, 548826db0f1SSukadev Bhattiprolu {, 549826db0f1SSukadev Bhattiprolu "EventCode": "0x3005A", 550826db0f1SSukadev Bhattiprolu "EventName": "PM_ISQ_0_8_ENTRIES", 551826db0f1SSukadev Bhattiprolu "BriefDescription": "Cycles in which 8 or less Issue Queue entries are in use. This is a shared event, not per thread", 552826db0f1SSukadev Bhattiprolu "PublicDescription": "" 553826db0f1SSukadev Bhattiprolu }, 554826db0f1SSukadev Bhattiprolu {, 555826db0f1SSukadev Bhattiprolu "EventCode": "0x3005C", 556826db0f1SSukadev Bhattiprolu "EventName": "PM_BFU_BUSY", 557826db0f1SSukadev Bhattiprolu "BriefDescription": "Cycles in which all 4 Binary Floating Point units are busy. The BFU is running at capacity", 558826db0f1SSukadev Bhattiprolu "PublicDescription": "" 559826db0f1SSukadev Bhattiprolu }, 560826db0f1SSukadev Bhattiprolu {, 561826db0f1SSukadev Bhattiprolu "EventCode": "0x3C05E", 562826db0f1SSukadev Bhattiprolu "EventName": "PM_MEM_RWITM", 563826db0f1SSukadev Bhattiprolu "BriefDescription": "Memory Read With Intent to Modify for this thread", 564826db0f1SSukadev Bhattiprolu "PublicDescription": "" 565826db0f1SSukadev Bhattiprolu }, 566826db0f1SSukadev Bhattiprolu {, 567826db0f1SSukadev Bhattiprolu "EventCode": "0x34054", 568826db0f1SSukadev Bhattiprolu "EventName": "PM_PARTIAL_ST_FIN", 569826db0f1SSukadev Bhattiprolu "BriefDescription": "Any store finished by an LSU slice", 570826db0f1SSukadev Bhattiprolu "PublicDescription": "" 571826db0f1SSukadev Bhattiprolu }, 572826db0f1SSukadev Bhattiprolu {, 573826db0f1SSukadev Bhattiprolu "EventCode": "0x3D15E", 574826db0f1SSukadev Bhattiprolu "EventName": "PM_MULT_MRK", 575826db0f1SSukadev Bhattiprolu "BriefDescription": "mult marked instr", 576826db0f1SSukadev Bhattiprolu "PublicDescription": "" 577826db0f1SSukadev Bhattiprolu }, 578826db0f1SSukadev Bhattiprolu {, 579826db0f1SSukadev Bhattiprolu "EventCode": "0x35152", 580826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2MISS_CYC", 581826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from a location other than the local core's L2 due to a marked load", 582826db0f1SSukadev Bhattiprolu "PublicDescription": "" 583826db0f1SSukadev Bhattiprolu }, 584826db0f1SSukadev Bhattiprolu {, 585826db0f1SSukadev Bhattiprolu "EventCode": "0x35154", 586826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_CYC", 587826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load", 588826db0f1SSukadev Bhattiprolu "PublicDescription": "" 589826db0f1SSukadev Bhattiprolu }, 590826db0f1SSukadev Bhattiprolu {, 591826db0f1SSukadev Bhattiprolu "EventCode": "0x35156", 592826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3.1_SHR_CYC", 593826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load", 594826db0f1SSukadev Bhattiprolu "PublicDescription": "" 595826db0f1SSukadev Bhattiprolu }, 596826db0f1SSukadev Bhattiprolu {, 597826db0f1SSukadev Bhattiprolu "EventCode": "0x35158", 598826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3.1_ECO_MOD_CYC", 599826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load", 600826db0f1SSukadev Bhattiprolu "PublicDescription": "" 601826db0f1SSukadev Bhattiprolu }, 602826db0f1SSukadev Bhattiprolu {, 603826db0f1SSukadev Bhattiprolu "EventCode": "0x3515E", 604826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_BACK_BR_CMPL", 605826db0f1SSukadev Bhattiprolu "BriefDescription": "Marked branch instruction completed with a target address less than current instruction address", 606826db0f1SSukadev Bhattiprolu "PublicDescription": "" 607826db0f1SSukadev Bhattiprolu }, 608826db0f1SSukadev Bhattiprolu {, 609826db0f1SSukadev Bhattiprolu "EventCode": "0x3E05E", 610826db0f1SSukadev Bhattiprolu "EventName": "PM_L3_CO_MEPF", 611826db0f1SSukadev Bhattiprolu "BriefDescription": "L3 castouts in Mepf state for this thread", 612826db0f1SSukadev Bhattiprolu "PublicDescription": "" 613826db0f1SSukadev Bhattiprolu }, 614826db0f1SSukadev Bhattiprolu {, 615826db0f1SSukadev Bhattiprolu "EventCode": "0x3F150", 616826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_ST_DRAIN_TO_L2DISP_CYC", 617826db0f1SSukadev Bhattiprolu "BriefDescription": "cycles to drain st from core to L2", 618826db0f1SSukadev Bhattiprolu "PublicDescription": "" 619826db0f1SSukadev Bhattiprolu }, 620826db0f1SSukadev Bhattiprolu {, 621826db0f1SSukadev Bhattiprolu "EventCode": "0x3F054", 622826db0f1SSukadev Bhattiprolu "EventName": "PM_RADIX_PWC_L4_PTE_FROM_L3MISS", 623826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cache. This is the deepest level of PWC possible for a translation. The source could be local/remote/distant memory or another core's cache", 624826db0f1SSukadev Bhattiprolu "PublicDescription": "" 625826db0f1SSukadev Bhattiprolu }, 626826db0f1SSukadev Bhattiprolu {, 627826db0f1SSukadev Bhattiprolu "EventCode": "0x30162", 628826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_LSU_DERAT_MISS", 629826db0f1SSukadev Bhattiprolu "BriefDescription": "Marked derat reload (miss) for any page size", 630826db0f1SSukadev Bhattiprolu "PublicDescription": "" 631826db0f1SSukadev Bhattiprolu }, 632826db0f1SSukadev Bhattiprolu {, 633826db0f1SSukadev Bhattiprolu "EventCode": "0x3006A", 634826db0f1SSukadev Bhattiprolu "EventName": "PM_IERAT_RELOAD_64K", 635826db0f1SSukadev Bhattiprolu "BriefDescription": "IERAT Reloaded (Miss) for a 64k page", 636826db0f1SSukadev Bhattiprolu "PublicDescription": "" 637826db0f1SSukadev Bhattiprolu }, 638826db0f1SSukadev Bhattiprolu {, 639826db0f1SSukadev Bhattiprolu "EventCode": "0x300F8", 640826db0f1SSukadev Bhattiprolu "EventName": "PM_TB_BIT_TRANS", 641826db0f1SSukadev Bhattiprolu "BriefDescription": "timebase event", 642826db0f1SSukadev Bhattiprolu "PublicDescription": "" 643826db0f1SSukadev Bhattiprolu }, 644826db0f1SSukadev Bhattiprolu {, 645826db0f1SSukadev Bhattiprolu "EventCode": "0x40006", 646826db0f1SSukadev Bhattiprolu "EventName": "PM_ISLB_MISS", 647826db0f1SSukadev Bhattiprolu "BriefDescription": "Number of ISLB misses for this thread", 648826db0f1SSukadev Bhattiprolu "PublicDescription": "" 649826db0f1SSukadev Bhattiprolu }, 650826db0f1SSukadev Bhattiprolu {, 651826db0f1SSukadev Bhattiprolu "EventCode": "0x40008", 652826db0f1SSukadev Bhattiprolu "EventName": "PM_SRQ_EMPTY_CYC", 653826db0f1SSukadev Bhattiprolu "BriefDescription": "Cycles in which the SRQ has at least one (out of four) empty slice", 654826db0f1SSukadev Bhattiprolu "PublicDescription": "" 655826db0f1SSukadev Bhattiprolu }, 656826db0f1SSukadev Bhattiprolu {, 657826db0f1SSukadev Bhattiprolu "EventCode": "0x40014", 658826db0f1SSukadev Bhattiprolu "EventName": "PM_PROBE_NOP_DISP", 659826db0f1SSukadev Bhattiprolu "BriefDescription": "ProbeNops dispatched", 660826db0f1SSukadev Bhattiprolu "PublicDescription": "" 661826db0f1SSukadev Bhattiprolu }, 662826db0f1SSukadev Bhattiprolu {, 663826db0f1SSukadev Bhattiprolu "EventCode": "0x4001C", 664826db0f1SSukadev Bhattiprolu "EventName": "PM_INST_IMC_MATCH_CMPL", 665826db0f1SSukadev Bhattiprolu "BriefDescription": "IMC Match Count", 666826db0f1SSukadev Bhattiprolu "PublicDescription": "" 667826db0f1SSukadev Bhattiprolu }, 668826db0f1SSukadev Bhattiprolu {, 669826db0f1SSukadev Bhattiprolu "EventCode": "0x4C01A", 670826db0f1SSukadev Bhattiprolu "EventName": "PM_CMPLU_STALL_DMISS_L3MISS", 671826db0f1SSukadev Bhattiprolu "BriefDescription": "Completion stall due to cache miss resolving missed the L3", 672826db0f1SSukadev Bhattiprolu "PublicDescription": "" 673826db0f1SSukadev Bhattiprolu }, 674826db0f1SSukadev Bhattiprolu {, 675826db0f1SSukadev Bhattiprolu "EventCode": "0x4D012", 676826db0f1SSukadev Bhattiprolu "EventName": "PM_PMC3_SAVED", 677826db0f1SSukadev Bhattiprolu "BriefDescription": "PMC3 Rewind Value saved", 678826db0f1SSukadev Bhattiprolu "PublicDescription": "" 679826db0f1SSukadev Bhattiprolu }, 680826db0f1SSukadev Bhattiprolu {, 681826db0f1SSukadev Bhattiprolu "EventCode": "0x4E11E", 682826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DMEM_CYC", 683826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load", 684826db0f1SSukadev Bhattiprolu "PublicDescription": "" 685826db0f1SSukadev Bhattiprolu }, 686826db0f1SSukadev Bhattiprolu {, 687826db0f1SSukadev Bhattiprolu "EventCode": "0x4C124", 688826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC", 689826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload from local core's L3 without conflict due to a marked load", 690826db0f1SSukadev Bhattiprolu "PublicDescription": "" 691826db0f1SSukadev Bhattiprolu }, 692826db0f1SSukadev Bhattiprolu {, 693826db0f1SSukadev Bhattiprolu "EventCode": "0x4D12E", 694826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD_CYC", 695826db0f1SSukadev Bhattiprolu "BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 696826db0f1SSukadev Bhattiprolu "PublicDescription": "" 697826db0f1SSukadev Bhattiprolu }, 698826db0f1SSukadev Bhattiprolu {, 699826db0f1SSukadev Bhattiprolu "EventCode": "0x4013A", 700826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_IC_MISS", 701826db0f1SSukadev Bhattiprolu "BriefDescription": "Marked instruction experienced I cache miss", 702826db0f1SSukadev Bhattiprolu "PublicDescription": "" 703826db0f1SSukadev Bhattiprolu }, 704826db0f1SSukadev Bhattiprolu {, 705826db0f1SSukadev Bhattiprolu "EventCode": "0x44044", 706826db0f1SSukadev Bhattiprolu "EventName": "PM_INST_FROM_L3.1_ECO_MOD", 707826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)", 708826db0f1SSukadev Bhattiprolu "PublicDescription": "" 709826db0f1SSukadev Bhattiprolu }, 710826db0f1SSukadev Bhattiprolu {, 711826db0f1SSukadev Bhattiprolu "EventCode": "0x44046", 712826db0f1SSukadev Bhattiprolu "EventName": "PM_INST_FROM_L2.1_MOD", 713826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)", 714826db0f1SSukadev Bhattiprolu "PublicDescription": "" 715826db0f1SSukadev Bhattiprolu }, 716826db0f1SSukadev Bhattiprolu {, 717826db0f1SSukadev Bhattiprolu "EventCode": "0x4404A", 718826db0f1SSukadev Bhattiprolu "EventName": "PM_INST_FROM_OFF_CHIP_CACHE", 719826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)", 720826db0f1SSukadev Bhattiprolu "PublicDescription": "" 721826db0f1SSukadev Bhattiprolu }, 722826db0f1SSukadev Bhattiprolu {, 723826db0f1SSukadev Bhattiprolu "EventCode": "0x4D144", 724826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L3.1_ECO_MOD", 725826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load", 726826db0f1SSukadev Bhattiprolu "PublicDescription": "" 727826db0f1SSukadev Bhattiprolu }, 728826db0f1SSukadev Bhattiprolu {, 729826db0f1SSukadev Bhattiprolu "EventCode": "0x4D146", 730826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2.1_MOD", 731826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load", 732826db0f1SSukadev Bhattiprolu "PublicDescription": "" 733826db0f1SSukadev Bhattiprolu }, 734826db0f1SSukadev Bhattiprolu {, 735826db0f1SSukadev Bhattiprolu "EventCode": "0x4504C", 736826db0f1SSukadev Bhattiprolu "EventName": "PM_IPTEG_FROM_DMEM", 737826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request", 738826db0f1SSukadev Bhattiprolu "PublicDescription": "" 739826db0f1SSukadev Bhattiprolu }, 740826db0f1SSukadev Bhattiprolu {, 741826db0f1SSukadev Bhattiprolu "EventCode": "0x4E044", 742826db0f1SSukadev Bhattiprolu "EventName": "PM_DPTEG_FROM_L3.1_ECO_MOD", 743826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", 744826db0f1SSukadev Bhattiprolu "PublicDescription": "" 745826db0f1SSukadev Bhattiprolu }, 746826db0f1SSukadev Bhattiprolu {, 747826db0f1SSukadev Bhattiprolu "EventCode": "0x4E04A", 748826db0f1SSukadev Bhattiprolu "EventName": "PM_DPTEG_FROM_OFF_CHIP_CACHE", 749826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", 750826db0f1SSukadev Bhattiprolu "PublicDescription": "" 751826db0f1SSukadev Bhattiprolu }, 752826db0f1SSukadev Bhattiprolu {, 753826db0f1SSukadev Bhattiprolu "EventCode": "0x40154", 754826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_FAB_RSP_BKILL", 755826db0f1SSukadev Bhattiprolu "BriefDescription": "Marked store had to do a bkill", 756826db0f1SSukadev Bhattiprolu "PublicDescription": "" 757826db0f1SSukadev Bhattiprolu }, 758826db0f1SSukadev Bhattiprolu {, 759826db0f1SSukadev Bhattiprolu "EventCode": "0x4C054", 760826db0f1SSukadev Bhattiprolu "EventName": "PM_DERAT_MISS_16G", 761826db0f1SSukadev Bhattiprolu "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G", 762826db0f1SSukadev Bhattiprolu "PublicDescription": "" 763826db0f1SSukadev Bhattiprolu }, 764826db0f1SSukadev Bhattiprolu {, 765826db0f1SSukadev Bhattiprolu "EventCode": "0x4C05A", 766826db0f1SSukadev Bhattiprolu "EventName": "PM_DTLB_MISS_1G", 767826db0f1SSukadev Bhattiprolu "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used", 768826db0f1SSukadev Bhattiprolu "PublicDescription": "" 769826db0f1SSukadev Bhattiprolu }, 770826db0f1SSukadev Bhattiprolu {, 771826db0f1SSukadev Bhattiprolu "EventCode": "0x44054", 772826db0f1SSukadev Bhattiprolu "EventName": "PM_VECTOR_LD_CMPL", 773826db0f1SSukadev Bhattiprolu "BriefDescription": "Number of vector load instructions completed", 774826db0f1SSukadev Bhattiprolu "PublicDescription": "" 775826db0f1SSukadev Bhattiprolu }, 776826db0f1SSukadev Bhattiprolu {, 777826db0f1SSukadev Bhattiprolu "EventCode": "0x4D05E", 778826db0f1SSukadev Bhattiprolu "EventName": "PM_BR_CMPL", 779826db0f1SSukadev Bhattiprolu "BriefDescription": "Any Branch instruction completed", 780826db0f1SSukadev Bhattiprolu "PublicDescription": "" 781826db0f1SSukadev Bhattiprolu }, 782826db0f1SSukadev Bhattiprolu {, 783826db0f1SSukadev Bhattiprolu "EventCode": "0x45054", 784826db0f1SSukadev Bhattiprolu "EventName": "PM_FMA_CMPL", 785826db0f1SSukadev Bhattiprolu "BriefDescription": "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only. ", 786826db0f1SSukadev Bhattiprolu "PublicDescription": "" 787826db0f1SSukadev Bhattiprolu }, 788826db0f1SSukadev Bhattiprolu {, 789826db0f1SSukadev Bhattiprolu "EventCode": "0x45056", 790826db0f1SSukadev Bhattiprolu "EventName": "PM_SCALAR_FLOP_CMPL", 791826db0f1SSukadev Bhattiprolu "BriefDescription": "Scalar flop operation completed", 792826db0f1SSukadev Bhattiprolu "PublicDescription": "" 793826db0f1SSukadev Bhattiprolu }, 794826db0f1SSukadev Bhattiprolu {, 795826db0f1SSukadev Bhattiprolu "EventCode": "0x4505C", 796826db0f1SSukadev Bhattiprolu "EventName": "PM_MATH_FLOP_CMPL", 797826db0f1SSukadev Bhattiprolu "BriefDescription": "Math flop instruction completed", 798826db0f1SSukadev Bhattiprolu "PublicDescription": "" 799826db0f1SSukadev Bhattiprolu }, 800826db0f1SSukadev Bhattiprolu {, 801826db0f1SSukadev Bhattiprolu "EventCode": "0x4E05E", 802826db0f1SSukadev Bhattiprolu "EventName": "PM_TM_OUTER_TBEGIN_DISP", 803826db0f1SSukadev Bhattiprolu "BriefDescription": "Number of outer tbegin instructions dispatched. The dispatch unit determines whether the tbegin instruction is outer or nested. This is a speculative count, which includes flushed instructions", 804826db0f1SSukadev Bhattiprolu "PublicDescription": "" 805826db0f1SSukadev Bhattiprolu }, 806826db0f1SSukadev Bhattiprolu {, 807826db0f1SSukadev Bhattiprolu "EventCode": "0x4F054", 808826db0f1SSukadev Bhattiprolu "EventName": "PM_RADIX_PWC_MISS", 809826db0f1SSukadev Bhattiprolu "BriefDescription": "A radix translation attempt missed in the TLB and all levels of page walk cache.", 810826db0f1SSukadev Bhattiprolu "PublicDescription": "" 811826db0f1SSukadev Bhattiprolu }, 812826db0f1SSukadev Bhattiprolu {, 813826db0f1SSukadev Bhattiprolu "EventCode": "0x4F05C", 814826db0f1SSukadev Bhattiprolu "EventName": "PM_RADIX_PWC_L2_PTE_FROM_L3MISS", 815826db0f1SSukadev Bhattiprolu "BriefDescription": "A Page Table Entry was reloaded to a level 2 page walk cache from beyond the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation. The source could be local/remote/distant memory or another core's cache", 816826db0f1SSukadev Bhattiprolu "PublicDescription": "" 817826db0f1SSukadev Bhattiprolu }, 818826db0f1SSukadev Bhattiprolu {, 819826db0f1SSukadev Bhattiprolu "EventCode": "0x401E6", 820826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_INST_FROM_L3MISS", 821826db0f1SSukadev Bhattiprolu "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet", 822826db0f1SSukadev Bhattiprolu "PublicDescription": "" 823826db0f1SSukadev Bhattiprolu }, 824826db0f1SSukadev Bhattiprolu {, 825826db0f1SSukadev Bhattiprolu "EventCode": "0x401E8", 826826db0f1SSukadev Bhattiprolu "EventName": "PM_MRK_DATA_FROM_L2MISS", 827826db0f1SSukadev Bhattiprolu "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a marked load", 828826db0f1SSukadev Bhattiprolu "PublicDescription": "" 829826db0f1SSukadev Bhattiprolu }, 830826db0f1SSukadev Bhattiprolu {, 831826db0f1SSukadev Bhattiprolu "EventCode": "0x400FA", 832826db0f1SSukadev Bhattiprolu "EventName": "PM_RUN_INST_CMPL", 833826db0f1SSukadev Bhattiprolu "BriefDescription": "Run_Instructions", 834826db0f1SSukadev Bhattiprolu "PublicDescription": "" 835826db0f1SSukadev Bhattiprolu } 836826db0f1SSukadev Bhattiprolu] 837