[
  {,
    "EventCode": "0x1001C",
    "EventName": "PM_CMPLU_STALL_THRD",
    "BriefDescription": "Completion Stalled because the thread was blocked",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1002E",
    "EventName": "PM_LMQ_MERGE",
    "BriefDescription": "A demand miss collides with a prefetch for the same line",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x10134",
    "EventName": "PM_MRK_ST_DONE_L2",
    "BriefDescription": "marked store completed in L2 ( RC machine done)",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x10138",
    "EventName": "PM_MRK_BR_2PATH",
    "BriefDescription": "marked branches which are not strongly biased",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1C04A",
    "EventName": "PM_DATA_FROM_RL2L3_SHR",
    "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1C04C",
    "EventName": "PM_DATA_FROM_LL4",
    "BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1D140",
    "EventName": "PM_MRK_DATA_FROM_L3.1_MOD_CYC",
    "BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1D144",
    "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT",
    "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1D146",
    "EventName": "PM_MRK_DATA_FROM_MEMORY_CYC",
    "BriefDescription": "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1D148",
    "EventName": "PM_MRK_DATA_FROM_RMEM",
    "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1D14E",
    "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC",
    "BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x15040",
    "EventName": "PM_IPTEG_FROM_L2_NO_CONFLICT",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1504C",
    "EventName": "PM_IPTEG_FROM_LL4",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1E048",
    "EventName": "PM_DPTEG_FROM_ON_CHIP_CACHE",
    "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1E04E",
    "EventName": "PM_DPTEG_FROM_L2MISS",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1F146",
    "EventName": "PM_MRK_DPTEG_FROM_L3.1_SHR",
    "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x10052",
    "EventName": "PM_GRP_PUMP_MPRED_RTY",
    "BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1C05C",
    "EventName": "PM_DTLB_MISS_2M",
    "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x14156",
    "EventName": "PM_MRK_DATA_FROM_L2_CYC",
    "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x14158",
    "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC",
    "BriefDescription": "Duration in cycles to reload from local core's L2 without conflict due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1415C",
    "EventName": "PM_MRK_DATA_FROM_L3_MEPF_CYC",
    "BriefDescription": "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1D150",
    "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR",
    "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1D152",
    "EventName": "PM_MRK_DATA_FROM_DL4",
    "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1D156",
    "EventName": "PM_MRK_LD_MISS_L1_CYC",
    "BriefDescription": "Marked ld latency",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x15154",
    "EventName": "PM_SYNC_MRK_L3MISS",
    "BriefDescription": "Marked L3 misses that can throw a synchronous interrupt",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1515A",
    "EventName": "PM_SYNC_MRK_L2MISS",
    "BriefDescription": "Marked L2 Miss that can throw a synchronous interrupt",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1E05A",
    "EventName": "PM_CMPLU_STALL_ANY_SYNC",
    "BriefDescription": "Cycles in which the NTC sync instruction (isync, lwsync or hwsync) is not allowed to complete ",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1E05C",
    "EventName": "PM_CMPLU_STALL_NESTED_TBEGIN",
    "BriefDescription": "Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin. This is a short delay, and it includes ROT",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1F152",
    "EventName": "PM_MRK_FAB_RSP_BKILL_CYC",
    "BriefDescription": "cycles L2 RC took for a bkill",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x1F056",
    "EventName": "PM_RADIX_PWC_L1_HIT",
    "BriefDescription": "A radix translation attempt missed in the TLB and only the first level page walk cache was a hit.",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x101E4",
    "EventName": "PM_MRK_L1_ICACHE_MISS",
    "BriefDescription": "sampled Instruction suffered an icache Miss",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x101EA",
    "EventName": "PM_MRK_L1_RELOAD_VALID",
    "BriefDescription": "Marked demand reload",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x100FA",
    "EventName": "PM_ANY_THRD_RUN_CYC",
    "BriefDescription": "Cycles in which at least one thread has the run latch set",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x100FC",
    "EventName": "PM_LD_REF_L1",
    "BriefDescription": "All L1 D cache load references counted at finish, gated by reject",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x20006",
    "EventName": "PM_DISP_HELD_ISSQ_FULL",
    "BriefDescription": "Dispatch held due to Issue q full. Includes issue queue and branch queue",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2000C",
    "EventName": "PM_THRD_ALL_RUN_CYC",
    "BriefDescription": "Cycles in which all the threads have the run latch set",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2001A",
    "EventName": "PM_NTC_ALL_FIN",
    "BriefDescription": "Cycles after all instructions have finished to group completed",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2D014",
    "EventName": "PM_CMPLU_STALL_LRQ_FULL",
    "BriefDescription": "Finish stall because the NTF instruction was a load that was held in LSAQ (load-store address queue) because the LRQ (load-reorder queue) was full",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2D018",
    "EventName": "PM_CMPLU_STALL_EXEC_UNIT",
    "BriefDescription": "Completion stall due to execution units (FXU/VSU/CRU)",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2D01E",
    "EventName": "PM_ICT_NOSLOT_DISP_HELD_ISSQ",
    "BriefDescription": "Ict empty for this thread due to dispatch hold on this thread due to Issue q full, BRQ full, XVCF Full, Count cache, Link, Tar full",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2E014",
    "EventName": "PM_STCX_FIN",
    "BriefDescription": "Number of stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2C120",
    "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT",
    "BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2C122",
    "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC",
    "BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2C126",
    "EventName": "PM_MRK_DATA_FROM_L2",
    "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2C12A",
    "EventName": "PM_MRK_DATA_FROM_RMEM_CYC",
    "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2C12C",
    "EventName": "PM_MRK_DATA_FROM_DL4_CYC",
    "BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2D120",
    "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE",
    "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2D026",
    "EventName": "PM_RADIX_PWC_L1_PDE_FROM_L2",
    "BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L2 data cache",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x20132",
    "EventName": "PM_MRK_DFU_FIN",
    "BriefDescription": "Decimal Unit marked Instruction Finish",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x20134",
    "EventName": "PM_MRK_FXU_FIN",
    "BriefDescription": "fxu marked instr finish",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2C04E",
    "EventName": "PM_LD_MISS_L1_FIN",
    "BriefDescription": "Number of load instructions that finished with an L1 miss. Note that even if a load spans multiple slices this event will increment only once per load op.",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x24040",
    "EventName": "PM_INST_FROM_L2_MEPF",
    "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch)",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x24048",
    "EventName": "PM_INST_FROM_LMEM",
    "BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2D142",
    "EventName": "PM_MRK_DATA_FROM_L3_MEPF",
    "BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2D144",
    "EventName": "PM_MRK_DATA_FROM_L3.1_MOD",
    "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2D148",
    "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
    "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x25048",
    "EventName": "PM_IPTEG_FROM_LMEM",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2E040",
    "EventName": "PM_DPTEG_FROM_L2_MEPF",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2E04A",
    "EventName": "PM_DPTEG_FROM_RL4",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2F14A",
    "EventName": "PM_MRK_DPTEG_FROM_RL4",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x20054",
    "EventName": "PM_L1_PREF",
    "BriefDescription": "A data line was written to the L1 due to a hardware or software prefetch",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x20056",
    "EventName": "PM_TAKEN_BR_MPRED_CMPL",
    "BriefDescription": "Total number of taken branches that were incorrectly predicted as not-taken. This event counts branches completed and does not include speculative instructions",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x20058",
    "EventName": "PM_DARQ1_10_12_ENTRIES",
    "BriefDescription": "Cycles in which 10 or  more DARQ1 entries (out of 12) are in use",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2C050",
    "EventName": "PM_DATA_GRP_PUMP_CPRED",
    "BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2C05E",
    "EventName": "PM_INST_GRP_PUMP_MPRED",
    "BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only)",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2505C",
    "EventName": "PM_VSU_FIN",
    "BriefDescription": "VSU instruction finished. Up to 4 per cycle",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2505E",
    "EventName": "PM_BACK_BR_CMPL",
    "BriefDescription": "Branch instruction completed with a target address less than current instruction address",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2E052",
    "EventName": "PM_TM_PASSED",
    "BriefDescription": "Number of TM transactions that passed",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x20064",
    "EventName": "PM_IERAT_RELOAD_4K",
    "BriefDescription": "IERAT reloaded (after a miss) for 4K pages",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x2006C",
    "EventName": "PM_RUN_CYC_SMT4_MODE",
    "BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT4 mode",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x201E0",
    "EventName": "PM_MRK_DATA_FROM_MEMORY",
    "BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x201E4",
    "EventName": "PM_MRK_DATA_FROM_L3MISS",
    "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x201E8",
    "EventName": "PM_THRESH_EXC_512",
    "BriefDescription": "Threshold counter exceeded a value of 512",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x200F2",
    "EventName": "PM_INST_DISP",
    "BriefDescription": "# PPC Dispatched",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x30016",
    "EventName": "PM_CMPLU_STALL_SRQ_FULL",
    "BriefDescription": "Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x30018",
    "EventName": "PM_ICT_NOSLOT_DISP_HELD_HB_FULL",
    "BriefDescription": "Ict empty for this thread due to dispatch holds because the History Buffer was full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3001A",
    "EventName": "PM_DATA_TABLEWALK_CYC",
    "BriefDescription": "Data Tablewalk Cycles.  Could be 1 or 2 active tablewalks. Includes data prefetches.",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x30132",
    "EventName": "PM_MRK_VSU_FIN",
    "BriefDescription": "VSU marked instr finish",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x30134",
    "EventName": "PM_MRK_ST_CMPL_INT",
    "BriefDescription": "marked store finished with intervention",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x30038",
    "EventName": "PM_CMPLU_STALL_DMISS_LMEM",
    "BriefDescription": "Completion stall due to cache miss that resolves in local memory",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3C040",
    "EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
    "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3C042",
    "EventName": "PM_DATA_FROM_L3_DISP_CONFLICT",
    "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3D140",
    "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC",
    "BriefDescription": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3D144",
    "EventName": "PM_MRK_DATA_FROM_L2_MEPF_CYC",
    "BriefDescription": "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3D146",
    "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT",
    "BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3D14C",
    "EventName": "PM_MRK_DATA_FROM_DMEM",
    "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3D14E",
    "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD",
    "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x35042",
    "EventName": "PM_IPTEG_FROM_L3_DISP_CONFLICT",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x35048",
    "EventName": "PM_IPTEG_FROM_DL2L3_SHR",
    "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3504C",
    "EventName": "PM_IPTEG_FROM_DL4",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3F146",
    "EventName": "PM_MRK_DPTEG_FROM_L2.1_SHR",
    "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3005A",
    "EventName": "PM_ISQ_0_8_ENTRIES",
    "BriefDescription": "Cycles in which 8 or less Issue Queue entries are in use. This is a shared event, not per thread",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3005C",
    "EventName": "PM_BFU_BUSY",
    "BriefDescription": "Cycles in which all 4 Binary Floating Point units are busy. The BFU is running at capacity",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3C05E",
    "EventName": "PM_MEM_RWITM",
    "BriefDescription": "Memory Read With Intent to Modify for this thread",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x34054",
    "EventName": "PM_PARTIAL_ST_FIN",
    "BriefDescription": "Any store finished by an LSU slice",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3D15E",
    "EventName": "PM_MULT_MRK",
    "BriefDescription": "mult marked instr",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x35152",
    "EventName": "PM_MRK_DATA_FROM_L2MISS_CYC",
    "BriefDescription": "Duration in cycles to reload from a location other than the local core's L2 due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x35154",
    "EventName": "PM_MRK_DATA_FROM_L3_CYC",
    "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x35156",
    "EventName": "PM_MRK_DATA_FROM_L3.1_SHR_CYC",
    "BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x35158",
    "EventName": "PM_MRK_DATA_FROM_L3.1_ECO_MOD_CYC",
    "BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3515E",
    "EventName": "PM_MRK_BACK_BR_CMPL",
    "BriefDescription": "Marked branch instruction completed with a target address less than current instruction address",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3E05E",
    "EventName": "PM_L3_CO_MEPF",
    "BriefDescription": "L3 castouts in Mepf state for this thread",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3F150",
    "EventName": "PM_MRK_ST_DRAIN_TO_L2DISP_CYC",
    "BriefDescription": "cycles to drain st from core to L2",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3F054",
    "EventName": "PM_RADIX_PWC_L4_PTE_FROM_L3MISS",
    "BriefDescription": "A Page Table Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cache. This is the deepest level of PWC possible for a translation. The source could be local/remote/distant memory or another core's cache",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x30162",
    "EventName": "PM_MRK_LSU_DERAT_MISS",
    "BriefDescription": "Marked derat reload (miss) for any page size",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x3006A",
    "EventName": "PM_IERAT_RELOAD_64K",
    "BriefDescription": "IERAT Reloaded (Miss) for a 64k page",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x300F8",
    "EventName": "PM_TB_BIT_TRANS",
    "BriefDescription": "timebase event",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x40006",
    "EventName": "PM_ISLB_MISS",
    "BriefDescription": "Number of ISLB misses for this thread",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x40008",
    "EventName": "PM_SRQ_EMPTY_CYC",
    "BriefDescription": "Cycles in which the SRQ has at least one (out of four) empty slice",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x40014",
    "EventName": "PM_PROBE_NOP_DISP",
    "BriefDescription": "ProbeNops dispatched",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4001C",
    "EventName": "PM_INST_IMC_MATCH_CMPL",
    "BriefDescription": "IMC Match Count",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4C01A",
    "EventName": "PM_CMPLU_STALL_DMISS_L3MISS",
    "BriefDescription": "Completion stall due to cache miss resolving missed the L3",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4D012",
    "EventName": "PM_PMC3_SAVED",
    "BriefDescription": "PMC3 Rewind Value saved",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4E11E",
    "EventName": "PM_MRK_DATA_FROM_DMEM_CYC",
    "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4C124",
    "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC",
    "BriefDescription": "Duration in cycles to reload from local core's L3 without conflict due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4D12E",
    "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD_CYC",
    "BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4013A",
    "EventName": "PM_MRK_IC_MISS",
    "BriefDescription": "Marked instruction experienced I cache miss",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x44044",
    "EventName": "PM_INST_FROM_L3.1_ECO_MOD",
    "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x44046",
    "EventName": "PM_INST_FROM_L2.1_MOD",
    "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4404A",
    "EventName": "PM_INST_FROM_OFF_CHIP_CACHE",
    "BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4D144",
    "EventName": "PM_MRK_DATA_FROM_L3.1_ECO_MOD",
    "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4D146",
    "EventName": "PM_MRK_DATA_FROM_L2.1_MOD",
    "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4504C",
    "EventName": "PM_IPTEG_FROM_DMEM",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4E044",
    "EventName": "PM_DPTEG_FROM_L3.1_ECO_MOD",
    "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4E04A",
    "EventName": "PM_DPTEG_FROM_OFF_CHIP_CACHE",
    "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x40154",
    "EventName": "PM_MRK_FAB_RSP_BKILL",
    "BriefDescription": "Marked store had to do a bkill",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4C054",
    "EventName": "PM_DERAT_MISS_16G",
    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4C05A",
    "EventName": "PM_DTLB_MISS_1G",
    "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x44054",
    "EventName": "PM_VECTOR_LD_CMPL",
    "BriefDescription": "Number of vector load instructions completed",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4D05E",
    "EventName": "PM_BR_CMPL",
    "BriefDescription": "Any Branch instruction completed",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x45054",
    "EventName": "PM_FMA_CMPL",
    "BriefDescription": "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only. ",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x45056",
    "EventName": "PM_SCALAR_FLOP_CMPL",
    "BriefDescription": "Scalar flop operation completed",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4505C",
    "EventName": "PM_MATH_FLOP_CMPL",
    "BriefDescription": "Math flop instruction completed",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4E05E",
    "EventName": "PM_TM_OUTER_TBEGIN_DISP",
    "BriefDescription": "Number of outer tbegin instructions dispatched. The dispatch unit determines whether the tbegin instruction is outer or nested. This is a speculative count, which includes flushed instructions",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4F054",
    "EventName": "PM_RADIX_PWC_MISS",
    "BriefDescription": "A radix translation attempt missed in the TLB and all levels of page walk cache.",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x4F05C",
    "EventName": "PM_RADIX_PWC_L2_PTE_FROM_L3MISS",
    "BriefDescription": "A Page Table Entry was reloaded to a level 2 page walk cache from beyond the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation. The source could be local/remote/distant memory or another core's cache",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x401E6",
    "EventName": "PM_MRK_INST_FROM_L3MISS",
    "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x401E8",
    "EventName": "PM_MRK_DATA_FROM_L2MISS",
    "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a marked load",
    "PublicDescription": ""
  },
  {,
    "EventCode": "0x400FA",
    "EventName": "PM_RUN_INST_CMPL",
    "BriefDescription": "Run_Instructions",
    "PublicDescription": ""
  }
]