1064520e8SBard Liao /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2064520e8SBard Liao /* 3064520e8SBard Liao * This file is provided under a dual BSD/GPLv2 license. When using or 4064520e8SBard Liao * redistributing this file, you may do so under either license. 5064520e8SBard Liao * 6064520e8SBard Liao * Copyright(c) 2020-2022 Intel Corporation. All rights reserved. 7064520e8SBard Liao */ 8064520e8SBard Liao 9064520e8SBard Liao /* DSP Registers */ 10064520e8SBard Liao #define MTL_HFDSSCS 0x1000 11064520e8SBard Liao #define MTL_HFDSSCS_SPA_MASK BIT(16) 12064520e8SBard Liao #define MTL_HFDSSCS_CPA_MASK BIT(24) 13064520e8SBard Liao #define MTL_HFSNDWIE 0x114C 14064520e8SBard Liao #define MTL_HFPWRCTL 0x1D18 15064520e8SBard Liao #define MTL_HfPWRCTL_WPIOXPG(x) BIT((x) + 8) 16064520e8SBard Liao #define MTL_HFPWRCTL_WPDSPHPXPG BIT(0) 17064520e8SBard Liao #define MTL_HFPWRSTS 0x1D1C 18064520e8SBard Liao #define MTL_HFPWRSTS_DSPHPXPGS_MASK BIT(0) 19064520e8SBard Liao #define MTL_HFINTIPPTR 0x1108 20064520e8SBard Liao #define MTL_IRQ_INTEN_L_HOST_IPC_MASK BIT(0) 21064520e8SBard Liao #define MTL_IRQ_INTEN_L_SOUNDWIRE_MASK BIT(6) 22064520e8SBard Liao #define MTL_HFINTIPPTR_PTR_MASK GENMASK(20, 0) 23064520e8SBard Liao 24*09e3c1d3SRander Wang #define MTL_HDA_VS_D0I3C 0x1D4A 25*09e3c1d3SRander Wang 26064520e8SBard Liao #define MTL_DSP2CXCAP_PRIMARY_CORE 0x178D00 27064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE 0x178D04 28064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK BIT(0) 29064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK BIT(8) 30064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL GENMASK(25, 24) 31064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT 24 32064520e8SBard Liao 33064520e8SBard Liao /* IPC Registers */ 34064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDR 0x73200 35064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDR_BUSY BIT(31) 36064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDR_MSG_MASK GENMASK(30, 0) 37064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDA 0x73204 38064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDA_BUSY BIT(31) 39064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDR 0x73210 40064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDR_BUSY BIT(31) 41064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDR_MSG_MASK GENMASK(30, 0) 42064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDA 0x73214 43064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDA_DONE BIT(31) 44064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDA_MSG_MASK GENMASK(30, 0) 45064520e8SBard Liao #define MTL_DSP_REG_HFIPCXCTL 0x73228 46064520e8SBard Liao #define MTL_DSP_REG_HFIPCXCTL_BUSY BIT(0) 47064520e8SBard Liao #define MTL_DSP_REG_HFIPCXCTL_DONE BIT(1) 48064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDDY 0x73300 49064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDDY 0x73380 50064520e8SBard Liao #define MTL_DSP_REG_HfHIPCIE 0x1140 51064520e8SBard Liao #define MTL_DSP_REG_HfHIPCIE_IE_MASK BIT(0) 52064520e8SBard Liao #define MTL_DSP_REG_HfSNDWIE 0x114C 53064520e8SBard Liao #define MTL_DSP_REG_HfSNDWIE_IE_MASK GENMASK(3, 0) 54064520e8SBard Liao 55064520e8SBard Liao #define MTL_DSP_IRQSTS 0x20 56064520e8SBard Liao #define MTL_DSP_IRQSTS_IPC BIT(0) 57064520e8SBard Liao #define MTL_DSP_IRQSTS_SDW BIT(6) 58064520e8SBard Liao 59064520e8SBard Liao #define MTL_DSP_PURGE_TIMEOUT_US 20000000 /* 20s */ 60064520e8SBard Liao #define MTL_DSP_REG_POLL_INTERVAL_US 10 /* 10 us */ 61064520e8SBard Liao 62064520e8SBard Liao /* Memory windows */ 63064520e8SBard Liao #define MTL_SRAM_WINDOW_OFFSET(x) (0x180000 + 0x8000 * (x)) 64064520e8SBard Liao 65064520e8SBard Liao #define MTL_DSP_MBOX_UPLINK_OFFSET (MTL_SRAM_WINDOW_OFFSET(0) + 0x1000) 66064520e8SBard Liao #define MTL_DSP_MBOX_UPLINK_SIZE 0x1000 67064520e8SBard Liao #define MTL_DSP_MBOX_DOWNLINK_OFFSET MTL_SRAM_WINDOW_OFFSET(1) 68064520e8SBard Liao #define MTL_DSP_MBOX_DOWNLINK_SIZE 0x1000 69064520e8SBard Liao 70064520e8SBard Liao /* FW registers */ 71064520e8SBard Liao #define MTL_DSP_ROM_STS MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */ 72064520e8SBard Liao #define MTL_DSP_ROM_ERROR (MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */ 73064520e8SBard Liao 74064520e8SBard Liao #define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* ROM debug status */ 75064520e8SBard Liao #define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* ROM debug error code */ 76064520e8SBard Liao #define MTL_DSP_REG_HfIMRIS1 0x162088 77064520e8SBard Liao #define MTL_DSP_REG_HfIMRIS1_IU_MASK BIT(0) 78064520e8SBard Liao 79