1*064520e8SBard Liao /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2*064520e8SBard Liao /* 3*064520e8SBard Liao * This file is provided under a dual BSD/GPLv2 license. When using or 4*064520e8SBard Liao * redistributing this file, you may do so under either license. 5*064520e8SBard Liao * 6*064520e8SBard Liao * Copyright(c) 2020-2022 Intel Corporation. All rights reserved. 7*064520e8SBard Liao */ 8*064520e8SBard Liao 9*064520e8SBard Liao /* DSP Registers */ 10*064520e8SBard Liao #define MTL_HFDSSCS 0x1000 11*064520e8SBard Liao #define MTL_HFDSSCS_SPA_MASK BIT(16) 12*064520e8SBard Liao #define MTL_HFDSSCS_CPA_MASK BIT(24) 13*064520e8SBard Liao #define MTL_HFSNDWIE 0x114C 14*064520e8SBard Liao #define MTL_HFPWRCTL 0x1D18 15*064520e8SBard Liao #define MTL_HfPWRCTL_WPIOXPG(x) BIT((x) + 8) 16*064520e8SBard Liao #define MTL_HFPWRCTL_WPDSPHPXPG BIT(0) 17*064520e8SBard Liao #define MTL_HFPWRSTS 0x1D1C 18*064520e8SBard Liao #define MTL_HFPWRSTS_DSPHPXPGS_MASK BIT(0) 19*064520e8SBard Liao #define MTL_HFINTIPPTR 0x1108 20*064520e8SBard Liao #define MTL_IRQ_INTEN_L_HOST_IPC_MASK BIT(0) 21*064520e8SBard Liao #define MTL_IRQ_INTEN_L_SOUNDWIRE_MASK BIT(6) 22*064520e8SBard Liao #define MTL_HFINTIPPTR_PTR_MASK GENMASK(20, 0) 23*064520e8SBard Liao 24*064520e8SBard Liao #define MTL_DSP2CXCAP_PRIMARY_CORE 0x178D00 25*064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE 0x178D04 26*064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK BIT(0) 27*064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK BIT(8) 28*064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL GENMASK(25, 24) 29*064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT 24 30*064520e8SBard Liao 31*064520e8SBard Liao /* IPC Registers */ 32*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDR 0x73200 33*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDR_BUSY BIT(31) 34*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDR_MSG_MASK GENMASK(30, 0) 35*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDA 0x73204 36*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDA_BUSY BIT(31) 37*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDR 0x73210 38*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDR_BUSY BIT(31) 39*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDR_MSG_MASK GENMASK(30, 0) 40*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDA 0x73214 41*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDA_DONE BIT(31) 42*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDA_MSG_MASK GENMASK(30, 0) 43*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXCTL 0x73228 44*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXCTL_BUSY BIT(0) 45*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXCTL_DONE BIT(1) 46*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDDY 0x73300 47*064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDDY 0x73380 48*064520e8SBard Liao #define MTL_DSP_REG_HfHIPCIE 0x1140 49*064520e8SBard Liao #define MTL_DSP_REG_HfHIPCIE_IE_MASK BIT(0) 50*064520e8SBard Liao #define MTL_DSP_REG_HfSNDWIE 0x114C 51*064520e8SBard Liao #define MTL_DSP_REG_HfSNDWIE_IE_MASK GENMASK(3, 0) 52*064520e8SBard Liao 53*064520e8SBard Liao #define MTL_DSP_IRQSTS 0x20 54*064520e8SBard Liao #define MTL_DSP_IRQSTS_IPC BIT(0) 55*064520e8SBard Liao #define MTL_DSP_IRQSTS_SDW BIT(6) 56*064520e8SBard Liao 57*064520e8SBard Liao #define MTL_DSP_PURGE_TIMEOUT_US 20000000 /* 20s */ 58*064520e8SBard Liao #define MTL_DSP_REG_POLL_INTERVAL_US 10 /* 10 us */ 59*064520e8SBard Liao 60*064520e8SBard Liao /* Memory windows */ 61*064520e8SBard Liao #define MTL_SRAM_WINDOW_OFFSET(x) (0x180000 + 0x8000 * (x)) 62*064520e8SBard Liao 63*064520e8SBard Liao #define MTL_DSP_MBOX_UPLINK_OFFSET (MTL_SRAM_WINDOW_OFFSET(0) + 0x1000) 64*064520e8SBard Liao #define MTL_DSP_MBOX_UPLINK_SIZE 0x1000 65*064520e8SBard Liao #define MTL_DSP_MBOX_DOWNLINK_OFFSET MTL_SRAM_WINDOW_OFFSET(1) 66*064520e8SBard Liao #define MTL_DSP_MBOX_DOWNLINK_SIZE 0x1000 67*064520e8SBard Liao 68*064520e8SBard Liao /* FW registers */ 69*064520e8SBard Liao #define MTL_DSP_ROM_STS MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */ 70*064520e8SBard Liao #define MTL_DSP_ROM_ERROR (MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */ 71*064520e8SBard Liao 72*064520e8SBard Liao #define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* ROM debug status */ 73*064520e8SBard Liao #define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* ROM debug error code */ 74*064520e8SBard Liao #define MTL_DSP_REG_HfIMRIS1 0x162088 75*064520e8SBard Liao #define MTL_DSP_REG_HfIMRIS1_IU_MASK BIT(0) 76*064520e8SBard Liao 77