1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc.
7 //
8 // Authors: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9
10 /*
11 * Hardware interface for ACP DSP Firmware binaries loader
12 */
13
14 #include <linux/firmware.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17
18 #include "../ops.h"
19 #include "acp-dsp-offset.h"
20 #include "acp.h"
21
22 #define FW_BIN 0
23 #define FW_DATA_BIN 1
24
25 #define FW_BIN_PTE_OFFSET 0x00
26 #define FW_DATA_BIN_PTE_OFFSET 0x08
27
28 #define ACP_DSP_RUN 0x00
29
acp_dsp_block_read(struct snd_sof_dev * sdev,enum snd_sof_fw_blk_type blk_type,u32 offset,void * dest,size_t size)30 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
31 u32 offset, void *dest, size_t size)
32 {
33 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
34 switch (blk_type) {
35 case SOF_FW_BLK_TYPE_SRAM:
36 offset = offset - desc->sram_pte_offset;
37 memcpy_from_scratch(sdev, offset, dest, size);
38 break;
39 default:
40 dev_err(sdev->dev, "bad blk type 0x%x\n", blk_type);
41 return -EINVAL;
42 }
43
44 return 0;
45 }
46 EXPORT_SYMBOL_NS(acp_dsp_block_read, SND_SOC_SOF_AMD_COMMON);
47
acp_dsp_block_write(struct snd_sof_dev * sdev,enum snd_sof_fw_blk_type blk_type,u32 offset,void * src,size_t size)48 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
49 u32 offset, void *src, size_t size)
50 {
51 struct pci_dev *pci = to_pci_dev(sdev->dev);
52 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
53 struct acp_dev_data *adata;
54 void *dest;
55 u32 dma_size, page_count;
56 unsigned int size_fw;
57
58 adata = sdev->pdata->hw_pdata;
59
60 switch (blk_type) {
61 case SOF_FW_BLK_TYPE_IRAM:
62 if (!adata->bin_buf) {
63 size_fw = sdev->basefw.fw->size;
64 page_count = PAGE_ALIGN(size_fw) >> PAGE_SHIFT;
65 dma_size = page_count * ACP_PAGE_SIZE;
66 adata->bin_buf = dma_alloc_coherent(&pci->dev, dma_size,
67 &adata->sha_dma_addr,
68 GFP_ATOMIC);
69 if (!adata->bin_buf)
70 return -ENOMEM;
71 }
72 adata->fw_bin_size = size + offset;
73 dest = adata->bin_buf + offset;
74 break;
75 case SOF_FW_BLK_TYPE_DRAM:
76 if (!adata->data_buf) {
77 adata->data_buf = dma_alloc_coherent(&pci->dev,
78 ACP_DEFAULT_DRAM_LENGTH,
79 &adata->dma_addr,
80 GFP_ATOMIC);
81 if (!adata->data_buf)
82 return -ENOMEM;
83 }
84 dest = adata->data_buf + offset;
85 adata->fw_data_bin_size = size + offset;
86 break;
87 case SOF_FW_BLK_TYPE_SRAM:
88 offset = offset - desc->sram_pte_offset;
89 memcpy_to_scratch(sdev, offset, src, size);
90 return 0;
91 default:
92 dev_err(sdev->dev, "bad blk type 0x%x\n", blk_type);
93 return -EINVAL;
94 }
95
96 memcpy(dest, src, size);
97 return 0;
98 }
99 EXPORT_SYMBOL_NS(acp_dsp_block_write, SND_SOC_SOF_AMD_COMMON);
100
acp_get_bar_index(struct snd_sof_dev * sdev,u32 type)101 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type)
102 {
103 return type;
104 }
105 EXPORT_SYMBOL_NS(acp_get_bar_index, SND_SOC_SOF_AMD_COMMON);
106
configure_pte_for_fw_loading(int type,int num_pages,struct acp_dev_data * adata)107 static void configure_pte_for_fw_loading(int type, int num_pages, struct acp_dev_data *adata)
108 {
109 struct snd_sof_dev *sdev = adata->dev;
110 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
111 unsigned int low, high;
112 dma_addr_t addr;
113 u16 page_idx;
114 u32 offset;
115
116 switch (type) {
117 case FW_BIN:
118 offset = FW_BIN_PTE_OFFSET;
119 addr = adata->sha_dma_addr;
120 break;
121 case FW_DATA_BIN:
122 offset = adata->fw_bin_page_count * 8;
123 addr = adata->dma_addr;
124 break;
125 default:
126 dev_err(sdev->dev, "Invalid data type %x\n", type);
127 return;
128 }
129
130 /* Group Enable */
131 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_BASE_ADDR_GRP_1,
132 desc->sram_pte_offset | BIT(31));
133 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1,
134 PAGE_SIZE_4K_ENABLE);
135
136 for (page_idx = 0; page_idx < num_pages; page_idx++) {
137 low = lower_32_bits(addr);
138 high = upper_32_bits(addr);
139 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + offset, low);
140 high |= BIT(31);
141 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + offset + 4, high);
142 offset += 8;
143 addr += PAGE_SIZE;
144 }
145
146 /* Flush ATU Cache after PTE Update */
147 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_CTRL, ACP_ATU_CACHE_INVALID);
148 }
149
150 /* pre fw run operations */
acp_dsp_pre_fw_run(struct snd_sof_dev * sdev)151 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev)
152 {
153 struct pci_dev *pci = to_pci_dev(sdev->dev);
154 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
155 struct acp_dev_data *adata;
156 unsigned int src_addr, size_fw;
157 u32 page_count, dma_size;
158 int ret;
159
160 adata = sdev->pdata->hw_pdata;
161
162 if (adata->signed_fw_image)
163 size_fw = adata->fw_bin_size - ACP_FIRMWARE_SIGNATURE;
164 else
165 size_fw = adata->fw_bin_size;
166
167 page_count = PAGE_ALIGN(size_fw) >> PAGE_SHIFT;
168 adata->fw_bin_page_count = page_count;
169
170 configure_pte_for_fw_loading(FW_BIN, page_count, adata);
171 ret = configure_and_run_sha_dma(adata, adata->bin_buf, ACP_SYSTEM_MEMORY_WINDOW,
172 ACP_IRAM_BASE_ADDRESS, size_fw);
173 if (ret < 0) {
174 dev_err(sdev->dev, "SHA DMA transfer failed status: %d\n", ret);
175 return ret;
176 }
177 configure_pte_for_fw_loading(FW_DATA_BIN, ACP_DRAM_PAGE_COUNT, adata);
178
179 src_addr = ACP_SYSTEM_MEMORY_WINDOW + page_count * ACP_PAGE_SIZE;
180 ret = configure_and_run_dma(adata, src_addr, ACP_DATA_RAM_BASE_ADDRESS,
181 adata->fw_data_bin_size);
182 if (ret < 0) {
183 dev_err(sdev->dev, "acp dma configuration failed: %d\n", ret);
184 return ret;
185 }
186
187 ret = acp_dma_status(adata, 0);
188 if (ret < 0)
189 dev_err(sdev->dev, "acp dma transfer status: %d\n", ret);
190
191 if (desc->rev > 3) {
192 /* Cache Window enable */
193 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_CACHE_OFFSET0, desc->sram_pte_offset);
194 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_CACHE_SIZE0, SRAM1_SIZE | BIT(31));
195 }
196
197 /* Free memory once DMA is complete */
198 dma_size = (PAGE_ALIGN(sdev->basefw.fw->size) >> PAGE_SHIFT) * ACP_PAGE_SIZE;
199 dma_free_coherent(&pci->dev, dma_size, adata->bin_buf, adata->sha_dma_addr);
200 dma_free_coherent(&pci->dev, ACP_DEFAULT_DRAM_LENGTH, adata->data_buf, adata->dma_addr);
201 adata->bin_buf = NULL;
202 adata->data_buf = NULL;
203
204 return ret;
205 }
206 EXPORT_SYMBOL_NS(acp_dsp_pre_fw_run, SND_SOC_SOF_AMD_COMMON);
207
acp_sof_dsp_run(struct snd_sof_dev * sdev)208 int acp_sof_dsp_run(struct snd_sof_dev *sdev)
209 {
210 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
211 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
212 int val;
213
214 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_RUNSTALL, ACP_DSP_RUN);
215 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DSP0_RUNSTALL);
216 dev_dbg(sdev->dev, "ACP_DSP0_RUNSTALL : 0x%0x\n", val);
217
218 /* Some platforms won't support fusion DSP,keep offset zero for no support */
219 if (desc->fusion_dsp_offset && adata->enable_fw_debug) {
220 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->fusion_dsp_offset, ACP_DSP_RUN);
221 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->fusion_dsp_offset);
222 dev_dbg(sdev->dev, "ACP_DSP0_FUSION_RUNSTALL : 0x%0x\n", val);
223 }
224 return 0;
225 }
226 EXPORT_SYMBOL_NS(acp_sof_dsp_run, SND_SOC_SOF_AMD_COMMON);
227
acp_sof_load_signed_firmware(struct snd_sof_dev * sdev)228 int acp_sof_load_signed_firmware(struct snd_sof_dev *sdev)
229 {
230 struct snd_sof_pdata *plat_data = sdev->pdata;
231 struct acp_dev_data *adata = plat_data->hw_pdata;
232 int ret;
233
234 ret = request_firmware(&sdev->basefw.fw, adata->fw_code_bin, sdev->dev);
235 if (ret < 0) {
236 dev_err(sdev->dev, "sof signed firmware code bin is missing\n");
237 return ret;
238 } else {
239 dev_dbg(sdev->dev, "request_firmware %s successful\n", adata->fw_code_bin);
240 }
241 ret = snd_sof_dsp_block_write(sdev, SOF_FW_BLK_TYPE_IRAM, 0,
242 (void *)sdev->basefw.fw->data, sdev->basefw.fw->size);
243
244 ret = request_firmware(&adata->fw_dbin, adata->fw_data_bin, sdev->dev);
245 if (ret < 0) {
246 dev_err(sdev->dev, "sof signed firmware data bin is missing\n");
247 return ret;
248
249 } else {
250 dev_dbg(sdev->dev, "request_firmware %s successful\n", adata->fw_data_bin);
251 }
252
253 ret = snd_sof_dsp_block_write(sdev, SOF_FW_BLK_TYPE_DRAM, 0,
254 (void *)adata->fw_dbin->data, adata->fw_dbin->size);
255 return ret;
256 }
257 EXPORT_SYMBOL_NS(acp_sof_load_signed_firmware, SND_SOC_SOF_AMD_COMMON);
258