1 // SPDX-License-Identifier: GPL-2.0-only 2 /* sound/soc/rockchip/rockchip_i2s.c 3 * 4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver 5 * 6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd. 7 * Author: Jianqun <jay.xu@rock-chips.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/delay.h> 13 #include <linux/of_gpio.h> 14 #include <linux/of_device.h> 15 #include <linux/clk.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <sound/pcm_params.h> 19 #include <sound/dmaengine_pcm.h> 20 21 #include "rockchip_i2s.h" 22 #include "rockchip_pcm.h" 23 24 #define DRV_NAME "rockchip-i2s" 25 26 struct rk_i2s_pins { 27 u32 reg_offset; 28 u32 shift; 29 }; 30 31 struct rk_i2s_dev { 32 struct device *dev; 33 34 struct clk *hclk; 35 struct clk *mclk; 36 37 struct snd_dmaengine_dai_dma_data capture_dma_data; 38 struct snd_dmaengine_dai_dma_data playback_dma_data; 39 40 struct regmap *regmap; 41 struct regmap *grf; 42 43 bool has_capture; 44 bool has_playback; 45 46 /* 47 * Used to indicate the tx/rx status. 48 * I2S controller hopes to start the tx and rx together, 49 * also to stop them when they are both try to stop. 50 */ 51 bool tx_start; 52 bool rx_start; 53 bool is_master_mode; 54 const struct rk_i2s_pins *pins; 55 unsigned int bclk_ratio; 56 }; 57 58 static int i2s_runtime_suspend(struct device *dev) 59 { 60 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 61 62 regcache_cache_only(i2s->regmap, true); 63 clk_disable_unprepare(i2s->mclk); 64 65 return 0; 66 } 67 68 static int i2s_runtime_resume(struct device *dev) 69 { 70 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 71 int ret; 72 73 ret = clk_prepare_enable(i2s->mclk); 74 if (ret) { 75 dev_err(i2s->dev, "clock enable failed %d\n", ret); 76 return ret; 77 } 78 79 regcache_cache_only(i2s->regmap, false); 80 regcache_mark_dirty(i2s->regmap); 81 82 ret = regcache_sync(i2s->regmap); 83 if (ret) 84 clk_disable_unprepare(i2s->mclk); 85 86 return ret; 87 } 88 89 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai) 90 { 91 return snd_soc_dai_get_drvdata(dai); 92 } 93 94 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) 95 { 96 unsigned int val = 0; 97 int retry = 10; 98 99 if (on) { 100 regmap_update_bits(i2s->regmap, I2S_DMACR, 101 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE); 102 103 regmap_update_bits(i2s->regmap, I2S_XFER, 104 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 105 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 106 107 i2s->tx_start = true; 108 } else { 109 i2s->tx_start = false; 110 111 regmap_update_bits(i2s->regmap, I2S_DMACR, 112 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE); 113 114 if (!i2s->rx_start) { 115 regmap_update_bits(i2s->regmap, I2S_XFER, 116 I2S_XFER_TXS_START | 117 I2S_XFER_RXS_START, 118 I2S_XFER_TXS_STOP | 119 I2S_XFER_RXS_STOP); 120 121 udelay(150); 122 regmap_update_bits(i2s->regmap, I2S_CLR, 123 I2S_CLR_TXC | I2S_CLR_RXC, 124 I2S_CLR_TXC | I2S_CLR_RXC); 125 126 regmap_read(i2s->regmap, I2S_CLR, &val); 127 128 /* Should wait for clear operation to finish */ 129 while (val) { 130 regmap_read(i2s->regmap, I2S_CLR, &val); 131 retry--; 132 if (!retry) { 133 dev_warn(i2s->dev, "fail to clear\n"); 134 break; 135 } 136 } 137 } 138 } 139 } 140 141 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) 142 { 143 unsigned int val = 0; 144 int retry = 10; 145 146 if (on) { 147 regmap_update_bits(i2s->regmap, I2S_DMACR, 148 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE); 149 150 regmap_update_bits(i2s->regmap, I2S_XFER, 151 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 152 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 153 154 i2s->rx_start = true; 155 } else { 156 i2s->rx_start = false; 157 158 regmap_update_bits(i2s->regmap, I2S_DMACR, 159 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE); 160 161 if (!i2s->tx_start) { 162 regmap_update_bits(i2s->regmap, I2S_XFER, 163 I2S_XFER_TXS_START | 164 I2S_XFER_RXS_START, 165 I2S_XFER_TXS_STOP | 166 I2S_XFER_RXS_STOP); 167 168 udelay(150); 169 regmap_update_bits(i2s->regmap, I2S_CLR, 170 I2S_CLR_TXC | I2S_CLR_RXC, 171 I2S_CLR_TXC | I2S_CLR_RXC); 172 173 regmap_read(i2s->regmap, I2S_CLR, &val); 174 175 /* Should wait for clear operation to finish */ 176 while (val) { 177 regmap_read(i2s->regmap, I2S_CLR, &val); 178 retry--; 179 if (!retry) { 180 dev_warn(i2s->dev, "fail to clear\n"); 181 break; 182 } 183 } 184 } 185 } 186 } 187 188 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, 189 unsigned int fmt) 190 { 191 struct rk_i2s_dev *i2s = to_info(cpu_dai); 192 unsigned int mask = 0, val = 0; 193 int ret = 0; 194 195 pm_runtime_get_sync(cpu_dai->dev); 196 mask = I2S_CKR_MSS_MASK; 197 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 198 case SND_SOC_DAIFMT_CBS_CFS: 199 /* Set source clock in Master mode */ 200 val = I2S_CKR_MSS_MASTER; 201 i2s->is_master_mode = true; 202 break; 203 case SND_SOC_DAIFMT_CBM_CFM: 204 val = I2S_CKR_MSS_SLAVE; 205 i2s->is_master_mode = false; 206 break; 207 default: 208 ret = -EINVAL; 209 goto err_pm_put; 210 } 211 212 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 213 214 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK; 215 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 216 case SND_SOC_DAIFMT_NB_NF: 217 val = I2S_CKR_CKP_NORMAL | 218 I2S_CKR_TLP_NORMAL | 219 I2S_CKR_RLP_NORMAL; 220 break; 221 case SND_SOC_DAIFMT_NB_IF: 222 val = I2S_CKR_CKP_NORMAL | 223 I2S_CKR_TLP_INVERTED | 224 I2S_CKR_RLP_INVERTED; 225 break; 226 case SND_SOC_DAIFMT_IB_NF: 227 val = I2S_CKR_CKP_INVERTED | 228 I2S_CKR_TLP_NORMAL | 229 I2S_CKR_RLP_NORMAL; 230 break; 231 case SND_SOC_DAIFMT_IB_IF: 232 val = I2S_CKR_CKP_INVERTED | 233 I2S_CKR_TLP_INVERTED | 234 I2S_CKR_RLP_INVERTED; 235 break; 236 default: 237 ret = -EINVAL; 238 goto err_pm_put; 239 } 240 241 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 242 243 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; 244 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 245 case SND_SOC_DAIFMT_RIGHT_J: 246 val = I2S_TXCR_IBM_RSJM; 247 break; 248 case SND_SOC_DAIFMT_LEFT_J: 249 val = I2S_TXCR_IBM_LSJM; 250 break; 251 case SND_SOC_DAIFMT_I2S: 252 val = I2S_TXCR_IBM_NORMAL; 253 break; 254 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */ 255 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); 256 break; 257 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */ 258 val = I2S_TXCR_TFS_PCM; 259 break; 260 default: 261 ret = -EINVAL; 262 goto err_pm_put; 263 } 264 265 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); 266 267 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; 268 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 269 case SND_SOC_DAIFMT_RIGHT_J: 270 val = I2S_RXCR_IBM_RSJM; 271 break; 272 case SND_SOC_DAIFMT_LEFT_J: 273 val = I2S_RXCR_IBM_LSJM; 274 break; 275 case SND_SOC_DAIFMT_I2S: 276 val = I2S_RXCR_IBM_NORMAL; 277 break; 278 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */ 279 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); 280 break; 281 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */ 282 val = I2S_RXCR_TFS_PCM; 283 break; 284 default: 285 ret = -EINVAL; 286 goto err_pm_put; 287 } 288 289 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val); 290 291 err_pm_put: 292 pm_runtime_put(cpu_dai->dev); 293 294 return ret; 295 } 296 297 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, 298 struct snd_pcm_hw_params *params, 299 struct snd_soc_dai *dai) 300 { 301 struct rk_i2s_dev *i2s = to_info(dai); 302 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 303 unsigned int val = 0; 304 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck; 305 306 if (i2s->is_master_mode) { 307 mclk_rate = clk_get_rate(i2s->mclk); 308 bclk_rate = i2s->bclk_ratio * params_rate(params); 309 if (!bclk_rate) 310 return -EINVAL; 311 312 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); 313 div_lrck = bclk_rate / params_rate(params); 314 regmap_update_bits(i2s->regmap, I2S_CKR, 315 I2S_CKR_MDIV_MASK, 316 I2S_CKR_MDIV(div_bclk)); 317 318 regmap_update_bits(i2s->regmap, I2S_CKR, 319 I2S_CKR_TSD_MASK | 320 I2S_CKR_RSD_MASK, 321 I2S_CKR_TSD(div_lrck) | 322 I2S_CKR_RSD(div_lrck)); 323 } 324 325 switch (params_format(params)) { 326 case SNDRV_PCM_FORMAT_S8: 327 val |= I2S_TXCR_VDW(8); 328 break; 329 case SNDRV_PCM_FORMAT_S16_LE: 330 val |= I2S_TXCR_VDW(16); 331 break; 332 case SNDRV_PCM_FORMAT_S20_3LE: 333 val |= I2S_TXCR_VDW(20); 334 break; 335 case SNDRV_PCM_FORMAT_S24_LE: 336 val |= I2S_TXCR_VDW(24); 337 break; 338 case SNDRV_PCM_FORMAT_S32_LE: 339 val |= I2S_TXCR_VDW(32); 340 break; 341 default: 342 return -EINVAL; 343 } 344 345 switch (params_channels(params)) { 346 case 8: 347 val |= I2S_CHN_8; 348 break; 349 case 6: 350 val |= I2S_CHN_6; 351 break; 352 case 4: 353 val |= I2S_CHN_4; 354 break; 355 case 2: 356 val |= I2S_CHN_2; 357 break; 358 default: 359 dev_err(i2s->dev, "invalid channel: %d\n", 360 params_channels(params)); 361 return -EINVAL; 362 } 363 364 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 365 regmap_update_bits(i2s->regmap, I2S_RXCR, 366 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 367 val); 368 else 369 regmap_update_bits(i2s->regmap, I2S_TXCR, 370 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 371 val); 372 373 if (!IS_ERR(i2s->grf) && i2s->pins) { 374 regmap_read(i2s->regmap, I2S_TXCR, &val); 375 val &= I2S_TXCR_CSR_MASK; 376 377 switch (val) { 378 case I2S_CHN_4: 379 val = I2S_IO_4CH_OUT_6CH_IN; 380 break; 381 case I2S_CHN_6: 382 val = I2S_IO_6CH_OUT_4CH_IN; 383 break; 384 case I2S_CHN_8: 385 val = I2S_IO_8CH_OUT_2CH_IN; 386 break; 387 default: 388 val = I2S_IO_2CH_OUT_8CH_IN; 389 break; 390 } 391 392 val <<= i2s->pins->shift; 393 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16; 394 regmap_write(i2s->grf, i2s->pins->reg_offset, val); 395 } 396 397 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, 398 I2S_DMACR_TDL(16)); 399 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, 400 I2S_DMACR_RDL(16)); 401 402 val = I2S_CKR_TRCM_TXRX; 403 if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate) 404 val = I2S_CKR_TRCM_TXONLY; 405 406 regmap_update_bits(i2s->regmap, I2S_CKR, 407 I2S_CKR_TRCM_MASK, 408 val); 409 return 0; 410 } 411 412 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, 413 int cmd, struct snd_soc_dai *dai) 414 { 415 struct rk_i2s_dev *i2s = to_info(dai); 416 int ret = 0; 417 418 switch (cmd) { 419 case SNDRV_PCM_TRIGGER_START: 420 case SNDRV_PCM_TRIGGER_RESUME: 421 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 422 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 423 rockchip_snd_rxctrl(i2s, 1); 424 else 425 rockchip_snd_txctrl(i2s, 1); 426 break; 427 case SNDRV_PCM_TRIGGER_SUSPEND: 428 case SNDRV_PCM_TRIGGER_STOP: 429 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 430 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 431 rockchip_snd_rxctrl(i2s, 0); 432 else 433 rockchip_snd_txctrl(i2s, 0); 434 break; 435 default: 436 ret = -EINVAL; 437 break; 438 } 439 440 return ret; 441 } 442 443 static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai, 444 unsigned int ratio) 445 { 446 struct rk_i2s_dev *i2s = to_info(dai); 447 448 i2s->bclk_ratio = ratio; 449 450 return 0; 451 } 452 453 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, 454 unsigned int freq, int dir) 455 { 456 struct rk_i2s_dev *i2s = to_info(cpu_dai); 457 int ret; 458 459 if (freq == 0) 460 return 0; 461 462 ret = clk_set_rate(i2s->mclk, freq); 463 if (ret) 464 dev_err(i2s->dev, "Fail to set mclk %d\n", ret); 465 466 return ret; 467 } 468 469 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai) 470 { 471 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); 472 473 snd_soc_dai_init_dma_data(dai, 474 i2s->has_playback ? &i2s->playback_dma_data : NULL, 475 i2s->has_capture ? &i2s->capture_dma_data : NULL); 476 477 return 0; 478 } 479 480 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = { 481 .hw_params = rockchip_i2s_hw_params, 482 .set_bclk_ratio = rockchip_i2s_set_bclk_ratio, 483 .set_sysclk = rockchip_i2s_set_sysclk, 484 .set_fmt = rockchip_i2s_set_fmt, 485 .trigger = rockchip_i2s_trigger, 486 }; 487 488 static struct snd_soc_dai_driver rockchip_i2s_dai = { 489 .probe = rockchip_i2s_dai_probe, 490 .ops = &rockchip_i2s_dai_ops, 491 .symmetric_rate = 1, 492 }; 493 494 static const struct snd_soc_component_driver rockchip_i2s_component = { 495 .name = DRV_NAME, 496 }; 497 498 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg) 499 { 500 switch (reg) { 501 case I2S_TXCR: 502 case I2S_RXCR: 503 case I2S_CKR: 504 case I2S_DMACR: 505 case I2S_INTCR: 506 case I2S_XFER: 507 case I2S_CLR: 508 case I2S_TXDR: 509 return true; 510 default: 511 return false; 512 } 513 } 514 515 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg) 516 { 517 switch (reg) { 518 case I2S_TXCR: 519 case I2S_RXCR: 520 case I2S_CKR: 521 case I2S_DMACR: 522 case I2S_INTCR: 523 case I2S_XFER: 524 case I2S_CLR: 525 case I2S_TXDR: 526 case I2S_RXDR: 527 case I2S_FIFOLR: 528 case I2S_INTSR: 529 return true; 530 default: 531 return false; 532 } 533 } 534 535 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg) 536 { 537 switch (reg) { 538 case I2S_INTSR: 539 case I2S_CLR: 540 case I2S_FIFOLR: 541 case I2S_TXDR: 542 case I2S_RXDR: 543 return true; 544 default: 545 return false; 546 } 547 } 548 549 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg) 550 { 551 switch (reg) { 552 case I2S_RXDR: 553 return true; 554 default: 555 return false; 556 } 557 } 558 559 static const struct reg_default rockchip_i2s_reg_defaults[] = { 560 {0x00, 0x0000000f}, 561 {0x04, 0x0000000f}, 562 {0x08, 0x00071f1f}, 563 {0x10, 0x001f0000}, 564 {0x14, 0x01f00000}, 565 }; 566 567 static const struct regmap_config rockchip_i2s_regmap_config = { 568 .reg_bits = 32, 569 .reg_stride = 4, 570 .val_bits = 32, 571 .max_register = I2S_RXDR, 572 .reg_defaults = rockchip_i2s_reg_defaults, 573 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults), 574 .writeable_reg = rockchip_i2s_wr_reg, 575 .readable_reg = rockchip_i2s_rd_reg, 576 .volatile_reg = rockchip_i2s_volatile_reg, 577 .precious_reg = rockchip_i2s_precious_reg, 578 .cache_type = REGCACHE_FLAT, 579 }; 580 581 static const struct rk_i2s_pins rk3399_i2s_pins = { 582 .reg_offset = 0xe220, 583 .shift = 11, 584 }; 585 586 static const struct of_device_id rockchip_i2s_match[] __maybe_unused = { 587 { .compatible = "rockchip,px30-i2s", }, 588 { .compatible = "rockchip,rk1808-i2s", }, 589 { .compatible = "rockchip,rk3036-i2s", }, 590 { .compatible = "rockchip,rk3066-i2s", }, 591 { .compatible = "rockchip,rk3128-i2s", }, 592 { .compatible = "rockchip,rk3188-i2s", }, 593 { .compatible = "rockchip,rk3228-i2s", }, 594 { .compatible = "rockchip,rk3288-i2s", }, 595 { .compatible = "rockchip,rk3308-i2s", }, 596 { .compatible = "rockchip,rk3328-i2s", }, 597 { .compatible = "rockchip,rk3366-i2s", }, 598 { .compatible = "rockchip,rk3368-i2s", }, 599 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins }, 600 { .compatible = "rockchip,rv1126-i2s", }, 601 {}, 602 }; 603 604 static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res, 605 struct snd_soc_dai_driver **dp) 606 { 607 struct device_node *node = i2s->dev->of_node; 608 struct snd_soc_dai_driver *dai; 609 struct property *dma_names; 610 const char *dma_name; 611 unsigned int val; 612 613 of_property_for_each_string(node, "dma-names", dma_names, dma_name) { 614 if (!strcmp(dma_name, "tx")) 615 i2s->has_playback = true; 616 if (!strcmp(dma_name, "rx")) 617 i2s->has_capture = true; 618 } 619 620 dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai, 621 sizeof(*dai), GFP_KERNEL); 622 if (!dai) 623 return -ENOMEM; 624 625 if (i2s->has_playback) { 626 dai->playback.stream_name = "Playback"; 627 dai->playback.channels_min = 2; 628 dai->playback.channels_max = 8; 629 dai->playback.rates = SNDRV_PCM_RATE_8000_192000; 630 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 | 631 SNDRV_PCM_FMTBIT_S16_LE | 632 SNDRV_PCM_FMTBIT_S20_3LE | 633 SNDRV_PCM_FMTBIT_S24_LE | 634 SNDRV_PCM_FMTBIT_S32_LE; 635 636 i2s->playback_dma_data.addr = res->start + I2S_TXDR; 637 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 638 i2s->playback_dma_data.maxburst = 8; 639 640 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) { 641 if (val >= 2 && val <= 8) 642 dai->playback.channels_max = val; 643 } 644 } 645 646 if (i2s->has_capture) { 647 dai->capture.stream_name = "Capture"; 648 dai->capture.channels_min = 2; 649 dai->capture.channels_max = 8; 650 dai->capture.rates = SNDRV_PCM_RATE_8000_192000; 651 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 | 652 SNDRV_PCM_FMTBIT_S16_LE | 653 SNDRV_PCM_FMTBIT_S20_3LE | 654 SNDRV_PCM_FMTBIT_S24_LE | 655 SNDRV_PCM_FMTBIT_S32_LE; 656 657 i2s->capture_dma_data.addr = res->start + I2S_RXDR; 658 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 659 i2s->capture_dma_data.maxburst = 8; 660 661 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) { 662 if (val >= 2 && val <= 8) 663 dai->capture.channels_max = val; 664 } 665 } 666 667 if (dp) 668 *dp = dai; 669 670 return 0; 671 } 672 673 static int rockchip_i2s_probe(struct platform_device *pdev) 674 { 675 struct device_node *node = pdev->dev.of_node; 676 const struct of_device_id *of_id; 677 struct rk_i2s_dev *i2s; 678 struct snd_soc_dai_driver *dai; 679 struct resource *res; 680 void __iomem *regs; 681 int ret; 682 683 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 684 if (!i2s) 685 return -ENOMEM; 686 687 i2s->dev = &pdev->dev; 688 689 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); 690 if (!IS_ERR(i2s->grf)) { 691 of_id = of_match_device(rockchip_i2s_match, &pdev->dev); 692 if (!of_id || !of_id->data) 693 return -EINVAL; 694 695 i2s->pins = of_id->data; 696 } 697 698 /* try to prepare related clocks */ 699 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk"); 700 if (IS_ERR(i2s->hclk)) { 701 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n"); 702 return PTR_ERR(i2s->hclk); 703 } 704 ret = clk_prepare_enable(i2s->hclk); 705 if (ret) { 706 dev_err(i2s->dev, "hclock enable failed %d\n", ret); 707 return ret; 708 } 709 710 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk"); 711 if (IS_ERR(i2s->mclk)) { 712 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n"); 713 return PTR_ERR(i2s->mclk); 714 } 715 716 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 717 if (IS_ERR(regs)) 718 return PTR_ERR(regs); 719 720 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 721 &rockchip_i2s_regmap_config); 722 if (IS_ERR(i2s->regmap)) { 723 dev_err(&pdev->dev, 724 "Failed to initialise managed register map\n"); 725 return PTR_ERR(i2s->regmap); 726 } 727 728 i2s->bclk_ratio = 64; 729 730 dev_set_drvdata(&pdev->dev, i2s); 731 732 pm_runtime_enable(&pdev->dev); 733 if (!pm_runtime_enabled(&pdev->dev)) { 734 ret = i2s_runtime_resume(&pdev->dev); 735 if (ret) 736 goto err_pm_disable; 737 } 738 739 ret = rockchip_i2s_init_dai(i2s, res, &dai); 740 if (ret) 741 goto err_pm_disable; 742 743 ret = devm_snd_soc_register_component(&pdev->dev, 744 &rockchip_i2s_component, 745 dai, 1); 746 747 if (ret) { 748 dev_err(&pdev->dev, "Could not register DAI\n"); 749 goto err_suspend; 750 } 751 752 ret = rockchip_pcm_platform_register(&pdev->dev); 753 if (ret) { 754 dev_err(&pdev->dev, "Could not register PCM\n"); 755 goto err_suspend; 756 } 757 758 return 0; 759 760 err_suspend: 761 if (!pm_runtime_status_suspended(&pdev->dev)) 762 i2s_runtime_suspend(&pdev->dev); 763 err_pm_disable: 764 pm_runtime_disable(&pdev->dev); 765 766 return ret; 767 } 768 769 static int rockchip_i2s_remove(struct platform_device *pdev) 770 { 771 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev); 772 773 pm_runtime_disable(&pdev->dev); 774 if (!pm_runtime_status_suspended(&pdev->dev)) 775 i2s_runtime_suspend(&pdev->dev); 776 777 clk_disable_unprepare(i2s->hclk); 778 779 return 0; 780 } 781 782 static const struct dev_pm_ops rockchip_i2s_pm_ops = { 783 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume, 784 NULL) 785 }; 786 787 static struct platform_driver rockchip_i2s_driver = { 788 .probe = rockchip_i2s_probe, 789 .remove = rockchip_i2s_remove, 790 .driver = { 791 .name = DRV_NAME, 792 .of_match_table = of_match_ptr(rockchip_i2s_match), 793 .pm = &rockchip_i2s_pm_ops, 794 }, 795 }; 796 module_platform_driver(rockchip_i2s_driver); 797 798 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface"); 799 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>"); 800 MODULE_LICENSE("GPL v2"); 801 MODULE_ALIAS("platform:" DRV_NAME); 802 MODULE_DEVICE_TABLE(of, rockchip_i2s_match); 803