1 // SPDX-License-Identifier: GPL-2.0-only
2 /* sound/soc/rockchip/rockchip_i2s.c
3 *
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 *
6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7 * Author: Jianqun <jay.xu@rock-chips.com>
8 */
9
10 #include <linux/module.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/delay.h>
13 #include <linux/of_gpio.h>
14 #include <linux/of_device.h>
15 #include <linux/clk.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <linux/spinlock.h>
20 #include <sound/pcm_params.h>
21 #include <sound/dmaengine_pcm.h>
22
23 #include "rockchip_i2s.h"
24
25 #define DRV_NAME "rockchip-i2s"
26
27 struct rk_i2s_pins {
28 u32 reg_offset;
29 u32 shift;
30 };
31
32 struct rk_i2s_dev {
33 struct device *dev;
34
35 struct clk *hclk;
36 struct clk *mclk;
37
38 struct snd_dmaengine_dai_dma_data capture_dma_data;
39 struct snd_dmaengine_dai_dma_data playback_dma_data;
40
41 struct regmap *regmap;
42 struct regmap *grf;
43
44 bool has_capture;
45 bool has_playback;
46
47 /*
48 * Used to indicate the tx/rx status.
49 * I2S controller hopes to start the tx and rx together,
50 * also to stop them when they are both try to stop.
51 */
52 bool tx_start;
53 bool rx_start;
54 bool is_master_mode;
55 const struct rk_i2s_pins *pins;
56 unsigned int bclk_ratio;
57 spinlock_t lock; /* tx/rx lock */
58 struct pinctrl *pinctrl;
59 struct pinctrl_state *bclk_on;
60 struct pinctrl_state *bclk_off;
61 };
62
i2s_pinctrl_select_bclk_on(struct rk_i2s_dev * i2s)63 static int i2s_pinctrl_select_bclk_on(struct rk_i2s_dev *i2s)
64 {
65 int ret = 0;
66
67 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_on))
68 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_on);
69
70 if (ret)
71 dev_err(i2s->dev, "bclk enable failed %d\n", ret);
72
73 return ret;
74 }
75
i2s_pinctrl_select_bclk_off(struct rk_i2s_dev * i2s)76 static int i2s_pinctrl_select_bclk_off(struct rk_i2s_dev *i2s)
77 {
78
79 int ret = 0;
80
81 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_off))
82 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_off);
83
84 if (ret)
85 dev_err(i2s->dev, "bclk disable failed %d\n", ret);
86
87 return ret;
88 }
89
i2s_runtime_suspend(struct device * dev)90 static int i2s_runtime_suspend(struct device *dev)
91 {
92 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
93
94 regcache_cache_only(i2s->regmap, true);
95 clk_disable_unprepare(i2s->mclk);
96
97 return 0;
98 }
99
i2s_runtime_resume(struct device * dev)100 static int i2s_runtime_resume(struct device *dev)
101 {
102 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
103 int ret;
104
105 ret = clk_prepare_enable(i2s->mclk);
106 if (ret) {
107 dev_err(i2s->dev, "clock enable failed %d\n", ret);
108 return ret;
109 }
110
111 regcache_cache_only(i2s->regmap, false);
112 regcache_mark_dirty(i2s->regmap);
113
114 ret = regcache_sync(i2s->regmap);
115 if (ret)
116 clk_disable_unprepare(i2s->mclk);
117
118 return ret;
119 }
120
to_info(struct snd_soc_dai * dai)121 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
122 {
123 return snd_soc_dai_get_drvdata(dai);
124 }
125
rockchip_snd_txctrl(struct rk_i2s_dev * i2s,int on)126 static int rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
127 {
128 unsigned int val = 0;
129 int ret = 0;
130
131 spin_lock(&i2s->lock);
132 if (on) {
133 ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
134 I2S_DMACR_TDE_ENABLE,
135 I2S_DMACR_TDE_ENABLE);
136 if (ret < 0)
137 goto end;
138 ret = regmap_update_bits(i2s->regmap, I2S_XFER,
139 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
140 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
141 if (ret < 0)
142 goto end;
143 i2s->tx_start = true;
144 } else {
145 i2s->tx_start = false;
146
147 ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
148 I2S_DMACR_TDE_ENABLE,
149 I2S_DMACR_TDE_DISABLE);
150 if (ret < 0)
151 goto end;
152
153 if (!i2s->rx_start) {
154 ret = regmap_update_bits(i2s->regmap, I2S_XFER,
155 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
156 I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
157 if (ret < 0)
158 goto end;
159 udelay(150);
160 ret = regmap_update_bits(i2s->regmap, I2S_CLR,
161 I2S_CLR_TXC | I2S_CLR_RXC,
162 I2S_CLR_TXC | I2S_CLR_RXC);
163 if (ret < 0)
164 goto end;
165 ret = regmap_read_poll_timeout_atomic(i2s->regmap,
166 I2S_CLR,
167 val,
168 val == 0,
169 20,
170 200);
171 if (ret < 0)
172 dev_warn(i2s->dev, "fail to clear: %d\n", ret);
173 }
174 }
175 end:
176 spin_unlock(&i2s->lock);
177 if (ret < 0)
178 dev_err(i2s->dev, "lrclk update failed\n");
179
180 return ret;
181 }
182
rockchip_snd_rxctrl(struct rk_i2s_dev * i2s,int on)183 static int rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
184 {
185 unsigned int val = 0;
186 int ret = 0;
187
188 spin_lock(&i2s->lock);
189 if (on) {
190 ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
191 I2S_DMACR_RDE_ENABLE,
192 I2S_DMACR_RDE_ENABLE);
193 if (ret < 0)
194 goto end;
195
196 ret = regmap_update_bits(i2s->regmap, I2S_XFER,
197 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
198 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
199 if (ret < 0)
200 goto end;
201 i2s->rx_start = true;
202 } else {
203 i2s->rx_start = false;
204
205 ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
206 I2S_DMACR_RDE_ENABLE,
207 I2S_DMACR_RDE_DISABLE);
208 if (ret < 0)
209 goto end;
210
211 if (!i2s->tx_start) {
212 ret = regmap_update_bits(i2s->regmap, I2S_XFER,
213 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
214 I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
215 if (ret < 0)
216 goto end;
217 udelay(150);
218 ret = regmap_update_bits(i2s->regmap, I2S_CLR,
219 I2S_CLR_TXC | I2S_CLR_RXC,
220 I2S_CLR_TXC | I2S_CLR_RXC);
221 if (ret < 0)
222 goto end;
223 ret = regmap_read_poll_timeout_atomic(i2s->regmap,
224 I2S_CLR,
225 val,
226 val == 0,
227 20,
228 200);
229 if (ret < 0)
230 dev_warn(i2s->dev, "fail to clear: %d\n", ret);
231 }
232 }
233 end:
234 spin_unlock(&i2s->lock);
235 if (ret < 0)
236 dev_err(i2s->dev, "lrclk update failed\n");
237
238 return ret;
239 }
240
rockchip_i2s_set_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)241 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
242 unsigned int fmt)
243 {
244 struct rk_i2s_dev *i2s = to_info(cpu_dai);
245 unsigned int mask = 0, val = 0;
246 int ret = 0;
247
248 pm_runtime_get_sync(cpu_dai->dev);
249 mask = I2S_CKR_MSS_MASK;
250 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
251 case SND_SOC_DAIFMT_BP_FP:
252 /* Set source clock in Master mode */
253 val = I2S_CKR_MSS_MASTER;
254 i2s->is_master_mode = true;
255 break;
256 case SND_SOC_DAIFMT_BC_FC:
257 val = I2S_CKR_MSS_SLAVE;
258 i2s->is_master_mode = false;
259 break;
260 default:
261 ret = -EINVAL;
262 goto err_pm_put;
263 }
264
265 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
266
267 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
268 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
269 case SND_SOC_DAIFMT_NB_NF:
270 val = I2S_CKR_CKP_NORMAL |
271 I2S_CKR_TLP_NORMAL |
272 I2S_CKR_RLP_NORMAL;
273 break;
274 case SND_SOC_DAIFMT_NB_IF:
275 val = I2S_CKR_CKP_NORMAL |
276 I2S_CKR_TLP_INVERTED |
277 I2S_CKR_RLP_INVERTED;
278 break;
279 case SND_SOC_DAIFMT_IB_NF:
280 val = I2S_CKR_CKP_INVERTED |
281 I2S_CKR_TLP_NORMAL |
282 I2S_CKR_RLP_NORMAL;
283 break;
284 case SND_SOC_DAIFMT_IB_IF:
285 val = I2S_CKR_CKP_INVERTED |
286 I2S_CKR_TLP_INVERTED |
287 I2S_CKR_RLP_INVERTED;
288 break;
289 default:
290 ret = -EINVAL;
291 goto err_pm_put;
292 }
293
294 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
295
296 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
297 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
298 case SND_SOC_DAIFMT_RIGHT_J:
299 val = I2S_TXCR_IBM_RSJM;
300 break;
301 case SND_SOC_DAIFMT_LEFT_J:
302 val = I2S_TXCR_IBM_LSJM;
303 break;
304 case SND_SOC_DAIFMT_I2S:
305 val = I2S_TXCR_IBM_NORMAL;
306 break;
307 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
308 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
309 break;
310 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
311 val = I2S_TXCR_TFS_PCM;
312 break;
313 default:
314 ret = -EINVAL;
315 goto err_pm_put;
316 }
317
318 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
319
320 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
321 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
322 case SND_SOC_DAIFMT_RIGHT_J:
323 val = I2S_RXCR_IBM_RSJM;
324 break;
325 case SND_SOC_DAIFMT_LEFT_J:
326 val = I2S_RXCR_IBM_LSJM;
327 break;
328 case SND_SOC_DAIFMT_I2S:
329 val = I2S_RXCR_IBM_NORMAL;
330 break;
331 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
332 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
333 break;
334 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
335 val = I2S_RXCR_TFS_PCM;
336 break;
337 default:
338 ret = -EINVAL;
339 goto err_pm_put;
340 }
341
342 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
343
344 err_pm_put:
345 pm_runtime_put(cpu_dai->dev);
346
347 return ret;
348 }
349
rockchip_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)350 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
351 struct snd_pcm_hw_params *params,
352 struct snd_soc_dai *dai)
353 {
354 struct rk_i2s_dev *i2s = to_info(dai);
355 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
356 unsigned int val = 0;
357 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
358
359 if (i2s->is_master_mode) {
360 mclk_rate = clk_get_rate(i2s->mclk);
361 bclk_rate = i2s->bclk_ratio * params_rate(params);
362 if (!bclk_rate)
363 return -EINVAL;
364
365 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
366 div_lrck = bclk_rate / params_rate(params);
367 regmap_update_bits(i2s->regmap, I2S_CKR,
368 I2S_CKR_MDIV_MASK,
369 I2S_CKR_MDIV(div_bclk));
370
371 regmap_update_bits(i2s->regmap, I2S_CKR,
372 I2S_CKR_TSD_MASK |
373 I2S_CKR_RSD_MASK,
374 I2S_CKR_TSD(div_lrck) |
375 I2S_CKR_RSD(div_lrck));
376 }
377
378 switch (params_format(params)) {
379 case SNDRV_PCM_FORMAT_S8:
380 val |= I2S_TXCR_VDW(8);
381 break;
382 case SNDRV_PCM_FORMAT_S16_LE:
383 val |= I2S_TXCR_VDW(16);
384 break;
385 case SNDRV_PCM_FORMAT_S20_3LE:
386 val |= I2S_TXCR_VDW(20);
387 break;
388 case SNDRV_PCM_FORMAT_S24_LE:
389 val |= I2S_TXCR_VDW(24);
390 break;
391 case SNDRV_PCM_FORMAT_S32_LE:
392 val |= I2S_TXCR_VDW(32);
393 break;
394 default:
395 return -EINVAL;
396 }
397
398 switch (params_channels(params)) {
399 case 8:
400 val |= I2S_CHN_8;
401 break;
402 case 6:
403 val |= I2S_CHN_6;
404 break;
405 case 4:
406 val |= I2S_CHN_4;
407 break;
408 case 2:
409 val |= I2S_CHN_2;
410 break;
411 default:
412 dev_err(i2s->dev, "invalid channel: %d\n",
413 params_channels(params));
414 return -EINVAL;
415 }
416
417 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
418 regmap_update_bits(i2s->regmap, I2S_RXCR,
419 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
420 val);
421 else
422 regmap_update_bits(i2s->regmap, I2S_TXCR,
423 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
424 val);
425
426 if (!IS_ERR(i2s->grf) && i2s->pins) {
427 regmap_read(i2s->regmap, I2S_TXCR, &val);
428 val &= I2S_TXCR_CSR_MASK;
429
430 switch (val) {
431 case I2S_CHN_4:
432 val = I2S_IO_4CH_OUT_6CH_IN;
433 break;
434 case I2S_CHN_6:
435 val = I2S_IO_6CH_OUT_4CH_IN;
436 break;
437 case I2S_CHN_8:
438 val = I2S_IO_8CH_OUT_2CH_IN;
439 break;
440 default:
441 val = I2S_IO_2CH_OUT_8CH_IN;
442 break;
443 }
444
445 val <<= i2s->pins->shift;
446 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
447 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
448 }
449
450 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
451 I2S_DMACR_TDL(16));
452 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
453 I2S_DMACR_RDL(16));
454
455 val = I2S_CKR_TRCM_TXRX;
456 if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate)
457 val = I2S_CKR_TRCM_TXONLY;
458
459 regmap_update_bits(i2s->regmap, I2S_CKR,
460 I2S_CKR_TRCM_MASK,
461 val);
462 return 0;
463 }
464
rockchip_i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)465 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
466 int cmd, struct snd_soc_dai *dai)
467 {
468 struct rk_i2s_dev *i2s = to_info(dai);
469 int ret = 0;
470
471 switch (cmd) {
472 case SNDRV_PCM_TRIGGER_START:
473 case SNDRV_PCM_TRIGGER_RESUME:
474 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
475 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
476 ret = rockchip_snd_rxctrl(i2s, 1);
477 else
478 ret = rockchip_snd_txctrl(i2s, 1);
479 if (ret < 0)
480 return ret;
481 i2s_pinctrl_select_bclk_on(i2s);
482 break;
483 case SNDRV_PCM_TRIGGER_SUSPEND:
484 case SNDRV_PCM_TRIGGER_STOP:
485 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
486 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
487 if (!i2s->tx_start)
488 i2s_pinctrl_select_bclk_off(i2s);
489 ret = rockchip_snd_rxctrl(i2s, 0);
490 } else {
491 if (!i2s->rx_start)
492 i2s_pinctrl_select_bclk_off(i2s);
493 ret = rockchip_snd_txctrl(i2s, 0);
494 }
495 break;
496 default:
497 ret = -EINVAL;
498 break;
499 }
500
501 return ret;
502 }
503
rockchip_i2s_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)504 static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
505 unsigned int ratio)
506 {
507 struct rk_i2s_dev *i2s = to_info(dai);
508
509 i2s->bclk_ratio = ratio;
510
511 return 0;
512 }
513
rockchip_i2s_set_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)514 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
515 unsigned int freq, int dir)
516 {
517 struct rk_i2s_dev *i2s = to_info(cpu_dai);
518 int ret;
519
520 if (freq == 0)
521 return 0;
522
523 ret = clk_set_rate(i2s->mclk, freq);
524 if (ret)
525 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
526
527 return ret;
528 }
529
rockchip_i2s_dai_probe(struct snd_soc_dai * dai)530 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
531 {
532 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
533
534 snd_soc_dai_init_dma_data(dai,
535 i2s->has_playback ? &i2s->playback_dma_data : NULL,
536 i2s->has_capture ? &i2s->capture_dma_data : NULL);
537
538 return 0;
539 }
540
541 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
542 .probe = rockchip_i2s_dai_probe,
543 .hw_params = rockchip_i2s_hw_params,
544 .set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
545 .set_sysclk = rockchip_i2s_set_sysclk,
546 .set_fmt = rockchip_i2s_set_fmt,
547 .trigger = rockchip_i2s_trigger,
548 };
549
550 static struct snd_soc_dai_driver rockchip_i2s_dai = {
551 .ops = &rockchip_i2s_dai_ops,
552 .symmetric_rate = 1,
553 };
554
555 static const struct snd_soc_component_driver rockchip_i2s_component = {
556 .name = DRV_NAME,
557 .legacy_dai_naming = 1,
558 };
559
rockchip_i2s_wr_reg(struct device * dev,unsigned int reg)560 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
561 {
562 switch (reg) {
563 case I2S_TXCR:
564 case I2S_RXCR:
565 case I2S_CKR:
566 case I2S_DMACR:
567 case I2S_INTCR:
568 case I2S_XFER:
569 case I2S_CLR:
570 case I2S_TXDR:
571 return true;
572 default:
573 return false;
574 }
575 }
576
rockchip_i2s_rd_reg(struct device * dev,unsigned int reg)577 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
578 {
579 switch (reg) {
580 case I2S_TXCR:
581 case I2S_RXCR:
582 case I2S_CKR:
583 case I2S_DMACR:
584 case I2S_INTCR:
585 case I2S_XFER:
586 case I2S_CLR:
587 case I2S_TXDR:
588 case I2S_RXDR:
589 case I2S_FIFOLR:
590 case I2S_INTSR:
591 return true;
592 default:
593 return false;
594 }
595 }
596
rockchip_i2s_volatile_reg(struct device * dev,unsigned int reg)597 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
598 {
599 switch (reg) {
600 case I2S_INTSR:
601 case I2S_CLR:
602 case I2S_FIFOLR:
603 case I2S_TXDR:
604 case I2S_RXDR:
605 return true;
606 default:
607 return false;
608 }
609 }
610
rockchip_i2s_precious_reg(struct device * dev,unsigned int reg)611 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
612 {
613 switch (reg) {
614 case I2S_RXDR:
615 return true;
616 default:
617 return false;
618 }
619 }
620
621 static const struct reg_default rockchip_i2s_reg_defaults[] = {
622 {0x00, 0x0000000f},
623 {0x04, 0x0000000f},
624 {0x08, 0x00071f1f},
625 {0x10, 0x001f0000},
626 {0x14, 0x01f00000},
627 };
628
629 static const struct regmap_config rockchip_i2s_regmap_config = {
630 .reg_bits = 32,
631 .reg_stride = 4,
632 .val_bits = 32,
633 .max_register = I2S_RXDR,
634 .reg_defaults = rockchip_i2s_reg_defaults,
635 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
636 .writeable_reg = rockchip_i2s_wr_reg,
637 .readable_reg = rockchip_i2s_rd_reg,
638 .volatile_reg = rockchip_i2s_volatile_reg,
639 .precious_reg = rockchip_i2s_precious_reg,
640 .cache_type = REGCACHE_FLAT,
641 };
642
643 static const struct rk_i2s_pins rk3399_i2s_pins = {
644 .reg_offset = 0xe220,
645 .shift = 11,
646 };
647
648 static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
649 { .compatible = "rockchip,px30-i2s", },
650 { .compatible = "rockchip,rk1808-i2s", },
651 { .compatible = "rockchip,rk3036-i2s", },
652 { .compatible = "rockchip,rk3066-i2s", },
653 { .compatible = "rockchip,rk3128-i2s", },
654 { .compatible = "rockchip,rk3188-i2s", },
655 { .compatible = "rockchip,rk3228-i2s", },
656 { .compatible = "rockchip,rk3288-i2s", },
657 { .compatible = "rockchip,rk3308-i2s", },
658 { .compatible = "rockchip,rk3328-i2s", },
659 { .compatible = "rockchip,rk3366-i2s", },
660 { .compatible = "rockchip,rk3368-i2s", },
661 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
662 { .compatible = "rockchip,rk3588-i2s", },
663 { .compatible = "rockchip,rv1126-i2s", },
664 {},
665 };
666
rockchip_i2s_init_dai(struct rk_i2s_dev * i2s,struct resource * res,struct snd_soc_dai_driver ** dp)667 static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
668 struct snd_soc_dai_driver **dp)
669 {
670 struct device_node *node = i2s->dev->of_node;
671 struct snd_soc_dai_driver *dai;
672 struct property *dma_names;
673 const char *dma_name;
674 unsigned int val;
675
676 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
677 if (!strcmp(dma_name, "tx"))
678 i2s->has_playback = true;
679 if (!strcmp(dma_name, "rx"))
680 i2s->has_capture = true;
681 }
682
683 dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
684 sizeof(*dai), GFP_KERNEL);
685 if (!dai)
686 return -ENOMEM;
687
688 if (i2s->has_playback) {
689 dai->playback.stream_name = "Playback";
690 dai->playback.channels_min = 2;
691 dai->playback.channels_max = 8;
692 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
693 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
694 SNDRV_PCM_FMTBIT_S16_LE |
695 SNDRV_PCM_FMTBIT_S20_3LE |
696 SNDRV_PCM_FMTBIT_S24_LE |
697 SNDRV_PCM_FMTBIT_S32_LE;
698
699 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
700 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
701 i2s->playback_dma_data.maxburst = 8;
702
703 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
704 if (val >= 2 && val <= 8)
705 dai->playback.channels_max = val;
706 }
707 }
708
709 if (i2s->has_capture) {
710 dai->capture.stream_name = "Capture";
711 dai->capture.channels_min = 2;
712 dai->capture.channels_max = 8;
713 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
714 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
715 SNDRV_PCM_FMTBIT_S16_LE |
716 SNDRV_PCM_FMTBIT_S20_3LE |
717 SNDRV_PCM_FMTBIT_S24_LE |
718 SNDRV_PCM_FMTBIT_S32_LE;
719
720 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
721 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
722 i2s->capture_dma_data.maxburst = 8;
723
724 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
725 if (val >= 2 && val <= 8)
726 dai->capture.channels_max = val;
727 }
728 }
729
730 if (dp)
731 *dp = dai;
732
733 return 0;
734 }
735
rockchip_i2s_probe(struct platform_device * pdev)736 static int rockchip_i2s_probe(struct platform_device *pdev)
737 {
738 struct device_node *node = pdev->dev.of_node;
739 const struct of_device_id *of_id;
740 struct rk_i2s_dev *i2s;
741 struct snd_soc_dai_driver *dai;
742 struct resource *res;
743 void __iomem *regs;
744 int ret;
745
746 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
747 if (!i2s)
748 return -ENOMEM;
749
750 spin_lock_init(&i2s->lock);
751 i2s->dev = &pdev->dev;
752
753 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
754 if (!IS_ERR(i2s->grf)) {
755 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
756 if (!of_id || !of_id->data)
757 return -EINVAL;
758
759 i2s->pins = of_id->data;
760 }
761
762 /* try to prepare related clocks */
763 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
764 if (IS_ERR(i2s->hclk)) {
765 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
766 return PTR_ERR(i2s->hclk);
767 }
768 ret = clk_prepare_enable(i2s->hclk);
769 if (ret) {
770 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
771 return ret;
772 }
773
774 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
775 if (IS_ERR(i2s->mclk)) {
776 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
777 ret = PTR_ERR(i2s->mclk);
778 goto err_clk;
779 }
780
781 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
782 if (IS_ERR(regs)) {
783 ret = PTR_ERR(regs);
784 goto err_clk;
785 }
786
787 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
788 &rockchip_i2s_regmap_config);
789 if (IS_ERR(i2s->regmap)) {
790 dev_err(&pdev->dev,
791 "Failed to initialise managed register map\n");
792 ret = PTR_ERR(i2s->regmap);
793 goto err_clk;
794 }
795
796 i2s->bclk_ratio = 64;
797 i2s->pinctrl = devm_pinctrl_get(&pdev->dev);
798 if (!IS_ERR(i2s->pinctrl)) {
799 i2s->bclk_on = pinctrl_lookup_state(i2s->pinctrl, "bclk_on");
800 if (!IS_ERR_OR_NULL(i2s->bclk_on)) {
801 i2s->bclk_off = pinctrl_lookup_state(i2s->pinctrl, "bclk_off");
802 if (IS_ERR_OR_NULL(i2s->bclk_off)) {
803 dev_err(&pdev->dev, "failed to find i2s bclk_off\n");
804 ret = -EINVAL;
805 goto err_clk;
806 }
807 }
808 } else {
809 dev_dbg(&pdev->dev, "failed to find i2s pinctrl\n");
810 }
811
812 i2s_pinctrl_select_bclk_off(i2s);
813
814 dev_set_drvdata(&pdev->dev, i2s);
815
816 pm_runtime_enable(&pdev->dev);
817 if (!pm_runtime_enabled(&pdev->dev)) {
818 ret = i2s_runtime_resume(&pdev->dev);
819 if (ret)
820 goto err_pm_disable;
821 }
822
823 ret = rockchip_i2s_init_dai(i2s, res, &dai);
824 if (ret)
825 goto err_pm_disable;
826
827 ret = devm_snd_soc_register_component(&pdev->dev,
828 &rockchip_i2s_component,
829 dai, 1);
830
831 if (ret) {
832 dev_err(&pdev->dev, "Could not register DAI\n");
833 goto err_suspend;
834 }
835
836 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
837 if (ret) {
838 dev_err(&pdev->dev, "Could not register PCM\n");
839 goto err_suspend;
840 }
841
842 return 0;
843
844 err_suspend:
845 if (!pm_runtime_status_suspended(&pdev->dev))
846 i2s_runtime_suspend(&pdev->dev);
847 err_pm_disable:
848 pm_runtime_disable(&pdev->dev);
849 err_clk:
850 clk_disable_unprepare(i2s->hclk);
851 return ret;
852 }
853
rockchip_i2s_remove(struct platform_device * pdev)854 static void rockchip_i2s_remove(struct platform_device *pdev)
855 {
856 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
857
858 pm_runtime_disable(&pdev->dev);
859 if (!pm_runtime_status_suspended(&pdev->dev))
860 i2s_runtime_suspend(&pdev->dev);
861
862 clk_disable_unprepare(i2s->hclk);
863 }
864
865 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
866 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
867 NULL)
868 };
869
870 static struct platform_driver rockchip_i2s_driver = {
871 .probe = rockchip_i2s_probe,
872 .remove_new = rockchip_i2s_remove,
873 .driver = {
874 .name = DRV_NAME,
875 .of_match_table = of_match_ptr(rockchip_i2s_match),
876 .pm = &rockchip_i2s_pm_ops,
877 },
878 };
879 module_platform_driver(rockchip_i2s_driver);
880
881 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
882 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
883 MODULE_LICENSE("GPL v2");
884 MODULE_ALIAS("platform:" DRV_NAME);
885 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
886