1 /* sound/soc/rockchip/rockchip_i2s.c 2 * 3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver 4 * 5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd. 6 * Author: Jianqun <jay.xu@rock-chips.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/delay.h> 15 #include <linux/of_gpio.h> 16 #include <linux/clk.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <sound/pcm_params.h> 20 #include <sound/dmaengine_pcm.h> 21 22 #include "rockchip_i2s.h" 23 24 #define DRV_NAME "rockchip-i2s" 25 26 struct rk_i2s_dev { 27 struct device *dev; 28 29 struct clk *hclk; 30 struct clk *mclk; 31 32 struct snd_dmaengine_dai_dma_data capture_dma_data; 33 struct snd_dmaengine_dai_dma_data playback_dma_data; 34 35 struct regmap *regmap; 36 37 /* 38 * Used to indicate the tx/rx status. 39 * I2S controller hopes to start the tx and rx together, 40 * also to stop them when they are both try to stop. 41 */ 42 bool tx_start; 43 bool rx_start; 44 }; 45 46 static int i2s_runtime_suspend(struct device *dev) 47 { 48 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 49 50 clk_disable_unprepare(i2s->mclk); 51 52 return 0; 53 } 54 55 static int i2s_runtime_resume(struct device *dev) 56 { 57 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 58 int ret; 59 60 ret = clk_prepare_enable(i2s->mclk); 61 if (ret) { 62 dev_err(i2s->dev, "clock enable failed %d\n", ret); 63 return ret; 64 } 65 66 return 0; 67 } 68 69 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai) 70 { 71 return snd_soc_dai_get_drvdata(dai); 72 } 73 74 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) 75 { 76 unsigned int val = 0; 77 int retry = 10; 78 79 if (on) { 80 regmap_update_bits(i2s->regmap, I2S_DMACR, 81 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE); 82 83 regmap_update_bits(i2s->regmap, I2S_XFER, 84 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 85 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 86 87 i2s->tx_start = true; 88 } else { 89 i2s->tx_start = false; 90 91 regmap_update_bits(i2s->regmap, I2S_DMACR, 92 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE); 93 94 if (!i2s->rx_start) { 95 regmap_update_bits(i2s->regmap, I2S_XFER, 96 I2S_XFER_TXS_START | 97 I2S_XFER_RXS_START, 98 I2S_XFER_TXS_STOP | 99 I2S_XFER_RXS_STOP); 100 101 regmap_update_bits(i2s->regmap, I2S_CLR, 102 I2S_CLR_TXC | I2S_CLR_RXC, 103 I2S_CLR_TXC | I2S_CLR_RXC); 104 105 regmap_read(i2s->regmap, I2S_CLR, &val); 106 107 /* Should wait for clear operation to finish */ 108 while (val) { 109 regmap_read(i2s->regmap, I2S_CLR, &val); 110 retry--; 111 if (!retry) { 112 dev_warn(i2s->dev, "fail to clear\n"); 113 break; 114 } 115 } 116 } 117 } 118 } 119 120 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) 121 { 122 unsigned int val = 0; 123 int retry = 10; 124 125 if (on) { 126 regmap_update_bits(i2s->regmap, I2S_DMACR, 127 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE); 128 129 regmap_update_bits(i2s->regmap, I2S_XFER, 130 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 131 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 132 133 i2s->rx_start = true; 134 } else { 135 i2s->rx_start = false; 136 137 regmap_update_bits(i2s->regmap, I2S_DMACR, 138 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE); 139 140 if (!i2s->tx_start) { 141 regmap_update_bits(i2s->regmap, I2S_XFER, 142 I2S_XFER_TXS_START | 143 I2S_XFER_RXS_START, 144 I2S_XFER_TXS_STOP | 145 I2S_XFER_RXS_STOP); 146 147 regmap_update_bits(i2s->regmap, I2S_CLR, 148 I2S_CLR_TXC | I2S_CLR_RXC, 149 I2S_CLR_TXC | I2S_CLR_RXC); 150 151 regmap_read(i2s->regmap, I2S_CLR, &val); 152 153 /* Should wait for clear operation to finish */ 154 while (val) { 155 regmap_read(i2s->regmap, I2S_CLR, &val); 156 retry--; 157 if (!retry) { 158 dev_warn(i2s->dev, "fail to clear\n"); 159 break; 160 } 161 } 162 } 163 } 164 } 165 166 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, 167 unsigned int fmt) 168 { 169 struct rk_i2s_dev *i2s = to_info(cpu_dai); 170 unsigned int mask = 0, val = 0; 171 172 mask = I2S_CKR_MSS_MASK; 173 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 174 case SND_SOC_DAIFMT_CBS_CFS: 175 /* Set source clock in Master mode */ 176 val = I2S_CKR_MSS_MASTER; 177 break; 178 case SND_SOC_DAIFMT_CBM_CFM: 179 val = I2S_CKR_MSS_SLAVE; 180 break; 181 default: 182 return -EINVAL; 183 } 184 185 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 186 187 mask = I2S_TXCR_IBM_MASK; 188 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 189 case SND_SOC_DAIFMT_RIGHT_J: 190 val = I2S_TXCR_IBM_RSJM; 191 break; 192 case SND_SOC_DAIFMT_LEFT_J: 193 val = I2S_TXCR_IBM_LSJM; 194 break; 195 case SND_SOC_DAIFMT_I2S: 196 val = I2S_TXCR_IBM_NORMAL; 197 break; 198 default: 199 return -EINVAL; 200 } 201 202 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); 203 204 mask = I2S_RXCR_IBM_MASK; 205 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 206 case SND_SOC_DAIFMT_RIGHT_J: 207 val = I2S_RXCR_IBM_RSJM; 208 break; 209 case SND_SOC_DAIFMT_LEFT_J: 210 val = I2S_RXCR_IBM_LSJM; 211 break; 212 case SND_SOC_DAIFMT_I2S: 213 val = I2S_RXCR_IBM_NORMAL; 214 break; 215 default: 216 return -EINVAL; 217 } 218 219 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val); 220 221 return 0; 222 } 223 224 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, 225 struct snd_pcm_hw_params *params, 226 struct snd_soc_dai *dai) 227 { 228 struct rk_i2s_dev *i2s = to_info(dai); 229 struct snd_soc_pcm_runtime *rtd = substream->private_data; 230 unsigned int val = 0; 231 232 switch (params_format(params)) { 233 case SNDRV_PCM_FORMAT_S8: 234 val |= I2S_TXCR_VDW(8); 235 break; 236 case SNDRV_PCM_FORMAT_S16_LE: 237 val |= I2S_TXCR_VDW(16); 238 break; 239 case SNDRV_PCM_FORMAT_S20_3LE: 240 val |= I2S_TXCR_VDW(20); 241 break; 242 case SNDRV_PCM_FORMAT_S24_LE: 243 val |= I2S_TXCR_VDW(24); 244 break; 245 default: 246 return -EINVAL; 247 } 248 249 switch (params_channels(params)) { 250 case 8: 251 val |= I2S_CHN_8; 252 break; 253 case 6: 254 val |= I2S_CHN_6; 255 break; 256 case 4: 257 val |= I2S_CHN_4; 258 break; 259 case 2: 260 val |= I2S_CHN_2; 261 break; 262 default: 263 dev_err(i2s->dev, "invalid channel: %d\n", 264 params_channels(params)); 265 return -EINVAL; 266 } 267 268 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 269 regmap_update_bits(i2s->regmap, I2S_RXCR, 270 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 271 val); 272 else 273 regmap_update_bits(i2s->regmap, I2S_TXCR, 274 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 275 val); 276 277 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, 278 I2S_DMACR_TDL(16)); 279 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, 280 I2S_DMACR_RDL(16)); 281 282 val = I2S_CKR_TRCM_TXRX; 283 if (dai->driver->symmetric_rates || rtd->dai_link->symmetric_rates) 284 val = I2S_CKR_TRCM_TXSHARE; 285 286 regmap_update_bits(i2s->regmap, I2S_CKR, 287 I2S_CKR_TRCM_MASK, 288 val); 289 return 0; 290 } 291 292 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, 293 int cmd, struct snd_soc_dai *dai) 294 { 295 struct rk_i2s_dev *i2s = to_info(dai); 296 int ret = 0; 297 298 switch (cmd) { 299 case SNDRV_PCM_TRIGGER_START: 300 case SNDRV_PCM_TRIGGER_RESUME: 301 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 302 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 303 rockchip_snd_rxctrl(i2s, 1); 304 else 305 rockchip_snd_txctrl(i2s, 1); 306 break; 307 case SNDRV_PCM_TRIGGER_SUSPEND: 308 case SNDRV_PCM_TRIGGER_STOP: 309 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 310 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 311 rockchip_snd_rxctrl(i2s, 0); 312 else 313 rockchip_snd_txctrl(i2s, 0); 314 break; 315 default: 316 ret = -EINVAL; 317 break; 318 } 319 320 return ret; 321 } 322 323 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, 324 unsigned int freq, int dir) 325 { 326 struct rk_i2s_dev *i2s = to_info(cpu_dai); 327 int ret; 328 329 ret = clk_set_rate(i2s->mclk, freq); 330 if (ret) 331 dev_err(i2s->dev, "Fail to set mclk %d\n", ret); 332 333 return ret; 334 } 335 336 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai) 337 { 338 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); 339 340 dai->capture_dma_data = &i2s->capture_dma_data; 341 dai->playback_dma_data = &i2s->playback_dma_data; 342 343 return 0; 344 } 345 346 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = { 347 .hw_params = rockchip_i2s_hw_params, 348 .set_sysclk = rockchip_i2s_set_sysclk, 349 .set_fmt = rockchip_i2s_set_fmt, 350 .trigger = rockchip_i2s_trigger, 351 }; 352 353 static struct snd_soc_dai_driver rockchip_i2s_dai = { 354 .probe = rockchip_i2s_dai_probe, 355 .playback = { 356 .stream_name = "Playback", 357 .channels_min = 2, 358 .channels_max = 8, 359 .rates = SNDRV_PCM_RATE_8000_192000, 360 .formats = (SNDRV_PCM_FMTBIT_S8 | 361 SNDRV_PCM_FMTBIT_S16_LE | 362 SNDRV_PCM_FMTBIT_S20_3LE | 363 SNDRV_PCM_FMTBIT_S24_LE), 364 }, 365 .capture = { 366 .stream_name = "Capture", 367 .channels_min = 2, 368 .channels_max = 2, 369 .rates = SNDRV_PCM_RATE_8000_192000, 370 .formats = (SNDRV_PCM_FMTBIT_S8 | 371 SNDRV_PCM_FMTBIT_S16_LE | 372 SNDRV_PCM_FMTBIT_S20_3LE | 373 SNDRV_PCM_FMTBIT_S24_LE), 374 }, 375 .ops = &rockchip_i2s_dai_ops, 376 .symmetric_rates = 1, 377 }; 378 379 static const struct snd_soc_component_driver rockchip_i2s_component = { 380 .name = DRV_NAME, 381 }; 382 383 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg) 384 { 385 switch (reg) { 386 case I2S_TXCR: 387 case I2S_RXCR: 388 case I2S_CKR: 389 case I2S_DMACR: 390 case I2S_INTCR: 391 case I2S_XFER: 392 case I2S_CLR: 393 case I2S_TXDR: 394 return true; 395 default: 396 return false; 397 } 398 } 399 400 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg) 401 { 402 switch (reg) { 403 case I2S_TXCR: 404 case I2S_RXCR: 405 case I2S_CKR: 406 case I2S_DMACR: 407 case I2S_INTCR: 408 case I2S_XFER: 409 case I2S_CLR: 410 case I2S_RXDR: 411 case I2S_FIFOLR: 412 case I2S_INTSR: 413 return true; 414 default: 415 return false; 416 } 417 } 418 419 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg) 420 { 421 switch (reg) { 422 case I2S_INTSR: 423 case I2S_CLR: 424 return true; 425 default: 426 return false; 427 } 428 } 429 430 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg) 431 { 432 switch (reg) { 433 default: 434 return false; 435 } 436 } 437 438 static const struct regmap_config rockchip_i2s_regmap_config = { 439 .reg_bits = 32, 440 .reg_stride = 4, 441 .val_bits = 32, 442 .max_register = I2S_RXDR, 443 .writeable_reg = rockchip_i2s_wr_reg, 444 .readable_reg = rockchip_i2s_rd_reg, 445 .volatile_reg = rockchip_i2s_volatile_reg, 446 .precious_reg = rockchip_i2s_precious_reg, 447 .cache_type = REGCACHE_FLAT, 448 }; 449 450 static int rockchip_i2s_probe(struct platform_device *pdev) 451 { 452 struct device_node *node = pdev->dev.of_node; 453 struct rk_i2s_dev *i2s; 454 struct resource *res; 455 void __iomem *regs; 456 int ret; 457 int val; 458 459 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 460 if (!i2s) { 461 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n"); 462 return -ENOMEM; 463 } 464 465 /* try to prepare related clocks */ 466 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk"); 467 if (IS_ERR(i2s->hclk)) { 468 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n"); 469 return PTR_ERR(i2s->hclk); 470 } 471 ret = clk_prepare_enable(i2s->hclk); 472 if (ret) { 473 dev_err(i2s->dev, "hclock enable failed %d\n", ret); 474 return ret; 475 } 476 477 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk"); 478 if (IS_ERR(i2s->mclk)) { 479 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n"); 480 return PTR_ERR(i2s->mclk); 481 } 482 483 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 484 regs = devm_ioremap_resource(&pdev->dev, res); 485 if (IS_ERR(regs)) 486 return PTR_ERR(regs); 487 488 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 489 &rockchip_i2s_regmap_config); 490 if (IS_ERR(i2s->regmap)) { 491 dev_err(&pdev->dev, 492 "Failed to initialise managed register map\n"); 493 return PTR_ERR(i2s->regmap); 494 } 495 496 i2s->playback_dma_data.addr = res->start + I2S_TXDR; 497 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 498 i2s->playback_dma_data.maxburst = 4; 499 500 i2s->capture_dma_data.addr = res->start + I2S_RXDR; 501 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 502 i2s->capture_dma_data.maxburst = 4; 503 504 i2s->dev = &pdev->dev; 505 dev_set_drvdata(&pdev->dev, i2s); 506 507 pm_runtime_enable(&pdev->dev); 508 if (!pm_runtime_enabled(&pdev->dev)) { 509 ret = i2s_runtime_resume(&pdev->dev); 510 if (ret) 511 goto err_pm_disable; 512 } 513 514 /* refine capture channels */ 515 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) { 516 if (val >= 2 && val <= 8) 517 rockchip_i2s_dai.capture.channels_max = val; 518 else 519 rockchip_i2s_dai.capture.channels_max = 2; 520 } 521 522 ret = devm_snd_soc_register_component(&pdev->dev, 523 &rockchip_i2s_component, 524 &rockchip_i2s_dai, 1); 525 if (ret) { 526 dev_err(&pdev->dev, "Could not register DAI\n"); 527 goto err_suspend; 528 } 529 530 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 531 if (ret) { 532 dev_err(&pdev->dev, "Could not register PCM\n"); 533 return ret; 534 } 535 536 return 0; 537 538 err_suspend: 539 if (!pm_runtime_status_suspended(&pdev->dev)) 540 i2s_runtime_suspend(&pdev->dev); 541 err_pm_disable: 542 pm_runtime_disable(&pdev->dev); 543 544 return ret; 545 } 546 547 static int rockchip_i2s_remove(struct platform_device *pdev) 548 { 549 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev); 550 551 pm_runtime_disable(&pdev->dev); 552 if (!pm_runtime_status_suspended(&pdev->dev)) 553 i2s_runtime_suspend(&pdev->dev); 554 555 clk_disable_unprepare(i2s->mclk); 556 clk_disable_unprepare(i2s->hclk); 557 558 return 0; 559 } 560 561 static const struct of_device_id rockchip_i2s_match[] = { 562 { .compatible = "rockchip,rk3066-i2s", }, 563 {}, 564 }; 565 566 static const struct dev_pm_ops rockchip_i2s_pm_ops = { 567 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume, 568 NULL) 569 }; 570 571 static struct platform_driver rockchip_i2s_driver = { 572 .probe = rockchip_i2s_probe, 573 .remove = rockchip_i2s_remove, 574 .driver = { 575 .name = DRV_NAME, 576 .of_match_table = of_match_ptr(rockchip_i2s_match), 577 .pm = &rockchip_i2s_pm_ops, 578 }, 579 }; 580 module_platform_driver(rockchip_i2s_driver); 581 582 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface"); 583 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>"); 584 MODULE_LICENSE("GPL v2"); 585 MODULE_ALIAS("platform:" DRV_NAME); 586 MODULE_DEVICE_TABLE(of, rockchip_i2s_match); 587