1 // SPDX-License-Identifier: GPL-2.0-only 2 /* sound/soc/rockchip/rockchip_i2s.c 3 * 4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver 5 * 6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd. 7 * Author: Jianqun <jay.xu@rock-chips.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/delay.h> 13 #include <linux/of_gpio.h> 14 #include <linux/of_device.h> 15 #include <linux/clk.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <sound/pcm_params.h> 19 #include <sound/dmaengine_pcm.h> 20 21 #include "rockchip_i2s.h" 22 #include "rockchip_pcm.h" 23 24 #define DRV_NAME "rockchip-i2s" 25 26 struct rk_i2s_pins { 27 u32 reg_offset; 28 u32 shift; 29 }; 30 31 struct rk_i2s_dev { 32 struct device *dev; 33 34 struct clk *hclk; 35 struct clk *mclk; 36 37 struct snd_dmaengine_dai_dma_data capture_dma_data; 38 struct snd_dmaengine_dai_dma_data playback_dma_data; 39 40 struct regmap *regmap; 41 struct regmap *grf; 42 43 /* 44 * Used to indicate the tx/rx status. 45 * I2S controller hopes to start the tx and rx together, 46 * also to stop them when they are both try to stop. 47 */ 48 bool tx_start; 49 bool rx_start; 50 bool is_master_mode; 51 const struct rk_i2s_pins *pins; 52 }; 53 54 static int i2s_runtime_suspend(struct device *dev) 55 { 56 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 57 58 regcache_cache_only(i2s->regmap, true); 59 clk_disable_unprepare(i2s->mclk); 60 61 return 0; 62 } 63 64 static int i2s_runtime_resume(struct device *dev) 65 { 66 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 67 int ret; 68 69 ret = clk_prepare_enable(i2s->mclk); 70 if (ret) { 71 dev_err(i2s->dev, "clock enable failed %d\n", ret); 72 return ret; 73 } 74 75 regcache_cache_only(i2s->regmap, false); 76 regcache_mark_dirty(i2s->regmap); 77 78 ret = regcache_sync(i2s->regmap); 79 if (ret) 80 clk_disable_unprepare(i2s->mclk); 81 82 return ret; 83 } 84 85 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai) 86 { 87 return snd_soc_dai_get_drvdata(dai); 88 } 89 90 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) 91 { 92 unsigned int val = 0; 93 int retry = 10; 94 95 if (on) { 96 regmap_update_bits(i2s->regmap, I2S_DMACR, 97 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE); 98 99 regmap_update_bits(i2s->regmap, I2S_XFER, 100 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 101 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 102 103 i2s->tx_start = true; 104 } else { 105 i2s->tx_start = false; 106 107 regmap_update_bits(i2s->regmap, I2S_DMACR, 108 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE); 109 110 if (!i2s->rx_start) { 111 regmap_update_bits(i2s->regmap, I2S_XFER, 112 I2S_XFER_TXS_START | 113 I2S_XFER_RXS_START, 114 I2S_XFER_TXS_STOP | 115 I2S_XFER_RXS_STOP); 116 117 udelay(150); 118 regmap_update_bits(i2s->regmap, I2S_CLR, 119 I2S_CLR_TXC | I2S_CLR_RXC, 120 I2S_CLR_TXC | I2S_CLR_RXC); 121 122 regmap_read(i2s->regmap, I2S_CLR, &val); 123 124 /* Should wait for clear operation to finish */ 125 while (val) { 126 regmap_read(i2s->regmap, I2S_CLR, &val); 127 retry--; 128 if (!retry) { 129 dev_warn(i2s->dev, "fail to clear\n"); 130 break; 131 } 132 } 133 } 134 } 135 } 136 137 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) 138 { 139 unsigned int val = 0; 140 int retry = 10; 141 142 if (on) { 143 regmap_update_bits(i2s->regmap, I2S_DMACR, 144 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE); 145 146 regmap_update_bits(i2s->regmap, I2S_XFER, 147 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 148 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 149 150 i2s->rx_start = true; 151 } else { 152 i2s->rx_start = false; 153 154 regmap_update_bits(i2s->regmap, I2S_DMACR, 155 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE); 156 157 if (!i2s->tx_start) { 158 regmap_update_bits(i2s->regmap, I2S_XFER, 159 I2S_XFER_TXS_START | 160 I2S_XFER_RXS_START, 161 I2S_XFER_TXS_STOP | 162 I2S_XFER_RXS_STOP); 163 164 udelay(150); 165 regmap_update_bits(i2s->regmap, I2S_CLR, 166 I2S_CLR_TXC | I2S_CLR_RXC, 167 I2S_CLR_TXC | I2S_CLR_RXC); 168 169 regmap_read(i2s->regmap, I2S_CLR, &val); 170 171 /* Should wait for clear operation to finish */ 172 while (val) { 173 regmap_read(i2s->regmap, I2S_CLR, &val); 174 retry--; 175 if (!retry) { 176 dev_warn(i2s->dev, "fail to clear\n"); 177 break; 178 } 179 } 180 } 181 } 182 } 183 184 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, 185 unsigned int fmt) 186 { 187 struct rk_i2s_dev *i2s = to_info(cpu_dai); 188 unsigned int mask = 0, val = 0; 189 190 mask = I2S_CKR_MSS_MASK; 191 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 192 case SND_SOC_DAIFMT_CBS_CFS: 193 /* Set source clock in Master mode */ 194 val = I2S_CKR_MSS_MASTER; 195 i2s->is_master_mode = true; 196 break; 197 case SND_SOC_DAIFMT_CBM_CFM: 198 val = I2S_CKR_MSS_SLAVE; 199 i2s->is_master_mode = false; 200 break; 201 default: 202 return -EINVAL; 203 } 204 205 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 206 207 mask = I2S_CKR_CKP_MASK; 208 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 209 case SND_SOC_DAIFMT_NB_NF: 210 val = I2S_CKR_CKP_NEG; 211 break; 212 case SND_SOC_DAIFMT_IB_NF: 213 val = I2S_CKR_CKP_POS; 214 break; 215 default: 216 return -EINVAL; 217 } 218 219 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 220 221 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; 222 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 223 case SND_SOC_DAIFMT_RIGHT_J: 224 val = I2S_TXCR_IBM_RSJM; 225 break; 226 case SND_SOC_DAIFMT_LEFT_J: 227 val = I2S_TXCR_IBM_LSJM; 228 break; 229 case SND_SOC_DAIFMT_I2S: 230 val = I2S_TXCR_IBM_NORMAL; 231 break; 232 case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */ 233 val = I2S_TXCR_TFS_PCM; 234 break; 235 case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */ 236 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); 237 break; 238 default: 239 return -EINVAL; 240 } 241 242 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); 243 244 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; 245 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 246 case SND_SOC_DAIFMT_RIGHT_J: 247 val = I2S_RXCR_IBM_RSJM; 248 break; 249 case SND_SOC_DAIFMT_LEFT_J: 250 val = I2S_RXCR_IBM_LSJM; 251 break; 252 case SND_SOC_DAIFMT_I2S: 253 val = I2S_RXCR_IBM_NORMAL; 254 break; 255 case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */ 256 val = I2S_RXCR_TFS_PCM; 257 break; 258 case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */ 259 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); 260 break; 261 default: 262 return -EINVAL; 263 } 264 265 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val); 266 267 return 0; 268 } 269 270 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, 271 struct snd_pcm_hw_params *params, 272 struct snd_soc_dai *dai) 273 { 274 struct rk_i2s_dev *i2s = to_info(dai); 275 struct snd_soc_pcm_runtime *rtd = substream->private_data; 276 unsigned int val = 0; 277 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck; 278 279 if (i2s->is_master_mode) { 280 mclk_rate = clk_get_rate(i2s->mclk); 281 bclk_rate = 2 * 32 * params_rate(params); 282 if (bclk_rate && mclk_rate % bclk_rate) 283 return -EINVAL; 284 285 div_bclk = mclk_rate / bclk_rate; 286 div_lrck = bclk_rate / params_rate(params); 287 regmap_update_bits(i2s->regmap, I2S_CKR, 288 I2S_CKR_MDIV_MASK, 289 I2S_CKR_MDIV(div_bclk)); 290 291 regmap_update_bits(i2s->regmap, I2S_CKR, 292 I2S_CKR_TSD_MASK | 293 I2S_CKR_RSD_MASK, 294 I2S_CKR_TSD(div_lrck) | 295 I2S_CKR_RSD(div_lrck)); 296 } 297 298 switch (params_format(params)) { 299 case SNDRV_PCM_FORMAT_S8: 300 val |= I2S_TXCR_VDW(8); 301 break; 302 case SNDRV_PCM_FORMAT_S16_LE: 303 val |= I2S_TXCR_VDW(16); 304 break; 305 case SNDRV_PCM_FORMAT_S20_3LE: 306 val |= I2S_TXCR_VDW(20); 307 break; 308 case SNDRV_PCM_FORMAT_S24_LE: 309 val |= I2S_TXCR_VDW(24); 310 break; 311 case SNDRV_PCM_FORMAT_S32_LE: 312 val |= I2S_TXCR_VDW(32); 313 break; 314 default: 315 return -EINVAL; 316 } 317 318 switch (params_channels(params)) { 319 case 8: 320 val |= I2S_CHN_8; 321 break; 322 case 6: 323 val |= I2S_CHN_6; 324 break; 325 case 4: 326 val |= I2S_CHN_4; 327 break; 328 case 2: 329 case 1: 330 val |= I2S_CHN_2; 331 break; 332 default: 333 dev_err(i2s->dev, "invalid channel: %d\n", 334 params_channels(params)); 335 return -EINVAL; 336 } 337 338 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 339 regmap_update_bits(i2s->regmap, I2S_RXCR, 340 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 341 val); 342 else 343 regmap_update_bits(i2s->regmap, I2S_TXCR, 344 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 345 val); 346 347 if (!IS_ERR(i2s->grf) && i2s->pins) { 348 regmap_read(i2s->regmap, I2S_TXCR, &val); 349 val &= I2S_TXCR_CSR_MASK; 350 351 switch (val) { 352 case I2S_CHN_4: 353 val = I2S_IO_4CH_OUT_6CH_IN; 354 break; 355 case I2S_CHN_6: 356 val = I2S_IO_6CH_OUT_4CH_IN; 357 break; 358 case I2S_CHN_8: 359 val = I2S_IO_8CH_OUT_2CH_IN; 360 break; 361 default: 362 val = I2S_IO_2CH_OUT_8CH_IN; 363 break; 364 } 365 366 val <<= i2s->pins->shift; 367 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16; 368 regmap_write(i2s->grf, i2s->pins->reg_offset, val); 369 } 370 371 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, 372 I2S_DMACR_TDL(16)); 373 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, 374 I2S_DMACR_RDL(16)); 375 376 val = I2S_CKR_TRCM_TXRX; 377 if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates) 378 val = I2S_CKR_TRCM_TXONLY; 379 380 regmap_update_bits(i2s->regmap, I2S_CKR, 381 I2S_CKR_TRCM_MASK, 382 val); 383 return 0; 384 } 385 386 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, 387 int cmd, struct snd_soc_dai *dai) 388 { 389 struct rk_i2s_dev *i2s = to_info(dai); 390 int ret = 0; 391 392 switch (cmd) { 393 case SNDRV_PCM_TRIGGER_START: 394 case SNDRV_PCM_TRIGGER_RESUME: 395 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 396 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 397 rockchip_snd_rxctrl(i2s, 1); 398 else 399 rockchip_snd_txctrl(i2s, 1); 400 break; 401 case SNDRV_PCM_TRIGGER_SUSPEND: 402 case SNDRV_PCM_TRIGGER_STOP: 403 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 404 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 405 rockchip_snd_rxctrl(i2s, 0); 406 else 407 rockchip_snd_txctrl(i2s, 0); 408 break; 409 default: 410 ret = -EINVAL; 411 break; 412 } 413 414 return ret; 415 } 416 417 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, 418 unsigned int freq, int dir) 419 { 420 struct rk_i2s_dev *i2s = to_info(cpu_dai); 421 int ret; 422 423 ret = clk_set_rate(i2s->mclk, freq); 424 if (ret) 425 dev_err(i2s->dev, "Fail to set mclk %d\n", ret); 426 427 return ret; 428 } 429 430 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai) 431 { 432 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); 433 434 dai->capture_dma_data = &i2s->capture_dma_data; 435 dai->playback_dma_data = &i2s->playback_dma_data; 436 437 return 0; 438 } 439 440 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = { 441 .hw_params = rockchip_i2s_hw_params, 442 .set_sysclk = rockchip_i2s_set_sysclk, 443 .set_fmt = rockchip_i2s_set_fmt, 444 .trigger = rockchip_i2s_trigger, 445 }; 446 447 static struct snd_soc_dai_driver rockchip_i2s_dai = { 448 .probe = rockchip_i2s_dai_probe, 449 .playback = { 450 .stream_name = "Playback", 451 .channels_min = 2, 452 .channels_max = 8, 453 .rates = SNDRV_PCM_RATE_8000_192000, 454 .formats = (SNDRV_PCM_FMTBIT_S8 | 455 SNDRV_PCM_FMTBIT_S16_LE | 456 SNDRV_PCM_FMTBIT_S20_3LE | 457 SNDRV_PCM_FMTBIT_S24_LE | 458 SNDRV_PCM_FMTBIT_S32_LE), 459 }, 460 .capture = { 461 .stream_name = "Capture", 462 .channels_min = 1, 463 .channels_max = 2, 464 .rates = SNDRV_PCM_RATE_8000_192000, 465 .formats = (SNDRV_PCM_FMTBIT_S8 | 466 SNDRV_PCM_FMTBIT_S16_LE | 467 SNDRV_PCM_FMTBIT_S20_3LE | 468 SNDRV_PCM_FMTBIT_S24_LE | 469 SNDRV_PCM_FMTBIT_S32_LE), 470 }, 471 .ops = &rockchip_i2s_dai_ops, 472 .symmetric_rates = 1, 473 }; 474 475 static const struct snd_soc_component_driver rockchip_i2s_component = { 476 .name = DRV_NAME, 477 }; 478 479 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg) 480 { 481 switch (reg) { 482 case I2S_TXCR: 483 case I2S_RXCR: 484 case I2S_CKR: 485 case I2S_DMACR: 486 case I2S_INTCR: 487 case I2S_XFER: 488 case I2S_CLR: 489 case I2S_TXDR: 490 return true; 491 default: 492 return false; 493 } 494 } 495 496 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg) 497 { 498 switch (reg) { 499 case I2S_TXCR: 500 case I2S_RXCR: 501 case I2S_CKR: 502 case I2S_DMACR: 503 case I2S_INTCR: 504 case I2S_XFER: 505 case I2S_CLR: 506 case I2S_TXDR: 507 case I2S_RXDR: 508 case I2S_FIFOLR: 509 case I2S_INTSR: 510 return true; 511 default: 512 return false; 513 } 514 } 515 516 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg) 517 { 518 switch (reg) { 519 case I2S_INTSR: 520 case I2S_CLR: 521 case I2S_FIFOLR: 522 case I2S_TXDR: 523 case I2S_RXDR: 524 return true; 525 default: 526 return false; 527 } 528 } 529 530 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg) 531 { 532 switch (reg) { 533 case I2S_RXDR: 534 return true; 535 default: 536 return false; 537 } 538 } 539 540 static const struct reg_default rockchip_i2s_reg_defaults[] = { 541 {0x00, 0x0000000f}, 542 {0x04, 0x0000000f}, 543 {0x08, 0x00071f1f}, 544 {0x10, 0x001f0000}, 545 {0x14, 0x01f00000}, 546 }; 547 548 static const struct regmap_config rockchip_i2s_regmap_config = { 549 .reg_bits = 32, 550 .reg_stride = 4, 551 .val_bits = 32, 552 .max_register = I2S_RXDR, 553 .reg_defaults = rockchip_i2s_reg_defaults, 554 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults), 555 .writeable_reg = rockchip_i2s_wr_reg, 556 .readable_reg = rockchip_i2s_rd_reg, 557 .volatile_reg = rockchip_i2s_volatile_reg, 558 .precious_reg = rockchip_i2s_precious_reg, 559 .cache_type = REGCACHE_FLAT, 560 }; 561 562 static const struct rk_i2s_pins rk3399_i2s_pins = { 563 .reg_offset = 0xe220, 564 .shift = 11, 565 }; 566 567 static const struct of_device_id rockchip_i2s_match[] = { 568 { .compatible = "rockchip,rk3066-i2s", }, 569 { .compatible = "rockchip,rk3188-i2s", }, 570 { .compatible = "rockchip,rk3288-i2s", }, 571 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins }, 572 {}, 573 }; 574 575 static int rockchip_i2s_probe(struct platform_device *pdev) 576 { 577 struct device_node *node = pdev->dev.of_node; 578 const struct of_device_id *of_id; 579 struct rk_i2s_dev *i2s; 580 struct snd_soc_dai_driver *soc_dai; 581 struct resource *res; 582 void __iomem *regs; 583 int ret; 584 int val; 585 586 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 587 if (!i2s) 588 return -ENOMEM; 589 590 i2s->dev = &pdev->dev; 591 592 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); 593 if (!IS_ERR(i2s->grf)) { 594 of_id = of_match_device(rockchip_i2s_match, &pdev->dev); 595 if (!of_id || !of_id->data) 596 return -EINVAL; 597 598 i2s->pins = of_id->data; 599 } 600 601 /* try to prepare related clocks */ 602 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk"); 603 if (IS_ERR(i2s->hclk)) { 604 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n"); 605 return PTR_ERR(i2s->hclk); 606 } 607 ret = clk_prepare_enable(i2s->hclk); 608 if (ret) { 609 dev_err(i2s->dev, "hclock enable failed %d\n", ret); 610 return ret; 611 } 612 613 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk"); 614 if (IS_ERR(i2s->mclk)) { 615 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n"); 616 return PTR_ERR(i2s->mclk); 617 } 618 619 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 620 regs = devm_ioremap_resource(&pdev->dev, res); 621 if (IS_ERR(regs)) 622 return PTR_ERR(regs); 623 624 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 625 &rockchip_i2s_regmap_config); 626 if (IS_ERR(i2s->regmap)) { 627 dev_err(&pdev->dev, 628 "Failed to initialise managed register map\n"); 629 return PTR_ERR(i2s->regmap); 630 } 631 632 i2s->playback_dma_data.addr = res->start + I2S_TXDR; 633 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 634 i2s->playback_dma_data.maxburst = 4; 635 636 i2s->capture_dma_data.addr = res->start + I2S_RXDR; 637 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 638 i2s->capture_dma_data.maxburst = 4; 639 640 dev_set_drvdata(&pdev->dev, i2s); 641 642 pm_runtime_enable(&pdev->dev); 643 if (!pm_runtime_enabled(&pdev->dev)) { 644 ret = i2s_runtime_resume(&pdev->dev); 645 if (ret) 646 goto err_pm_disable; 647 } 648 649 soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai, 650 sizeof(*soc_dai), GFP_KERNEL); 651 if (!soc_dai) { 652 ret = -ENOMEM; 653 goto err_pm_disable; 654 } 655 656 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) { 657 if (val >= 2 && val <= 8) 658 soc_dai->playback.channels_max = val; 659 } 660 661 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) { 662 if (val >= 1 && val <= 8) 663 soc_dai->capture.channels_max = val; 664 } 665 666 ret = devm_snd_soc_register_component(&pdev->dev, 667 &rockchip_i2s_component, 668 soc_dai, 1); 669 670 if (ret) { 671 dev_err(&pdev->dev, "Could not register DAI\n"); 672 goto err_suspend; 673 } 674 675 ret = rockchip_pcm_platform_register(&pdev->dev); 676 if (ret) { 677 dev_err(&pdev->dev, "Could not register PCM\n"); 678 return ret; 679 } 680 681 return 0; 682 683 err_suspend: 684 if (!pm_runtime_status_suspended(&pdev->dev)) 685 i2s_runtime_suspend(&pdev->dev); 686 err_pm_disable: 687 pm_runtime_disable(&pdev->dev); 688 689 return ret; 690 } 691 692 static int rockchip_i2s_remove(struct platform_device *pdev) 693 { 694 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev); 695 696 pm_runtime_disable(&pdev->dev); 697 if (!pm_runtime_status_suspended(&pdev->dev)) 698 i2s_runtime_suspend(&pdev->dev); 699 700 clk_disable_unprepare(i2s->hclk); 701 702 return 0; 703 } 704 705 static const struct dev_pm_ops rockchip_i2s_pm_ops = { 706 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume, 707 NULL) 708 }; 709 710 static struct platform_driver rockchip_i2s_driver = { 711 .probe = rockchip_i2s_probe, 712 .remove = rockchip_i2s_remove, 713 .driver = { 714 .name = DRV_NAME, 715 .of_match_table = of_match_ptr(rockchip_i2s_match), 716 .pm = &rockchip_i2s_pm_ops, 717 }, 718 }; 719 module_platform_driver(rockchip_i2s_driver); 720 721 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface"); 722 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>"); 723 MODULE_LICENSE("GPL v2"); 724 MODULE_ALIAS("platform:" DRV_NAME); 725 MODULE_DEVICE_TABLE(of, rockchip_i2s_match); 726