1 // SPDX-License-Identifier: GPL-2.0-only 2 /* sound/soc/rockchip/rockchip_i2s.c 3 * 4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver 5 * 6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd. 7 * Author: Jianqun <jay.xu@rock-chips.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/delay.h> 13 #include <linux/of_gpio.h> 14 #include <linux/of_device.h> 15 #include <linux/clk.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/spinlock.h> 20 #include <sound/pcm_params.h> 21 #include <sound/dmaengine_pcm.h> 22 23 #include "rockchip_i2s.h" 24 25 #define DRV_NAME "rockchip-i2s" 26 27 struct rk_i2s_pins { 28 u32 reg_offset; 29 u32 shift; 30 }; 31 32 struct rk_i2s_dev { 33 struct device *dev; 34 35 struct clk *hclk; 36 struct clk *mclk; 37 38 struct snd_dmaengine_dai_dma_data capture_dma_data; 39 struct snd_dmaengine_dai_dma_data playback_dma_data; 40 41 struct regmap *regmap; 42 struct regmap *grf; 43 44 bool has_capture; 45 bool has_playback; 46 47 /* 48 * Used to indicate the tx/rx status. 49 * I2S controller hopes to start the tx and rx together, 50 * also to stop them when they are both try to stop. 51 */ 52 bool tx_start; 53 bool rx_start; 54 bool is_master_mode; 55 const struct rk_i2s_pins *pins; 56 unsigned int bclk_ratio; 57 spinlock_t lock; /* tx/rx lock */ 58 struct pinctrl *pinctrl; 59 struct pinctrl_state *bclk_on; 60 struct pinctrl_state *bclk_off; 61 }; 62 63 static int i2s_pinctrl_select_bclk_on(struct rk_i2s_dev *i2s) 64 { 65 int ret = 0; 66 67 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_on)) 68 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_on); 69 70 if (ret) 71 dev_err(i2s->dev, "bclk enable failed %d\n", ret); 72 73 return ret; 74 } 75 76 static int i2s_pinctrl_select_bclk_off(struct rk_i2s_dev *i2s) 77 { 78 79 int ret = 0; 80 81 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_off)) 82 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_off); 83 84 if (ret) 85 dev_err(i2s->dev, "bclk disable failed %d\n", ret); 86 87 return ret; 88 } 89 90 static int i2s_runtime_suspend(struct device *dev) 91 { 92 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 93 94 regcache_cache_only(i2s->regmap, true); 95 clk_disable_unprepare(i2s->mclk); 96 97 return 0; 98 } 99 100 static int i2s_runtime_resume(struct device *dev) 101 { 102 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 103 int ret; 104 105 ret = clk_prepare_enable(i2s->mclk); 106 if (ret) { 107 dev_err(i2s->dev, "clock enable failed %d\n", ret); 108 return ret; 109 } 110 111 regcache_cache_only(i2s->regmap, false); 112 regcache_mark_dirty(i2s->regmap); 113 114 ret = regcache_sync(i2s->regmap); 115 if (ret) 116 clk_disable_unprepare(i2s->mclk); 117 118 return ret; 119 } 120 121 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai) 122 { 123 return snd_soc_dai_get_drvdata(dai); 124 } 125 126 static int rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) 127 { 128 unsigned int val = 0; 129 int retry = 10; 130 int ret = 0; 131 132 spin_lock(&i2s->lock); 133 if (on) { 134 ret = regmap_update_bits(i2s->regmap, I2S_DMACR, 135 I2S_DMACR_TDE_ENABLE, 136 I2S_DMACR_TDE_ENABLE); 137 if (ret < 0) 138 goto end; 139 ret = regmap_update_bits(i2s->regmap, I2S_XFER, 140 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 141 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 142 if (ret < 0) 143 goto end; 144 i2s->tx_start = true; 145 } else { 146 i2s->tx_start = false; 147 148 ret = regmap_update_bits(i2s->regmap, I2S_DMACR, 149 I2S_DMACR_TDE_ENABLE, 150 I2S_DMACR_TDE_DISABLE); 151 if (ret < 0) 152 goto end; 153 154 if (!i2s->rx_start) { 155 ret = regmap_update_bits(i2s->regmap, I2S_XFER, 156 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 157 I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); 158 if (ret < 0) 159 goto end; 160 udelay(150); 161 ret = regmap_update_bits(i2s->regmap, I2S_CLR, 162 I2S_CLR_TXC | I2S_CLR_RXC, 163 I2S_CLR_TXC | I2S_CLR_RXC); 164 if (ret < 0) 165 goto end; 166 regmap_read(i2s->regmap, I2S_CLR, &val); 167 168 /* Should wait for clear operation to finish */ 169 while (val) { 170 regmap_read(i2s->regmap, I2S_CLR, &val); 171 retry--; 172 if (!retry) { 173 dev_warn(i2s->dev, "fail to clear\n"); 174 ret = -EBUSY; 175 break; 176 } 177 } 178 } 179 } 180 end: 181 spin_unlock(&i2s->lock); 182 if (ret < 0) 183 dev_err(i2s->dev, "lrclk update failed\n"); 184 185 return ret; 186 } 187 188 static int rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) 189 { 190 unsigned int val = 0; 191 int retry = 10; 192 int ret = 0; 193 194 spin_lock(&i2s->lock); 195 if (on) { 196 ret = regmap_update_bits(i2s->regmap, I2S_DMACR, 197 I2S_DMACR_RDE_ENABLE, 198 I2S_DMACR_RDE_ENABLE); 199 if (ret < 0) 200 goto end; 201 202 ret = regmap_update_bits(i2s->regmap, I2S_XFER, 203 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 204 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 205 if (ret < 0) 206 goto end; 207 i2s->rx_start = true; 208 } else { 209 i2s->rx_start = false; 210 211 ret = regmap_update_bits(i2s->regmap, I2S_DMACR, 212 I2S_DMACR_RDE_ENABLE, 213 I2S_DMACR_RDE_DISABLE); 214 if (ret < 0) 215 goto end; 216 217 if (!i2s->tx_start) { 218 ret = regmap_update_bits(i2s->regmap, I2S_XFER, 219 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 220 I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); 221 if (ret < 0) 222 goto end; 223 udelay(150); 224 ret = regmap_update_bits(i2s->regmap, I2S_CLR, 225 I2S_CLR_TXC | I2S_CLR_RXC, 226 I2S_CLR_TXC | I2S_CLR_RXC); 227 if (ret < 0) 228 goto end; 229 regmap_read(i2s->regmap, I2S_CLR, &val); 230 /* Should wait for clear operation to finish */ 231 while (val) { 232 regmap_read(i2s->regmap, I2S_CLR, &val); 233 retry--; 234 if (!retry) { 235 dev_warn(i2s->dev, "fail to clear\n"); 236 ret = -EBUSY; 237 break; 238 } 239 } 240 } 241 } 242 end: 243 spin_unlock(&i2s->lock); 244 if (ret < 0) 245 dev_err(i2s->dev, "lrclk update failed\n"); 246 247 return ret; 248 } 249 250 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, 251 unsigned int fmt) 252 { 253 struct rk_i2s_dev *i2s = to_info(cpu_dai); 254 unsigned int mask = 0, val = 0; 255 int ret = 0; 256 257 pm_runtime_get_sync(cpu_dai->dev); 258 mask = I2S_CKR_MSS_MASK; 259 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 260 case SND_SOC_DAIFMT_BP_FP: 261 /* Set source clock in Master mode */ 262 val = I2S_CKR_MSS_MASTER; 263 i2s->is_master_mode = true; 264 break; 265 case SND_SOC_DAIFMT_BC_FC: 266 val = I2S_CKR_MSS_SLAVE; 267 i2s->is_master_mode = false; 268 break; 269 default: 270 ret = -EINVAL; 271 goto err_pm_put; 272 } 273 274 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 275 276 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK; 277 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 278 case SND_SOC_DAIFMT_NB_NF: 279 val = I2S_CKR_CKP_NORMAL | 280 I2S_CKR_TLP_NORMAL | 281 I2S_CKR_RLP_NORMAL; 282 break; 283 case SND_SOC_DAIFMT_NB_IF: 284 val = I2S_CKR_CKP_NORMAL | 285 I2S_CKR_TLP_INVERTED | 286 I2S_CKR_RLP_INVERTED; 287 break; 288 case SND_SOC_DAIFMT_IB_NF: 289 val = I2S_CKR_CKP_INVERTED | 290 I2S_CKR_TLP_NORMAL | 291 I2S_CKR_RLP_NORMAL; 292 break; 293 case SND_SOC_DAIFMT_IB_IF: 294 val = I2S_CKR_CKP_INVERTED | 295 I2S_CKR_TLP_INVERTED | 296 I2S_CKR_RLP_INVERTED; 297 break; 298 default: 299 ret = -EINVAL; 300 goto err_pm_put; 301 } 302 303 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 304 305 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; 306 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 307 case SND_SOC_DAIFMT_RIGHT_J: 308 val = I2S_TXCR_IBM_RSJM; 309 break; 310 case SND_SOC_DAIFMT_LEFT_J: 311 val = I2S_TXCR_IBM_LSJM; 312 break; 313 case SND_SOC_DAIFMT_I2S: 314 val = I2S_TXCR_IBM_NORMAL; 315 break; 316 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */ 317 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); 318 break; 319 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */ 320 val = I2S_TXCR_TFS_PCM; 321 break; 322 default: 323 ret = -EINVAL; 324 goto err_pm_put; 325 } 326 327 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); 328 329 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; 330 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 331 case SND_SOC_DAIFMT_RIGHT_J: 332 val = I2S_RXCR_IBM_RSJM; 333 break; 334 case SND_SOC_DAIFMT_LEFT_J: 335 val = I2S_RXCR_IBM_LSJM; 336 break; 337 case SND_SOC_DAIFMT_I2S: 338 val = I2S_RXCR_IBM_NORMAL; 339 break; 340 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */ 341 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); 342 break; 343 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */ 344 val = I2S_RXCR_TFS_PCM; 345 break; 346 default: 347 ret = -EINVAL; 348 goto err_pm_put; 349 } 350 351 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val); 352 353 err_pm_put: 354 pm_runtime_put(cpu_dai->dev); 355 356 return ret; 357 } 358 359 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, 360 struct snd_pcm_hw_params *params, 361 struct snd_soc_dai *dai) 362 { 363 struct rk_i2s_dev *i2s = to_info(dai); 364 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 365 unsigned int val = 0; 366 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck; 367 368 if (i2s->is_master_mode) { 369 mclk_rate = clk_get_rate(i2s->mclk); 370 bclk_rate = i2s->bclk_ratio * params_rate(params); 371 if (!bclk_rate) 372 return -EINVAL; 373 374 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); 375 div_lrck = bclk_rate / params_rate(params); 376 regmap_update_bits(i2s->regmap, I2S_CKR, 377 I2S_CKR_MDIV_MASK, 378 I2S_CKR_MDIV(div_bclk)); 379 380 regmap_update_bits(i2s->regmap, I2S_CKR, 381 I2S_CKR_TSD_MASK | 382 I2S_CKR_RSD_MASK, 383 I2S_CKR_TSD(div_lrck) | 384 I2S_CKR_RSD(div_lrck)); 385 } 386 387 switch (params_format(params)) { 388 case SNDRV_PCM_FORMAT_S8: 389 val |= I2S_TXCR_VDW(8); 390 break; 391 case SNDRV_PCM_FORMAT_S16_LE: 392 val |= I2S_TXCR_VDW(16); 393 break; 394 case SNDRV_PCM_FORMAT_S20_3LE: 395 val |= I2S_TXCR_VDW(20); 396 break; 397 case SNDRV_PCM_FORMAT_S24_LE: 398 val |= I2S_TXCR_VDW(24); 399 break; 400 case SNDRV_PCM_FORMAT_S32_LE: 401 val |= I2S_TXCR_VDW(32); 402 break; 403 default: 404 return -EINVAL; 405 } 406 407 switch (params_channels(params)) { 408 case 8: 409 val |= I2S_CHN_8; 410 break; 411 case 6: 412 val |= I2S_CHN_6; 413 break; 414 case 4: 415 val |= I2S_CHN_4; 416 break; 417 case 2: 418 val |= I2S_CHN_2; 419 break; 420 default: 421 dev_err(i2s->dev, "invalid channel: %d\n", 422 params_channels(params)); 423 return -EINVAL; 424 } 425 426 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 427 regmap_update_bits(i2s->regmap, I2S_RXCR, 428 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 429 val); 430 else 431 regmap_update_bits(i2s->regmap, I2S_TXCR, 432 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 433 val); 434 435 if (!IS_ERR(i2s->grf) && i2s->pins) { 436 regmap_read(i2s->regmap, I2S_TXCR, &val); 437 val &= I2S_TXCR_CSR_MASK; 438 439 switch (val) { 440 case I2S_CHN_4: 441 val = I2S_IO_4CH_OUT_6CH_IN; 442 break; 443 case I2S_CHN_6: 444 val = I2S_IO_6CH_OUT_4CH_IN; 445 break; 446 case I2S_CHN_8: 447 val = I2S_IO_8CH_OUT_2CH_IN; 448 break; 449 default: 450 val = I2S_IO_2CH_OUT_8CH_IN; 451 break; 452 } 453 454 val <<= i2s->pins->shift; 455 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16; 456 regmap_write(i2s->grf, i2s->pins->reg_offset, val); 457 } 458 459 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, 460 I2S_DMACR_TDL(16)); 461 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, 462 I2S_DMACR_RDL(16)); 463 464 val = I2S_CKR_TRCM_TXRX; 465 if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate) 466 val = I2S_CKR_TRCM_TXONLY; 467 468 regmap_update_bits(i2s->regmap, I2S_CKR, 469 I2S_CKR_TRCM_MASK, 470 val); 471 return 0; 472 } 473 474 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, 475 int cmd, struct snd_soc_dai *dai) 476 { 477 struct rk_i2s_dev *i2s = to_info(dai); 478 int ret = 0; 479 480 switch (cmd) { 481 case SNDRV_PCM_TRIGGER_START: 482 case SNDRV_PCM_TRIGGER_RESUME: 483 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 484 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 485 ret = rockchip_snd_rxctrl(i2s, 1); 486 else 487 ret = rockchip_snd_txctrl(i2s, 1); 488 if (ret < 0) 489 return ret; 490 i2s_pinctrl_select_bclk_on(i2s); 491 break; 492 case SNDRV_PCM_TRIGGER_SUSPEND: 493 case SNDRV_PCM_TRIGGER_STOP: 494 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 495 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 496 if (!i2s->tx_start) 497 i2s_pinctrl_select_bclk_off(i2s); 498 ret = rockchip_snd_rxctrl(i2s, 0); 499 } else { 500 if (!i2s->rx_start) 501 i2s_pinctrl_select_bclk_off(i2s); 502 ret = rockchip_snd_txctrl(i2s, 0); 503 } 504 break; 505 default: 506 ret = -EINVAL; 507 break; 508 } 509 510 return ret; 511 } 512 513 static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai, 514 unsigned int ratio) 515 { 516 struct rk_i2s_dev *i2s = to_info(dai); 517 518 i2s->bclk_ratio = ratio; 519 520 return 0; 521 } 522 523 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, 524 unsigned int freq, int dir) 525 { 526 struct rk_i2s_dev *i2s = to_info(cpu_dai); 527 int ret; 528 529 if (freq == 0) 530 return 0; 531 532 ret = clk_set_rate(i2s->mclk, freq); 533 if (ret) 534 dev_err(i2s->dev, "Fail to set mclk %d\n", ret); 535 536 return ret; 537 } 538 539 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai) 540 { 541 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); 542 543 snd_soc_dai_init_dma_data(dai, 544 i2s->has_playback ? &i2s->playback_dma_data : NULL, 545 i2s->has_capture ? &i2s->capture_dma_data : NULL); 546 547 return 0; 548 } 549 550 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = { 551 .hw_params = rockchip_i2s_hw_params, 552 .set_bclk_ratio = rockchip_i2s_set_bclk_ratio, 553 .set_sysclk = rockchip_i2s_set_sysclk, 554 .set_fmt = rockchip_i2s_set_fmt, 555 .trigger = rockchip_i2s_trigger, 556 }; 557 558 static struct snd_soc_dai_driver rockchip_i2s_dai = { 559 .probe = rockchip_i2s_dai_probe, 560 .ops = &rockchip_i2s_dai_ops, 561 .symmetric_rate = 1, 562 }; 563 564 static const struct snd_soc_component_driver rockchip_i2s_component = { 565 .name = DRV_NAME, 566 .legacy_dai_naming = 1, 567 }; 568 569 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg) 570 { 571 switch (reg) { 572 case I2S_TXCR: 573 case I2S_RXCR: 574 case I2S_CKR: 575 case I2S_DMACR: 576 case I2S_INTCR: 577 case I2S_XFER: 578 case I2S_CLR: 579 case I2S_TXDR: 580 return true; 581 default: 582 return false; 583 } 584 } 585 586 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg) 587 { 588 switch (reg) { 589 case I2S_TXCR: 590 case I2S_RXCR: 591 case I2S_CKR: 592 case I2S_DMACR: 593 case I2S_INTCR: 594 case I2S_XFER: 595 case I2S_CLR: 596 case I2S_TXDR: 597 case I2S_RXDR: 598 case I2S_FIFOLR: 599 case I2S_INTSR: 600 return true; 601 default: 602 return false; 603 } 604 } 605 606 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg) 607 { 608 switch (reg) { 609 case I2S_INTSR: 610 case I2S_CLR: 611 case I2S_FIFOLR: 612 case I2S_TXDR: 613 case I2S_RXDR: 614 return true; 615 default: 616 return false; 617 } 618 } 619 620 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg) 621 { 622 switch (reg) { 623 case I2S_RXDR: 624 return true; 625 default: 626 return false; 627 } 628 } 629 630 static const struct reg_default rockchip_i2s_reg_defaults[] = { 631 {0x00, 0x0000000f}, 632 {0x04, 0x0000000f}, 633 {0x08, 0x00071f1f}, 634 {0x10, 0x001f0000}, 635 {0x14, 0x01f00000}, 636 }; 637 638 static const struct regmap_config rockchip_i2s_regmap_config = { 639 .reg_bits = 32, 640 .reg_stride = 4, 641 .val_bits = 32, 642 .max_register = I2S_RXDR, 643 .reg_defaults = rockchip_i2s_reg_defaults, 644 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults), 645 .writeable_reg = rockchip_i2s_wr_reg, 646 .readable_reg = rockchip_i2s_rd_reg, 647 .volatile_reg = rockchip_i2s_volatile_reg, 648 .precious_reg = rockchip_i2s_precious_reg, 649 .cache_type = REGCACHE_FLAT, 650 }; 651 652 static const struct rk_i2s_pins rk3399_i2s_pins = { 653 .reg_offset = 0xe220, 654 .shift = 11, 655 }; 656 657 static const struct of_device_id rockchip_i2s_match[] __maybe_unused = { 658 { .compatible = "rockchip,px30-i2s", }, 659 { .compatible = "rockchip,rk1808-i2s", }, 660 { .compatible = "rockchip,rk3036-i2s", }, 661 { .compatible = "rockchip,rk3066-i2s", }, 662 { .compatible = "rockchip,rk3128-i2s", }, 663 { .compatible = "rockchip,rk3188-i2s", }, 664 { .compatible = "rockchip,rk3228-i2s", }, 665 { .compatible = "rockchip,rk3288-i2s", }, 666 { .compatible = "rockchip,rk3308-i2s", }, 667 { .compatible = "rockchip,rk3328-i2s", }, 668 { .compatible = "rockchip,rk3366-i2s", }, 669 { .compatible = "rockchip,rk3368-i2s", }, 670 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins }, 671 { .compatible = "rockchip,rv1126-i2s", }, 672 {}, 673 }; 674 675 static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res, 676 struct snd_soc_dai_driver **dp) 677 { 678 struct device_node *node = i2s->dev->of_node; 679 struct snd_soc_dai_driver *dai; 680 struct property *dma_names; 681 const char *dma_name; 682 unsigned int val; 683 684 of_property_for_each_string(node, "dma-names", dma_names, dma_name) { 685 if (!strcmp(dma_name, "tx")) 686 i2s->has_playback = true; 687 if (!strcmp(dma_name, "rx")) 688 i2s->has_capture = true; 689 } 690 691 dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai, 692 sizeof(*dai), GFP_KERNEL); 693 if (!dai) 694 return -ENOMEM; 695 696 if (i2s->has_playback) { 697 dai->playback.stream_name = "Playback"; 698 dai->playback.channels_min = 2; 699 dai->playback.channels_max = 8; 700 dai->playback.rates = SNDRV_PCM_RATE_8000_192000; 701 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 | 702 SNDRV_PCM_FMTBIT_S16_LE | 703 SNDRV_PCM_FMTBIT_S20_3LE | 704 SNDRV_PCM_FMTBIT_S24_LE | 705 SNDRV_PCM_FMTBIT_S32_LE; 706 707 i2s->playback_dma_data.addr = res->start + I2S_TXDR; 708 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 709 i2s->playback_dma_data.maxburst = 8; 710 711 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) { 712 if (val >= 2 && val <= 8) 713 dai->playback.channels_max = val; 714 } 715 } 716 717 if (i2s->has_capture) { 718 dai->capture.stream_name = "Capture"; 719 dai->capture.channels_min = 2; 720 dai->capture.channels_max = 8; 721 dai->capture.rates = SNDRV_PCM_RATE_8000_192000; 722 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 | 723 SNDRV_PCM_FMTBIT_S16_LE | 724 SNDRV_PCM_FMTBIT_S20_3LE | 725 SNDRV_PCM_FMTBIT_S24_LE | 726 SNDRV_PCM_FMTBIT_S32_LE; 727 728 i2s->capture_dma_data.addr = res->start + I2S_RXDR; 729 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 730 i2s->capture_dma_data.maxburst = 8; 731 732 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) { 733 if (val >= 2 && val <= 8) 734 dai->capture.channels_max = val; 735 } 736 } 737 738 if (dp) 739 *dp = dai; 740 741 return 0; 742 } 743 744 static int rockchip_i2s_probe(struct platform_device *pdev) 745 { 746 struct device_node *node = pdev->dev.of_node; 747 const struct of_device_id *of_id; 748 struct rk_i2s_dev *i2s; 749 struct snd_soc_dai_driver *dai; 750 struct resource *res; 751 void __iomem *regs; 752 int ret; 753 754 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 755 if (!i2s) 756 return -ENOMEM; 757 758 spin_lock_init(&i2s->lock); 759 i2s->dev = &pdev->dev; 760 761 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); 762 if (!IS_ERR(i2s->grf)) { 763 of_id = of_match_device(rockchip_i2s_match, &pdev->dev); 764 if (!of_id || !of_id->data) 765 return -EINVAL; 766 767 i2s->pins = of_id->data; 768 } 769 770 /* try to prepare related clocks */ 771 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk"); 772 if (IS_ERR(i2s->hclk)) { 773 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n"); 774 return PTR_ERR(i2s->hclk); 775 } 776 ret = clk_prepare_enable(i2s->hclk); 777 if (ret) { 778 dev_err(i2s->dev, "hclock enable failed %d\n", ret); 779 return ret; 780 } 781 782 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk"); 783 if (IS_ERR(i2s->mclk)) { 784 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n"); 785 ret = PTR_ERR(i2s->mclk); 786 goto err_clk; 787 } 788 789 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 790 if (IS_ERR(regs)) { 791 ret = PTR_ERR(regs); 792 goto err_clk; 793 } 794 795 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 796 &rockchip_i2s_regmap_config); 797 if (IS_ERR(i2s->regmap)) { 798 dev_err(&pdev->dev, 799 "Failed to initialise managed register map\n"); 800 ret = PTR_ERR(i2s->regmap); 801 goto err_clk; 802 } 803 804 i2s->bclk_ratio = 64; 805 i2s->pinctrl = devm_pinctrl_get(&pdev->dev); 806 if (!IS_ERR(i2s->pinctrl)) { 807 i2s->bclk_on = pinctrl_lookup_state(i2s->pinctrl, "bclk_on"); 808 if (!IS_ERR_OR_NULL(i2s->bclk_on)) { 809 i2s->bclk_off = pinctrl_lookup_state(i2s->pinctrl, "bclk_off"); 810 if (IS_ERR_OR_NULL(i2s->bclk_off)) { 811 dev_err(&pdev->dev, "failed to find i2s bclk_off\n"); 812 ret = -EINVAL; 813 goto err_clk; 814 } 815 } 816 } else { 817 dev_dbg(&pdev->dev, "failed to find i2s pinctrl\n"); 818 } 819 820 i2s_pinctrl_select_bclk_off(i2s); 821 822 dev_set_drvdata(&pdev->dev, i2s); 823 824 pm_runtime_enable(&pdev->dev); 825 if (!pm_runtime_enabled(&pdev->dev)) { 826 ret = i2s_runtime_resume(&pdev->dev); 827 if (ret) 828 goto err_pm_disable; 829 } 830 831 ret = rockchip_i2s_init_dai(i2s, res, &dai); 832 if (ret) 833 goto err_pm_disable; 834 835 ret = devm_snd_soc_register_component(&pdev->dev, 836 &rockchip_i2s_component, 837 dai, 1); 838 839 if (ret) { 840 dev_err(&pdev->dev, "Could not register DAI\n"); 841 goto err_suspend; 842 } 843 844 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 845 if (ret) { 846 dev_err(&pdev->dev, "Could not register PCM\n"); 847 goto err_suspend; 848 } 849 850 return 0; 851 852 err_suspend: 853 if (!pm_runtime_status_suspended(&pdev->dev)) 854 i2s_runtime_suspend(&pdev->dev); 855 err_pm_disable: 856 pm_runtime_disable(&pdev->dev); 857 err_clk: 858 clk_disable_unprepare(i2s->hclk); 859 return ret; 860 } 861 862 static int rockchip_i2s_remove(struct platform_device *pdev) 863 { 864 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev); 865 866 pm_runtime_disable(&pdev->dev); 867 if (!pm_runtime_status_suspended(&pdev->dev)) 868 i2s_runtime_suspend(&pdev->dev); 869 870 clk_disable_unprepare(i2s->hclk); 871 872 return 0; 873 } 874 875 static const struct dev_pm_ops rockchip_i2s_pm_ops = { 876 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume, 877 NULL) 878 }; 879 880 static struct platform_driver rockchip_i2s_driver = { 881 .probe = rockchip_i2s_probe, 882 .remove = rockchip_i2s_remove, 883 .driver = { 884 .name = DRV_NAME, 885 .of_match_table = of_match_ptr(rockchip_i2s_match), 886 .pm = &rockchip_i2s_pm_ops, 887 }, 888 }; 889 module_platform_driver(rockchip_i2s_driver); 890 891 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface"); 892 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>"); 893 MODULE_LICENSE("GPL v2"); 894 MODULE_ALIAS("platform:" DRV_NAME); 895 MODULE_DEVICE_TABLE(of, rockchip_i2s_match); 896