1 /* sound/soc/rockchip/rockchip_i2s.c
2  *
3  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
4  *
5  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6  * Author: Jianqun <jay.xu@rock-chips.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/of_gpio.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <sound/pcm_params.h>
20 #include <sound/dmaengine_pcm.h>
21 
22 #include "rockchip_i2s.h"
23 
24 #define DRV_NAME "rockchip-i2s"
25 
26 struct rk_i2s_dev {
27 	struct device *dev;
28 
29 	struct clk *hclk;
30 	struct clk *mclk;
31 
32 	struct snd_dmaengine_dai_dma_data capture_dma_data;
33 	struct snd_dmaengine_dai_dma_data playback_dma_data;
34 
35 	struct regmap *regmap;
36 
37 /*
38  * Used to indicate the tx/rx status.
39  * I2S controller hopes to start the tx and rx together,
40  * also to stop them when they are both try to stop.
41 */
42 	bool tx_start;
43 	bool rx_start;
44 };
45 
46 static int i2s_runtime_suspend(struct device *dev)
47 {
48 	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
49 
50 	clk_disable_unprepare(i2s->mclk);
51 
52 	return 0;
53 }
54 
55 static int i2s_runtime_resume(struct device *dev)
56 {
57 	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
58 	int ret;
59 
60 	ret = clk_prepare_enable(i2s->mclk);
61 	if (ret) {
62 		dev_err(i2s->dev, "clock enable failed %d\n", ret);
63 		return ret;
64 	}
65 
66 	return 0;
67 }
68 
69 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
70 {
71 	return snd_soc_dai_get_drvdata(dai);
72 }
73 
74 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
75 {
76 	unsigned int val = 0;
77 	int retry = 10;
78 
79 	if (on) {
80 		regmap_update_bits(i2s->regmap, I2S_DMACR,
81 				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
82 
83 		regmap_update_bits(i2s->regmap, I2S_XFER,
84 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
85 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);
86 
87 		i2s->tx_start = true;
88 	} else {
89 		i2s->tx_start = false;
90 
91 		regmap_update_bits(i2s->regmap, I2S_DMACR,
92 				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
93 
94 		if (!i2s->rx_start) {
95 			regmap_update_bits(i2s->regmap, I2S_XFER,
96 					   I2S_XFER_TXS_START |
97 					   I2S_XFER_RXS_START,
98 					   I2S_XFER_TXS_STOP |
99 					   I2S_XFER_RXS_STOP);
100 
101 			regmap_update_bits(i2s->regmap, I2S_CLR,
102 					   I2S_CLR_TXC | I2S_CLR_RXC,
103 					   I2S_CLR_TXC | I2S_CLR_RXC);
104 
105 			regmap_read(i2s->regmap, I2S_CLR, &val);
106 
107 			/* Should wait for clear operation to finish */
108 			while (val) {
109 				regmap_read(i2s->regmap, I2S_CLR, &val);
110 				retry--;
111 				if (!retry) {
112 					dev_warn(i2s->dev, "fail to clear\n");
113 					break;
114 				}
115 			}
116 		}
117 	}
118 }
119 
120 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
121 {
122 	unsigned int val = 0;
123 	int retry = 10;
124 
125 	if (on) {
126 		regmap_update_bits(i2s->regmap, I2S_DMACR,
127 				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
128 
129 		regmap_update_bits(i2s->regmap, I2S_XFER,
130 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
131 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);
132 
133 		i2s->rx_start = true;
134 	} else {
135 		i2s->rx_start = false;
136 
137 		regmap_update_bits(i2s->regmap, I2S_DMACR,
138 				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
139 
140 		if (!i2s->tx_start) {
141 			regmap_update_bits(i2s->regmap, I2S_XFER,
142 					   I2S_XFER_TXS_START |
143 					   I2S_XFER_RXS_START,
144 					   I2S_XFER_TXS_STOP |
145 					   I2S_XFER_RXS_STOP);
146 
147 			regmap_update_bits(i2s->regmap, I2S_CLR,
148 					   I2S_CLR_TXC | I2S_CLR_RXC,
149 					   I2S_CLR_TXC | I2S_CLR_RXC);
150 
151 			regmap_read(i2s->regmap, I2S_CLR, &val);
152 
153 			/* Should wait for clear operation to finish */
154 			while (val) {
155 				regmap_read(i2s->regmap, I2S_CLR, &val);
156 				retry--;
157 				if (!retry) {
158 					dev_warn(i2s->dev, "fail to clear\n");
159 					break;
160 				}
161 			}
162 		}
163 	}
164 }
165 
166 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
167 				unsigned int fmt)
168 {
169 	struct rk_i2s_dev *i2s = to_info(cpu_dai);
170 	unsigned int mask = 0, val = 0;
171 
172 	mask = I2S_CKR_MSS_MASK;
173 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
174 	case SND_SOC_DAIFMT_CBS_CFS:
175 		/* Set source clock in Master mode */
176 		val = I2S_CKR_MSS_MASTER;
177 		break;
178 	case SND_SOC_DAIFMT_CBM_CFM:
179 		val = I2S_CKR_MSS_SLAVE;
180 		break;
181 	default:
182 		return -EINVAL;
183 	}
184 
185 	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
186 
187 	mask = I2S_TXCR_IBM_MASK;
188 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
189 	case SND_SOC_DAIFMT_RIGHT_J:
190 		val = I2S_TXCR_IBM_RSJM;
191 		break;
192 	case SND_SOC_DAIFMT_LEFT_J:
193 		val = I2S_TXCR_IBM_LSJM;
194 		break;
195 	case SND_SOC_DAIFMT_I2S:
196 		val = I2S_TXCR_IBM_NORMAL;
197 		break;
198 	default:
199 		return -EINVAL;
200 	}
201 
202 	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
203 
204 	mask = I2S_RXCR_IBM_MASK;
205 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
206 	case SND_SOC_DAIFMT_RIGHT_J:
207 		val = I2S_RXCR_IBM_RSJM;
208 		break;
209 	case SND_SOC_DAIFMT_LEFT_J:
210 		val = I2S_RXCR_IBM_LSJM;
211 		break;
212 	case SND_SOC_DAIFMT_I2S:
213 		val = I2S_RXCR_IBM_NORMAL;
214 		break;
215 	default:
216 		return -EINVAL;
217 	}
218 
219 	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
220 
221 	return 0;
222 }
223 
224 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
225 				  struct snd_pcm_hw_params *params,
226 				  struct snd_soc_dai *dai)
227 {
228 	struct rk_i2s_dev *i2s = to_info(dai);
229 	unsigned int val = 0;
230 
231 	switch (params_format(params)) {
232 	case SNDRV_PCM_FORMAT_S8:
233 		val |= I2S_TXCR_VDW(8);
234 		break;
235 	case SNDRV_PCM_FORMAT_S16_LE:
236 		val |= I2S_TXCR_VDW(16);
237 		break;
238 	case SNDRV_PCM_FORMAT_S20_3LE:
239 		val |= I2S_TXCR_VDW(20);
240 		break;
241 	case SNDRV_PCM_FORMAT_S24_LE:
242 		val |= I2S_TXCR_VDW(24);
243 		break;
244 	default:
245 		return -EINVAL;
246 	}
247 
248 	regmap_update_bits(i2s->regmap, I2S_TXCR, I2S_TXCR_VDW_MASK, val);
249 	regmap_update_bits(i2s->regmap, I2S_RXCR, I2S_RXCR_VDW_MASK, val);
250 
251 	return 0;
252 }
253 
254 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
255 				int cmd, struct snd_soc_dai *dai)
256 {
257 	struct rk_i2s_dev *i2s = to_info(dai);
258 	int ret = 0;
259 
260 	switch (cmd) {
261 	case SNDRV_PCM_TRIGGER_START:
262 	case SNDRV_PCM_TRIGGER_RESUME:
263 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
264 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
265 			rockchip_snd_rxctrl(i2s, 1);
266 		else
267 			rockchip_snd_txctrl(i2s, 1);
268 		break;
269 	case SNDRV_PCM_TRIGGER_SUSPEND:
270 	case SNDRV_PCM_TRIGGER_STOP:
271 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
272 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
273 			rockchip_snd_rxctrl(i2s, 0);
274 		else
275 			rockchip_snd_txctrl(i2s, 0);
276 		break;
277 	default:
278 		ret = -EINVAL;
279 		break;
280 	}
281 
282 	return ret;
283 }
284 
285 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
286 				   unsigned int freq, int dir)
287 {
288 	struct rk_i2s_dev *i2s = to_info(cpu_dai);
289 	int ret;
290 
291 	ret = clk_set_rate(i2s->mclk, freq);
292 	if (ret)
293 		dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
294 
295 	return ret;
296 }
297 
298 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
299 {
300 	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
301 
302 	dai->capture_dma_data = &i2s->capture_dma_data;
303 	dai->playback_dma_data = &i2s->playback_dma_data;
304 
305 	return 0;
306 }
307 
308 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
309 	.hw_params = rockchip_i2s_hw_params,
310 	.set_sysclk = rockchip_i2s_set_sysclk,
311 	.set_fmt = rockchip_i2s_set_fmt,
312 	.trigger = rockchip_i2s_trigger,
313 };
314 
315 static struct snd_soc_dai_driver rockchip_i2s_dai = {
316 	.probe = rockchip_i2s_dai_probe,
317 	.playback = {
318 		.stream_name = "Playback",
319 		.channels_min = 2,
320 		.channels_max = 8,
321 		.rates = SNDRV_PCM_RATE_8000_192000,
322 		.formats = (SNDRV_PCM_FMTBIT_S8 |
323 			    SNDRV_PCM_FMTBIT_S16_LE |
324 			    SNDRV_PCM_FMTBIT_S20_3LE |
325 			    SNDRV_PCM_FMTBIT_S24_LE),
326 	},
327 	.capture = {
328 		.stream_name = "Capture",
329 		.channels_min = 2,
330 		.channels_max = 2,
331 		.rates = SNDRV_PCM_RATE_8000_192000,
332 		.formats = (SNDRV_PCM_FMTBIT_S8 |
333 			    SNDRV_PCM_FMTBIT_S16_LE |
334 			    SNDRV_PCM_FMTBIT_S20_3LE |
335 			    SNDRV_PCM_FMTBIT_S24_LE),
336 	},
337 	.ops = &rockchip_i2s_dai_ops,
338 	.symmetric_rates = 1,
339 };
340 
341 static const struct snd_soc_component_driver rockchip_i2s_component = {
342 	.name = DRV_NAME,
343 };
344 
345 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
346 {
347 	switch (reg) {
348 	case I2S_TXCR:
349 	case I2S_RXCR:
350 	case I2S_CKR:
351 	case I2S_DMACR:
352 	case I2S_INTCR:
353 	case I2S_XFER:
354 	case I2S_CLR:
355 	case I2S_TXDR:
356 		return true;
357 	default:
358 		return false;
359 	}
360 }
361 
362 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
363 {
364 	switch (reg) {
365 	case I2S_TXCR:
366 	case I2S_RXCR:
367 	case I2S_CKR:
368 	case I2S_DMACR:
369 	case I2S_INTCR:
370 	case I2S_XFER:
371 	case I2S_CLR:
372 	case I2S_RXDR:
373 	case I2S_FIFOLR:
374 	case I2S_INTSR:
375 		return true;
376 	default:
377 		return false;
378 	}
379 }
380 
381 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
382 {
383 	switch (reg) {
384 	case I2S_INTSR:
385 	case I2S_CLR:
386 		return true;
387 	default:
388 		return false;
389 	}
390 }
391 
392 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
393 {
394 	switch (reg) {
395 	default:
396 		return false;
397 	}
398 }
399 
400 static const struct regmap_config rockchip_i2s_regmap_config = {
401 	.reg_bits = 32,
402 	.reg_stride = 4,
403 	.val_bits = 32,
404 	.max_register = I2S_RXDR,
405 	.writeable_reg = rockchip_i2s_wr_reg,
406 	.readable_reg = rockchip_i2s_rd_reg,
407 	.volatile_reg = rockchip_i2s_volatile_reg,
408 	.precious_reg = rockchip_i2s_precious_reg,
409 	.cache_type = REGCACHE_FLAT,
410 };
411 
412 static int rockchip_i2s_probe(struct platform_device *pdev)
413 {
414 	struct rk_i2s_dev *i2s;
415 	struct resource *res;
416 	void __iomem *regs;
417 	int ret;
418 
419 	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
420 	if (!i2s) {
421 		dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
422 		return -ENOMEM;
423 	}
424 
425 	/* try to prepare related clocks */
426 	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
427 	if (IS_ERR(i2s->hclk)) {
428 		dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
429 		return PTR_ERR(i2s->hclk);
430 	}
431 	ret = clk_prepare_enable(i2s->hclk);
432 	if (ret) {
433 		dev_err(i2s->dev, "hclock enable failed %d\n", ret);
434 		return ret;
435 	}
436 
437 	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
438 	if (IS_ERR(i2s->mclk)) {
439 		dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
440 		return PTR_ERR(i2s->mclk);
441 	}
442 
443 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
444 	regs = devm_ioremap_resource(&pdev->dev, res);
445 	if (IS_ERR(regs))
446 		return PTR_ERR(regs);
447 
448 	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
449 					    &rockchip_i2s_regmap_config);
450 	if (IS_ERR(i2s->regmap)) {
451 		dev_err(&pdev->dev,
452 			"Failed to initialise managed register map\n");
453 		return PTR_ERR(i2s->regmap);
454 	}
455 
456 	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
457 	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
458 	i2s->playback_dma_data.maxburst = 4;
459 
460 	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
461 	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
462 	i2s->capture_dma_data.maxburst = 4;
463 
464 	i2s->dev = &pdev->dev;
465 	dev_set_drvdata(&pdev->dev, i2s);
466 
467 	pm_runtime_enable(&pdev->dev);
468 	if (!pm_runtime_enabled(&pdev->dev)) {
469 		ret = i2s_runtime_resume(&pdev->dev);
470 		if (ret)
471 			goto err_pm_disable;
472 	}
473 
474 	ret = devm_snd_soc_register_component(&pdev->dev,
475 					      &rockchip_i2s_component,
476 					      &rockchip_i2s_dai, 1);
477 	if (ret) {
478 		dev_err(&pdev->dev, "Could not register DAI\n");
479 		goto err_suspend;
480 	}
481 
482 	ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
483 	if (ret) {
484 		dev_err(&pdev->dev, "Could not register PCM\n");
485 		goto err_pcm_register;
486 	}
487 
488 	return 0;
489 
490 err_pcm_register:
491 	snd_dmaengine_pcm_unregister(&pdev->dev);
492 err_suspend:
493 	if (!pm_runtime_status_suspended(&pdev->dev))
494 		i2s_runtime_suspend(&pdev->dev);
495 err_pm_disable:
496 	pm_runtime_disable(&pdev->dev);
497 
498 	return ret;
499 }
500 
501 static int rockchip_i2s_remove(struct platform_device *pdev)
502 {
503 	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
504 
505 	pm_runtime_disable(&pdev->dev);
506 	if (!pm_runtime_status_suspended(&pdev->dev))
507 		i2s_runtime_suspend(&pdev->dev);
508 
509 	clk_disable_unprepare(i2s->mclk);
510 	clk_disable_unprepare(i2s->hclk);
511 	snd_dmaengine_pcm_unregister(&pdev->dev);
512 	snd_soc_unregister_component(&pdev->dev);
513 
514 	return 0;
515 }
516 
517 static const struct of_device_id rockchip_i2s_match[] = {
518 	{ .compatible = "rockchip,rk3066-i2s", },
519 	{},
520 };
521 
522 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
523 	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
524 			   NULL)
525 };
526 
527 static struct platform_driver rockchip_i2s_driver = {
528 	.probe = rockchip_i2s_probe,
529 	.remove = rockchip_i2s_remove,
530 	.driver = {
531 		.name = DRV_NAME,
532 		.of_match_table = of_match_ptr(rockchip_i2s_match),
533 		.pm = &rockchip_i2s_pm_ops,
534 	},
535 };
536 module_platform_driver(rockchip_i2s_driver);
537 
538 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
539 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
540 MODULE_LICENSE("GPL v2");
541 MODULE_ALIAS("platform:" DRV_NAME);
542 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
543