1 /* sound/soc/rockchip/rockchip_i2s.c 2 * 3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver 4 * 5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd. 6 * Author: Jianqun <jay.xu@rock-chips.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/delay.h> 15 #include <linux/of_gpio.h> 16 #include <linux/clk.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <sound/pcm_params.h> 20 #include <sound/dmaengine_pcm.h> 21 22 #include "rockchip_i2s.h" 23 24 #define DRV_NAME "rockchip-i2s" 25 26 struct rk_i2s_dev { 27 struct device *dev; 28 29 struct clk *hclk; 30 struct clk *mclk; 31 32 struct snd_dmaengine_dai_dma_data capture_dma_data; 33 struct snd_dmaengine_dai_dma_data playback_dma_data; 34 35 struct regmap *regmap; 36 37 /* 38 * Used to indicate the tx/rx status. 39 * I2S controller hopes to start the tx and rx together, 40 * also to stop them when they are both try to stop. 41 */ 42 bool tx_start; 43 bool rx_start; 44 }; 45 46 static int i2s_runtime_suspend(struct device *dev) 47 { 48 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 49 50 clk_disable_unprepare(i2s->mclk); 51 52 return 0; 53 } 54 55 static int i2s_runtime_resume(struct device *dev) 56 { 57 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 58 int ret; 59 60 ret = clk_prepare_enable(i2s->mclk); 61 if (ret) { 62 dev_err(i2s->dev, "clock enable failed %d\n", ret); 63 return ret; 64 } 65 66 return 0; 67 } 68 69 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai) 70 { 71 return snd_soc_dai_get_drvdata(dai); 72 } 73 74 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) 75 { 76 unsigned int val = 0; 77 int retry = 10; 78 79 if (on) { 80 regmap_update_bits(i2s->regmap, I2S_DMACR, 81 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE); 82 83 regmap_update_bits(i2s->regmap, I2S_XFER, 84 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 85 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 86 87 i2s->tx_start = true; 88 } else { 89 i2s->tx_start = false; 90 91 regmap_update_bits(i2s->regmap, I2S_DMACR, 92 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE); 93 94 if (!i2s->rx_start) { 95 regmap_update_bits(i2s->regmap, I2S_XFER, 96 I2S_XFER_TXS_START | 97 I2S_XFER_RXS_START, 98 I2S_XFER_TXS_STOP | 99 I2S_XFER_RXS_STOP); 100 101 regmap_update_bits(i2s->regmap, I2S_CLR, 102 I2S_CLR_TXC | I2S_CLR_RXC, 103 I2S_CLR_TXC | I2S_CLR_RXC); 104 105 regmap_read(i2s->regmap, I2S_CLR, &val); 106 107 /* Should wait for clear operation to finish */ 108 while (val) { 109 regmap_read(i2s->regmap, I2S_CLR, &val); 110 retry--; 111 if (!retry) 112 dev_warn(i2s->dev, "fail to clear\n"); 113 } 114 } 115 } 116 } 117 118 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) 119 { 120 unsigned int val = 0; 121 int retry = 10; 122 123 if (on) { 124 regmap_update_bits(i2s->regmap, I2S_DMACR, 125 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE); 126 127 regmap_update_bits(i2s->regmap, I2S_XFER, 128 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 129 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 130 131 i2s->rx_start = true; 132 } else { 133 i2s->rx_start = false; 134 135 regmap_update_bits(i2s->regmap, I2S_DMACR, 136 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE); 137 138 if (!i2s->tx_start) { 139 regmap_update_bits(i2s->regmap, I2S_XFER, 140 I2S_XFER_TXS_START | 141 I2S_XFER_RXS_START, 142 I2S_XFER_TXS_STOP | 143 I2S_XFER_RXS_STOP); 144 145 regmap_update_bits(i2s->regmap, I2S_CLR, 146 I2S_CLR_TXC | I2S_CLR_RXC, 147 I2S_CLR_TXC | I2S_CLR_RXC); 148 149 regmap_read(i2s->regmap, I2S_CLR, &val); 150 151 /* Should wait for clear operation to finish */ 152 while (val) { 153 regmap_read(i2s->regmap, I2S_CLR, &val); 154 retry--; 155 if (!retry) 156 dev_warn(i2s->dev, "fail to clear\n"); 157 } 158 } 159 } 160 } 161 162 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, 163 unsigned int fmt) 164 { 165 struct rk_i2s_dev *i2s = to_info(cpu_dai); 166 unsigned int mask = 0, val = 0; 167 168 mask = I2S_CKR_MSS_SLAVE; 169 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 170 case SND_SOC_DAIFMT_CBS_CFS: 171 val = I2S_CKR_MSS_SLAVE; 172 break; 173 case SND_SOC_DAIFMT_CBM_CFM: 174 val = I2S_CKR_MSS_MASTER; 175 break; 176 default: 177 return -EINVAL; 178 } 179 180 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 181 182 mask = I2S_TXCR_IBM_MASK; 183 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 184 case SND_SOC_DAIFMT_RIGHT_J: 185 val = I2S_TXCR_IBM_RSJM; 186 break; 187 case SND_SOC_DAIFMT_LEFT_J: 188 val = I2S_TXCR_IBM_LSJM; 189 break; 190 case SND_SOC_DAIFMT_I2S: 191 val = I2S_TXCR_IBM_NORMAL; 192 break; 193 default: 194 return -EINVAL; 195 } 196 197 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); 198 199 mask = I2S_RXCR_IBM_MASK; 200 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 201 case SND_SOC_DAIFMT_RIGHT_J: 202 val = I2S_RXCR_IBM_RSJM; 203 break; 204 case SND_SOC_DAIFMT_LEFT_J: 205 val = I2S_RXCR_IBM_LSJM; 206 break; 207 case SND_SOC_DAIFMT_I2S: 208 val = I2S_RXCR_IBM_NORMAL; 209 break; 210 default: 211 return -EINVAL; 212 } 213 214 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val); 215 216 return 0; 217 } 218 219 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, 220 struct snd_pcm_hw_params *params, 221 struct snd_soc_dai *dai) 222 { 223 struct rk_i2s_dev *i2s = to_info(dai); 224 unsigned int val = 0; 225 226 switch (params_format(params)) { 227 case SNDRV_PCM_FORMAT_S8: 228 val |= I2S_TXCR_VDW(8); 229 break; 230 case SNDRV_PCM_FORMAT_S16_LE: 231 val |= I2S_TXCR_VDW(16); 232 break; 233 case SNDRV_PCM_FORMAT_S20_3LE: 234 val |= I2S_TXCR_VDW(20); 235 break; 236 case SNDRV_PCM_FORMAT_S24_LE: 237 val |= I2S_TXCR_VDW(24); 238 break; 239 default: 240 return -EINVAL; 241 } 242 243 regmap_update_bits(i2s->regmap, I2S_TXCR, I2S_TXCR_VDW_MASK, val); 244 regmap_update_bits(i2s->regmap, I2S_RXCR, I2S_RXCR_VDW_MASK, val); 245 246 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 247 dai->playback_dma_data = &i2s->playback_dma_data; 248 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, 249 I2S_DMACR_TDL(1) | I2S_DMACR_TDE_ENABLE); 250 } else { 251 dai->capture_dma_data = &i2s->capture_dma_data; 252 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, 253 I2S_DMACR_RDL(1) | I2S_DMACR_RDE_ENABLE); 254 } 255 256 return 0; 257 } 258 259 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, 260 int cmd, struct snd_soc_dai *dai) 261 { 262 struct rk_i2s_dev *i2s = to_info(dai); 263 int ret = 0; 264 265 switch (cmd) { 266 case SNDRV_PCM_TRIGGER_START: 267 case SNDRV_PCM_TRIGGER_RESUME: 268 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 269 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 270 rockchip_snd_rxctrl(i2s, 1); 271 else 272 rockchip_snd_txctrl(i2s, 1); 273 break; 274 case SNDRV_PCM_TRIGGER_SUSPEND: 275 case SNDRV_PCM_TRIGGER_STOP: 276 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 277 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 278 rockchip_snd_rxctrl(i2s, 0); 279 else 280 rockchip_snd_txctrl(i2s, 0); 281 break; 282 default: 283 ret = -EINVAL; 284 break; 285 } 286 287 return ret; 288 } 289 290 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, 291 unsigned int freq, int dir) 292 { 293 struct rk_i2s_dev *i2s = to_info(cpu_dai); 294 int ret; 295 296 ret = clk_set_rate(i2s->mclk, freq); 297 if (ret) 298 dev_err(i2s->dev, "Fail to set mclk %d\n", ret); 299 300 return ret; 301 } 302 303 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = { 304 .hw_params = rockchip_i2s_hw_params, 305 .set_sysclk = rockchip_i2s_set_sysclk, 306 .set_fmt = rockchip_i2s_set_fmt, 307 .trigger = rockchip_i2s_trigger, 308 }; 309 310 static struct snd_soc_dai_driver rockchip_i2s_dai = { 311 .playback = { 312 .channels_min = 2, 313 .channels_max = 8, 314 .rates = SNDRV_PCM_RATE_8000_192000, 315 .formats = (SNDRV_PCM_FMTBIT_S8 | 316 SNDRV_PCM_FMTBIT_S16_LE | 317 SNDRV_PCM_FMTBIT_S20_3LE | 318 SNDRV_PCM_FMTBIT_S24_LE), 319 }, 320 .capture = { 321 .channels_min = 2, 322 .channels_max = 2, 323 .rates = SNDRV_PCM_RATE_8000_192000, 324 .formats = (SNDRV_PCM_FMTBIT_S8 | 325 SNDRV_PCM_FMTBIT_S16_LE | 326 SNDRV_PCM_FMTBIT_S20_3LE | 327 SNDRV_PCM_FMTBIT_S24_LE), 328 }, 329 .ops = &rockchip_i2s_dai_ops, 330 }; 331 332 static const struct snd_soc_component_driver rockchip_i2s_component = { 333 .name = DRV_NAME, 334 }; 335 336 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg) 337 { 338 switch (reg) { 339 case I2S_TXCR: 340 case I2S_RXCR: 341 case I2S_CKR: 342 case I2S_DMACR: 343 case I2S_INTCR: 344 case I2S_XFER: 345 case I2S_CLR: 346 case I2S_TXDR: 347 return true; 348 default: 349 return false; 350 } 351 } 352 353 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg) 354 { 355 switch (reg) { 356 case I2S_TXCR: 357 case I2S_RXCR: 358 case I2S_CKR: 359 case I2S_DMACR: 360 case I2S_INTCR: 361 case I2S_XFER: 362 case I2S_CLR: 363 case I2S_RXDR: 364 return true; 365 default: 366 return false; 367 } 368 } 369 370 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg) 371 { 372 switch (reg) { 373 case I2S_FIFOLR: 374 case I2S_INTSR: 375 return true; 376 default: 377 return false; 378 } 379 } 380 381 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg) 382 { 383 switch (reg) { 384 case I2S_FIFOLR: 385 return true; 386 default: 387 return false; 388 } 389 } 390 391 static const struct regmap_config rockchip_i2s_regmap_config = { 392 .reg_bits = 32, 393 .reg_stride = 4, 394 .val_bits = 32, 395 .max_register = I2S_RXDR, 396 .writeable_reg = rockchip_i2s_wr_reg, 397 .readable_reg = rockchip_i2s_rd_reg, 398 .volatile_reg = rockchip_i2s_volatile_reg, 399 .precious_reg = rockchip_i2s_precious_reg, 400 .cache_type = REGCACHE_FLAT, 401 }; 402 403 static int rockchip_i2s_probe(struct platform_device *pdev) 404 { 405 struct rk_i2s_dev *i2s; 406 struct resource *res; 407 void __iomem *regs; 408 int ret; 409 410 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 411 if (!i2s) { 412 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n"); 413 return -ENOMEM; 414 } 415 416 /* try to prepare related clocks */ 417 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk"); 418 if (IS_ERR(i2s->hclk)) { 419 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n"); 420 return PTR_ERR(i2s->hclk); 421 } 422 423 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk"); 424 if (IS_ERR(i2s->mclk)) { 425 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n"); 426 return PTR_ERR(i2s->mclk); 427 } 428 429 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 430 regs = devm_ioremap_resource(&pdev->dev, res); 431 if (IS_ERR(regs)) 432 return PTR_ERR(regs); 433 434 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 435 &rockchip_i2s_regmap_config); 436 if (IS_ERR(i2s->regmap)) { 437 dev_err(&pdev->dev, 438 "Failed to initialise managed register map\n"); 439 return PTR_ERR(i2s->regmap); 440 } 441 442 i2s->playback_dma_data.addr = res->start + I2S_TXDR; 443 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 444 i2s->playback_dma_data.maxburst = 16; 445 446 i2s->capture_dma_data.addr = res->start + I2S_RXDR; 447 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 448 i2s->capture_dma_data.maxburst = 16; 449 450 i2s->dev = &pdev->dev; 451 dev_set_drvdata(&pdev->dev, i2s); 452 453 pm_runtime_enable(&pdev->dev); 454 if (!pm_runtime_enabled(&pdev->dev)) { 455 ret = i2s_runtime_resume(&pdev->dev); 456 if (ret) 457 goto err_pm_disable; 458 } 459 460 ret = devm_snd_soc_register_component(&pdev->dev, 461 &rockchip_i2s_component, 462 &rockchip_i2s_dai, 1); 463 if (ret) { 464 dev_err(&pdev->dev, "Could not register DAI\n"); 465 goto err_suspend; 466 } 467 468 ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 469 if (ret) { 470 dev_err(&pdev->dev, "Could not register PCM\n"); 471 goto err_pcm_register; 472 } 473 474 return 0; 475 476 err_pcm_register: 477 snd_dmaengine_pcm_unregister(&pdev->dev); 478 err_suspend: 479 if (!pm_runtime_status_suspended(&pdev->dev)) 480 i2s_runtime_suspend(&pdev->dev); 481 err_pm_disable: 482 pm_runtime_disable(&pdev->dev); 483 484 return ret; 485 } 486 487 static int rockchip_i2s_remove(struct platform_device *pdev) 488 { 489 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev); 490 491 pm_runtime_disable(&pdev->dev); 492 if (!pm_runtime_status_suspended(&pdev->dev)) 493 i2s_runtime_suspend(&pdev->dev); 494 495 clk_disable_unprepare(i2s->mclk); 496 clk_disable_unprepare(i2s->hclk); 497 snd_dmaengine_pcm_unregister(&pdev->dev); 498 snd_soc_unregister_component(&pdev->dev); 499 500 return 0; 501 } 502 503 static const struct of_device_id rockchip_i2s_match[] = { 504 { .compatible = "rockchip,rk3066-i2s", }, 505 {}, 506 }; 507 508 static const struct dev_pm_ops rockchip_i2s_pm_ops = { 509 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume, 510 NULL) 511 }; 512 513 static struct platform_driver rockchip_i2s_driver = { 514 .probe = rockchip_i2s_probe, 515 .remove = rockchip_i2s_remove, 516 .driver = { 517 .name = DRV_NAME, 518 .owner = THIS_MODULE, 519 .of_match_table = of_match_ptr(rockchip_i2s_match), 520 .pm = &rockchip_i2s_pm_ops, 521 }, 522 }; 523 module_platform_driver(rockchip_i2s_driver); 524 525 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface"); 526 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>"); 527 MODULE_LICENSE("GPL v2"); 528 MODULE_ALIAS("platform:" DRV_NAME); 529 MODULE_DEVICE_TABLE(of, rockchip_i2s_match); 530