1 // SPDX-License-Identifier: GPL-2.0-only 2 /* sound/soc/rockchip/rockchip_i2s.c 3 * 4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver 5 * 6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd. 7 * Author: Jianqun <jay.xu@rock-chips.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/delay.h> 13 #include <linux/of_gpio.h> 14 #include <linux/of_device.h> 15 #include <linux/clk.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/spinlock.h> 20 #include <sound/pcm_params.h> 21 #include <sound/dmaengine_pcm.h> 22 23 #include "rockchip_i2s.h" 24 25 #define DRV_NAME "rockchip-i2s" 26 27 struct rk_i2s_pins { 28 u32 reg_offset; 29 u32 shift; 30 }; 31 32 struct rk_i2s_dev { 33 struct device *dev; 34 35 struct clk *hclk; 36 struct clk *mclk; 37 38 struct snd_dmaengine_dai_dma_data capture_dma_data; 39 struct snd_dmaengine_dai_dma_data playback_dma_data; 40 41 struct regmap *regmap; 42 struct regmap *grf; 43 44 bool has_capture; 45 bool has_playback; 46 47 /* 48 * Used to indicate the tx/rx status. 49 * I2S controller hopes to start the tx and rx together, 50 * also to stop them when they are both try to stop. 51 */ 52 bool tx_start; 53 bool rx_start; 54 bool is_master_mode; 55 const struct rk_i2s_pins *pins; 56 unsigned int bclk_ratio; 57 spinlock_t lock; /* tx/rx lock */ 58 struct pinctrl *pinctrl; 59 struct pinctrl_state *bclk_on; 60 struct pinctrl_state *bclk_off; 61 }; 62 63 static int i2s_pinctrl_select_bclk_on(struct rk_i2s_dev *i2s) 64 { 65 int ret = 0; 66 67 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_on)) 68 ret = pinctrl_select_state(i2s->pinctrl, 69 i2s->bclk_on); 70 71 if (ret) 72 dev_err(i2s->dev, "bclk enable failed %d\n", ret); 73 74 return ret; 75 } 76 77 static int i2s_pinctrl_select_bclk_off(struct rk_i2s_dev *i2s) 78 { 79 80 int ret = 0; 81 82 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_off)) 83 ret = pinctrl_select_state(i2s->pinctrl, 84 i2s->bclk_off); 85 86 if (ret) 87 dev_err(i2s->dev, "bclk disable failed %d\n", ret); 88 89 return ret; 90 } 91 92 static int i2s_runtime_suspend(struct device *dev) 93 { 94 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 95 96 regcache_cache_only(i2s->regmap, true); 97 clk_disable_unprepare(i2s->mclk); 98 99 return 0; 100 } 101 102 static int i2s_runtime_resume(struct device *dev) 103 { 104 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 105 int ret; 106 107 ret = clk_prepare_enable(i2s->mclk); 108 if (ret) { 109 dev_err(i2s->dev, "clock enable failed %d\n", ret); 110 return ret; 111 } 112 113 regcache_cache_only(i2s->regmap, false); 114 regcache_mark_dirty(i2s->regmap); 115 116 ret = regcache_sync(i2s->regmap); 117 if (ret) 118 clk_disable_unprepare(i2s->mclk); 119 120 return ret; 121 } 122 123 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai) 124 { 125 return snd_soc_dai_get_drvdata(dai); 126 } 127 128 static int rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) 129 { 130 unsigned int val = 0; 131 int retry = 10; 132 int ret = 0; 133 134 spin_lock(&i2s->lock); 135 if (on) { 136 ret = regmap_update_bits(i2s->regmap, I2S_DMACR, 137 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE); 138 if (ret < 0) 139 goto end; 140 141 ret = regmap_update_bits(i2s->regmap, I2S_XFER, 142 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 143 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 144 if (ret < 0) 145 goto end; 146 147 i2s->tx_start = true; 148 } else { 149 i2s->tx_start = false; 150 151 ret = regmap_update_bits(i2s->regmap, I2S_DMACR, 152 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE); 153 if (ret < 0) 154 goto end; 155 156 if (!i2s->rx_start) { 157 ret = regmap_update_bits(i2s->regmap, I2S_XFER, 158 I2S_XFER_TXS_START | 159 I2S_XFER_RXS_START, 160 I2S_XFER_TXS_STOP | 161 I2S_XFER_RXS_STOP); 162 if (ret < 0) 163 goto end; 164 165 udelay(150); 166 ret = regmap_update_bits(i2s->regmap, I2S_CLR, 167 I2S_CLR_TXC | I2S_CLR_RXC, 168 I2S_CLR_TXC | I2S_CLR_RXC); 169 if (ret < 0) 170 goto end; 171 172 regmap_read(i2s->regmap, I2S_CLR, &val); 173 174 /* Should wait for clear operation to finish */ 175 while (val) { 176 regmap_read(i2s->regmap, I2S_CLR, &val); 177 retry--; 178 if (!retry) { 179 dev_warn(i2s->dev, "fail to clear\n"); 180 break; 181 } 182 } 183 } 184 } 185 end: 186 spin_unlock(&i2s->lock); 187 if (ret < 0) 188 dev_err(i2s->dev, "lrclk update failed\n"); 189 190 return ret; 191 } 192 193 static int rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) 194 { 195 unsigned int val = 0; 196 int retry = 10; 197 int ret = 0; 198 199 spin_lock(&i2s->lock); 200 if (on) { 201 ret = regmap_update_bits(i2s->regmap, I2S_DMACR, 202 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE); 203 if (ret < 0) 204 goto end; 205 206 ret = regmap_update_bits(i2s->regmap, I2S_XFER, 207 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 208 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 209 if (ret < 0) 210 goto end; 211 212 i2s->rx_start = true; 213 } else { 214 i2s->rx_start = false; 215 216 ret = regmap_update_bits(i2s->regmap, I2S_DMACR, 217 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE); 218 if (ret < 0) 219 goto end; 220 221 if (!i2s->tx_start) { 222 ret = regmap_update_bits(i2s->regmap, I2S_XFER, 223 I2S_XFER_TXS_START | 224 I2S_XFER_RXS_START, 225 I2S_XFER_TXS_STOP | 226 I2S_XFER_RXS_STOP); 227 if (ret < 0) 228 goto end; 229 udelay(150); 230 ret = regmap_update_bits(i2s->regmap, I2S_CLR, 231 I2S_CLR_TXC | I2S_CLR_RXC, 232 I2S_CLR_TXC | I2S_CLR_RXC); 233 if (ret < 0) 234 goto end; 235 regmap_read(i2s->regmap, I2S_CLR, &val); 236 /* Should wait for clear operation to finish */ 237 while (val) { 238 regmap_read(i2s->regmap, I2S_CLR, &val); 239 retry--; 240 if (!retry) { 241 dev_warn(i2s->dev, "fail to clear\n"); 242 break; 243 } 244 } 245 } 246 } 247 end: 248 spin_unlock(&i2s->lock); 249 if (ret < 0) 250 dev_err(i2s->dev, "lrclk update failed\n"); 251 252 return ret; 253 } 254 255 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, 256 unsigned int fmt) 257 { 258 struct rk_i2s_dev *i2s = to_info(cpu_dai); 259 unsigned int mask = 0, val = 0; 260 int ret = 0; 261 262 pm_runtime_get_sync(cpu_dai->dev); 263 mask = I2S_CKR_MSS_MASK; 264 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 265 case SND_SOC_DAIFMT_CBS_CFS: 266 /* Set source clock in Master mode */ 267 val = I2S_CKR_MSS_MASTER; 268 i2s->is_master_mode = true; 269 break; 270 case SND_SOC_DAIFMT_CBM_CFM: 271 val = I2S_CKR_MSS_SLAVE; 272 i2s->is_master_mode = false; 273 break; 274 default: 275 ret = -EINVAL; 276 goto err_pm_put; 277 } 278 279 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 280 281 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK; 282 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 283 case SND_SOC_DAIFMT_NB_NF: 284 val = I2S_CKR_CKP_NORMAL | 285 I2S_CKR_TLP_NORMAL | 286 I2S_CKR_RLP_NORMAL; 287 break; 288 case SND_SOC_DAIFMT_NB_IF: 289 val = I2S_CKR_CKP_NORMAL | 290 I2S_CKR_TLP_INVERTED | 291 I2S_CKR_RLP_INVERTED; 292 break; 293 case SND_SOC_DAIFMT_IB_NF: 294 val = I2S_CKR_CKP_INVERTED | 295 I2S_CKR_TLP_NORMAL | 296 I2S_CKR_RLP_NORMAL; 297 break; 298 case SND_SOC_DAIFMT_IB_IF: 299 val = I2S_CKR_CKP_INVERTED | 300 I2S_CKR_TLP_INVERTED | 301 I2S_CKR_RLP_INVERTED; 302 break; 303 default: 304 ret = -EINVAL; 305 goto err_pm_put; 306 } 307 308 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 309 310 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; 311 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 312 case SND_SOC_DAIFMT_RIGHT_J: 313 val = I2S_TXCR_IBM_RSJM; 314 break; 315 case SND_SOC_DAIFMT_LEFT_J: 316 val = I2S_TXCR_IBM_LSJM; 317 break; 318 case SND_SOC_DAIFMT_I2S: 319 val = I2S_TXCR_IBM_NORMAL; 320 break; 321 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */ 322 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); 323 break; 324 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */ 325 val = I2S_TXCR_TFS_PCM; 326 break; 327 default: 328 ret = -EINVAL; 329 goto err_pm_put; 330 } 331 332 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); 333 334 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; 335 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 336 case SND_SOC_DAIFMT_RIGHT_J: 337 val = I2S_RXCR_IBM_RSJM; 338 break; 339 case SND_SOC_DAIFMT_LEFT_J: 340 val = I2S_RXCR_IBM_LSJM; 341 break; 342 case SND_SOC_DAIFMT_I2S: 343 val = I2S_RXCR_IBM_NORMAL; 344 break; 345 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */ 346 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); 347 break; 348 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */ 349 val = I2S_RXCR_TFS_PCM; 350 break; 351 default: 352 ret = -EINVAL; 353 goto err_pm_put; 354 } 355 356 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val); 357 358 err_pm_put: 359 pm_runtime_put(cpu_dai->dev); 360 361 return ret; 362 } 363 364 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, 365 struct snd_pcm_hw_params *params, 366 struct snd_soc_dai *dai) 367 { 368 struct rk_i2s_dev *i2s = to_info(dai); 369 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 370 unsigned int val = 0; 371 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck; 372 373 if (i2s->is_master_mode) { 374 mclk_rate = clk_get_rate(i2s->mclk); 375 bclk_rate = i2s->bclk_ratio * params_rate(params); 376 if (!bclk_rate) 377 return -EINVAL; 378 379 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); 380 div_lrck = bclk_rate / params_rate(params); 381 regmap_update_bits(i2s->regmap, I2S_CKR, 382 I2S_CKR_MDIV_MASK, 383 I2S_CKR_MDIV(div_bclk)); 384 385 regmap_update_bits(i2s->regmap, I2S_CKR, 386 I2S_CKR_TSD_MASK | 387 I2S_CKR_RSD_MASK, 388 I2S_CKR_TSD(div_lrck) | 389 I2S_CKR_RSD(div_lrck)); 390 } 391 392 switch (params_format(params)) { 393 case SNDRV_PCM_FORMAT_S8: 394 val |= I2S_TXCR_VDW(8); 395 break; 396 case SNDRV_PCM_FORMAT_S16_LE: 397 val |= I2S_TXCR_VDW(16); 398 break; 399 case SNDRV_PCM_FORMAT_S20_3LE: 400 val |= I2S_TXCR_VDW(20); 401 break; 402 case SNDRV_PCM_FORMAT_S24_LE: 403 val |= I2S_TXCR_VDW(24); 404 break; 405 case SNDRV_PCM_FORMAT_S32_LE: 406 val |= I2S_TXCR_VDW(32); 407 break; 408 default: 409 return -EINVAL; 410 } 411 412 switch (params_channels(params)) { 413 case 8: 414 val |= I2S_CHN_8; 415 break; 416 case 6: 417 val |= I2S_CHN_6; 418 break; 419 case 4: 420 val |= I2S_CHN_4; 421 break; 422 case 2: 423 val |= I2S_CHN_2; 424 break; 425 default: 426 dev_err(i2s->dev, "invalid channel: %d\n", 427 params_channels(params)); 428 return -EINVAL; 429 } 430 431 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 432 regmap_update_bits(i2s->regmap, I2S_RXCR, 433 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 434 val); 435 else 436 regmap_update_bits(i2s->regmap, I2S_TXCR, 437 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 438 val); 439 440 if (!IS_ERR(i2s->grf) && i2s->pins) { 441 regmap_read(i2s->regmap, I2S_TXCR, &val); 442 val &= I2S_TXCR_CSR_MASK; 443 444 switch (val) { 445 case I2S_CHN_4: 446 val = I2S_IO_4CH_OUT_6CH_IN; 447 break; 448 case I2S_CHN_6: 449 val = I2S_IO_6CH_OUT_4CH_IN; 450 break; 451 case I2S_CHN_8: 452 val = I2S_IO_8CH_OUT_2CH_IN; 453 break; 454 default: 455 val = I2S_IO_2CH_OUT_8CH_IN; 456 break; 457 } 458 459 val <<= i2s->pins->shift; 460 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16; 461 regmap_write(i2s->grf, i2s->pins->reg_offset, val); 462 } 463 464 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, 465 I2S_DMACR_TDL(16)); 466 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, 467 I2S_DMACR_RDL(16)); 468 469 val = I2S_CKR_TRCM_TXRX; 470 if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate) 471 val = I2S_CKR_TRCM_TXONLY; 472 473 regmap_update_bits(i2s->regmap, I2S_CKR, 474 I2S_CKR_TRCM_MASK, 475 val); 476 return 0; 477 } 478 479 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, 480 int cmd, struct snd_soc_dai *dai) 481 { 482 struct rk_i2s_dev *i2s = to_info(dai); 483 int ret = 0; 484 485 switch (cmd) { 486 case SNDRV_PCM_TRIGGER_START: 487 case SNDRV_PCM_TRIGGER_RESUME: 488 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 489 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 490 ret = rockchip_snd_rxctrl(i2s, 1); 491 else 492 ret = rockchip_snd_txctrl(i2s, 1); 493 /* Do not turn on bclk if lrclk open fails. */ 494 if (ret < 0) 495 return ret; 496 i2s_pinctrl_select_bclk_on(i2s); 497 break; 498 case SNDRV_PCM_TRIGGER_SUSPEND: 499 case SNDRV_PCM_TRIGGER_STOP: 500 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 501 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 502 if (!i2s->tx_start) 503 i2s_pinctrl_select_bclk_off(i2s); 504 ret = rockchip_snd_rxctrl(i2s, 0); 505 } else { 506 if (!i2s->rx_start) 507 i2s_pinctrl_select_bclk_off(i2s); 508 ret = rockchip_snd_txctrl(i2s, 0); 509 } 510 break; 511 default: 512 ret = -EINVAL; 513 break; 514 } 515 516 return ret; 517 } 518 519 static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai, 520 unsigned int ratio) 521 { 522 struct rk_i2s_dev *i2s = to_info(dai); 523 524 i2s->bclk_ratio = ratio; 525 526 return 0; 527 } 528 529 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, 530 unsigned int freq, int dir) 531 { 532 struct rk_i2s_dev *i2s = to_info(cpu_dai); 533 int ret; 534 535 if (freq == 0) 536 return 0; 537 538 ret = clk_set_rate(i2s->mclk, freq); 539 if (ret) 540 dev_err(i2s->dev, "Fail to set mclk %d\n", ret); 541 542 return ret; 543 } 544 545 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai) 546 { 547 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); 548 549 snd_soc_dai_init_dma_data(dai, 550 i2s->has_playback ? &i2s->playback_dma_data : NULL, 551 i2s->has_capture ? &i2s->capture_dma_data : NULL); 552 553 return 0; 554 } 555 556 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = { 557 .hw_params = rockchip_i2s_hw_params, 558 .set_bclk_ratio = rockchip_i2s_set_bclk_ratio, 559 .set_sysclk = rockchip_i2s_set_sysclk, 560 .set_fmt = rockchip_i2s_set_fmt, 561 .trigger = rockchip_i2s_trigger, 562 }; 563 564 static struct snd_soc_dai_driver rockchip_i2s_dai = { 565 .probe = rockchip_i2s_dai_probe, 566 .ops = &rockchip_i2s_dai_ops, 567 .symmetric_rate = 1, 568 }; 569 570 static const struct snd_soc_component_driver rockchip_i2s_component = { 571 .name = DRV_NAME, 572 }; 573 574 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg) 575 { 576 switch (reg) { 577 case I2S_TXCR: 578 case I2S_RXCR: 579 case I2S_CKR: 580 case I2S_DMACR: 581 case I2S_INTCR: 582 case I2S_XFER: 583 case I2S_CLR: 584 case I2S_TXDR: 585 return true; 586 default: 587 return false; 588 } 589 } 590 591 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg) 592 { 593 switch (reg) { 594 case I2S_TXCR: 595 case I2S_RXCR: 596 case I2S_CKR: 597 case I2S_DMACR: 598 case I2S_INTCR: 599 case I2S_XFER: 600 case I2S_CLR: 601 case I2S_TXDR: 602 case I2S_RXDR: 603 case I2S_FIFOLR: 604 case I2S_INTSR: 605 return true; 606 default: 607 return false; 608 } 609 } 610 611 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg) 612 { 613 switch (reg) { 614 case I2S_INTSR: 615 case I2S_CLR: 616 case I2S_FIFOLR: 617 case I2S_TXDR: 618 case I2S_RXDR: 619 return true; 620 default: 621 return false; 622 } 623 } 624 625 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg) 626 { 627 switch (reg) { 628 case I2S_RXDR: 629 return true; 630 default: 631 return false; 632 } 633 } 634 635 static const struct reg_default rockchip_i2s_reg_defaults[] = { 636 {0x00, 0x0000000f}, 637 {0x04, 0x0000000f}, 638 {0x08, 0x00071f1f}, 639 {0x10, 0x001f0000}, 640 {0x14, 0x01f00000}, 641 }; 642 643 static const struct regmap_config rockchip_i2s_regmap_config = { 644 .reg_bits = 32, 645 .reg_stride = 4, 646 .val_bits = 32, 647 .max_register = I2S_RXDR, 648 .reg_defaults = rockchip_i2s_reg_defaults, 649 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults), 650 .writeable_reg = rockchip_i2s_wr_reg, 651 .readable_reg = rockchip_i2s_rd_reg, 652 .volatile_reg = rockchip_i2s_volatile_reg, 653 .precious_reg = rockchip_i2s_precious_reg, 654 .cache_type = REGCACHE_FLAT, 655 }; 656 657 static const struct rk_i2s_pins rk3399_i2s_pins = { 658 .reg_offset = 0xe220, 659 .shift = 11, 660 }; 661 662 static const struct of_device_id rockchip_i2s_match[] __maybe_unused = { 663 { .compatible = "rockchip,px30-i2s", }, 664 { .compatible = "rockchip,rk1808-i2s", }, 665 { .compatible = "rockchip,rk3036-i2s", }, 666 { .compatible = "rockchip,rk3066-i2s", }, 667 { .compatible = "rockchip,rk3128-i2s", }, 668 { .compatible = "rockchip,rk3188-i2s", }, 669 { .compatible = "rockchip,rk3228-i2s", }, 670 { .compatible = "rockchip,rk3288-i2s", }, 671 { .compatible = "rockchip,rk3308-i2s", }, 672 { .compatible = "rockchip,rk3328-i2s", }, 673 { .compatible = "rockchip,rk3366-i2s", }, 674 { .compatible = "rockchip,rk3368-i2s", }, 675 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins }, 676 { .compatible = "rockchip,rv1126-i2s", }, 677 {}, 678 }; 679 680 static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res, 681 struct snd_soc_dai_driver **dp) 682 { 683 struct device_node *node = i2s->dev->of_node; 684 struct snd_soc_dai_driver *dai; 685 struct property *dma_names; 686 const char *dma_name; 687 unsigned int val; 688 689 of_property_for_each_string(node, "dma-names", dma_names, dma_name) { 690 if (!strcmp(dma_name, "tx")) 691 i2s->has_playback = true; 692 if (!strcmp(dma_name, "rx")) 693 i2s->has_capture = true; 694 } 695 696 dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai, 697 sizeof(*dai), GFP_KERNEL); 698 if (!dai) 699 return -ENOMEM; 700 701 if (i2s->has_playback) { 702 dai->playback.stream_name = "Playback"; 703 dai->playback.channels_min = 2; 704 dai->playback.channels_max = 8; 705 dai->playback.rates = SNDRV_PCM_RATE_8000_192000; 706 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 | 707 SNDRV_PCM_FMTBIT_S16_LE | 708 SNDRV_PCM_FMTBIT_S20_3LE | 709 SNDRV_PCM_FMTBIT_S24_LE | 710 SNDRV_PCM_FMTBIT_S32_LE; 711 712 i2s->playback_dma_data.addr = res->start + I2S_TXDR; 713 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 714 i2s->playback_dma_data.maxburst = 8; 715 716 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) { 717 if (val >= 2 && val <= 8) 718 dai->playback.channels_max = val; 719 } 720 } 721 722 if (i2s->has_capture) { 723 dai->capture.stream_name = "Capture"; 724 dai->capture.channels_min = 2; 725 dai->capture.channels_max = 8; 726 dai->capture.rates = SNDRV_PCM_RATE_8000_192000; 727 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 | 728 SNDRV_PCM_FMTBIT_S16_LE | 729 SNDRV_PCM_FMTBIT_S20_3LE | 730 SNDRV_PCM_FMTBIT_S24_LE | 731 SNDRV_PCM_FMTBIT_S32_LE; 732 733 i2s->capture_dma_data.addr = res->start + I2S_RXDR; 734 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 735 i2s->capture_dma_data.maxburst = 8; 736 737 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) { 738 if (val >= 2 && val <= 8) 739 dai->capture.channels_max = val; 740 } 741 } 742 743 if (dp) 744 *dp = dai; 745 746 return 0; 747 } 748 749 static int rockchip_i2s_probe(struct platform_device *pdev) 750 { 751 struct device_node *node = pdev->dev.of_node; 752 const struct of_device_id *of_id; 753 struct rk_i2s_dev *i2s; 754 struct snd_soc_dai_driver *dai; 755 struct resource *res; 756 void __iomem *regs; 757 int ret; 758 759 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 760 if (!i2s) 761 return -ENOMEM; 762 763 spin_lock_init(&i2s->lock); 764 i2s->dev = &pdev->dev; 765 766 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); 767 if (!IS_ERR(i2s->grf)) { 768 of_id = of_match_device(rockchip_i2s_match, &pdev->dev); 769 if (!of_id || !of_id->data) 770 return -EINVAL; 771 772 i2s->pins = of_id->data; 773 } 774 775 /* try to prepare related clocks */ 776 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk"); 777 if (IS_ERR(i2s->hclk)) { 778 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n"); 779 return PTR_ERR(i2s->hclk); 780 } 781 ret = clk_prepare_enable(i2s->hclk); 782 if (ret) { 783 dev_err(i2s->dev, "hclock enable failed %d\n", ret); 784 return ret; 785 } 786 787 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk"); 788 if (IS_ERR(i2s->mclk)) { 789 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n"); 790 ret = PTR_ERR(i2s->mclk); 791 goto err_clk; 792 } 793 794 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 795 if (IS_ERR(regs)) { 796 ret = PTR_ERR(regs); 797 goto err_clk; 798 } 799 800 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 801 &rockchip_i2s_regmap_config); 802 if (IS_ERR(i2s->regmap)) { 803 dev_err(&pdev->dev, 804 "Failed to initialise managed register map\n"); 805 ret = PTR_ERR(i2s->regmap); 806 goto err_clk; 807 } 808 809 i2s->bclk_ratio = 64; 810 i2s->pinctrl = devm_pinctrl_get(&pdev->dev); 811 if (IS_ERR(i2s->pinctrl)) 812 dev_err(&pdev->dev, "failed to find i2s pinctrl\n"); 813 814 i2s->bclk_on = pinctrl_lookup_state(i2s->pinctrl, 815 "bclk_on"); 816 if (IS_ERR_OR_NULL(i2s->bclk_on)) 817 dev_err(&pdev->dev, "failed to find i2s default state\n"); 818 else 819 dev_dbg(&pdev->dev, "find i2s bclk state\n"); 820 821 i2s->bclk_off = pinctrl_lookup_state(i2s->pinctrl, 822 "bclk_off"); 823 if (IS_ERR_OR_NULL(i2s->bclk_off)) 824 dev_err(&pdev->dev, "failed to find i2s gpio state\n"); 825 else 826 dev_dbg(&pdev->dev, "find i2s bclk_off state\n"); 827 828 i2s_pinctrl_select_bclk_off(i2s); 829 830 i2s->playback_dma_data.addr = res->start + I2S_TXDR; 831 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 832 i2s->playback_dma_data.maxburst = 4; 833 834 i2s->capture_dma_data.addr = res->start + I2S_RXDR; 835 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 836 i2s->capture_dma_data.maxburst = 4; 837 838 dev_set_drvdata(&pdev->dev, i2s); 839 840 pm_runtime_enable(&pdev->dev); 841 if (!pm_runtime_enabled(&pdev->dev)) { 842 ret = i2s_runtime_resume(&pdev->dev); 843 if (ret) 844 goto err_pm_disable; 845 } 846 847 ret = rockchip_i2s_init_dai(i2s, res, &dai); 848 if (ret) 849 goto err_pm_disable; 850 851 ret = devm_snd_soc_register_component(&pdev->dev, 852 &rockchip_i2s_component, 853 dai, 1); 854 855 if (ret) { 856 dev_err(&pdev->dev, "Could not register DAI\n"); 857 goto err_suspend; 858 } 859 860 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 861 if (ret) { 862 dev_err(&pdev->dev, "Could not register PCM\n"); 863 goto err_suspend; 864 } 865 866 return 0; 867 868 err_suspend: 869 if (!pm_runtime_status_suspended(&pdev->dev)) 870 i2s_runtime_suspend(&pdev->dev); 871 err_pm_disable: 872 pm_runtime_disable(&pdev->dev); 873 err_clk: 874 clk_disable_unprepare(i2s->hclk); 875 return ret; 876 } 877 878 static int rockchip_i2s_remove(struct platform_device *pdev) 879 { 880 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev); 881 882 pm_runtime_disable(&pdev->dev); 883 if (!pm_runtime_status_suspended(&pdev->dev)) 884 i2s_runtime_suspend(&pdev->dev); 885 886 clk_disable_unprepare(i2s->hclk); 887 888 return 0; 889 } 890 891 static const struct dev_pm_ops rockchip_i2s_pm_ops = { 892 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume, 893 NULL) 894 }; 895 896 static struct platform_driver rockchip_i2s_driver = { 897 .probe = rockchip_i2s_probe, 898 .remove = rockchip_i2s_remove, 899 .driver = { 900 .name = DRV_NAME, 901 .of_match_table = of_match_ptr(rockchip_i2s_match), 902 .pm = &rockchip_i2s_pm_ops, 903 }, 904 }; 905 module_platform_driver(rockchip_i2s_driver); 906 907 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface"); 908 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>"); 909 MODULE_LICENSE("GPL v2"); 910 MODULE_ALIAS("platform:" DRV_NAME); 911 MODULE_DEVICE_TABLE(of, rockchip_i2s_match); 912