1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 // 3 // Copyright (c) 2018 BayLibre, SAS. 4 // Author: Jerome Brunet <jbrunet@baylibre.com> 5 6 /* This driver implements the frontend capture DAI of AXG based SoCs */ 7 8 #include <linux/clk.h> 9 #include <linux/regmap.h> 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <sound/pcm_params.h> 13 #include <sound/soc.h> 14 #include <sound/soc-dai.h> 15 16 #include "axg-fifo.h" 17 18 #define CTRL0_TODDR_SEL_RESAMPLE BIT(30) 19 #define CTRL0_TODDR_EXT_SIGNED BIT(29) 20 #define CTRL0_TODDR_PP_MODE BIT(28) 21 #define CTRL0_TODDR_TYPE_MASK GENMASK(15, 13) 22 #define CTRL0_TODDR_TYPE(x) ((x) << 13) 23 #define CTRL0_TODDR_MSB_POS_MASK GENMASK(12, 8) 24 #define CTRL0_TODDR_MSB_POS(x) ((x) << 8) 25 #define CTRL0_TODDR_LSB_POS_MASK GENMASK(7, 3) 26 #define CTRL0_TODDR_LSB_POS(x) ((x) << 3) 27 #define CTRL1_TODDR_FORCE_FINISH BIT(25) 28 #define CTRL1_SEL_SHIFT 28 29 30 #define TODDR_MSB_POS 31 31 32 static int axg_toddr_pcm_new(struct snd_soc_pcm_runtime *rtd, 33 struct snd_soc_dai *dai) 34 { 35 return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_CAPTURE); 36 } 37 38 static int g12a_toddr_dai_prepare(struct snd_pcm_substream *substream, 39 struct snd_soc_dai *dai) 40 { 41 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); 42 43 /* Reset the write pointer to the FIFO_INIT_ADDR */ 44 regmap_update_bits(fifo->map, FIFO_CTRL1, 45 CTRL1_TODDR_FORCE_FINISH, 0); 46 regmap_update_bits(fifo->map, FIFO_CTRL1, 47 CTRL1_TODDR_FORCE_FINISH, CTRL1_TODDR_FORCE_FINISH); 48 regmap_update_bits(fifo->map, FIFO_CTRL1, 49 CTRL1_TODDR_FORCE_FINISH, 0); 50 51 return 0; 52 } 53 54 static int axg_toddr_dai_hw_params(struct snd_pcm_substream *substream, 55 struct snd_pcm_hw_params *params, 56 struct snd_soc_dai *dai) 57 { 58 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); 59 unsigned int type, width; 60 61 switch (params_physical_width(params)) { 62 case 8: 63 type = 0; /* 8 samples of 8 bits */ 64 break; 65 case 16: 66 type = 2; /* 4 samples of 16 bits - right justified */ 67 break; 68 case 32: 69 type = 4; /* 2 samples of 32 bits - right justified */ 70 break; 71 default: 72 return -EINVAL; 73 } 74 75 width = params_width(params); 76 77 regmap_update_bits(fifo->map, FIFO_CTRL0, 78 CTRL0_TODDR_TYPE_MASK | 79 CTRL0_TODDR_MSB_POS_MASK | 80 CTRL0_TODDR_LSB_POS_MASK, 81 CTRL0_TODDR_TYPE(type) | 82 CTRL0_TODDR_MSB_POS(TODDR_MSB_POS) | 83 CTRL0_TODDR_LSB_POS(TODDR_MSB_POS - (width - 1))); 84 85 return 0; 86 } 87 88 static int axg_toddr_dai_startup(struct snd_pcm_substream *substream, 89 struct snd_soc_dai *dai) 90 { 91 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); 92 unsigned int fifo_threshold; 93 int ret; 94 95 /* Enable pclk to access registers and clock the fifo ip */ 96 ret = clk_prepare_enable(fifo->pclk); 97 if (ret) 98 return ret; 99 100 /* Select orginal data - resampling not supported ATM */ 101 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_SEL_RESAMPLE, 0); 102 103 /* Only signed format are supported ATM */ 104 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_EXT_SIGNED, 105 CTRL0_TODDR_EXT_SIGNED); 106 107 /* Apply single buffer mode to the interface */ 108 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_PP_MODE, 0); 109 110 /* TODDR does not have a configurable fifo depth */ 111 fifo_threshold = AXG_FIFO_MIN_CNT - 1; 112 regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_THRESHOLD_MASK, 113 CTRL1_THRESHOLD(fifo_threshold)); 114 115 return 0; 116 } 117 118 static void axg_toddr_dai_shutdown(struct snd_pcm_substream *substream, 119 struct snd_soc_dai *dai) 120 { 121 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); 122 123 clk_disable_unprepare(fifo->pclk); 124 } 125 126 static const struct snd_soc_dai_ops axg_toddr_ops = { 127 .hw_params = axg_toddr_dai_hw_params, 128 .startup = axg_toddr_dai_startup, 129 .shutdown = axg_toddr_dai_shutdown, 130 }; 131 132 static struct snd_soc_dai_driver axg_toddr_dai_drv = { 133 .name = "TODDR", 134 .capture = { 135 .stream_name = "Capture", 136 .channels_min = 1, 137 .channels_max = AXG_FIFO_CH_MAX, 138 .rates = AXG_FIFO_RATES, 139 .formats = AXG_FIFO_FORMATS, 140 }, 141 .ops = &axg_toddr_ops, 142 .pcm_new = axg_toddr_pcm_new, 143 }; 144 145 static const char * const axg_toddr_sel_texts[] = { 146 "IN 0", "IN 1", "IN 2", "IN 3", "IN 4", "IN 5", "IN 6", "IN 7" 147 }; 148 149 static SOC_ENUM_SINGLE_DECL(axg_toddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT, 150 axg_toddr_sel_texts); 151 152 static const struct snd_kcontrol_new axg_toddr_in_mux = 153 SOC_DAPM_ENUM("Input Source", axg_toddr_sel_enum); 154 155 static const struct snd_soc_dapm_widget axg_toddr_dapm_widgets[] = { 156 SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &axg_toddr_in_mux), 157 SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0), 158 SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0), 159 SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0), 160 SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0), 161 SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0), 162 SND_SOC_DAPM_AIF_IN("IN 5", NULL, 0, SND_SOC_NOPM, 0, 0), 163 SND_SOC_DAPM_AIF_IN("IN 6", NULL, 0, SND_SOC_NOPM, 0, 0), 164 SND_SOC_DAPM_AIF_IN("IN 7", NULL, 0, SND_SOC_NOPM, 0, 0), 165 }; 166 167 static const struct snd_soc_dapm_route axg_toddr_dapm_routes[] = { 168 { "Capture", NULL, "SRC SEL" }, 169 { "SRC SEL", "IN 0", "IN 0" }, 170 { "SRC SEL", "IN 1", "IN 1" }, 171 { "SRC SEL", "IN 2", "IN 2" }, 172 { "SRC SEL", "IN 3", "IN 3" }, 173 { "SRC SEL", "IN 4", "IN 4" }, 174 { "SRC SEL", "IN 5", "IN 5" }, 175 { "SRC SEL", "IN 6", "IN 6" }, 176 { "SRC SEL", "IN 7", "IN 7" }, 177 }; 178 179 static const struct snd_soc_component_driver axg_toddr_component_drv = { 180 .dapm_widgets = axg_toddr_dapm_widgets, 181 .num_dapm_widgets = ARRAY_SIZE(axg_toddr_dapm_widgets), 182 .dapm_routes = axg_toddr_dapm_routes, 183 .num_dapm_routes = ARRAY_SIZE(axg_toddr_dapm_routes), 184 .open = axg_fifo_pcm_open, 185 .close = axg_fifo_pcm_close, 186 .ioctl = snd_soc_pcm_lib_ioctl, 187 .hw_params = axg_fifo_pcm_hw_params, 188 .hw_free = axg_fifo_pcm_hw_free, 189 .pointer = axg_fifo_pcm_pointer, 190 .trigger = axg_fifo_pcm_trigger, 191 }; 192 193 static const struct axg_fifo_match_data axg_toddr_match_data = { 194 .component_drv = &axg_toddr_component_drv, 195 .dai_drv = &axg_toddr_dai_drv 196 }; 197 198 static const struct snd_soc_dai_ops g12a_toddr_ops = { 199 .prepare = g12a_toddr_dai_prepare, 200 .hw_params = axg_toddr_dai_hw_params, 201 .startup = axg_toddr_dai_startup, 202 .shutdown = axg_toddr_dai_shutdown, 203 }; 204 205 static struct snd_soc_dai_driver g12a_toddr_dai_drv = { 206 .name = "TODDR", 207 .capture = { 208 .stream_name = "Capture", 209 .channels_min = 1, 210 .channels_max = AXG_FIFO_CH_MAX, 211 .rates = AXG_FIFO_RATES, 212 .formats = AXG_FIFO_FORMATS, 213 }, 214 .ops = &g12a_toddr_ops, 215 .pcm_new = axg_toddr_pcm_new, 216 }; 217 218 static const struct snd_soc_component_driver g12a_toddr_component_drv = { 219 .dapm_widgets = axg_toddr_dapm_widgets, 220 .num_dapm_widgets = ARRAY_SIZE(axg_toddr_dapm_widgets), 221 .dapm_routes = axg_toddr_dapm_routes, 222 .num_dapm_routes = ARRAY_SIZE(axg_toddr_dapm_routes), 223 .open = axg_fifo_pcm_open, 224 .close = axg_fifo_pcm_close, 225 .ioctl = snd_soc_pcm_lib_ioctl, 226 .hw_params = g12a_fifo_pcm_hw_params, 227 .hw_free = axg_fifo_pcm_hw_free, 228 .pointer = axg_fifo_pcm_pointer, 229 .trigger = axg_fifo_pcm_trigger, 230 }; 231 232 static const struct axg_fifo_match_data g12a_toddr_match_data = { 233 .component_drv = &g12a_toddr_component_drv, 234 .dai_drv = &g12a_toddr_dai_drv 235 }; 236 237 static const char * const sm1_toddr_sel_texts[] = { 238 "IN 0", "IN 1", "IN 2", "IN 3", "IN 4", "IN 5", "IN 6", "IN 7", 239 "IN 8", "IN 9", "IN 10", "IN 11", "IN 12", "IN 13", "IN 14", "IN 15" 240 }; 241 242 static SOC_ENUM_SINGLE_DECL(sm1_toddr_sel_enum, FIFO_CTRL1, CTRL1_SEL_SHIFT, 243 sm1_toddr_sel_texts); 244 245 static const struct snd_kcontrol_new sm1_toddr_in_mux = 246 SOC_DAPM_ENUM("Input Source", sm1_toddr_sel_enum); 247 248 static const struct snd_soc_dapm_widget sm1_toddr_dapm_widgets[] = { 249 SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &sm1_toddr_in_mux), 250 SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0), 251 SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0), 252 SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0), 253 SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0), 254 SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0), 255 SND_SOC_DAPM_AIF_IN("IN 5", NULL, 0, SND_SOC_NOPM, 0, 0), 256 SND_SOC_DAPM_AIF_IN("IN 6", NULL, 0, SND_SOC_NOPM, 0, 0), 257 SND_SOC_DAPM_AIF_IN("IN 7", NULL, 0, SND_SOC_NOPM, 0, 0), 258 SND_SOC_DAPM_AIF_IN("IN 8", NULL, 0, SND_SOC_NOPM, 0, 0), 259 SND_SOC_DAPM_AIF_IN("IN 9", NULL, 0, SND_SOC_NOPM, 0, 0), 260 SND_SOC_DAPM_AIF_IN("IN 10", NULL, 0, SND_SOC_NOPM, 0, 0), 261 SND_SOC_DAPM_AIF_IN("IN 11", NULL, 0, SND_SOC_NOPM, 0, 0), 262 SND_SOC_DAPM_AIF_IN("IN 12", NULL, 0, SND_SOC_NOPM, 0, 0), 263 SND_SOC_DAPM_AIF_IN("IN 13", NULL, 0, SND_SOC_NOPM, 0, 0), 264 SND_SOC_DAPM_AIF_IN("IN 14", NULL, 0, SND_SOC_NOPM, 0, 0), 265 SND_SOC_DAPM_AIF_IN("IN 15", NULL, 0, SND_SOC_NOPM, 0, 0), 266 }; 267 268 static const struct snd_soc_dapm_route sm1_toddr_dapm_routes[] = { 269 { "Capture", NULL, "SRC SEL" }, 270 { "SRC SEL", "IN 0", "IN 0" }, 271 { "SRC SEL", "IN 1", "IN 1" }, 272 { "SRC SEL", "IN 2", "IN 2" }, 273 { "SRC SEL", "IN 3", "IN 3" }, 274 { "SRC SEL", "IN 4", "IN 4" }, 275 { "SRC SEL", "IN 5", "IN 5" }, 276 { "SRC SEL", "IN 6", "IN 6" }, 277 { "SRC SEL", "IN 7", "IN 7" }, 278 { "SRC SEL", "IN 8", "IN 8" }, 279 { "SRC SEL", "IN 9", "IN 9" }, 280 { "SRC SEL", "IN 10", "IN 10" }, 281 { "SRC SEL", "IN 11", "IN 11" }, 282 { "SRC SEL", "IN 12", "IN 12" }, 283 { "SRC SEL", "IN 13", "IN 13" }, 284 { "SRC SEL", "IN 14", "IN 14" }, 285 { "SRC SEL", "IN 15", "IN 15" }, 286 }; 287 288 static const struct snd_soc_component_driver sm1_toddr_component_drv = { 289 .dapm_widgets = sm1_toddr_dapm_widgets, 290 .num_dapm_widgets = ARRAY_SIZE(sm1_toddr_dapm_widgets), 291 .dapm_routes = sm1_toddr_dapm_routes, 292 .num_dapm_routes = ARRAY_SIZE(sm1_toddr_dapm_routes), 293 .open = axg_fifo_pcm_open, 294 .close = axg_fifo_pcm_close, 295 .ioctl = snd_soc_pcm_lib_ioctl, 296 .hw_params = g12a_fifo_pcm_hw_params, 297 .hw_free = axg_fifo_pcm_hw_free, 298 .pointer = axg_fifo_pcm_pointer, 299 .trigger = axg_fifo_pcm_trigger, 300 }; 301 302 static const struct axg_fifo_match_data sm1_toddr_match_data = { 303 .component_drv = &sm1_toddr_component_drv, 304 .dai_drv = &g12a_toddr_dai_drv 305 }; 306 307 static const struct of_device_id axg_toddr_of_match[] = { 308 { 309 .compatible = "amlogic,axg-toddr", 310 .data = &axg_toddr_match_data, 311 }, { 312 .compatible = "amlogic,g12a-toddr", 313 .data = &g12a_toddr_match_data, 314 }, { 315 .compatible = "amlogic,sm1-toddr", 316 .data = &sm1_toddr_match_data, 317 }, {} 318 }; 319 MODULE_DEVICE_TABLE(of, axg_toddr_of_match); 320 321 static struct platform_driver axg_toddr_pdrv = { 322 .probe = axg_fifo_probe, 323 .driver = { 324 .name = "axg-toddr", 325 .of_match_table = axg_toddr_of_match, 326 }, 327 }; 328 module_platform_driver(axg_toddr_pdrv); 329 330 MODULE_DESCRIPTION("Amlogic AXG capture fifo driver"); 331 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); 332 MODULE_LICENSE("GPL v2"); 333