1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * skl.h - HD Audio skylake defintions. 4 * 5 * Copyright (C) 2015 Intel Corp 6 * Author: Jeeja KP <jeeja.kp@intel.com> 7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8 * 9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 10 */ 11 12 #ifndef __SOUND_SOC_SKL_H 13 #define __SOUND_SOC_SKL_H 14 15 #include <sound/hda_register.h> 16 #include <sound/hdaudio_ext.h> 17 #include <sound/hda_codec.h> 18 #include <sound/soc.h> 19 #include "skl-nhlt.h" 20 #include "skl-ssp-clk.h" 21 22 #define SKL_SUSPEND_DELAY 2000 23 24 #define SKL_MAX_ASTATE_CFG 3 25 26 #define AZX_PCIREG_PGCTL 0x44 27 #define AZX_PGCTL_LSRMD_MASK (1 << 4) 28 #define AZX_PGCTL_ADSPPGD BIT(2) 29 #define AZX_PCIREG_CGCTL 0x48 30 #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6) 31 #define AZX_CGCTL_ADSPDCGE BIT(1) 32 /* D0I3C Register fields */ 33 #define AZX_REG_VS_D0I3C_CIP 0x1 /* Command in progress */ 34 #define AZX_REG_VS_D0I3C_I3 0x4 /* D0i3 enable */ 35 #define SKL_MAX_DMACTRL_CFG 18 36 #define DMA_CLK_CONTROLS 1 37 #define DMA_TRANSMITION_START 2 38 #define DMA_TRANSMITION_STOP 3 39 40 #define AZX_VS_EM2_DUM BIT(23) 41 #define AZX_REG_VS_EM2_L1SEN BIT(13) 42 43 struct skl_dsp_resource { 44 u32 max_mcps; 45 u32 max_mem; 46 u32 mcps; 47 u32 mem; 48 }; 49 50 struct skl_debug; 51 52 struct skl_astate_param { 53 u32 kcps; 54 u32 clk_src; 55 }; 56 57 struct skl_astate_config { 58 u32 count; 59 struct skl_astate_param astate_table[0]; 60 }; 61 62 struct skl_fw_config { 63 struct skl_astate_config *astate_cfg; 64 }; 65 66 struct skl { 67 struct hda_bus hbus; 68 struct pci_dev *pci; 69 70 unsigned int init_done:1; /* delayed init status */ 71 struct platform_device *dmic_dev; 72 struct platform_device *i2s_dev; 73 struct platform_device *clk_dev; 74 struct snd_soc_component *component; 75 struct snd_soc_dai_driver *dais; 76 77 struct nhlt_acpi_table *nhlt; /* nhlt ptr */ 78 struct skl_sst *skl_sst; /* sst skl ctx */ 79 80 struct skl_dsp_resource resource; 81 struct list_head ppl_list; 82 struct list_head bind_list; 83 84 const char *fw_name; 85 char tplg_name[64]; 86 unsigned short pci_id; 87 const struct firmware *tplg; 88 89 int supend_active; 90 91 struct work_struct probe_work; 92 93 struct skl_debug *debugfs; 94 u8 nr_modules; 95 struct skl_module **modules; 96 bool use_tplg_pcm; 97 struct skl_fw_config cfg; 98 struct snd_soc_acpi_mach *mach; 99 }; 100 101 #define skl_to_bus(s) (&(s)->hbus.core) 102 #define bus_to_skl(bus) container_of(bus, struct skl, hbus.core) 103 104 #define skl_to_hbus(s) (&(s)->hbus) 105 #define hbus_to_skl(hbus) container_of((hbus), struct skl, (hbus)) 106 107 /* to pass dai dma data */ 108 struct skl_dma_params { 109 u32 format; 110 u8 stream_tag; 111 }; 112 113 struct skl_machine_pdata { 114 bool use_tplg_pcm; /* use dais and dai links from topology */ 115 }; 116 117 struct skl_dsp_ops { 118 int id; 119 unsigned int num_cores; 120 struct skl_dsp_loader_ops (*loader_ops)(void); 121 int (*init)(struct device *dev, void __iomem *mmio_base, 122 int irq, const char *fw_name, 123 struct skl_dsp_loader_ops loader_ops, 124 struct skl_sst **skl_sst); 125 int (*init_fw)(struct device *dev, struct skl_sst *ctx); 126 void (*cleanup)(struct device *dev, struct skl_sst *ctx); 127 }; 128 129 int skl_platform_unregister(struct device *dev); 130 int skl_platform_register(struct device *dev); 131 132 struct nhlt_acpi_table *skl_nhlt_init(struct device *dev); 133 void skl_nhlt_free(struct nhlt_acpi_table *addr); 134 struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance, 135 u8 link_type, u8 s_fmt, u8 no_ch, 136 u32 s_rate, u8 dirn, u8 dev_type); 137 138 int skl_get_dmic_geo(struct skl *skl); 139 int skl_nhlt_update_topology_bin(struct skl *skl); 140 int skl_init_dsp(struct skl *skl); 141 int skl_free_dsp(struct skl *skl); 142 int skl_suspend_late_dsp(struct skl *skl); 143 int skl_suspend_dsp(struct skl *skl); 144 int skl_resume_dsp(struct skl *skl); 145 void skl_cleanup_resources(struct skl *skl); 146 const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id); 147 void skl_update_d0i3c(struct device *dev, bool enable); 148 int skl_nhlt_create_sysfs(struct skl *skl); 149 void skl_nhlt_remove_sysfs(struct skl *skl); 150 void skl_get_clks(struct skl *skl, struct skl_ssp_clk *ssp_clks); 151 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id); 152 int skl_dsp_set_dma_control(struct skl_sst *ctx, u32 *caps, 153 u32 caps_size, u32 node_id); 154 155 struct skl_module_cfg; 156 157 #ifdef CONFIG_DEBUG_FS 158 struct skl_debug *skl_debugfs_init(struct skl *skl); 159 void skl_debugfs_exit(struct skl *skl); 160 void skl_debug_init_module(struct skl_debug *d, 161 struct snd_soc_dapm_widget *w, 162 struct skl_module_cfg *mconfig); 163 #else 164 static inline struct skl_debug *skl_debugfs_init(struct skl *skl) 165 { 166 return NULL; 167 } 168 169 static inline void skl_debugfs_exit(struct skl *skl) 170 {} 171 172 static inline void skl_debug_init_module(struct skl_debug *d, 173 struct snd_soc_dapm_widget *w, 174 struct skl_module_cfg *mconfig) 175 {} 176 #endif 177 178 #endif /* __SOUND_SOC_SKL_H */ 179