1 /* 2 * skl.h - HD Audio skylake defintions. 3 * 4 * Copyright (C) 2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 18 * 19 */ 20 21 #ifndef __SOUND_SOC_SKL_H 22 #define __SOUND_SOC_SKL_H 23 24 #include <sound/hda_register.h> 25 #include <sound/hdaudio_ext.h> 26 #include <sound/hda_codec.h> 27 #include <sound/soc.h> 28 #include "skl-nhlt.h" 29 #include "skl-ssp-clk.h" 30 31 #define SKL_SUSPEND_DELAY 2000 32 33 #define SKL_MAX_ASTATE_CFG 3 34 35 #define AZX_PCIREG_PGCTL 0x44 36 #define AZX_PGCTL_LSRMD_MASK (1 << 4) 37 #define AZX_PGCTL_ADSPPGD BIT(2) 38 #define AZX_PCIREG_CGCTL 0x48 39 #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6) 40 #define AZX_CGCTL_ADSPDCGE BIT(1) 41 /* D0I3C Register fields */ 42 #define AZX_REG_VS_D0I3C_CIP 0x1 /* Command in progress */ 43 #define AZX_REG_VS_D0I3C_I3 0x4 /* D0i3 enable */ 44 #define SKL_MAX_DMACTRL_CFG 18 45 #define DMA_CLK_CONTROLS 1 46 #define DMA_TRANSMITION_START 2 47 #define DMA_TRANSMITION_STOP 3 48 49 #define AZX_REG_VS_EM2_L1SEN BIT(13) 50 51 struct skl_dsp_resource { 52 u32 max_mcps; 53 u32 max_mem; 54 u32 mcps; 55 u32 mem; 56 }; 57 58 struct skl_debug; 59 60 struct skl_astate_param { 61 u32 kcps; 62 u32 clk_src; 63 }; 64 65 struct skl_astate_config { 66 u32 count; 67 struct skl_astate_param astate_table[0]; 68 }; 69 70 struct skl_fw_config { 71 struct skl_astate_config *astate_cfg; 72 }; 73 74 struct skl { 75 struct hda_bus hbus; 76 struct pci_dev *pci; 77 78 unsigned int init_done:1; /* delayed init status */ 79 struct platform_device *dmic_dev; 80 struct platform_device *i2s_dev; 81 struct platform_device *clk_dev; 82 struct snd_soc_component *component; 83 struct snd_soc_dai_driver *dais; 84 85 struct nhlt_acpi_table *nhlt; /* nhlt ptr */ 86 struct skl_sst *skl_sst; /* sst skl ctx */ 87 88 struct skl_dsp_resource resource; 89 struct list_head ppl_list; 90 struct list_head bind_list; 91 92 const char *fw_name; 93 char tplg_name[64]; 94 unsigned short pci_id; 95 const struct firmware *tplg; 96 97 int supend_active; 98 99 struct work_struct probe_work; 100 101 struct skl_debug *debugfs; 102 u8 nr_modules; 103 struct skl_module **modules; 104 bool use_tplg_pcm; 105 struct skl_fw_config cfg; 106 struct snd_soc_acpi_mach *mach; 107 }; 108 109 #define skl_to_bus(s) (&(s)->hbus.core) 110 #define bus_to_skl(bus) container_of(bus, struct skl, hbus.core) 111 112 #define skl_to_hbus(s) (&(s)->hbus) 113 #define hbus_to_skl(hbus) container_of((hbus), struct skl, (hbus)) 114 115 /* to pass dai dma data */ 116 struct skl_dma_params { 117 u32 format; 118 u8 stream_tag; 119 }; 120 121 struct skl_machine_pdata { 122 u32 dmic_num; 123 bool use_tplg_pcm; /* use dais and dai links from topology */ 124 const char *platform; 125 u32 codec_mask; 126 }; 127 128 struct skl_dsp_ops { 129 int id; 130 unsigned int num_cores; 131 struct skl_dsp_loader_ops (*loader_ops)(void); 132 int (*init)(struct device *dev, void __iomem *mmio_base, 133 int irq, const char *fw_name, 134 struct skl_dsp_loader_ops loader_ops, 135 struct skl_sst **skl_sst); 136 int (*init_fw)(struct device *dev, struct skl_sst *ctx); 137 void (*cleanup)(struct device *dev, struct skl_sst *ctx); 138 }; 139 140 int skl_platform_unregister(struct device *dev); 141 int skl_platform_register(struct device *dev); 142 143 struct nhlt_acpi_table *skl_nhlt_init(struct device *dev); 144 void skl_nhlt_free(struct nhlt_acpi_table *addr); 145 struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance, 146 u8 link_type, u8 s_fmt, u8 no_ch, 147 u32 s_rate, u8 dirn, u8 dev_type); 148 149 int skl_get_dmic_geo(struct skl *skl); 150 int skl_nhlt_update_topology_bin(struct skl *skl); 151 int skl_init_dsp(struct skl *skl); 152 int skl_free_dsp(struct skl *skl); 153 int skl_suspend_late_dsp(struct skl *skl); 154 int skl_suspend_dsp(struct skl *skl); 155 int skl_resume_dsp(struct skl *skl); 156 void skl_cleanup_resources(struct skl *skl); 157 const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id); 158 void skl_update_d0i3c(struct device *dev, bool enable); 159 int skl_nhlt_create_sysfs(struct skl *skl); 160 void skl_nhlt_remove_sysfs(struct skl *skl); 161 void skl_get_clks(struct skl *skl, struct skl_ssp_clk *ssp_clks); 162 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id); 163 int skl_dsp_set_dma_control(struct skl_sst *ctx, u32 *caps, 164 u32 caps_size, u32 node_id); 165 166 struct skl_module_cfg; 167 168 #ifdef CONFIG_DEBUG_FS 169 struct skl_debug *skl_debugfs_init(struct skl *skl); 170 void skl_debug_init_module(struct skl_debug *d, 171 struct snd_soc_dapm_widget *w, 172 struct skl_module_cfg *mconfig); 173 #else 174 static inline struct skl_debug *skl_debugfs_init(struct skl *skl) 175 { 176 return NULL; 177 } 178 static inline void skl_debug_init_module(struct skl_debug *d, 179 struct snd_soc_dapm_widget *w, 180 struct skl_module_cfg *mconfig) 181 {} 182 #endif 183 184 #endif /* __SOUND_SOC_SKL_H */ 185