1 /* 2 * skl.h - HD Audio skylake defintions. 3 * 4 * Copyright (C) 2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 18 * 19 */ 20 21 #ifndef __SOUND_SOC_SKL_H 22 #define __SOUND_SOC_SKL_H 23 24 #include <sound/hda_register.h> 25 #include <sound/hdaudio_ext.h> 26 #include "skl-nhlt.h" 27 28 #define SKL_SUSPEND_DELAY 2000 29 30 /* Vendor Specific Registers */ 31 #define AZX_REG_VS_EM1 0x1000 32 #define AZX_REG_VS_INRC 0x1004 33 #define AZX_REG_VS_OUTRC 0x1008 34 #define AZX_REG_VS_FIFOTRK 0x100C 35 #define AZX_REG_VS_FIFOTRK2 0x1010 36 #define AZX_REG_VS_EM2 0x1030 37 #define AZX_REG_VS_EM3L 0x1038 38 #define AZX_REG_VS_EM3U 0x103C 39 #define AZX_REG_VS_EM4L 0x1040 40 #define AZX_REG_VS_EM4U 0x1044 41 #define AZX_REG_VS_LTRC 0x1048 42 #define AZX_REG_VS_D0I3C 0x104A 43 #define AZX_REG_VS_PCE 0x104B 44 #define AZX_REG_VS_L2MAGC 0x1050 45 #define AZX_REG_VS_L2LAHPT 0x1054 46 #define AZX_REG_VS_SDXDPIB_XBASE 0x1084 47 #define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20 48 #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 49 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 50 51 #define AZX_PCIREG_PGCTL 0x44 52 #define AZX_PGCTL_LSRMD_MASK (1 << 4) 53 #define AZX_PCIREG_CGCTL 0x48 54 #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6) 55 56 struct skl_dsp_resource { 57 u32 max_mcps; 58 u32 max_mem; 59 u32 mcps; 60 u32 mem; 61 }; 62 63 struct skl { 64 struct hdac_ext_bus ebus; 65 struct pci_dev *pci; 66 67 unsigned int init_failed:1; /* delayed init failed */ 68 struct platform_device *dmic_dev; 69 struct platform_device *i2s_dev; 70 struct snd_soc_platform *platform; 71 72 struct nhlt_acpi_table *nhlt; /* nhlt ptr */ 73 struct skl_sst *skl_sst; /* sst skl ctx */ 74 75 struct skl_dsp_resource resource; 76 struct list_head ppl_list; 77 78 const char *fw_name; 79 char tplg_name[64]; 80 unsigned short pci_id; 81 const struct firmware *tplg; 82 83 int supend_active; 84 }; 85 86 #define skl_to_ebus(s) (&(s)->ebus) 87 #define ebus_to_skl(sbus) \ 88 container_of(sbus, struct skl, sbus) 89 90 /* to pass dai dma data */ 91 struct skl_dma_params { 92 u32 format; 93 u8 stream_tag; 94 }; 95 96 /* to pass dmic data */ 97 struct skl_machine_pdata { 98 u32 dmic_num; 99 }; 100 101 struct skl_dsp_ops { 102 int id; 103 struct skl_dsp_loader_ops (*loader_ops)(void); 104 int (*init)(struct device *dev, void __iomem *mmio_base, 105 int irq, const char *fw_name, 106 struct skl_dsp_loader_ops loader_ops, 107 struct skl_sst **skl_sst); 108 int (*init_fw)(struct device *dev, struct skl_sst *ctx); 109 void (*cleanup)(struct device *dev, struct skl_sst *ctx); 110 }; 111 112 int skl_platform_unregister(struct device *dev); 113 int skl_platform_register(struct device *dev); 114 115 struct nhlt_acpi_table *skl_nhlt_init(struct device *dev); 116 void skl_nhlt_free(struct nhlt_acpi_table *addr); 117 struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance, 118 u8 link_type, u8 s_fmt, u8 no_ch, u32 s_rate, u8 dirn); 119 120 int skl_get_dmic_geo(struct skl *skl); 121 int skl_nhlt_update_topology_bin(struct skl *skl); 122 int skl_init_dsp(struct skl *skl); 123 int skl_free_dsp(struct skl *skl); 124 int skl_suspend_dsp(struct skl *skl); 125 int skl_resume_dsp(struct skl *skl); 126 void skl_cleanup_resources(struct skl *skl); 127 const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id); 128 #endif /* __SOUND_SOC_SKL_H */ 129