1 /* 2 * skl.h - HD Audio skylake defintions. 3 * 4 * Copyright (C) 2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 18 * 19 */ 20 21 #ifndef __SOUND_SOC_SKL_H 22 #define __SOUND_SOC_SKL_H 23 24 #include <sound/hda_register.h> 25 #include <sound/hdaudio_ext.h> 26 #include "skl-nhlt.h" 27 28 #define SKL_SUSPEND_DELAY 2000 29 30 /* Vendor Specific Registers */ 31 #define AZX_REG_VS_EM1 0x1000 32 #define AZX_REG_VS_INRC 0x1004 33 #define AZX_REG_VS_OUTRC 0x1008 34 #define AZX_REG_VS_FIFOTRK 0x100C 35 #define AZX_REG_VS_FIFOTRK2 0x1010 36 #define AZX_REG_VS_EM2 0x1030 37 #define AZX_REG_VS_EM3L 0x1038 38 #define AZX_REG_VS_EM3U 0x103C 39 #define AZX_REG_VS_EM4L 0x1040 40 #define AZX_REG_VS_EM4U 0x1044 41 #define AZX_REG_VS_LTRC 0x1048 42 #define AZX_REG_VS_D0I3C 0x104A 43 #define AZX_REG_VS_PCE 0x104B 44 #define AZX_REG_VS_L2MAGC 0x1050 45 #define AZX_REG_VS_L2LAHPT 0x1054 46 #define AZX_REG_VS_SDXDPIB_XBASE 0x1084 47 #define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20 48 #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 49 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 50 51 #define AZX_PCIREG_CGCTL 0x48 52 #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6) 53 54 struct skl_dsp_resource { 55 u32 max_mcps; 56 u32 max_mem; 57 u32 mcps; 58 u32 mem; 59 }; 60 61 struct skl { 62 struct hdac_ext_bus ebus; 63 struct pci_dev *pci; 64 65 unsigned int init_failed:1; /* delayed init failed */ 66 struct platform_device *dmic_dev; 67 struct platform_device *i2s_dev; 68 69 struct nhlt_acpi_table *nhlt; /* nhlt ptr */ 70 struct skl_sst *skl_sst; /* sst skl ctx */ 71 72 struct skl_dsp_resource resource; 73 struct list_head ppl_list; 74 75 const char *fw_name; 76 char tplg_name[64]; 77 unsigned short pci_id; 78 const struct firmware *tplg; 79 80 int supend_active; 81 }; 82 83 #define skl_to_ebus(s) (&(s)->ebus) 84 #define ebus_to_skl(sbus) \ 85 container_of(sbus, struct skl, sbus) 86 87 /* to pass dai dma data */ 88 struct skl_dma_params { 89 u32 format; 90 u8 stream_tag; 91 }; 92 93 struct skl_dsp_ops { 94 int id; 95 struct skl_dsp_loader_ops (*loader_ops)(void); 96 int (*init)(struct device *dev, void __iomem *mmio_base, 97 int irq, const char *fw_name, 98 struct skl_dsp_loader_ops loader_ops, 99 struct skl_sst **skl_sst); 100 void (*cleanup)(struct device *dev, struct skl_sst *ctx); 101 }; 102 103 int skl_platform_unregister(struct device *dev); 104 int skl_platform_register(struct device *dev); 105 106 struct nhlt_acpi_table *skl_nhlt_init(struct device *dev); 107 void skl_nhlt_free(struct nhlt_acpi_table *addr); 108 struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance, 109 u8 link_type, u8 s_fmt, u8 no_ch, u32 s_rate, u8 dirn); 110 111 int skl_nhlt_update_topology_bin(struct skl *skl); 112 int skl_init_dsp(struct skl *skl); 113 int skl_free_dsp(struct skl *skl); 114 int skl_suspend_dsp(struct skl *skl); 115 int skl_resume_dsp(struct skl *skl); 116 #endif /* __SOUND_SOC_SKL_H */ 117