1a40e693cSJeeja KP /* 2a40e693cSJeeja KP * skl.h - HD Audio skylake defintions. 3a40e693cSJeeja KP * 4a40e693cSJeeja KP * Copyright (C) 2015 Intel Corp 5a40e693cSJeeja KP * Author: Jeeja KP <jeeja.kp@intel.com> 6a40e693cSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 7a40e693cSJeeja KP * 8a40e693cSJeeja KP * This program is free software; you can redistribute it and/or modify 9a40e693cSJeeja KP * it under the terms of the GNU General Public License as published by 10a40e693cSJeeja KP * the Free Software Foundation; version 2 of the License. 11a40e693cSJeeja KP * 12a40e693cSJeeja KP * This program is distributed in the hope that it will be useful, but 13a40e693cSJeeja KP * WITHOUT ANY WARRANTY; without even the implied warranty of 14a40e693cSJeeja KP * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15a40e693cSJeeja KP * General Public License for more details. 16a40e693cSJeeja KP * 17a40e693cSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 18a40e693cSJeeja KP * 19a40e693cSJeeja KP */ 20a40e693cSJeeja KP 21a40e693cSJeeja KP #ifndef __SOUND_SOC_SKL_H 22a40e693cSJeeja KP #define __SOUND_SOC_SKL_H 23a40e693cSJeeja KP 24a40e693cSJeeja KP #include <sound/hda_register.h> 25a40e693cSJeeja KP #include <sound/hdaudio_ext.h> 26a40e693cSJeeja KP 27a40e693cSJeeja KP #define SKL_SUSPEND_DELAY 2000 28a40e693cSJeeja KP 29a40e693cSJeeja KP /* Vendor Specific Registers */ 30a40e693cSJeeja KP #define AZX_REG_VS_EM1 0x1000 31a40e693cSJeeja KP #define AZX_REG_VS_INRC 0x1004 32a40e693cSJeeja KP #define AZX_REG_VS_OUTRC 0x1008 33a40e693cSJeeja KP #define AZX_REG_VS_FIFOTRK 0x100C 34a40e693cSJeeja KP #define AZX_REG_VS_FIFOTRK2 0x1010 35a40e693cSJeeja KP #define AZX_REG_VS_EM2 0x1030 36a40e693cSJeeja KP #define AZX_REG_VS_EM3L 0x1038 37a40e693cSJeeja KP #define AZX_REG_VS_EM3U 0x103C 38a40e693cSJeeja KP #define AZX_REG_VS_EM4L 0x1040 39a40e693cSJeeja KP #define AZX_REG_VS_EM4U 0x1044 40a40e693cSJeeja KP #define AZX_REG_VS_LTRC 0x1048 41a40e693cSJeeja KP #define AZX_REG_VS_D0I3C 0x104A 42a40e693cSJeeja KP #define AZX_REG_VS_PCE 0x104B 43a40e693cSJeeja KP #define AZX_REG_VS_L2MAGC 0x1050 44a40e693cSJeeja KP #define AZX_REG_VS_L2LAHPT 0x1054 45a40e693cSJeeja KP #define AZX_REG_VS_SDXDPIB_XBASE 0x1084 46a40e693cSJeeja KP #define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20 47a40e693cSJeeja KP #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 48a40e693cSJeeja KP #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 49a40e693cSJeeja KP 50a40e693cSJeeja KP struct skl { 51a40e693cSJeeja KP struct hdac_ext_bus ebus; 52a40e693cSJeeja KP struct pci_dev *pci; 53a40e693cSJeeja KP 54a40e693cSJeeja KP unsigned int init_failed:1; /* delayed init failed */ 55a40e693cSJeeja KP struct platform_device *dmic_dev; 56a40e693cSJeeja KP }; 57a40e693cSJeeja KP 58a40e693cSJeeja KP #define skl_to_ebus(s) (&(s)->ebus) 59a40e693cSJeeja KP #define ebus_to_skl(sbus) \ 60a40e693cSJeeja KP container_of(sbus, struct skl, sbus) 61a40e693cSJeeja KP 62a40e693cSJeeja KP /* to pass dai dma data */ 63a40e693cSJeeja KP struct skl_dma_params { 64a40e693cSJeeja KP u32 format; 65a40e693cSJeeja KP u8 stream_tag; 66a40e693cSJeeja KP }; 67a40e693cSJeeja KP 68a40e693cSJeeja KP int skl_platform_unregister(struct device *dev); 69a40e693cSJeeja KP int skl_platform_register(struct device *dev); 70a40e693cSJeeja KP 71a40e693cSJeeja KP #endif /* __SOUND_SOC_SKL_H */ 72