1 /* 2 * Intel SKL IPC Support 3 * 4 * Copyright (C) 2014-15, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as version 2, as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 */ 15 16 #ifndef __SKL_IPC_H 17 #define __SKL_IPC_H 18 19 #include <linux/kthread.h> 20 #include <linux/irqreturn.h> 21 #include "../common/sst-ipc.h" 22 23 struct sst_dsp; 24 struct skl_sst; 25 struct sst_generic_ipc; 26 27 enum skl_ipc_pipeline_state { 28 PPL_INVALID_STATE = 0, 29 PPL_UNINITIALIZED = 1, 30 PPL_RESET = 2, 31 PPL_PAUSED = 3, 32 PPL_RUNNING = 4, 33 PPL_ERROR_STOP = 5, 34 PPL_SAVED = 6, 35 PPL_RESTORED = 7 36 }; 37 38 struct skl_ipc_dxstate_info { 39 u32 core_mask; 40 u32 dx_mask; 41 }; 42 43 struct skl_ipc_header { 44 u32 primary; 45 u32 extension; 46 }; 47 48 #define SKL_DSP_CORES_MAX 2 49 50 struct skl_dsp_cores { 51 unsigned int count; 52 enum skl_dsp_states state[SKL_DSP_CORES_MAX]; 53 int usage_count[SKL_DSP_CORES_MAX]; 54 }; 55 56 /** 57 * skl_d0i3_data: skl D0i3 counters data struct 58 * 59 * @streaming: Count of usecases that can attempt streaming D0i3 60 * @non_streaming: Count of usecases that can attempt non-streaming D0i3 61 * @non_d0i3: Count of usecases that cannot attempt D0i3 62 * @state: current state 63 * @work: D0i3 worker thread 64 */ 65 struct skl_d0i3_data { 66 int streaming; 67 int non_streaming; 68 int non_d0i3; 69 enum skl_dsp_d0i3_states state; 70 struct delayed_work work; 71 }; 72 73 struct skl_sst { 74 struct device *dev; 75 struct sst_dsp *dsp; 76 77 /* boot */ 78 wait_queue_head_t boot_wait; 79 bool boot_complete; 80 81 /* IPC messaging */ 82 struct sst_generic_ipc ipc; 83 84 /* callback for miscbdge */ 85 void (*enable_miscbdcge)(struct device *dev, bool enable); 86 /* Is CGCTL.MISCBDCGE disabled */ 87 bool miscbdcg_disabled; 88 89 /* Populate module information */ 90 struct list_head uuid_list; 91 92 /* Is firmware loaded */ 93 bool fw_loaded; 94 95 /* first boot ? */ 96 bool is_first_boot; 97 98 /* multi-core */ 99 struct skl_dsp_cores cores; 100 101 /* tplg manifest */ 102 struct skl_dfw_manifest manifest; 103 104 /* Callback to update D0i3C register */ 105 void (*update_d0i3c)(struct device *dev, bool enable); 106 107 struct skl_d0i3_data d0i3; 108 }; 109 110 struct skl_ipc_init_instance_msg { 111 u32 module_id; 112 u32 instance_id; 113 u16 param_data_size; 114 u8 ppl_instance_id; 115 u8 core_id; 116 u8 domain; 117 }; 118 119 struct skl_ipc_bind_unbind_msg { 120 u32 module_id; 121 u32 instance_id; 122 u32 dst_module_id; 123 u32 dst_instance_id; 124 u8 src_queue; 125 u8 dst_queue; 126 bool bind; 127 }; 128 129 struct skl_ipc_large_config_msg { 130 u32 module_id; 131 u32 instance_id; 132 u32 large_param_id; 133 u32 param_data_size; 134 }; 135 136 struct skl_ipc_d0ix_msg { 137 u32 module_id; 138 u32 instance_id; 139 u8 streaming; 140 u8 wake; 141 }; 142 143 #define SKL_IPC_BOOT_MSECS 3000 144 145 #define SKL_IPC_D3_MASK 0 146 #define SKL_IPC_D0_MASK 3 147 148 irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context); 149 150 int skl_ipc_create_pipeline(struct sst_generic_ipc *sst_ipc, 151 u16 ppl_mem_size, u8 ppl_type, u8 instance_id, u8 lp_mode); 152 153 int skl_ipc_delete_pipeline(struct sst_generic_ipc *sst_ipc, u8 instance_id); 154 155 int skl_ipc_set_pipeline_state(struct sst_generic_ipc *sst_ipc, 156 u8 instance_id, enum skl_ipc_pipeline_state state); 157 158 int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc, 159 u8 instance_id, int dma_id); 160 161 int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id); 162 163 int skl_ipc_init_instance(struct sst_generic_ipc *sst_ipc, 164 struct skl_ipc_init_instance_msg *msg, void *param_data); 165 166 int skl_ipc_bind_unbind(struct sst_generic_ipc *sst_ipc, 167 struct skl_ipc_bind_unbind_msg *msg); 168 169 int skl_ipc_load_modules(struct sst_generic_ipc *ipc, 170 u8 module_cnt, void *data); 171 172 int skl_ipc_unload_modules(struct sst_generic_ipc *ipc, 173 u8 module_cnt, void *data); 174 175 int skl_ipc_set_dx(struct sst_generic_ipc *ipc, 176 u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx); 177 178 int skl_ipc_set_large_config(struct sst_generic_ipc *ipc, 179 struct skl_ipc_large_config_msg *msg, u32 *param); 180 181 int skl_ipc_get_large_config(struct sst_generic_ipc *ipc, 182 struct skl_ipc_large_config_msg *msg, u32 *param); 183 184 int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc, 185 u8 dma_id, u8 table_id); 186 187 int skl_ipc_set_d0ix(struct sst_generic_ipc *ipc, 188 struct skl_ipc_d0ix_msg *msg); 189 190 int skl_ipc_check_D0i0(struct sst_dsp *dsp, bool state); 191 192 void skl_ipc_int_enable(struct sst_dsp *dsp); 193 void skl_ipc_op_int_enable(struct sst_dsp *ctx); 194 void skl_ipc_op_int_disable(struct sst_dsp *ctx); 195 void skl_ipc_int_disable(struct sst_dsp *dsp); 196 197 bool skl_ipc_int_status(struct sst_dsp *dsp); 198 void skl_ipc_free(struct sst_generic_ipc *ipc); 199 int skl_ipc_init(struct device *dev, struct skl_sst *skl); 200 void skl_clear_module_cnt(struct sst_dsp *ctx); 201 202 #endif /* __SKL_IPC_H */ 203