1 /* 2 * Intel SKL IPC Support 3 * 4 * Copyright (C) 2014-15, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as version 2, as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 */ 15 16 #ifndef __SKL_IPC_H 17 #define __SKL_IPC_H 18 19 #include <linux/irqreturn.h> 20 #include "../common/sst-ipc.h" 21 22 struct sst_dsp; 23 struct skl_sst; 24 struct sst_generic_ipc; 25 26 enum skl_ipc_pipeline_state { 27 PPL_INVALID_STATE = 0, 28 PPL_UNINITIALIZED = 1, 29 PPL_RESET = 2, 30 PPL_PAUSED = 3, 31 PPL_RUNNING = 4, 32 PPL_ERROR_STOP = 5, 33 PPL_SAVED = 6, 34 PPL_RESTORED = 7 35 }; 36 37 struct skl_ipc_dxstate_info { 38 u32 core_mask; 39 u32 dx_mask; 40 }; 41 42 struct skl_ipc_header { 43 u32 primary; 44 u32 extension; 45 }; 46 47 #define SKL_DSP_CORES_MAX 2 48 49 struct skl_dsp_cores { 50 unsigned int count; 51 enum skl_dsp_states state[SKL_DSP_CORES_MAX]; 52 int usage_count[SKL_DSP_CORES_MAX]; 53 }; 54 55 /** 56 * skl_d0i3_data: skl D0i3 counters data struct 57 * 58 * @streaming: Count of usecases that can attempt streaming D0i3 59 * @non_streaming: Count of usecases that can attempt non-streaming D0i3 60 * @non_d0i3: Count of usecases that cannot attempt D0i3 61 * @state: current state 62 * @work: D0i3 worker thread 63 */ 64 struct skl_d0i3_data { 65 int streaming; 66 int non_streaming; 67 int non_d0i3; 68 enum skl_dsp_d0i3_states state; 69 struct delayed_work work; 70 }; 71 72 struct skl_sst { 73 struct device *dev; 74 struct sst_dsp *dsp; 75 76 /* boot */ 77 wait_queue_head_t boot_wait; 78 bool boot_complete; 79 80 /* IPC messaging */ 81 struct sst_generic_ipc ipc; 82 83 /* callback for miscbdge */ 84 void (*enable_miscbdcge)(struct device *dev, bool enable); 85 /* Is CGCTL.MISCBDCGE disabled */ 86 bool miscbdcg_disabled; 87 88 /* Populate module information */ 89 struct list_head uuid_list; 90 91 /* Is firmware loaded */ 92 bool fw_loaded; 93 94 /* first boot ? */ 95 bool is_first_boot; 96 97 /* multi-core */ 98 struct skl_dsp_cores cores; 99 100 /* tplg manifest */ 101 struct skl_dfw_manifest manifest; 102 103 /* Callback to update D0i3C register */ 104 void (*update_d0i3c)(struct device *dev, bool enable); 105 106 struct skl_d0i3_data d0i3; 107 }; 108 109 struct skl_ipc_init_instance_msg { 110 u32 module_id; 111 u32 instance_id; 112 u16 param_data_size; 113 u8 ppl_instance_id; 114 u8 core_id; 115 u8 domain; 116 }; 117 118 struct skl_ipc_bind_unbind_msg { 119 u32 module_id; 120 u32 instance_id; 121 u32 dst_module_id; 122 u32 dst_instance_id; 123 u8 src_queue; 124 u8 dst_queue; 125 bool bind; 126 }; 127 128 struct skl_ipc_large_config_msg { 129 u32 module_id; 130 u32 instance_id; 131 u32 large_param_id; 132 u32 param_data_size; 133 }; 134 135 struct skl_ipc_d0ix_msg { 136 u32 module_id; 137 u32 instance_id; 138 u8 streaming; 139 u8 wake; 140 }; 141 142 #define SKL_IPC_BOOT_MSECS 3000 143 144 #define SKL_IPC_D3_MASK 0 145 #define SKL_IPC_D0_MASK 3 146 147 irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context); 148 149 int skl_ipc_create_pipeline(struct sst_generic_ipc *sst_ipc, 150 u16 ppl_mem_size, u8 ppl_type, u8 instance_id, u8 lp_mode); 151 152 int skl_ipc_delete_pipeline(struct sst_generic_ipc *sst_ipc, u8 instance_id); 153 154 int skl_ipc_set_pipeline_state(struct sst_generic_ipc *sst_ipc, 155 u8 instance_id, enum skl_ipc_pipeline_state state); 156 157 int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc, 158 u8 instance_id, int dma_id); 159 160 int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id); 161 162 int skl_ipc_init_instance(struct sst_generic_ipc *sst_ipc, 163 struct skl_ipc_init_instance_msg *msg, void *param_data); 164 165 int skl_ipc_bind_unbind(struct sst_generic_ipc *sst_ipc, 166 struct skl_ipc_bind_unbind_msg *msg); 167 168 int skl_ipc_load_modules(struct sst_generic_ipc *ipc, 169 u8 module_cnt, void *data); 170 171 int skl_ipc_unload_modules(struct sst_generic_ipc *ipc, 172 u8 module_cnt, void *data); 173 174 int skl_ipc_set_dx(struct sst_generic_ipc *ipc, 175 u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx); 176 177 int skl_ipc_set_large_config(struct sst_generic_ipc *ipc, 178 struct skl_ipc_large_config_msg *msg, u32 *param); 179 180 int skl_ipc_get_large_config(struct sst_generic_ipc *ipc, 181 struct skl_ipc_large_config_msg *msg, u32 *param); 182 183 int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc, 184 u8 dma_id, u8 table_id); 185 186 int skl_ipc_set_d0ix(struct sst_generic_ipc *ipc, 187 struct skl_ipc_d0ix_msg *msg); 188 189 int skl_ipc_check_D0i0(struct sst_dsp *dsp, bool state); 190 191 void skl_ipc_int_enable(struct sst_dsp *dsp); 192 void skl_ipc_op_int_enable(struct sst_dsp *ctx); 193 void skl_ipc_op_int_disable(struct sst_dsp *ctx); 194 void skl_ipc_int_disable(struct sst_dsp *dsp); 195 196 bool skl_ipc_int_status(struct sst_dsp *dsp); 197 void skl_ipc_free(struct sst_generic_ipc *ipc); 198 int skl_ipc_init(struct device *dev, struct skl_sst *skl); 199 void skl_clear_module_cnt(struct sst_dsp *ctx); 200 201 #endif /* __SKL_IPC_H */ 202