1914426c8SVinod Koul /* 2914426c8SVinod Koul * skl-sst-cldma.c - Code Loader DMA handler 3914426c8SVinod Koul * 4914426c8SVinod Koul * Copyright (C) 2015, Intel Corporation. 5914426c8SVinod Koul * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com> 6914426c8SVinod Koul * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 7914426c8SVinod Koul * 8914426c8SVinod Koul * This program is free software; you can redistribute it and/or modify 9914426c8SVinod Koul * it under the terms of the GNU General Public License as version 2, as 10914426c8SVinod Koul * published by the Free Software Foundation. 11914426c8SVinod Koul * 12914426c8SVinod Koul * This program is distributed in the hope that it will be useful, but 13914426c8SVinod Koul * WITHOUT ANY WARRANTY; without even the implied warranty of 14914426c8SVinod Koul * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15914426c8SVinod Koul * General Public License for more details. 16914426c8SVinod Koul */ 17914426c8SVinod Koul 18914426c8SVinod Koul #include <linux/device.h> 19914426c8SVinod Koul #include <linux/mm.h> 20914426c8SVinod Koul #include <linux/kthread.h> 212434caf0SJeeja KP #include <linux/delay.h> 22914426c8SVinod Koul #include "../common/sst-dsp.h" 23914426c8SVinod Koul #include "../common/sst-dsp-priv.h" 24914426c8SVinod Koul 25914426c8SVinod Koul static void skl_cldma_int_enable(struct sst_dsp *ctx) 26914426c8SVinod Koul { 27914426c8SVinod Koul sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC, 28914426c8SVinod Koul SKL_ADSPIC_CL_DMA, SKL_ADSPIC_CL_DMA); 29914426c8SVinod Koul } 30914426c8SVinod Koul 31914426c8SVinod Koul void skl_cldma_int_disable(struct sst_dsp *ctx) 32914426c8SVinod Koul { 33914426c8SVinod Koul sst_dsp_shim_update_bits_unlocked(ctx, 34914426c8SVinod Koul SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0); 35914426c8SVinod Koul } 36914426c8SVinod Koul 372434caf0SJeeja KP static void skl_cldma_stream_run(struct sst_dsp *ctx, bool enable) 382434caf0SJeeja KP { 392434caf0SJeeja KP unsigned char val; 402434caf0SJeeja KP int timeout; 412434caf0SJeeja KP 422434caf0SJeeja KP sst_dsp_shim_update_bits_unlocked(ctx, 432434caf0SJeeja KP SKL_ADSP_REG_CL_SD_CTL, 442434caf0SJeeja KP CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(enable)); 452434caf0SJeeja KP 462434caf0SJeeja KP udelay(3); 472434caf0SJeeja KP timeout = 300; 482434caf0SJeeja KP do { 492434caf0SJeeja KP /* waiting for hardware to report that the stream Run bit set */ 502434caf0SJeeja KP val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) & 512434caf0SJeeja KP CL_SD_CTL_RUN_MASK; 522434caf0SJeeja KP if (enable && val) 532434caf0SJeeja KP break; 542434caf0SJeeja KP else if (!enable && !val) 552434caf0SJeeja KP break; 562434caf0SJeeja KP udelay(3); 572434caf0SJeeja KP } while (--timeout); 582434caf0SJeeja KP 592434caf0SJeeja KP if (timeout == 0) 602434caf0SJeeja KP dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable); 612434caf0SJeeja KP } 622434caf0SJeeja KP 63a4386450SJeeja KP static void skl_cldma_stream_clear(struct sst_dsp *ctx) 64a4386450SJeeja KP { 65a4386450SJeeja KP /* make sure Run bit is cleared before setting stream register */ 66a4386450SJeeja KP skl_cldma_stream_run(ctx, 0); 67a4386450SJeeja KP 68a4386450SJeeja KP sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, 69a4386450SJeeja KP CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0)); 70a4386450SJeeja KP sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, 71a4386450SJeeja KP CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0)); 72a4386450SJeeja KP sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, 73a4386450SJeeja KP CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0)); 74a4386450SJeeja KP sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, 75a4386450SJeeja KP CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0)); 76a4386450SJeeja KP 77a4386450SJeeja KP sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0)); 78a4386450SJeeja KP sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0); 79a4386450SJeeja KP 80a4386450SJeeja KP sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0); 81a4386450SJeeja KP sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0); 82a4386450SJeeja KP } 83a4386450SJeeja KP 84914426c8SVinod Koul /* Code loader helper APIs */ 85914426c8SVinod Koul static void skl_cldma_setup_bdle(struct sst_dsp *ctx, 86914426c8SVinod Koul struct snd_dma_buffer *dmab_data, 87914426c8SVinod Koul u32 **bdlp, int size, int with_ioc) 88914426c8SVinod Koul { 89914426c8SVinod Koul u32 *bdl = *bdlp; 90914426c8SVinod Koul 91914426c8SVinod Koul ctx->cl_dev.frags = 0; 92914426c8SVinod Koul while (size > 0) { 93914426c8SVinod Koul phys_addr_t addr = virt_to_phys(dmab_data->area + 94914426c8SVinod Koul (ctx->cl_dev.frags * ctx->cl_dev.bufsize)); 95914426c8SVinod Koul 96914426c8SVinod Koul bdl[0] = cpu_to_le32(lower_32_bits(addr)); 97914426c8SVinod Koul bdl[1] = cpu_to_le32(upper_32_bits(addr)); 98914426c8SVinod Koul 99914426c8SVinod Koul bdl[2] = cpu_to_le32(ctx->cl_dev.bufsize); 100914426c8SVinod Koul 101914426c8SVinod Koul size -= ctx->cl_dev.bufsize; 102914426c8SVinod Koul bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 103914426c8SVinod Koul 104914426c8SVinod Koul bdl += 4; 105914426c8SVinod Koul ctx->cl_dev.frags++; 106914426c8SVinod Koul } 107914426c8SVinod Koul } 108914426c8SVinod Koul 109914426c8SVinod Koul /* 110914426c8SVinod Koul * Setup controller 111914426c8SVinod Koul * Configure the registers to update the dma buffer address and 112914426c8SVinod Koul * enable interrupts. 113914426c8SVinod Koul * Note: Using the channel 1 for transfer 114914426c8SVinod Koul */ 115914426c8SVinod Koul static void skl_cldma_setup_controller(struct sst_dsp *ctx, 116914426c8SVinod Koul struct snd_dma_buffer *dmab_bdl, unsigned int max_size, 117914426c8SVinod Koul u32 count) 118914426c8SVinod Koul { 119a4386450SJeeja KP skl_cldma_stream_clear(ctx); 120914426c8SVinod Koul sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, 121914426c8SVinod Koul CL_SD_BDLPLBA(dmab_bdl->addr)); 122914426c8SVinod Koul sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 123914426c8SVinod Koul CL_SD_BDLPUBA(dmab_bdl->addr)); 124914426c8SVinod Koul 125914426c8SVinod Koul sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size); 126914426c8SVinod Koul sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1); 127914426c8SVinod Koul sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, 128914426c8SVinod Koul CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(1)); 129914426c8SVinod Koul sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, 130914426c8SVinod Koul CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(1)); 131914426c8SVinod Koul sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, 132914426c8SVinod Koul CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(1)); 133914426c8SVinod Koul sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, 134914426c8SVinod Koul CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(FW_CL_STREAM_NUMBER)); 135914426c8SVinod Koul } 136914426c8SVinod Koul 137914426c8SVinod Koul static void skl_cldma_setup_spb(struct sst_dsp *ctx, 138914426c8SVinod Koul unsigned int size, bool enable) 139914426c8SVinod Koul { 140914426c8SVinod Koul if (enable) 141914426c8SVinod Koul sst_dsp_shim_update_bits_unlocked(ctx, 142914426c8SVinod Koul SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL, 143914426c8SVinod Koul CL_SPBFIFO_SPBFCCTL_SPIBE_MASK, 144914426c8SVinod Koul CL_SPBFIFO_SPBFCCTL_SPIBE(1)); 145914426c8SVinod Koul 146914426c8SVinod Koul sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size); 147914426c8SVinod Koul } 148914426c8SVinod Koul 149914426c8SVinod Koul static void skl_cldma_cleanup_spb(struct sst_dsp *ctx) 150914426c8SVinod Koul { 151914426c8SVinod Koul sst_dsp_shim_update_bits_unlocked(ctx, 152914426c8SVinod Koul SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL, 153914426c8SVinod Koul CL_SPBFIFO_SPBFCCTL_SPIBE_MASK, 154914426c8SVinod Koul CL_SPBFIFO_SPBFCCTL_SPIBE(0)); 155914426c8SVinod Koul 156914426c8SVinod Koul sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0); 157914426c8SVinod Koul } 158914426c8SVinod Koul 159914426c8SVinod Koul static void skl_cldma_cleanup(struct sst_dsp *ctx) 160914426c8SVinod Koul { 161914426c8SVinod Koul skl_cldma_cleanup_spb(ctx); 162a4386450SJeeja KP skl_cldma_stream_clear(ctx); 163ae395937SJeeja KP 164ae395937SJeeja KP ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data); 165ae395937SJeeja KP ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl); 166914426c8SVinod Koul } 167914426c8SVinod Koul 168914426c8SVinod Koul static int skl_cldma_wait_interruptible(struct sst_dsp *ctx) 169914426c8SVinod Koul { 170914426c8SVinod Koul int ret = 0; 171914426c8SVinod Koul 172914426c8SVinod Koul if (!wait_event_timeout(ctx->cl_dev.wait_queue, 173914426c8SVinod Koul ctx->cl_dev.wait_condition, 174914426c8SVinod Koul msecs_to_jiffies(SKL_WAIT_TIMEOUT))) { 175914426c8SVinod Koul dev_err(ctx->dev, "%s: Wait timeout\n", __func__); 176914426c8SVinod Koul ret = -EIO; 177914426c8SVinod Koul goto cleanup; 178914426c8SVinod Koul } 179914426c8SVinod Koul 180914426c8SVinod Koul dev_dbg(ctx->dev, "%s: Event wake\n", __func__); 181914426c8SVinod Koul if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) { 182914426c8SVinod Koul dev_err(ctx->dev, "%s: DMA Error\n", __func__); 183914426c8SVinod Koul ret = -EIO; 184914426c8SVinod Koul } 185914426c8SVinod Koul 186914426c8SVinod Koul cleanup: 187914426c8SVinod Koul ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE; 188914426c8SVinod Koul return ret; 189914426c8SVinod Koul } 190914426c8SVinod Koul 191914426c8SVinod Koul static void skl_cldma_stop(struct sst_dsp *ctx) 192914426c8SVinod Koul { 1932434caf0SJeeja KP skl_cldma_stream_run(ctx, false); 194914426c8SVinod Koul } 195914426c8SVinod Koul 196914426c8SVinod Koul static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size, 197914426c8SVinod Koul const void *curr_pos, bool intr_enable, bool trigger) 198914426c8SVinod Koul { 199914426c8SVinod Koul dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable); 200914426c8SVinod Koul dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n", 201914426c8SVinod Koul ctx->cl_dev.dma_buffer_offset, trigger); 202914426c8SVinod Koul dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos); 203914426c8SVinod Koul 204e797af53SJeeja KP /* 205e797af53SJeeja KP * Check if the size exceeds buffer boundary. If it exceeds 206e797af53SJeeja KP * max_buffer size, then copy till buffer size and then copy 207e797af53SJeeja KP * remaining buffer from the start of ring buffer. 208e797af53SJeeja KP */ 209e797af53SJeeja KP if (ctx->cl_dev.dma_buffer_offset + size > ctx->cl_dev.bufsize) { 210e797af53SJeeja KP unsigned int size_b = ctx->cl_dev.bufsize - 211e797af53SJeeja KP ctx->cl_dev.dma_buffer_offset; 212e797af53SJeeja KP memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset, 213e797af53SJeeja KP curr_pos, size_b); 214e797af53SJeeja KP size -= size_b; 215e797af53SJeeja KP curr_pos += size_b; 216e797af53SJeeja KP ctx->cl_dev.dma_buffer_offset = 0; 217e797af53SJeeja KP } 218e797af53SJeeja KP 219914426c8SVinod Koul memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset, 220914426c8SVinod Koul curr_pos, size); 221914426c8SVinod Koul 222914426c8SVinod Koul if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize) 223914426c8SVinod Koul ctx->cl_dev.dma_buffer_offset = 0; 224914426c8SVinod Koul else 225914426c8SVinod Koul ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos; 226914426c8SVinod Koul 227914426c8SVinod Koul ctx->cl_dev.wait_condition = false; 228914426c8SVinod Koul 229914426c8SVinod Koul if (intr_enable) 230914426c8SVinod Koul skl_cldma_int_enable(ctx); 231914426c8SVinod Koul 232914426c8SVinod Koul ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger); 233914426c8SVinod Koul if (trigger) 234914426c8SVinod Koul ctx->cl_dev.ops.cl_trigger(ctx, true); 235914426c8SVinod Koul } 2363e40a784SVinod Koul 2373e40a784SVinod Koul /* 2383e40a784SVinod Koul * The CL dma doesn't have any way to update the transfer status until a BDL 2393e40a784SVinod Koul * buffer is fully transferred 2403e40a784SVinod Koul * 2413e40a784SVinod Koul * So Copying is divided in two parts. 2423e40a784SVinod Koul * 1. Interrupt on buffer done where the size to be transferred is more than 2433e40a784SVinod Koul * ring buffer size. 2443e40a784SVinod Koul * 2. Polling on fw register to identify if data left to transferred doesn't 2453e40a784SVinod Koul * fill the ring buffer. Caller takes care of polling the required status 2463e40a784SVinod Koul * register to identify the transfer status. 2473e40a784SVinod Koul */ 2483e40a784SVinod Koul static int 2493e40a784SVinod Koul skl_cldma_copy_to_buf(struct sst_dsp *ctx, const void *bin, u32 total_size) 2503e40a784SVinod Koul { 2513e40a784SVinod Koul int ret = 0; 2523e40a784SVinod Koul bool start = true; 2533e40a784SVinod Koul unsigned int excess_bytes; 2543e40a784SVinod Koul u32 size; 2553e40a784SVinod Koul unsigned int bytes_left = total_size; 2563e40a784SVinod Koul const void *curr_pos = bin; 2573e40a784SVinod Koul 2583e40a784SVinod Koul if (total_size <= 0) 2593e40a784SVinod Koul return -EINVAL; 2603e40a784SVinod Koul 2613e40a784SVinod Koul dev_dbg(ctx->dev, "%s: Total binary size: %u\n", __func__, bytes_left); 2623e40a784SVinod Koul 2633e40a784SVinod Koul while (bytes_left) { 2643e40a784SVinod Koul if (bytes_left > ctx->cl_dev.bufsize) { 2653e40a784SVinod Koul 2663e40a784SVinod Koul /* 2673e40a784SVinod Koul * dma transfers only till the write pointer as 2683e40a784SVinod Koul * updated in spib 2693e40a784SVinod Koul */ 2703e40a784SVinod Koul if (ctx->cl_dev.curr_spib_pos == 0) 2713e40a784SVinod Koul ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize; 2723e40a784SVinod Koul 2733e40a784SVinod Koul size = ctx->cl_dev.bufsize; 2743e40a784SVinod Koul skl_cldma_fill_buffer(ctx, size, curr_pos, true, start); 2753e40a784SVinod Koul 2763e40a784SVinod Koul start = false; 2773e40a784SVinod Koul ret = skl_cldma_wait_interruptible(ctx); 2783e40a784SVinod Koul if (ret < 0) { 2793e40a784SVinod Koul skl_cldma_stop(ctx); 2803e40a784SVinod Koul return ret; 2813e40a784SVinod Koul } 2823e40a784SVinod Koul 2833e40a784SVinod Koul } else { 2843e40a784SVinod Koul skl_cldma_int_disable(ctx); 2853e40a784SVinod Koul 2863e40a784SVinod Koul if ((ctx->cl_dev.curr_spib_pos + bytes_left) 2873e40a784SVinod Koul <= ctx->cl_dev.bufsize) { 2883e40a784SVinod Koul ctx->cl_dev.curr_spib_pos += bytes_left; 2893e40a784SVinod Koul } else { 2903e40a784SVinod Koul excess_bytes = bytes_left - 2913e40a784SVinod Koul (ctx->cl_dev.bufsize - 2923e40a784SVinod Koul ctx->cl_dev.curr_spib_pos); 2933e40a784SVinod Koul ctx->cl_dev.curr_spib_pos = excess_bytes; 2943e40a784SVinod Koul } 2953e40a784SVinod Koul 2963e40a784SVinod Koul size = bytes_left; 2973e40a784SVinod Koul skl_cldma_fill_buffer(ctx, size, 2983e40a784SVinod Koul curr_pos, false, start); 2993e40a784SVinod Koul } 3003e40a784SVinod Koul bytes_left -= size; 3013e40a784SVinod Koul curr_pos = curr_pos + size; 3023e40a784SVinod Koul } 3033e40a784SVinod Koul 3043e40a784SVinod Koul return ret; 3053e40a784SVinod Koul } 3063e40a784SVinod Koul 3073e40a784SVinod Koul void skl_cldma_process_intr(struct sst_dsp *ctx) 3083e40a784SVinod Koul { 3093e40a784SVinod Koul u8 cl_dma_intr_status; 3103e40a784SVinod Koul 3113e40a784SVinod Koul cl_dma_intr_status = 3123e40a784SVinod Koul sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_CL_SD_STS); 3133e40a784SVinod Koul 3143e40a784SVinod Koul if (!(cl_dma_intr_status & SKL_CL_DMA_SD_INT_COMPLETE)) 3153e40a784SVinod Koul ctx->cl_dev.wake_status = SKL_CL_DMA_ERR; 3163e40a784SVinod Koul else 3173e40a784SVinod Koul ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE; 3183e40a784SVinod Koul 3193e40a784SVinod Koul ctx->cl_dev.wait_condition = true; 3203e40a784SVinod Koul wake_up(&ctx->cl_dev.wait_queue); 3213e40a784SVinod Koul } 3223e40a784SVinod Koul 3233e40a784SVinod Koul int skl_cldma_prepare(struct sst_dsp *ctx) 3243e40a784SVinod Koul { 3253e40a784SVinod Koul int ret; 3263e40a784SVinod Koul u32 *bdl; 3273e40a784SVinod Koul 3283e40a784SVinod Koul ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE; 3293e40a784SVinod Koul 3303e40a784SVinod Koul /* Allocate cl ops */ 3313e40a784SVinod Koul ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle; 3323e40a784SVinod Koul ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller; 3333e40a784SVinod Koul ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb; 3343e40a784SVinod Koul ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb; 3352434caf0SJeeja KP ctx->cl_dev.ops.cl_trigger = skl_cldma_stream_run; 3363e40a784SVinod Koul ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup; 3373e40a784SVinod Koul ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf; 3383e40a784SVinod Koul ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop; 3393e40a784SVinod Koul 3403e40a784SVinod Koul /* Allocate buffer*/ 3413e40a784SVinod Koul ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev, 3423e40a784SVinod Koul &ctx->cl_dev.dmab_data, ctx->cl_dev.bufsize); 3433e40a784SVinod Koul if (ret < 0) { 344ecd286a9SColin Ian King dev_err(ctx->dev, "Alloc buffer for base fw failed: %x\n", ret); 3453e40a784SVinod Koul return ret; 3463e40a784SVinod Koul } 3473e40a784SVinod Koul /* Setup Code loader BDL */ 3483e40a784SVinod Koul ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev, 3493e40a784SVinod Koul &ctx->cl_dev.dmab_bdl, PAGE_SIZE); 3503e40a784SVinod Koul if (ret < 0) { 351ecd286a9SColin Ian King dev_err(ctx->dev, "Alloc buffer for blde failed: %x\n", ret); 3523e40a784SVinod Koul ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data); 3533e40a784SVinod Koul return ret; 3543e40a784SVinod Koul } 3553e40a784SVinod Koul bdl = (u32 *)ctx->cl_dev.dmab_bdl.area; 3563e40a784SVinod Koul 3573e40a784SVinod Koul /* Allocate BDLs */ 3583e40a784SVinod Koul ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data, 3593e40a784SVinod Koul &bdl, ctx->cl_dev.bufsize, 1); 3603e40a784SVinod Koul ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl, 3613e40a784SVinod Koul ctx->cl_dev.bufsize, ctx->cl_dev.frags); 3623e40a784SVinod Koul 3633e40a784SVinod Koul ctx->cl_dev.curr_spib_pos = 0; 3643e40a784SVinod Koul ctx->cl_dev.dma_buffer_offset = 0; 3653e40a784SVinod Koul init_waitqueue_head(&ctx->cl_dev.wait_queue); 3663e40a784SVinod Koul 3673e40a784SVinod Koul return ret; 3683e40a784SVinod Koul } 369