1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * skl-sst-cldma.c - Code Loader DMA handler
4 *
5 * Copyright (C) 2015, Intel Corporation.
6 * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 */
9
10 #include <linux/device.h>
11 #include <linux/io.h>
12 #include <linux/mm.h>
13 #include <linux/delay.h>
14 #include <sound/hda_register.h>
15 #include "../common/sst-dsp.h"
16 #include "../common/sst-dsp-priv.h"
17
skl_cldma_int_enable(struct sst_dsp * ctx)18 static void skl_cldma_int_enable(struct sst_dsp *ctx)
19 {
20 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
21 SKL_ADSPIC_CL_DMA, SKL_ADSPIC_CL_DMA);
22 }
23
skl_cldma_int_disable(struct sst_dsp * ctx)24 void skl_cldma_int_disable(struct sst_dsp *ctx)
25 {
26 sst_dsp_shim_update_bits_unlocked(ctx,
27 SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0);
28 }
29
skl_cldma_stream_run(struct sst_dsp * ctx,bool enable)30 static void skl_cldma_stream_run(struct sst_dsp *ctx, bool enable)
31 {
32 unsigned char val;
33 int timeout;
34
35 sst_dsp_shim_update_bits_unlocked(ctx,
36 SKL_ADSP_REG_CL_SD_CTL,
37 CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(enable));
38
39 udelay(3);
40 timeout = 300;
41 do {
42 /* waiting for hardware to report that the stream Run bit set */
43 val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) &
44 CL_SD_CTL_RUN_MASK;
45 if (enable && val)
46 break;
47 else if (!enable && !val)
48 break;
49 udelay(3);
50 } while (--timeout);
51
52 if (timeout == 0)
53 dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);
54 }
55
skl_cldma_stream_clear(struct sst_dsp * ctx)56 static void skl_cldma_stream_clear(struct sst_dsp *ctx)
57 {
58 /* make sure Run bit is cleared before setting stream register */
59 skl_cldma_stream_run(ctx, 0);
60
61 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
62 CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
63 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
64 CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
65 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
66 CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
67 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
68 CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));
69
70 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
71 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
72
73 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
74 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
75 }
76
77 /* Code loader helper APIs */
skl_cldma_setup_bdle(struct sst_dsp * ctx,struct snd_dma_buffer * dmab_data,__le32 ** bdlp,int size,int with_ioc)78 static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
79 struct snd_dma_buffer *dmab_data,
80 __le32 **bdlp, int size, int with_ioc)
81 {
82 __le32 *bdl = *bdlp;
83 int remaining = ctx->cl_dev.bufsize;
84 int offset = 0;
85
86 ctx->cl_dev.frags = 0;
87 while (remaining > 0) {
88 phys_addr_t addr;
89 int chunk;
90
91 addr = snd_sgbuf_get_addr(dmab_data, offset);
92 bdl[0] = cpu_to_le32(lower_32_bits(addr));
93 bdl[1] = cpu_to_le32(upper_32_bits(addr));
94 chunk = snd_sgbuf_get_chunk_size(dmab_data, offset, size);
95 bdl[2] = cpu_to_le32(chunk);
96
97 remaining -= chunk;
98 bdl[3] = (remaining > 0) ? 0 : cpu_to_le32(0x01);
99
100 bdl += 4;
101 offset += chunk;
102 ctx->cl_dev.frags++;
103 }
104 }
105
106 /*
107 * Setup controller
108 * Configure the registers to update the dma buffer address and
109 * enable interrupts.
110 * Note: Using the channel 1 for transfer
111 */
skl_cldma_setup_controller(struct sst_dsp * ctx,struct snd_dma_buffer * dmab_bdl,unsigned int max_size,u32 count)112 static void skl_cldma_setup_controller(struct sst_dsp *ctx,
113 struct snd_dma_buffer *dmab_bdl, unsigned int max_size,
114 u32 count)
115 {
116 skl_cldma_stream_clear(ctx);
117 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
118 CL_SD_BDLPLBA(dmab_bdl->addr));
119 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
120 CL_SD_BDLPUBA(dmab_bdl->addr));
121
122 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size);
123 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1);
124 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
125 CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(1));
126 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
127 CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(1));
128 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
129 CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(1));
130 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
131 CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(FW_CL_STREAM_NUMBER));
132 }
133
skl_cldma_setup_spb(struct sst_dsp * ctx,unsigned int size,bool enable)134 static void skl_cldma_setup_spb(struct sst_dsp *ctx,
135 unsigned int size, bool enable)
136 {
137 if (enable)
138 sst_dsp_shim_update_bits_unlocked(ctx,
139 SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
140 CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
141 CL_SPBFIFO_SPBFCCTL_SPIBE(1));
142
143 sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size);
144 }
145
skl_cldma_cleanup_spb(struct sst_dsp * ctx)146 static void skl_cldma_cleanup_spb(struct sst_dsp *ctx)
147 {
148 sst_dsp_shim_update_bits_unlocked(ctx,
149 SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
150 CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
151 CL_SPBFIFO_SPBFCCTL_SPIBE(0));
152
153 sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
154 }
155
skl_cldma_cleanup(struct sst_dsp * ctx)156 static void skl_cldma_cleanup(struct sst_dsp *ctx)
157 {
158 skl_cldma_cleanup_spb(ctx);
159 skl_cldma_stream_clear(ctx);
160
161 ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
162 ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);
163 }
164
skl_cldma_wait_interruptible(struct sst_dsp * ctx)165 int skl_cldma_wait_interruptible(struct sst_dsp *ctx)
166 {
167 int ret = 0;
168
169 if (!wait_event_timeout(ctx->cl_dev.wait_queue,
170 ctx->cl_dev.wait_condition,
171 msecs_to_jiffies(SKL_WAIT_TIMEOUT))) {
172 dev_err(ctx->dev, "%s: Wait timeout\n", __func__);
173 ret = -EIO;
174 goto cleanup;
175 }
176
177 dev_dbg(ctx->dev, "%s: Event wake\n", __func__);
178 if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {
179 dev_err(ctx->dev, "%s: DMA Error\n", __func__);
180 ret = -EIO;
181 }
182
183 cleanup:
184 ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;
185 return ret;
186 }
187
skl_cldma_stop(struct sst_dsp * ctx)188 static void skl_cldma_stop(struct sst_dsp *ctx)
189 {
190 skl_cldma_stream_run(ctx, false);
191 }
192
skl_cldma_fill_buffer(struct sst_dsp * ctx,unsigned int size,const void * curr_pos,bool intr_enable,bool trigger)193 static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
194 const void *curr_pos, bool intr_enable, bool trigger)
195 {
196 dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable);
197 dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n",
198 ctx->cl_dev.dma_buffer_offset, trigger);
199 dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);
200
201 /*
202 * Check if the size exceeds buffer boundary. If it exceeds
203 * max_buffer size, then copy till buffer size and then copy
204 * remaining buffer from the start of ring buffer.
205 */
206 if (ctx->cl_dev.dma_buffer_offset + size > ctx->cl_dev.bufsize) {
207 unsigned int size_b = ctx->cl_dev.bufsize -
208 ctx->cl_dev.dma_buffer_offset;
209 memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
210 curr_pos, size_b);
211 size -= size_b;
212 curr_pos += size_b;
213 ctx->cl_dev.dma_buffer_offset = 0;
214 }
215
216 memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
217 curr_pos, size);
218
219 if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)
220 ctx->cl_dev.dma_buffer_offset = 0;
221 else
222 ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;
223
224 ctx->cl_dev.wait_condition = false;
225
226 if (intr_enable)
227 skl_cldma_int_enable(ctx);
228
229 ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);
230 if (trigger)
231 ctx->cl_dev.ops.cl_trigger(ctx, true);
232 }
233
234 /*
235 * The CL dma doesn't have any way to update the transfer status until a BDL
236 * buffer is fully transferred
237 *
238 * So Copying is divided in two parts.
239 * 1. Interrupt on buffer done where the size to be transferred is more than
240 * ring buffer size.
241 * 2. Polling on fw register to identify if data left to transferred doesn't
242 * fill the ring buffer. Caller takes care of polling the required status
243 * register to identify the transfer status.
244 * 3. if wait flag is set, waits for DBL interrupt to copy the next chunk till
245 * bytes_left is 0.
246 * if wait flag is not set, doesn't wait for BDL interrupt. after ccopying
247 * the first chunk return the no of bytes_left to be copied.
248 */
249 static int
skl_cldma_copy_to_buf(struct sst_dsp * ctx,const void * bin,u32 total_size,bool wait)250 skl_cldma_copy_to_buf(struct sst_dsp *ctx, const void *bin,
251 u32 total_size, bool wait)
252 {
253 int ret;
254 bool start = true;
255 unsigned int excess_bytes;
256 u32 size;
257 unsigned int bytes_left = total_size;
258 const void *curr_pos = bin;
259
260 if (total_size <= 0)
261 return -EINVAL;
262
263 dev_dbg(ctx->dev, "%s: Total binary size: %u\n", __func__, bytes_left);
264
265 while (bytes_left) {
266 if (bytes_left > ctx->cl_dev.bufsize) {
267
268 /*
269 * dma transfers only till the write pointer as
270 * updated in spib
271 */
272 if (ctx->cl_dev.curr_spib_pos == 0)
273 ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize;
274
275 size = ctx->cl_dev.bufsize;
276 skl_cldma_fill_buffer(ctx, size, curr_pos, true, start);
277
278 if (wait) {
279 start = false;
280 ret = skl_cldma_wait_interruptible(ctx);
281 if (ret < 0) {
282 skl_cldma_stop(ctx);
283 return ret;
284 }
285 }
286 } else {
287 skl_cldma_int_disable(ctx);
288
289 if ((ctx->cl_dev.curr_spib_pos + bytes_left)
290 <= ctx->cl_dev.bufsize) {
291 ctx->cl_dev.curr_spib_pos += bytes_left;
292 } else {
293 excess_bytes = bytes_left -
294 (ctx->cl_dev.bufsize -
295 ctx->cl_dev.curr_spib_pos);
296 ctx->cl_dev.curr_spib_pos = excess_bytes;
297 }
298
299 size = bytes_left;
300 skl_cldma_fill_buffer(ctx, size,
301 curr_pos, false, start);
302 }
303 bytes_left -= size;
304 curr_pos = curr_pos + size;
305 if (!wait)
306 return bytes_left;
307 }
308
309 return bytes_left;
310 }
311
skl_cldma_process_intr(struct sst_dsp * ctx)312 void skl_cldma_process_intr(struct sst_dsp *ctx)
313 {
314 u8 cl_dma_intr_status;
315
316 cl_dma_intr_status =
317 sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_CL_SD_STS);
318
319 if (!(cl_dma_intr_status & SKL_CL_DMA_SD_INT_COMPLETE))
320 ctx->cl_dev.wake_status = SKL_CL_DMA_ERR;
321 else
322 ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE;
323
324 ctx->cl_dev.wait_condition = true;
325 wake_up(&ctx->cl_dev.wait_queue);
326 }
327
skl_cldma_prepare(struct sst_dsp * ctx)328 int skl_cldma_prepare(struct sst_dsp *ctx)
329 {
330 int ret;
331 __le32 *bdl;
332
333 ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE;
334
335 /* Allocate cl ops */
336 ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle;
337 ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
338 ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
339 ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
340 ctx->cl_dev.ops.cl_trigger = skl_cldma_stream_run;
341 ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
342 ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
343 ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
344
345 /* Allocate buffer*/
346 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, ctx->dev, ctx->cl_dev.bufsize,
347 &ctx->cl_dev.dmab_data);
348 if (ret < 0) {
349 dev_err(ctx->dev, "Alloc buffer for base fw failed: %x\n", ret);
350 return ret;
351 }
352
353 /* Setup Code loader BDL */
354 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, ctx->dev, BDL_SIZE, &ctx->cl_dev.dmab_bdl);
355 if (ret < 0) {
356 dev_err(ctx->dev, "Alloc buffer for blde failed: %x\n", ret);
357 ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
358 return ret;
359 }
360 bdl = (__le32 *)ctx->cl_dev.dmab_bdl.area;
361
362 /* Allocate BDLs */
363 ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data,
364 &bdl, ctx->cl_dev.bufsize, 1);
365 ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl,
366 ctx->cl_dev.bufsize, ctx->cl_dev.frags);
367
368 ctx->cl_dev.curr_spib_pos = 0;
369 ctx->cl_dev.dma_buffer_offset = 0;
370 init_waitqueue_head(&ctx->cl_dev.wait_queue);
371
372 return ret;
373 }
374