147d7195dSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2914426c8SVinod Koul /*
3914426c8SVinod Koul * skl-sst-cldma.c - Code Loader DMA handler
4914426c8SVinod Koul *
5914426c8SVinod Koul * Copyright (C) 2015, Intel Corporation.
6914426c8SVinod Koul * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
7914426c8SVinod Koul * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8914426c8SVinod Koul */
9914426c8SVinod Koul
10914426c8SVinod Koul #include <linux/device.h>
11321354baSSean Christopherson #include <linux/io.h>
12914426c8SVinod Koul #include <linux/mm.h>
132434caf0SJeeja KP #include <linux/delay.h>
14*451d85c4SCezary Rojewski #include <sound/hda_register.h>
15914426c8SVinod Koul #include "../common/sst-dsp.h"
16914426c8SVinod Koul #include "../common/sst-dsp-priv.h"
17914426c8SVinod Koul
skl_cldma_int_enable(struct sst_dsp * ctx)18914426c8SVinod Koul static void skl_cldma_int_enable(struct sst_dsp *ctx)
19914426c8SVinod Koul {
20914426c8SVinod Koul sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
21914426c8SVinod Koul SKL_ADSPIC_CL_DMA, SKL_ADSPIC_CL_DMA);
22914426c8SVinod Koul }
23914426c8SVinod Koul
skl_cldma_int_disable(struct sst_dsp * ctx)24914426c8SVinod Koul void skl_cldma_int_disable(struct sst_dsp *ctx)
25914426c8SVinod Koul {
26914426c8SVinod Koul sst_dsp_shim_update_bits_unlocked(ctx,
27914426c8SVinod Koul SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0);
28914426c8SVinod Koul }
29914426c8SVinod Koul
skl_cldma_stream_run(struct sst_dsp * ctx,bool enable)302434caf0SJeeja KP static void skl_cldma_stream_run(struct sst_dsp *ctx, bool enable)
312434caf0SJeeja KP {
322434caf0SJeeja KP unsigned char val;
332434caf0SJeeja KP int timeout;
342434caf0SJeeja KP
352434caf0SJeeja KP sst_dsp_shim_update_bits_unlocked(ctx,
362434caf0SJeeja KP SKL_ADSP_REG_CL_SD_CTL,
372434caf0SJeeja KP CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(enable));
382434caf0SJeeja KP
392434caf0SJeeja KP udelay(3);
402434caf0SJeeja KP timeout = 300;
412434caf0SJeeja KP do {
422434caf0SJeeja KP /* waiting for hardware to report that the stream Run bit set */
432434caf0SJeeja KP val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) &
442434caf0SJeeja KP CL_SD_CTL_RUN_MASK;
452434caf0SJeeja KP if (enable && val)
462434caf0SJeeja KP break;
472434caf0SJeeja KP else if (!enable && !val)
482434caf0SJeeja KP break;
492434caf0SJeeja KP udelay(3);
502434caf0SJeeja KP } while (--timeout);
512434caf0SJeeja KP
522434caf0SJeeja KP if (timeout == 0)
532434caf0SJeeja KP dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);
542434caf0SJeeja KP }
552434caf0SJeeja KP
skl_cldma_stream_clear(struct sst_dsp * ctx)56a4386450SJeeja KP static void skl_cldma_stream_clear(struct sst_dsp *ctx)
57a4386450SJeeja KP {
58a4386450SJeeja KP /* make sure Run bit is cleared before setting stream register */
59a4386450SJeeja KP skl_cldma_stream_run(ctx, 0);
60a4386450SJeeja KP
61a4386450SJeeja KP sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
62a4386450SJeeja KP CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
63a4386450SJeeja KP sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
64a4386450SJeeja KP CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
65a4386450SJeeja KP sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
66a4386450SJeeja KP CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
67a4386450SJeeja KP sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
68a4386450SJeeja KP CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));
69a4386450SJeeja KP
70a4386450SJeeja KP sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
71a4386450SJeeja KP sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
72a4386450SJeeja KP
73a4386450SJeeja KP sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
74a4386450SJeeja KP sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
75a4386450SJeeja KP }
76a4386450SJeeja KP
77914426c8SVinod Koul /* Code loader helper APIs */
skl_cldma_setup_bdle(struct sst_dsp * ctx,struct snd_dma_buffer * dmab_data,__le32 ** bdlp,int size,int with_ioc)78914426c8SVinod Koul static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
79914426c8SVinod Koul struct snd_dma_buffer *dmab_data,
8086efd35eSPierre-Louis Bossart __le32 **bdlp, int size, int with_ioc)
81914426c8SVinod Koul {
8286efd35eSPierre-Louis Bossart __le32 *bdl = *bdlp;
83*451d85c4SCezary Rojewski int remaining = ctx->cl_dev.bufsize;
84*451d85c4SCezary Rojewski int offset = 0;
85914426c8SVinod Koul
86914426c8SVinod Koul ctx->cl_dev.frags = 0;
87*451d85c4SCezary Rojewski while (remaining > 0) {
88*451d85c4SCezary Rojewski phys_addr_t addr;
89*451d85c4SCezary Rojewski int chunk;
90914426c8SVinod Koul
91*451d85c4SCezary Rojewski addr = snd_sgbuf_get_addr(dmab_data, offset);
92914426c8SVinod Koul bdl[0] = cpu_to_le32(lower_32_bits(addr));
93914426c8SVinod Koul bdl[1] = cpu_to_le32(upper_32_bits(addr));
94*451d85c4SCezary Rojewski chunk = snd_sgbuf_get_chunk_size(dmab_data, offset, size);
95*451d85c4SCezary Rojewski bdl[2] = cpu_to_le32(chunk);
96914426c8SVinod Koul
97*451d85c4SCezary Rojewski remaining -= chunk;
98*451d85c4SCezary Rojewski bdl[3] = (remaining > 0) ? 0 : cpu_to_le32(0x01);
99914426c8SVinod Koul
100914426c8SVinod Koul bdl += 4;
101*451d85c4SCezary Rojewski offset += chunk;
102914426c8SVinod Koul ctx->cl_dev.frags++;
103914426c8SVinod Koul }
104914426c8SVinod Koul }
105914426c8SVinod Koul
106914426c8SVinod Koul /*
107914426c8SVinod Koul * Setup controller
108914426c8SVinod Koul * Configure the registers to update the dma buffer address and
109914426c8SVinod Koul * enable interrupts.
110914426c8SVinod Koul * Note: Using the channel 1 for transfer
111914426c8SVinod Koul */
skl_cldma_setup_controller(struct sst_dsp * ctx,struct snd_dma_buffer * dmab_bdl,unsigned int max_size,u32 count)112914426c8SVinod Koul static void skl_cldma_setup_controller(struct sst_dsp *ctx,
113914426c8SVinod Koul struct snd_dma_buffer *dmab_bdl, unsigned int max_size,
114914426c8SVinod Koul u32 count)
115914426c8SVinod Koul {
116a4386450SJeeja KP skl_cldma_stream_clear(ctx);
117914426c8SVinod Koul sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
118914426c8SVinod Koul CL_SD_BDLPLBA(dmab_bdl->addr));
119914426c8SVinod Koul sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
120914426c8SVinod Koul CL_SD_BDLPUBA(dmab_bdl->addr));
121914426c8SVinod Koul
122914426c8SVinod Koul sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size);
123914426c8SVinod Koul sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1);
124914426c8SVinod Koul sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
125914426c8SVinod Koul CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(1));
126914426c8SVinod Koul sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
127914426c8SVinod Koul CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(1));
128914426c8SVinod Koul sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
129914426c8SVinod Koul CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(1));
130914426c8SVinod Koul sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
131914426c8SVinod Koul CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(FW_CL_STREAM_NUMBER));
132914426c8SVinod Koul }
133914426c8SVinod Koul
skl_cldma_setup_spb(struct sst_dsp * ctx,unsigned int size,bool enable)134914426c8SVinod Koul static void skl_cldma_setup_spb(struct sst_dsp *ctx,
135914426c8SVinod Koul unsigned int size, bool enable)
136914426c8SVinod Koul {
137914426c8SVinod Koul if (enable)
138914426c8SVinod Koul sst_dsp_shim_update_bits_unlocked(ctx,
139914426c8SVinod Koul SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
140914426c8SVinod Koul CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
141914426c8SVinod Koul CL_SPBFIFO_SPBFCCTL_SPIBE(1));
142914426c8SVinod Koul
143914426c8SVinod Koul sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size);
144914426c8SVinod Koul }
145914426c8SVinod Koul
skl_cldma_cleanup_spb(struct sst_dsp * ctx)146914426c8SVinod Koul static void skl_cldma_cleanup_spb(struct sst_dsp *ctx)
147914426c8SVinod Koul {
148914426c8SVinod Koul sst_dsp_shim_update_bits_unlocked(ctx,
149914426c8SVinod Koul SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
150914426c8SVinod Koul CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
151914426c8SVinod Koul CL_SPBFIFO_SPBFCCTL_SPIBE(0));
152914426c8SVinod Koul
153914426c8SVinod Koul sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
154914426c8SVinod Koul }
155914426c8SVinod Koul
skl_cldma_cleanup(struct sst_dsp * ctx)156914426c8SVinod Koul static void skl_cldma_cleanup(struct sst_dsp *ctx)
157914426c8SVinod Koul {
158914426c8SVinod Koul skl_cldma_cleanup_spb(ctx);
159a4386450SJeeja KP skl_cldma_stream_clear(ctx);
160ae395937SJeeja KP
161ae395937SJeeja KP ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
162ae395937SJeeja KP ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);
163914426c8SVinod Koul }
164914426c8SVinod Koul
skl_cldma_wait_interruptible(struct sst_dsp * ctx)165b7d0254cSJeeja KP int skl_cldma_wait_interruptible(struct sst_dsp *ctx)
166914426c8SVinod Koul {
167914426c8SVinod Koul int ret = 0;
168914426c8SVinod Koul
169914426c8SVinod Koul if (!wait_event_timeout(ctx->cl_dev.wait_queue,
170914426c8SVinod Koul ctx->cl_dev.wait_condition,
171914426c8SVinod Koul msecs_to_jiffies(SKL_WAIT_TIMEOUT))) {
172914426c8SVinod Koul dev_err(ctx->dev, "%s: Wait timeout\n", __func__);
173914426c8SVinod Koul ret = -EIO;
174914426c8SVinod Koul goto cleanup;
175914426c8SVinod Koul }
176914426c8SVinod Koul
177914426c8SVinod Koul dev_dbg(ctx->dev, "%s: Event wake\n", __func__);
178914426c8SVinod Koul if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {
179914426c8SVinod Koul dev_err(ctx->dev, "%s: DMA Error\n", __func__);
180914426c8SVinod Koul ret = -EIO;
181914426c8SVinod Koul }
182914426c8SVinod Koul
183914426c8SVinod Koul cleanup:
184914426c8SVinod Koul ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;
185914426c8SVinod Koul return ret;
186914426c8SVinod Koul }
187914426c8SVinod Koul
skl_cldma_stop(struct sst_dsp * ctx)188914426c8SVinod Koul static void skl_cldma_stop(struct sst_dsp *ctx)
189914426c8SVinod Koul {
1902434caf0SJeeja KP skl_cldma_stream_run(ctx, false);
191914426c8SVinod Koul }
192914426c8SVinod Koul
skl_cldma_fill_buffer(struct sst_dsp * ctx,unsigned int size,const void * curr_pos,bool intr_enable,bool trigger)193914426c8SVinod Koul static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
194914426c8SVinod Koul const void *curr_pos, bool intr_enable, bool trigger)
195914426c8SVinod Koul {
196914426c8SVinod Koul dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable);
197914426c8SVinod Koul dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n",
198914426c8SVinod Koul ctx->cl_dev.dma_buffer_offset, trigger);
199914426c8SVinod Koul dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);
200914426c8SVinod Koul
201e797af53SJeeja KP /*
202e797af53SJeeja KP * Check if the size exceeds buffer boundary. If it exceeds
203e797af53SJeeja KP * max_buffer size, then copy till buffer size and then copy
204e797af53SJeeja KP * remaining buffer from the start of ring buffer.
205e797af53SJeeja KP */
206e797af53SJeeja KP if (ctx->cl_dev.dma_buffer_offset + size > ctx->cl_dev.bufsize) {
207e797af53SJeeja KP unsigned int size_b = ctx->cl_dev.bufsize -
208e797af53SJeeja KP ctx->cl_dev.dma_buffer_offset;
209e797af53SJeeja KP memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
210e797af53SJeeja KP curr_pos, size_b);
211e797af53SJeeja KP size -= size_b;
212e797af53SJeeja KP curr_pos += size_b;
213e797af53SJeeja KP ctx->cl_dev.dma_buffer_offset = 0;
214e797af53SJeeja KP }
215e797af53SJeeja KP
216914426c8SVinod Koul memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
217914426c8SVinod Koul curr_pos, size);
218914426c8SVinod Koul
219914426c8SVinod Koul if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)
220914426c8SVinod Koul ctx->cl_dev.dma_buffer_offset = 0;
221914426c8SVinod Koul else
222914426c8SVinod Koul ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;
223914426c8SVinod Koul
224914426c8SVinod Koul ctx->cl_dev.wait_condition = false;
225914426c8SVinod Koul
226914426c8SVinod Koul if (intr_enable)
227914426c8SVinod Koul skl_cldma_int_enable(ctx);
228914426c8SVinod Koul
229914426c8SVinod Koul ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);
230914426c8SVinod Koul if (trigger)
231914426c8SVinod Koul ctx->cl_dev.ops.cl_trigger(ctx, true);
232914426c8SVinod Koul }
2333e40a784SVinod Koul
2343e40a784SVinod Koul /*
2353e40a784SVinod Koul * The CL dma doesn't have any way to update the transfer status until a BDL
2363e40a784SVinod Koul * buffer is fully transferred
2373e40a784SVinod Koul *
2383e40a784SVinod Koul * So Copying is divided in two parts.
2393e40a784SVinod Koul * 1. Interrupt on buffer done where the size to be transferred is more than
2403e40a784SVinod Koul * ring buffer size.
2413e40a784SVinod Koul * 2. Polling on fw register to identify if data left to transferred doesn't
2423e40a784SVinod Koul * fill the ring buffer. Caller takes care of polling the required status
2433e40a784SVinod Koul * register to identify the transfer status.
244b7d0254cSJeeja KP * 3. if wait flag is set, waits for DBL interrupt to copy the next chunk till
245b7d0254cSJeeja KP * bytes_left is 0.
246b7d0254cSJeeja KP * if wait flag is not set, doesn't wait for BDL interrupt. after ccopying
247b7d0254cSJeeja KP * the first chunk return the no of bytes_left to be copied.
2483e40a784SVinod Koul */
2493e40a784SVinod Koul static int
skl_cldma_copy_to_buf(struct sst_dsp * ctx,const void * bin,u32 total_size,bool wait)250b7d0254cSJeeja KP skl_cldma_copy_to_buf(struct sst_dsp *ctx, const void *bin,
251b7d0254cSJeeja KP u32 total_size, bool wait)
2523e40a784SVinod Koul {
2533b4d60f0SPierre-Louis Bossart int ret;
2543e40a784SVinod Koul bool start = true;
2553e40a784SVinod Koul unsigned int excess_bytes;
2563e40a784SVinod Koul u32 size;
2573e40a784SVinod Koul unsigned int bytes_left = total_size;
2583e40a784SVinod Koul const void *curr_pos = bin;
2593e40a784SVinod Koul
2603e40a784SVinod Koul if (total_size <= 0)
2613e40a784SVinod Koul return -EINVAL;
2623e40a784SVinod Koul
2633e40a784SVinod Koul dev_dbg(ctx->dev, "%s: Total binary size: %u\n", __func__, bytes_left);
2643e40a784SVinod Koul
2653e40a784SVinod Koul while (bytes_left) {
2663e40a784SVinod Koul if (bytes_left > ctx->cl_dev.bufsize) {
2673e40a784SVinod Koul
2683e40a784SVinod Koul /*
2693e40a784SVinod Koul * dma transfers only till the write pointer as
2703e40a784SVinod Koul * updated in spib
2713e40a784SVinod Koul */
2723e40a784SVinod Koul if (ctx->cl_dev.curr_spib_pos == 0)
2733e40a784SVinod Koul ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize;
2743e40a784SVinod Koul
2753e40a784SVinod Koul size = ctx->cl_dev.bufsize;
2763e40a784SVinod Koul skl_cldma_fill_buffer(ctx, size, curr_pos, true, start);
2773e40a784SVinod Koul
278b7d0254cSJeeja KP if (wait) {
2793e40a784SVinod Koul start = false;
2803e40a784SVinod Koul ret = skl_cldma_wait_interruptible(ctx);
2813e40a784SVinod Koul if (ret < 0) {
2823e40a784SVinod Koul skl_cldma_stop(ctx);
2833e40a784SVinod Koul return ret;
2843e40a784SVinod Koul }
285b7d0254cSJeeja KP }
2863e40a784SVinod Koul } else {
2873e40a784SVinod Koul skl_cldma_int_disable(ctx);
2883e40a784SVinod Koul
2893e40a784SVinod Koul if ((ctx->cl_dev.curr_spib_pos + bytes_left)
2903e40a784SVinod Koul <= ctx->cl_dev.bufsize) {
2913e40a784SVinod Koul ctx->cl_dev.curr_spib_pos += bytes_left;
2923e40a784SVinod Koul } else {
2933e40a784SVinod Koul excess_bytes = bytes_left -
2943e40a784SVinod Koul (ctx->cl_dev.bufsize -
2953e40a784SVinod Koul ctx->cl_dev.curr_spib_pos);
2963e40a784SVinod Koul ctx->cl_dev.curr_spib_pos = excess_bytes;
2973e40a784SVinod Koul }
2983e40a784SVinod Koul
2993e40a784SVinod Koul size = bytes_left;
3003e40a784SVinod Koul skl_cldma_fill_buffer(ctx, size,
3013e40a784SVinod Koul curr_pos, false, start);
3023e40a784SVinod Koul }
3033e40a784SVinod Koul bytes_left -= size;
3043e40a784SVinod Koul curr_pos = curr_pos + size;
305b7d0254cSJeeja KP if (!wait)
306b7d0254cSJeeja KP return bytes_left;
3073e40a784SVinod Koul }
3083e40a784SVinod Koul
309b7d0254cSJeeja KP return bytes_left;
3103e40a784SVinod Koul }
3113e40a784SVinod Koul
skl_cldma_process_intr(struct sst_dsp * ctx)3123e40a784SVinod Koul void skl_cldma_process_intr(struct sst_dsp *ctx)
3133e40a784SVinod Koul {
3143e40a784SVinod Koul u8 cl_dma_intr_status;
3153e40a784SVinod Koul
3163e40a784SVinod Koul cl_dma_intr_status =
3173e40a784SVinod Koul sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_CL_SD_STS);
3183e40a784SVinod Koul
3193e40a784SVinod Koul if (!(cl_dma_intr_status & SKL_CL_DMA_SD_INT_COMPLETE))
3203e40a784SVinod Koul ctx->cl_dev.wake_status = SKL_CL_DMA_ERR;
3213e40a784SVinod Koul else
3223e40a784SVinod Koul ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE;
3233e40a784SVinod Koul
3243e40a784SVinod Koul ctx->cl_dev.wait_condition = true;
3253e40a784SVinod Koul wake_up(&ctx->cl_dev.wait_queue);
3263e40a784SVinod Koul }
3273e40a784SVinod Koul
skl_cldma_prepare(struct sst_dsp * ctx)3283e40a784SVinod Koul int skl_cldma_prepare(struct sst_dsp *ctx)
3293e40a784SVinod Koul {
3303e40a784SVinod Koul int ret;
33186efd35eSPierre-Louis Bossart __le32 *bdl;
3323e40a784SVinod Koul
3333e40a784SVinod Koul ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE;
3343e40a784SVinod Koul
3353e40a784SVinod Koul /* Allocate cl ops */
3363e40a784SVinod Koul ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle;
3373e40a784SVinod Koul ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
3383e40a784SVinod Koul ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
3393e40a784SVinod Koul ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
3402434caf0SJeeja KP ctx->cl_dev.ops.cl_trigger = skl_cldma_stream_run;
3413e40a784SVinod Koul ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
3423e40a784SVinod Koul ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
3433e40a784SVinod Koul ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
3443e40a784SVinod Koul
3453e40a784SVinod Koul /* Allocate buffer*/
346*451d85c4SCezary Rojewski ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, ctx->dev, ctx->cl_dev.bufsize,
347*451d85c4SCezary Rojewski &ctx->cl_dev.dmab_data);
3483e40a784SVinod Koul if (ret < 0) {
349ecd286a9SColin Ian King dev_err(ctx->dev, "Alloc buffer for base fw failed: %x\n", ret);
3503e40a784SVinod Koul return ret;
3513e40a784SVinod Koul }
352*451d85c4SCezary Rojewski
3533e40a784SVinod Koul /* Setup Code loader BDL */
354*451d85c4SCezary Rojewski ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, ctx->dev, BDL_SIZE, &ctx->cl_dev.dmab_bdl);
3553e40a784SVinod Koul if (ret < 0) {
356ecd286a9SColin Ian King dev_err(ctx->dev, "Alloc buffer for blde failed: %x\n", ret);
3573e40a784SVinod Koul ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
3583e40a784SVinod Koul return ret;
3593e40a784SVinod Koul }
36086efd35eSPierre-Louis Bossart bdl = (__le32 *)ctx->cl_dev.dmab_bdl.area;
3613e40a784SVinod Koul
3623e40a784SVinod Koul /* Allocate BDLs */
3633e40a784SVinod Koul ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data,
3643e40a784SVinod Koul &bdl, ctx->cl_dev.bufsize, 1);
3653e40a784SVinod Koul ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl,
3663e40a784SVinod Koul ctx->cl_dev.bufsize, ctx->cl_dev.frags);
3673e40a784SVinod Koul
3683e40a784SVinod Koul ctx->cl_dev.curr_spib_pos = 0;
3693e40a784SVinod Koul ctx->cl_dev.dma_buffer_offset = 0;
3703e40a784SVinod Koul init_waitqueue_head(&ctx->cl_dev.wait_queue);
3713e40a784SVinod Koul
3723e40a784SVinod Koul return ret;
3733e40a784SVinod Koul }
374