1 /* 2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality 3 * 4 * Copyright (C) 2014-2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * 7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 19 * 20 */ 21 22 #include <linux/pci.h> 23 #include <linux/pm_runtime.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include "skl.h" 27 #include "skl-topology.h" 28 #include "skl-sst-dsp.h" 29 #include "skl-sst-ipc.h" 30 31 #define HDA_MONO 1 32 #define HDA_STEREO 2 33 #define HDA_QUAD 4 34 35 static struct snd_pcm_hardware azx_pcm_hw = { 36 .info = (SNDRV_PCM_INFO_MMAP | 37 SNDRV_PCM_INFO_INTERLEAVED | 38 SNDRV_PCM_INFO_BLOCK_TRANSFER | 39 SNDRV_PCM_INFO_MMAP_VALID | 40 SNDRV_PCM_INFO_PAUSE | 41 SNDRV_PCM_INFO_RESUME | 42 SNDRV_PCM_INFO_SYNC_START | 43 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */ 44 SNDRV_PCM_INFO_HAS_LINK_ATIME | 45 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 46 .formats = SNDRV_PCM_FMTBIT_S16_LE | 47 SNDRV_PCM_FMTBIT_S32_LE | 48 SNDRV_PCM_FMTBIT_S24_LE, 49 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 50 SNDRV_PCM_RATE_8000, 51 .rate_min = 8000, 52 .rate_max = 48000, 53 .channels_min = 1, 54 .channels_max = 8, 55 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 56 .period_bytes_min = 128, 57 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 58 .periods_min = 2, 59 .periods_max = AZX_MAX_FRAG, 60 .fifo_size = 0, 61 }; 62 63 static inline 64 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream) 65 { 66 return substream->runtime->private_data; 67 } 68 69 static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream) 70 { 71 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 72 struct hdac_stream *hstream = hdac_stream(stream); 73 struct hdac_bus *bus = hstream->bus; 74 75 return hbus_to_ebus(bus); 76 } 77 78 static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus, 79 struct snd_pcm_substream *substream, 80 size_t size) 81 { 82 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 83 84 hdac_stream(stream)->bufsize = 0; 85 hdac_stream(stream)->period_bytes = 0; 86 hdac_stream(stream)->format_val = 0; 87 88 return snd_pcm_lib_malloc_pages(substream, size); 89 } 90 91 static int skl_substream_free_pages(struct hdac_bus *bus, 92 struct snd_pcm_substream *substream) 93 { 94 return snd_pcm_lib_free_pages(substream); 95 } 96 97 static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus, 98 struct snd_pcm_runtime *runtime) 99 { 100 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 101 102 /* avoid wrap-around with wall-clock */ 103 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, 104 20, 178000000); 105 } 106 107 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus) 108 { 109 if ((ebus_to_hbus(ebus))->ppcap) 110 return HDAC_EXT_STREAM_TYPE_HOST; 111 else 112 return HDAC_EXT_STREAM_TYPE_COUPLED; 113 } 114 115 /* 116 * check if the stream opened is marked as ignore_suspend by machine, if so 117 * then enable suspend_active refcount 118 * 119 * The count supend_active does not need lock as it is used in open/close 120 * and suspend context 121 */ 122 static void skl_set_suspend_active(struct snd_pcm_substream *substream, 123 struct snd_soc_dai *dai, bool enable) 124 { 125 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 126 struct snd_soc_dapm_widget *w; 127 struct skl *skl = ebus_to_skl(ebus); 128 129 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 130 w = dai->playback_widget; 131 else 132 w = dai->capture_widget; 133 134 if (w->ignore_suspend && enable) 135 skl->supend_active++; 136 else if (w->ignore_suspend && !enable) 137 skl->supend_active--; 138 } 139 140 static int skl_pcm_open(struct snd_pcm_substream *substream, 141 struct snd_soc_dai *dai) 142 { 143 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 144 struct hdac_ext_stream *stream; 145 struct snd_pcm_runtime *runtime = substream->runtime; 146 struct skl_dma_params *dma_params; 147 struct skl *skl = get_skl_ctx(dai->dev); 148 struct skl_module_cfg *mconfig; 149 150 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 151 152 stream = snd_hdac_ext_stream_assign(ebus, substream, 153 skl_get_host_stream_type(ebus)); 154 if (stream == NULL) 155 return -EBUSY; 156 157 skl_set_pcm_constrains(ebus, runtime); 158 159 /* 160 * disable WALLCLOCK timestamps for capture streams 161 * until we figure out how to handle digital inputs 162 */ 163 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 164 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */ 165 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME; 166 } 167 168 runtime->private_data = stream; 169 170 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL); 171 if (!dma_params) 172 return -ENOMEM; 173 174 dma_params->stream_tag = hdac_stream(stream)->stream_tag; 175 snd_soc_dai_set_dma_data(dai, substream, dma_params); 176 177 dev_dbg(dai->dev, "stream tag set in dma params=%d\n", 178 dma_params->stream_tag); 179 skl_set_suspend_active(substream, dai, true); 180 snd_pcm_set_sync(substream); 181 182 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 183 if (!mconfig) 184 return -EINVAL; 185 186 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps); 187 188 return 0; 189 } 190 191 static int skl_get_format(struct snd_pcm_substream *substream, 192 struct snd_soc_dai *dai) 193 { 194 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 195 struct skl_dma_params *dma_params; 196 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 197 int format_val = 0; 198 199 if ((ebus_to_hbus(ebus))->ppcap) { 200 struct snd_pcm_runtime *runtime = substream->runtime; 201 202 format_val = snd_hdac_calc_stream_format(runtime->rate, 203 runtime->channels, 204 runtime->format, 205 32, 0); 206 } else { 207 struct snd_soc_dai *codec_dai = rtd->codec_dai; 208 209 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream); 210 if (dma_params) 211 format_val = dma_params->format; 212 } 213 214 return format_val; 215 } 216 217 static int skl_be_prepare(struct snd_pcm_substream *substream, 218 struct snd_soc_dai *dai) 219 { 220 struct skl *skl = get_skl_ctx(dai->dev); 221 struct skl_sst *ctx = skl->skl_sst; 222 struct skl_module_cfg *mconfig; 223 224 if (dai->playback_widget->power || dai->capture_widget->power) 225 return 0; 226 227 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream); 228 if (mconfig == NULL) 229 return -EINVAL; 230 231 return skl_dsp_set_dma_control(ctx, mconfig); 232 } 233 234 static int skl_pcm_prepare(struct snd_pcm_substream *substream, 235 struct snd_soc_dai *dai) 236 { 237 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 238 struct skl *skl = get_skl_ctx(dai->dev); 239 unsigned int format_val; 240 int err; 241 struct skl_module_cfg *mconfig; 242 243 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 244 245 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 246 247 format_val = skl_get_format(substream, dai); 248 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d\n", 249 hdac_stream(stream)->stream_tag, format_val); 250 snd_hdac_stream_reset(hdac_stream(stream)); 251 252 /* In case of XRUN recovery, reset the FW pipe to clean state */ 253 if (mconfig && (substream->runtime->status->state == 254 SNDRV_PCM_STATE_XRUN)) 255 skl_reset_pipe(skl->skl_sst, mconfig->pipe); 256 257 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val); 258 if (err < 0) 259 return err; 260 261 err = snd_hdac_stream_setup(hdac_stream(stream)); 262 if (err < 0) 263 return err; 264 265 hdac_stream(stream)->prepared = 1; 266 267 return err; 268 } 269 270 static int skl_pcm_hw_params(struct snd_pcm_substream *substream, 271 struct snd_pcm_hw_params *params, 272 struct snd_soc_dai *dai) 273 { 274 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 275 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 276 struct snd_pcm_runtime *runtime = substream->runtime; 277 struct skl_pipe_params p_params = {0}; 278 struct skl_module_cfg *m_cfg; 279 int ret, dma_id; 280 281 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 282 ret = skl_substream_alloc_pages(ebus, substream, 283 params_buffer_bytes(params)); 284 if (ret < 0) 285 return ret; 286 287 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n", 288 runtime->rate, runtime->channels, runtime->format); 289 290 dma_id = hdac_stream(stream)->stream_tag - 1; 291 dev_dbg(dai->dev, "dma_id=%d\n", dma_id); 292 293 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 294 p_params.ch = params_channels(params); 295 p_params.s_freq = params_rate(params); 296 p_params.host_dma_id = dma_id; 297 p_params.stream = substream->stream; 298 299 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream); 300 if (m_cfg) 301 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params); 302 303 return 0; 304 } 305 306 static void skl_pcm_close(struct snd_pcm_substream *substream, 307 struct snd_soc_dai *dai) 308 { 309 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 310 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 311 struct skl_dma_params *dma_params = NULL; 312 struct skl *skl = ebus_to_skl(ebus); 313 struct skl_module_cfg *mconfig; 314 315 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 316 317 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus)); 318 319 dma_params = snd_soc_dai_get_dma_data(dai, substream); 320 /* 321 * now we should set this to NULL as we are freeing by the 322 * dma_params 323 */ 324 snd_soc_dai_set_dma_data(dai, substream, NULL); 325 skl_set_suspend_active(substream, dai, false); 326 327 /* 328 * check if close is for "Reference Pin" and set back the 329 * CGCTL.MISCBDCGE if disabled by driver 330 */ 331 if (!strncmp(dai->name, "Reference Pin", 13) && 332 skl->skl_sst->miscbdcg_disabled) { 333 skl->skl_sst->enable_miscbdcge(dai->dev, true); 334 skl->skl_sst->miscbdcg_disabled = false; 335 } 336 337 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 338 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps); 339 340 kfree(dma_params); 341 } 342 343 static int skl_pcm_hw_free(struct snd_pcm_substream *substream, 344 struct snd_soc_dai *dai) 345 { 346 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 347 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 348 349 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 350 351 snd_hdac_stream_cleanup(hdac_stream(stream)); 352 hdac_stream(stream)->prepared = 0; 353 354 return skl_substream_free_pages(ebus_to_hbus(ebus), substream); 355 } 356 357 static int skl_be_hw_params(struct snd_pcm_substream *substream, 358 struct snd_pcm_hw_params *params, 359 struct snd_soc_dai *dai) 360 { 361 struct skl_pipe_params p_params = {0}; 362 363 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 364 p_params.ch = params_channels(params); 365 p_params.s_freq = params_rate(params); 366 p_params.stream = substream->stream; 367 368 return skl_tplg_be_update_params(dai, &p_params); 369 } 370 371 static int skl_decoupled_trigger(struct snd_pcm_substream *substream, 372 int cmd) 373 { 374 struct hdac_ext_bus *ebus = get_bus_ctx(substream); 375 struct hdac_bus *bus = ebus_to_hbus(ebus); 376 struct hdac_ext_stream *stream; 377 int start; 378 unsigned long cookie; 379 struct hdac_stream *hstr; 380 381 stream = get_hdac_ext_stream(substream); 382 hstr = hdac_stream(stream); 383 384 if (!hstr->prepared) 385 return -EPIPE; 386 387 switch (cmd) { 388 case SNDRV_PCM_TRIGGER_START: 389 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 390 case SNDRV_PCM_TRIGGER_RESUME: 391 start = 1; 392 break; 393 394 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 395 case SNDRV_PCM_TRIGGER_SUSPEND: 396 case SNDRV_PCM_TRIGGER_STOP: 397 start = 0; 398 break; 399 400 default: 401 return -EINVAL; 402 } 403 404 spin_lock_irqsave(&bus->reg_lock, cookie); 405 406 if (start) { 407 snd_hdac_stream_start(hdac_stream(stream), true); 408 snd_hdac_stream_timecounter_init(hstr, 0); 409 } else { 410 snd_hdac_stream_stop(hdac_stream(stream)); 411 } 412 413 spin_unlock_irqrestore(&bus->reg_lock, cookie); 414 415 return 0; 416 } 417 418 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 419 struct snd_soc_dai *dai) 420 { 421 struct skl *skl = get_skl_ctx(dai->dev); 422 struct skl_sst *ctx = skl->skl_sst; 423 struct skl_module_cfg *mconfig; 424 struct hdac_ext_bus *ebus = get_bus_ctx(substream); 425 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 426 struct snd_soc_dapm_widget *w; 427 int ret; 428 429 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 430 if (!mconfig) 431 return -EIO; 432 433 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 434 w = dai->playback_widget; 435 else 436 w = dai->capture_widget; 437 438 switch (cmd) { 439 case SNDRV_PCM_TRIGGER_RESUME: 440 if (!w->ignore_suspend) { 441 skl_pcm_prepare(substream, dai); 442 /* 443 * enable DMA Resume enable bit for the stream, set the 444 * dpib & lpib position to resume before starting the 445 * DMA 446 */ 447 snd_hdac_ext_stream_drsm_enable(ebus, true, 448 hdac_stream(stream)->index); 449 snd_hdac_ext_stream_set_dpibr(ebus, stream, 450 stream->dpib); 451 snd_hdac_ext_stream_set_lpib(stream, stream->lpib); 452 } 453 454 case SNDRV_PCM_TRIGGER_START: 455 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 456 /* 457 * Start HOST DMA and Start FE Pipe.This is to make sure that 458 * there are no underrun/overrun in the case when the FE 459 * pipeline is started but there is a delay in starting the 460 * DMA channel on the host. 461 */ 462 snd_hdac_ext_stream_decouple(ebus, stream, true); 463 ret = skl_decoupled_trigger(substream, cmd); 464 if (ret < 0) 465 return ret; 466 return skl_run_pipe(ctx, mconfig->pipe); 467 break; 468 469 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 470 case SNDRV_PCM_TRIGGER_SUSPEND: 471 case SNDRV_PCM_TRIGGER_STOP: 472 /* 473 * Stop FE Pipe first and stop DMA. This is to make sure that 474 * there are no underrun/overrun in the case if there is a delay 475 * between the two operations. 476 */ 477 ret = skl_stop_pipe(ctx, mconfig->pipe); 478 if (ret < 0) 479 return ret; 480 481 ret = skl_decoupled_trigger(substream, cmd); 482 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) { 483 /* save the dpib and lpib positions */ 484 stream->dpib = readl(ebus->bus.remap_addr + 485 AZX_REG_VS_SDXDPIB_XBASE + 486 (AZX_REG_VS_SDXDPIB_XINTERVAL * 487 hdac_stream(stream)->index)); 488 489 stream->lpib = snd_hdac_stream_get_pos_lpib( 490 hdac_stream(stream)); 491 snd_hdac_ext_stream_decouple(ebus, stream, false); 492 } 493 break; 494 495 default: 496 return -EINVAL; 497 } 498 499 return 0; 500 } 501 502 static int skl_link_hw_params(struct snd_pcm_substream *substream, 503 struct snd_pcm_hw_params *params, 504 struct snd_soc_dai *dai) 505 { 506 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 507 struct hdac_ext_stream *link_dev; 508 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 509 struct hdac_ext_dma_params *dma_params; 510 struct snd_soc_dai *codec_dai = rtd->codec_dai; 511 struct skl_pipe_params p_params = {0}; 512 513 link_dev = snd_hdac_ext_stream_assign(ebus, substream, 514 HDAC_EXT_STREAM_TYPE_LINK); 515 if (!link_dev) 516 return -EBUSY; 517 518 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev); 519 520 /* set the stream tag in the codec dai dma params */ 521 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream); 522 if (dma_params) 523 dma_params->stream_tag = hdac_stream(link_dev)->stream_tag; 524 525 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 526 p_params.ch = params_channels(params); 527 p_params.s_freq = params_rate(params); 528 p_params.stream = substream->stream; 529 p_params.link_dma_id = hdac_stream(link_dev)->stream_tag - 1; 530 531 return skl_tplg_be_update_params(dai, &p_params); 532 } 533 534 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream, 535 struct snd_soc_dai *dai) 536 { 537 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 538 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 539 struct hdac_ext_stream *link_dev = 540 snd_soc_dai_get_dma_data(dai, substream); 541 unsigned int format_val = 0; 542 struct skl_dma_params *dma_params; 543 struct snd_soc_dai *codec_dai = rtd->codec_dai; 544 struct hdac_ext_link *link; 545 struct skl *skl = get_skl_ctx(dai->dev); 546 struct skl_module_cfg *mconfig = NULL; 547 548 dma_params = (struct skl_dma_params *) 549 snd_soc_dai_get_dma_data(codec_dai, substream); 550 if (dma_params) 551 format_val = dma_params->format; 552 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d codec_dai_name=%s\n", 553 hdac_stream(link_dev)->stream_tag, format_val, codec_dai->name); 554 555 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name); 556 if (!link) 557 return -EINVAL; 558 559 snd_hdac_ext_link_stream_reset(link_dev); 560 561 /* In case of XRUN recovery, reset the FW pipe to clean state */ 562 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream); 563 if (mconfig && (substream->runtime->status->state == 564 SNDRV_PCM_STATE_XRUN)) 565 skl_reset_pipe(skl->skl_sst, mconfig->pipe); 566 567 snd_hdac_ext_link_stream_setup(link_dev, format_val); 568 569 snd_hdac_ext_link_set_stream_id(link, hdac_stream(link_dev)->stream_tag); 570 link_dev->link_prepared = 1; 571 572 return 0; 573 } 574 575 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream, 576 int cmd, struct snd_soc_dai *dai) 577 { 578 struct hdac_ext_stream *link_dev = 579 snd_soc_dai_get_dma_data(dai, substream); 580 struct hdac_ext_bus *ebus = get_bus_ctx(substream); 581 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 582 583 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd); 584 switch (cmd) { 585 case SNDRV_PCM_TRIGGER_RESUME: 586 skl_link_pcm_prepare(substream, dai); 587 case SNDRV_PCM_TRIGGER_START: 588 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 589 snd_hdac_ext_stream_decouple(ebus, stream, true); 590 snd_hdac_ext_link_stream_start(link_dev); 591 break; 592 593 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 594 case SNDRV_PCM_TRIGGER_SUSPEND: 595 case SNDRV_PCM_TRIGGER_STOP: 596 snd_hdac_ext_link_stream_clear(link_dev); 597 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND) 598 snd_hdac_ext_stream_decouple(ebus, stream, false); 599 break; 600 601 default: 602 return -EINVAL; 603 } 604 return 0; 605 } 606 607 static int skl_link_hw_free(struct snd_pcm_substream *substream, 608 struct snd_soc_dai *dai) 609 { 610 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 611 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 612 struct hdac_ext_stream *link_dev = 613 snd_soc_dai_get_dma_data(dai, substream); 614 struct hdac_ext_link *link; 615 616 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 617 618 link_dev->link_prepared = 0; 619 620 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name); 621 if (!link) 622 return -EINVAL; 623 624 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag); 625 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK); 626 return 0; 627 } 628 629 static struct snd_soc_dai_ops skl_pcm_dai_ops = { 630 .startup = skl_pcm_open, 631 .shutdown = skl_pcm_close, 632 .prepare = skl_pcm_prepare, 633 .hw_params = skl_pcm_hw_params, 634 .hw_free = skl_pcm_hw_free, 635 .trigger = skl_pcm_trigger, 636 }; 637 638 static struct snd_soc_dai_ops skl_dmic_dai_ops = { 639 .hw_params = skl_be_hw_params, 640 }; 641 642 static struct snd_soc_dai_ops skl_be_ssp_dai_ops = { 643 .hw_params = skl_be_hw_params, 644 .prepare = skl_be_prepare, 645 }; 646 647 static struct snd_soc_dai_ops skl_link_dai_ops = { 648 .prepare = skl_link_pcm_prepare, 649 .hw_params = skl_link_hw_params, 650 .hw_free = skl_link_hw_free, 651 .trigger = skl_link_pcm_trigger, 652 }; 653 654 static struct snd_soc_dai_driver skl_platform_dai[] = { 655 { 656 .name = "System Pin", 657 .ops = &skl_pcm_dai_ops, 658 .playback = { 659 .stream_name = "System Playback", 660 .channels_min = HDA_MONO, 661 .channels_max = HDA_STEREO, 662 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000, 663 .formats = SNDRV_PCM_FMTBIT_S16_LE | 664 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 665 }, 666 .capture = { 667 .stream_name = "System Capture", 668 .channels_min = HDA_MONO, 669 .channels_max = HDA_STEREO, 670 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 671 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 672 }, 673 }, 674 { 675 .name = "Reference Pin", 676 .ops = &skl_pcm_dai_ops, 677 .capture = { 678 .stream_name = "Reference Capture", 679 .channels_min = HDA_MONO, 680 .channels_max = HDA_QUAD, 681 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 682 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 683 }, 684 }, 685 { 686 .name = "Deepbuffer Pin", 687 .ops = &skl_pcm_dai_ops, 688 .playback = { 689 .stream_name = "Deepbuffer Playback", 690 .channels_min = HDA_STEREO, 691 .channels_max = HDA_STEREO, 692 .rates = SNDRV_PCM_RATE_48000, 693 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 694 }, 695 }, 696 { 697 .name = "LowLatency Pin", 698 .ops = &skl_pcm_dai_ops, 699 .playback = { 700 .stream_name = "Low Latency Playback", 701 .channels_min = HDA_STEREO, 702 .channels_max = HDA_STEREO, 703 .rates = SNDRV_PCM_RATE_48000, 704 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 705 }, 706 }, 707 { 708 .name = "DMIC Pin", 709 .ops = &skl_pcm_dai_ops, 710 .capture = { 711 .stream_name = "DMIC Capture", 712 .channels_min = HDA_MONO, 713 .channels_max = HDA_QUAD, 714 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 715 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 716 }, 717 }, 718 { 719 .name = "HDMI1 Pin", 720 .ops = &skl_pcm_dai_ops, 721 .playback = { 722 .stream_name = "HDMI1 Playback", 723 .channels_min = HDA_STEREO, 724 .channels_max = 8, 725 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 726 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 727 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 728 SNDRV_PCM_RATE_192000, 729 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 730 SNDRV_PCM_FMTBIT_S32_LE, 731 }, 732 }, 733 { 734 .name = "HDMI2 Pin", 735 .ops = &skl_pcm_dai_ops, 736 .playback = { 737 .stream_name = "HDMI2 Playback", 738 .channels_min = HDA_STEREO, 739 .channels_max = 8, 740 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 741 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 742 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 743 SNDRV_PCM_RATE_192000, 744 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 745 SNDRV_PCM_FMTBIT_S32_LE, 746 }, 747 }, 748 { 749 .name = "HDMI3 Pin", 750 .ops = &skl_pcm_dai_ops, 751 .playback = { 752 .stream_name = "HDMI3 Playback", 753 .channels_min = HDA_STEREO, 754 .channels_max = 8, 755 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 756 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 757 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 758 SNDRV_PCM_RATE_192000, 759 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 760 SNDRV_PCM_FMTBIT_S32_LE, 761 }, 762 }, 763 764 /* BE CPU Dais */ 765 { 766 .name = "SSP0 Pin", 767 .ops = &skl_be_ssp_dai_ops, 768 .playback = { 769 .stream_name = "ssp0 Tx", 770 .channels_min = HDA_STEREO, 771 .channels_max = HDA_STEREO, 772 .rates = SNDRV_PCM_RATE_48000, 773 .formats = SNDRV_PCM_FMTBIT_S16_LE, 774 }, 775 .capture = { 776 .stream_name = "ssp0 Rx", 777 .channels_min = HDA_STEREO, 778 .channels_max = HDA_STEREO, 779 .rates = SNDRV_PCM_RATE_48000, 780 .formats = SNDRV_PCM_FMTBIT_S16_LE, 781 }, 782 }, 783 { 784 .name = "SSP1 Pin", 785 .ops = &skl_be_ssp_dai_ops, 786 .playback = { 787 .stream_name = "ssp1 Tx", 788 .channels_min = HDA_STEREO, 789 .channels_max = HDA_STEREO, 790 .rates = SNDRV_PCM_RATE_48000, 791 .formats = SNDRV_PCM_FMTBIT_S16_LE, 792 }, 793 .capture = { 794 .stream_name = "ssp1 Rx", 795 .channels_min = HDA_STEREO, 796 .channels_max = HDA_STEREO, 797 .rates = SNDRV_PCM_RATE_48000, 798 .formats = SNDRV_PCM_FMTBIT_S16_LE, 799 }, 800 }, 801 { 802 .name = "SSP2 Pin", 803 .ops = &skl_be_ssp_dai_ops, 804 .playback = { 805 .stream_name = "ssp2 Tx", 806 .channels_min = HDA_STEREO, 807 .channels_max = HDA_STEREO, 808 .rates = SNDRV_PCM_RATE_48000, 809 .formats = SNDRV_PCM_FMTBIT_S16_LE, 810 }, 811 .capture = { 812 .stream_name = "ssp2 Rx", 813 .channels_min = HDA_STEREO, 814 .channels_max = HDA_STEREO, 815 .rates = SNDRV_PCM_RATE_48000, 816 .formats = SNDRV_PCM_FMTBIT_S16_LE, 817 }, 818 }, 819 { 820 .name = "SSP3 Pin", 821 .ops = &skl_be_ssp_dai_ops, 822 .playback = { 823 .stream_name = "ssp3 Tx", 824 .channels_min = HDA_STEREO, 825 .channels_max = HDA_STEREO, 826 .rates = SNDRV_PCM_RATE_48000, 827 .formats = SNDRV_PCM_FMTBIT_S16_LE, 828 }, 829 .capture = { 830 .stream_name = "ssp3 Rx", 831 .channels_min = HDA_STEREO, 832 .channels_max = HDA_STEREO, 833 .rates = SNDRV_PCM_RATE_48000, 834 .formats = SNDRV_PCM_FMTBIT_S16_LE, 835 }, 836 }, 837 { 838 .name = "SSP4 Pin", 839 .ops = &skl_be_ssp_dai_ops, 840 .playback = { 841 .stream_name = "ssp4 Tx", 842 .channels_min = HDA_STEREO, 843 .channels_max = HDA_STEREO, 844 .rates = SNDRV_PCM_RATE_48000, 845 .formats = SNDRV_PCM_FMTBIT_S16_LE, 846 }, 847 .capture = { 848 .stream_name = "ssp4 Rx", 849 .channels_min = HDA_STEREO, 850 .channels_max = HDA_STEREO, 851 .rates = SNDRV_PCM_RATE_48000, 852 .formats = SNDRV_PCM_FMTBIT_S16_LE, 853 }, 854 }, 855 { 856 .name = "SSP5 Pin", 857 .ops = &skl_be_ssp_dai_ops, 858 .playback = { 859 .stream_name = "ssp5 Tx", 860 .channels_min = HDA_STEREO, 861 .channels_max = HDA_STEREO, 862 .rates = SNDRV_PCM_RATE_48000, 863 .formats = SNDRV_PCM_FMTBIT_S16_LE, 864 }, 865 .capture = { 866 .stream_name = "ssp5 Rx", 867 .channels_min = HDA_STEREO, 868 .channels_max = HDA_STEREO, 869 .rates = SNDRV_PCM_RATE_48000, 870 .formats = SNDRV_PCM_FMTBIT_S16_LE, 871 }, 872 }, 873 { 874 .name = "iDisp1 Pin", 875 .ops = &skl_link_dai_ops, 876 .playback = { 877 .stream_name = "iDisp1 Tx", 878 .channels_min = HDA_STEREO, 879 .channels_max = 8, 880 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000, 881 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 882 SNDRV_PCM_FMTBIT_S24_LE, 883 }, 884 }, 885 { 886 .name = "iDisp2 Pin", 887 .ops = &skl_link_dai_ops, 888 .playback = { 889 .stream_name = "iDisp2 Tx", 890 .channels_min = HDA_STEREO, 891 .channels_max = 8, 892 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| 893 SNDRV_PCM_RATE_48000, 894 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 895 SNDRV_PCM_FMTBIT_S24_LE, 896 }, 897 }, 898 { 899 .name = "iDisp3 Pin", 900 .ops = &skl_link_dai_ops, 901 .playback = { 902 .stream_name = "iDisp3 Tx", 903 .channels_min = HDA_STEREO, 904 .channels_max = 8, 905 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| 906 SNDRV_PCM_RATE_48000, 907 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 908 SNDRV_PCM_FMTBIT_S24_LE, 909 }, 910 }, 911 { 912 .name = "DMIC01 Pin", 913 .ops = &skl_dmic_dai_ops, 914 .capture = { 915 .stream_name = "DMIC01 Rx", 916 .channels_min = HDA_MONO, 917 .channels_max = HDA_QUAD, 918 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 919 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 920 }, 921 }, 922 { 923 .name = "HD-Codec Pin", 924 .ops = &skl_link_dai_ops, 925 .playback = { 926 .stream_name = "HD-Codec Tx", 927 .channels_min = HDA_STEREO, 928 .channels_max = HDA_STEREO, 929 .rates = SNDRV_PCM_RATE_48000, 930 .formats = SNDRV_PCM_FMTBIT_S16_LE, 931 }, 932 .capture = { 933 .stream_name = "HD-Codec Rx", 934 .channels_min = HDA_STEREO, 935 .channels_max = HDA_STEREO, 936 .rates = SNDRV_PCM_RATE_48000, 937 .formats = SNDRV_PCM_FMTBIT_S16_LE, 938 }, 939 }, 940 }; 941 942 static int skl_platform_open(struct snd_pcm_substream *substream) 943 { 944 struct snd_pcm_runtime *runtime; 945 struct snd_soc_pcm_runtime *rtd = substream->private_data; 946 struct snd_soc_dai_link *dai_link = rtd->dai_link; 947 948 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__, 949 dai_link->cpu_dai_name); 950 951 runtime = substream->runtime; 952 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw); 953 954 return 0; 955 } 956 957 static int skl_coupled_trigger(struct snd_pcm_substream *substream, 958 int cmd) 959 { 960 struct hdac_ext_bus *ebus = get_bus_ctx(substream); 961 struct hdac_bus *bus = ebus_to_hbus(ebus); 962 struct hdac_ext_stream *stream; 963 struct snd_pcm_substream *s; 964 bool start; 965 int sbits = 0; 966 unsigned long cookie; 967 struct hdac_stream *hstr; 968 969 stream = get_hdac_ext_stream(substream); 970 hstr = hdac_stream(stream); 971 972 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd); 973 974 if (!hstr->prepared) 975 return -EPIPE; 976 977 switch (cmd) { 978 case SNDRV_PCM_TRIGGER_START: 979 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 980 case SNDRV_PCM_TRIGGER_RESUME: 981 start = true; 982 break; 983 984 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 985 case SNDRV_PCM_TRIGGER_SUSPEND: 986 case SNDRV_PCM_TRIGGER_STOP: 987 start = false; 988 break; 989 990 default: 991 return -EINVAL; 992 } 993 994 snd_pcm_group_for_each_entry(s, substream) { 995 if (s->pcm->card != substream->pcm->card) 996 continue; 997 stream = get_hdac_ext_stream(s); 998 sbits |= 1 << hdac_stream(stream)->index; 999 snd_pcm_trigger_done(s, substream); 1000 } 1001 1002 spin_lock_irqsave(&bus->reg_lock, cookie); 1003 1004 /* first, set SYNC bits of corresponding streams */ 1005 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC); 1006 1007 snd_pcm_group_for_each_entry(s, substream) { 1008 if (s->pcm->card != substream->pcm->card) 1009 continue; 1010 stream = get_hdac_ext_stream(s); 1011 if (start) 1012 snd_hdac_stream_start(hdac_stream(stream), true); 1013 else 1014 snd_hdac_stream_stop(hdac_stream(stream)); 1015 } 1016 spin_unlock_irqrestore(&bus->reg_lock, cookie); 1017 1018 snd_hdac_stream_sync(hstr, start, sbits); 1019 1020 spin_lock_irqsave(&bus->reg_lock, cookie); 1021 1022 /* reset SYNC bits */ 1023 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC); 1024 if (start) 1025 snd_hdac_stream_timecounter_init(hstr, sbits); 1026 spin_unlock_irqrestore(&bus->reg_lock, cookie); 1027 1028 return 0; 1029 } 1030 1031 static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream, 1032 int cmd) 1033 { 1034 struct hdac_ext_bus *ebus = get_bus_ctx(substream); 1035 1036 if (!(ebus_to_hbus(ebus))->ppcap) 1037 return skl_coupled_trigger(substream, cmd); 1038 1039 return 0; 1040 } 1041 1042 static snd_pcm_uframes_t skl_platform_pcm_pointer 1043 (struct snd_pcm_substream *substream) 1044 { 1045 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream); 1046 struct hdac_ext_bus *ebus = get_bus_ctx(substream); 1047 unsigned int pos; 1048 1049 /* 1050 * Use DPIB for Playback stream as the periodic DMA Position-in- 1051 * Buffer Writes may be scheduled at the same time or later than 1052 * the MSI and does not guarantee to reflect the Position of the 1053 * last buffer that was transferred. Whereas DPIB register in 1054 * HAD space reflects the actual data that is transferred. 1055 * Use the position buffer for capture, as DPIB write gets 1056 * completed earlier than the actual data written to the DDR. 1057 */ 1058 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1059 pos = readl(ebus->bus.remap_addr + AZX_REG_VS_SDXDPIB_XBASE + 1060 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1061 hdac_stream(hstream)->index)); 1062 else 1063 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream)); 1064 1065 if (pos >= hdac_stream(hstream)->bufsize) 1066 pos = 0; 1067 1068 return bytes_to_frames(substream->runtime, pos); 1069 } 1070 1071 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream, 1072 u64 nsec) 1073 { 1074 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 1075 struct snd_soc_dai *codec_dai = rtd->codec_dai; 1076 u64 codec_frames, codec_nsecs; 1077 1078 if (!codec_dai->driver->ops->delay) 1079 return nsec; 1080 1081 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai); 1082 codec_nsecs = div_u64(codec_frames * 1000000000LL, 1083 substream->runtime->rate); 1084 1085 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 1086 return nsec + codec_nsecs; 1087 1088 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; 1089 } 1090 1091 static int skl_get_time_info(struct snd_pcm_substream *substream, 1092 struct timespec *system_ts, struct timespec *audio_ts, 1093 struct snd_pcm_audio_tstamp_config *audio_tstamp_config, 1094 struct snd_pcm_audio_tstamp_report *audio_tstamp_report) 1095 { 1096 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream); 1097 struct hdac_stream *hstr = hdac_stream(sstream); 1098 u64 nsec; 1099 1100 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && 1101 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) { 1102 1103 snd_pcm_gettime(substream->runtime, system_ts); 1104 1105 nsec = timecounter_read(&hstr->tc); 1106 nsec = div_u64(nsec, 3); /* can be optimized */ 1107 if (audio_tstamp_config->report_delay) 1108 nsec = skl_adjust_codec_delay(substream, nsec); 1109 1110 *audio_ts = ns_to_timespec(nsec); 1111 1112 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK; 1113 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */ 1114 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */ 1115 1116 } else { 1117 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; 1118 } 1119 1120 return 0; 1121 } 1122 1123 static const struct snd_pcm_ops skl_platform_ops = { 1124 .open = skl_platform_open, 1125 .ioctl = snd_pcm_lib_ioctl, 1126 .trigger = skl_platform_pcm_trigger, 1127 .pointer = skl_platform_pcm_pointer, 1128 .get_time_info = skl_get_time_info, 1129 .mmap = snd_pcm_lib_default_mmap, 1130 .page = snd_pcm_sgbuf_ops_page, 1131 }; 1132 1133 static void skl_pcm_free(struct snd_pcm *pcm) 1134 { 1135 snd_pcm_lib_preallocate_free_for_all(pcm); 1136 } 1137 1138 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) 1139 1140 static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd) 1141 { 1142 struct snd_soc_dai *dai = rtd->cpu_dai; 1143 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 1144 struct snd_pcm *pcm = rtd->pcm; 1145 unsigned int size; 1146 int retval = 0; 1147 struct skl *skl = ebus_to_skl(ebus); 1148 1149 if (dai->driver->playback.channels_min || 1150 dai->driver->capture.channels_min) { 1151 /* buffer pre-allocation */ 1152 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; 1153 if (size > MAX_PREALLOC_SIZE) 1154 size = MAX_PREALLOC_SIZE; 1155 retval = snd_pcm_lib_preallocate_pages_for_all(pcm, 1156 SNDRV_DMA_TYPE_DEV_SG, 1157 snd_dma_pci_data(skl->pci), 1158 size, MAX_PREALLOC_SIZE); 1159 if (retval) { 1160 dev_err(dai->dev, "dma buffer allocationf fail\n"); 1161 return retval; 1162 } 1163 } 1164 1165 return retval; 1166 } 1167 1168 static int skl_populate_modules(struct skl *skl) 1169 { 1170 struct skl_pipeline *p; 1171 struct skl_pipe_module *m; 1172 struct snd_soc_dapm_widget *w; 1173 struct skl_module_cfg *mconfig; 1174 int ret; 1175 1176 list_for_each_entry(p, &skl->ppl_list, node) { 1177 list_for_each_entry(m, &p->pipe->w_list, node) { 1178 1179 w = m->w; 1180 mconfig = w->priv; 1181 1182 ret = snd_skl_get_module_info(skl->skl_sst, mconfig); 1183 if (ret < 0) { 1184 dev_err(skl->skl_sst->dev, 1185 "query module info failed:%d\n", ret); 1186 goto err; 1187 } 1188 } 1189 } 1190 err: 1191 return ret; 1192 } 1193 1194 static int skl_platform_soc_probe(struct snd_soc_platform *platform) 1195 { 1196 struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev); 1197 struct skl *skl = ebus_to_skl(ebus); 1198 const struct skl_dsp_ops *ops; 1199 int ret; 1200 1201 pm_runtime_get_sync(platform->dev); 1202 if ((ebus_to_hbus(ebus))->ppcap) { 1203 ret = skl_tplg_init(platform, ebus); 1204 if (ret < 0) { 1205 dev_err(platform->dev, "Failed to init topology!\n"); 1206 return ret; 1207 } 1208 skl->platform = platform; 1209 1210 /* load the firmwares, since all is set */ 1211 ops = skl_get_dsp_ops(skl->pci->device); 1212 if (!ops) 1213 return -EIO; 1214 1215 if (skl->skl_sst->is_first_boot == false) { 1216 dev_err(platform->dev, "DSP reports first boot done!!!\n"); 1217 return -EIO; 1218 } 1219 1220 ret = ops->init_fw(platform->dev, skl->skl_sst); 1221 if (ret < 0) { 1222 dev_err(platform->dev, "Failed to boot first fw: %d\n", ret); 1223 return ret; 1224 } 1225 skl_populate_modules(skl); 1226 skl->skl_sst->update_d0i3c = skl_update_d0i3c; 1227 } 1228 pm_runtime_mark_last_busy(platform->dev); 1229 pm_runtime_put_autosuspend(platform->dev); 1230 1231 return 0; 1232 } 1233 static struct snd_soc_platform_driver skl_platform_drv = { 1234 .probe = skl_platform_soc_probe, 1235 .ops = &skl_platform_ops, 1236 .pcm_new = skl_pcm_new, 1237 .pcm_free = skl_pcm_free, 1238 }; 1239 1240 static const struct snd_soc_component_driver skl_component = { 1241 .name = "pcm", 1242 }; 1243 1244 int skl_platform_register(struct device *dev) 1245 { 1246 int ret; 1247 struct hdac_ext_bus *ebus = dev_get_drvdata(dev); 1248 struct skl *skl = ebus_to_skl(ebus); 1249 1250 INIT_LIST_HEAD(&skl->ppl_list); 1251 1252 ret = snd_soc_register_platform(dev, &skl_platform_drv); 1253 if (ret) { 1254 dev_err(dev, "soc platform registration failed %d\n", ret); 1255 return ret; 1256 } 1257 ret = snd_soc_register_component(dev, &skl_component, 1258 skl_platform_dai, 1259 ARRAY_SIZE(skl_platform_dai)); 1260 if (ret) { 1261 dev_err(dev, "soc component registration failed %d\n", ret); 1262 snd_soc_unregister_platform(dev); 1263 } 1264 1265 return ret; 1266 1267 } 1268 1269 int skl_platform_unregister(struct device *dev) 1270 { 1271 snd_soc_unregister_component(dev); 1272 snd_soc_unregister_platform(dev); 1273 return 0; 1274 } 1275