1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 *
8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 *
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 */
12
13 #include <linux/pci.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/delay.h>
16 #include <sound/hdaudio.h>
17 #include <sound/pcm_params.h>
18 #include <sound/soc.h>
19 #include "skl.h"
20 #include "skl-topology.h"
21 #include "skl-sst-dsp.h"
22 #include "skl-sst-ipc.h"
23
24 #define HDA_MONO 1
25 #define HDA_STEREO 2
26 #define HDA_QUAD 4
27 #define HDA_MAX 8
28
29 static const struct snd_pcm_hardware azx_pcm_hw = {
30 .info = (SNDRV_PCM_INFO_MMAP |
31 SNDRV_PCM_INFO_INTERLEAVED |
32 SNDRV_PCM_INFO_BLOCK_TRANSFER |
33 SNDRV_PCM_INFO_MMAP_VALID |
34 SNDRV_PCM_INFO_PAUSE |
35 SNDRV_PCM_INFO_RESUME |
36 SNDRV_PCM_INFO_SYNC_START |
37 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
38 SNDRV_PCM_INFO_HAS_LINK_ATIME |
39 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
40 .formats = SNDRV_PCM_FMTBIT_S16_LE |
41 SNDRV_PCM_FMTBIT_S32_LE |
42 SNDRV_PCM_FMTBIT_S24_LE,
43 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
44 SNDRV_PCM_RATE_8000,
45 .rate_min = 8000,
46 .rate_max = 48000,
47 .channels_min = 1,
48 .channels_max = 8,
49 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
50 .period_bytes_min = 128,
51 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
52 .periods_min = 2,
53 .periods_max = AZX_MAX_FRAG,
54 .fifo_size = 0,
55 };
56
57 static inline
get_hdac_ext_stream(struct snd_pcm_substream * substream)58 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
59 {
60 return substream->runtime->private_data;
61 }
62
get_bus_ctx(struct snd_pcm_substream * substream)63 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
64 {
65 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
66 struct hdac_stream *hstream = hdac_stream(stream);
67 struct hdac_bus *bus = hstream->bus;
68 return bus;
69 }
70
skl_substream_alloc_pages(struct hdac_bus * bus,struct snd_pcm_substream * substream,size_t size)71 static int skl_substream_alloc_pages(struct hdac_bus *bus,
72 struct snd_pcm_substream *substream,
73 size_t size)
74 {
75 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
76
77 hdac_stream(stream)->bufsize = 0;
78 hdac_stream(stream)->period_bytes = 0;
79 hdac_stream(stream)->format_val = 0;
80
81 return 0;
82 }
83
skl_set_pcm_constrains(struct hdac_bus * bus,struct snd_pcm_runtime * runtime)84 static void skl_set_pcm_constrains(struct hdac_bus *bus,
85 struct snd_pcm_runtime *runtime)
86 {
87 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
88
89 /* avoid wrap-around with wall-clock */
90 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
91 20, 178000000);
92 }
93
skl_get_host_stream_type(struct hdac_bus * bus)94 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
95 {
96 if (bus->ppcap)
97 return HDAC_EXT_STREAM_TYPE_HOST;
98 else
99 return HDAC_EXT_STREAM_TYPE_COUPLED;
100 }
101
102 /*
103 * check if the stream opened is marked as ignore_suspend by machine, if so
104 * then enable suspend_active refcount
105 *
106 * The count supend_active does not need lock as it is used in open/close
107 * and suspend context
108 */
skl_set_suspend_active(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,bool enable)109 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
110 struct snd_soc_dai *dai, bool enable)
111 {
112 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
113 struct snd_soc_dapm_widget *w;
114 struct skl_dev *skl = bus_to_skl(bus);
115
116 w = snd_soc_dai_get_widget(dai, substream->stream);
117
118 if (w->ignore_suspend && enable)
119 skl->supend_active++;
120 else if (w->ignore_suspend && !enable)
121 skl->supend_active--;
122 }
123
skl_pcm_host_dma_prepare(struct device * dev,struct skl_pipe_params * params)124 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
125 {
126 struct hdac_bus *bus = dev_get_drvdata(dev);
127 struct skl_dev *skl = bus_to_skl(bus);
128 unsigned int format_val;
129 struct hdac_stream *hstream;
130 struct hdac_ext_stream *stream;
131 int err;
132
133 hstream = snd_hdac_get_stream(bus, params->stream,
134 params->host_dma_id + 1);
135 if (!hstream)
136 return -EINVAL;
137
138 stream = stream_to_hdac_ext_stream(hstream);
139 snd_hdac_ext_stream_decouple(bus, stream, true);
140
141 format_val = snd_hdac_calc_stream_format(params->s_freq,
142 params->ch, params->format, params->host_bps, 0);
143
144 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
145 format_val, params->s_freq, params->ch, params->format);
146
147 snd_hdac_stream_reset(hdac_stream(stream));
148 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
149 if (err < 0)
150 return err;
151
152 /*
153 * The recommended SDxFMT programming sequence for BXT
154 * platforms is to couple the stream before writing the format
155 */
156 if (HDA_CONTROLLER_IS_APL(skl->pci)) {
157 snd_hdac_ext_stream_decouple(bus, stream, false);
158 err = snd_hdac_stream_setup(hdac_stream(stream));
159 snd_hdac_ext_stream_decouple(bus, stream, true);
160 } else {
161 err = snd_hdac_stream_setup(hdac_stream(stream));
162 }
163
164 if (err < 0)
165 return err;
166
167 hdac_stream(stream)->prepared = 1;
168
169 return 0;
170 }
171
skl_pcm_link_dma_prepare(struct device * dev,struct skl_pipe_params * params)172 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
173 {
174 struct hdac_bus *bus = dev_get_drvdata(dev);
175 unsigned int format_val;
176 struct hdac_stream *hstream;
177 struct hdac_ext_stream *stream;
178 struct hdac_ext_link *link;
179 unsigned char stream_tag;
180
181 hstream = snd_hdac_get_stream(bus, params->stream,
182 params->link_dma_id + 1);
183 if (!hstream)
184 return -EINVAL;
185
186 stream = stream_to_hdac_ext_stream(hstream);
187 snd_hdac_ext_stream_decouple(bus, stream, true);
188 format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
189 params->format, params->link_bps, 0);
190
191 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
192 format_val, params->s_freq, params->ch, params->format);
193
194 snd_hdac_ext_stream_reset(stream);
195
196 snd_hdac_ext_stream_setup(stream, format_val);
197
198 stream_tag = hstream->stream_tag;
199 if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) {
200 list_for_each_entry(link, &bus->hlink_list, list) {
201 if (link->index == params->link_index)
202 snd_hdac_ext_bus_link_set_stream_id(link,
203 stream_tag);
204 }
205 }
206
207 stream->link_prepared = 1;
208
209 return 0;
210 }
211
skl_pcm_open(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)212 static int skl_pcm_open(struct snd_pcm_substream *substream,
213 struct snd_soc_dai *dai)
214 {
215 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
216 struct hdac_ext_stream *stream;
217 struct snd_pcm_runtime *runtime = substream->runtime;
218 struct skl_dma_params *dma_params;
219 struct skl_dev *skl = get_skl_ctx(dai->dev);
220 struct skl_module_cfg *mconfig;
221
222 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
223
224 stream = snd_hdac_ext_stream_assign(bus, substream,
225 skl_get_host_stream_type(bus));
226 if (stream == NULL)
227 return -EBUSY;
228
229 skl_set_pcm_constrains(bus, runtime);
230
231 /*
232 * disable WALLCLOCK timestamps for capture streams
233 * until we figure out how to handle digital inputs
234 */
235 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
236 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
237 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
238 }
239
240 runtime->private_data = stream;
241
242 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
243 if (!dma_params)
244 return -ENOMEM;
245
246 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
247 snd_soc_dai_set_dma_data(dai, substream, dma_params);
248
249 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
250 dma_params->stream_tag);
251 skl_set_suspend_active(substream, dai, true);
252 snd_pcm_set_sync(substream);
253
254 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
255 if (!mconfig) {
256 kfree(dma_params);
257 return -EINVAL;
258 }
259
260 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
261
262 return 0;
263 }
264
skl_pcm_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)265 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
266 struct snd_soc_dai *dai)
267 {
268 struct skl_dev *skl = get_skl_ctx(dai->dev);
269 struct skl_module_cfg *mconfig;
270 int ret;
271
272 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
273
274 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
275
276 /*
277 * In case of XRUN recovery or in the case when the application
278 * calls prepare another time, reset the FW pipe to clean state
279 */
280 if (mconfig &&
281 (substream->runtime->state == SNDRV_PCM_STATE_XRUN ||
282 mconfig->pipe->state == SKL_PIPE_CREATED ||
283 mconfig->pipe->state == SKL_PIPE_PAUSED)) {
284
285 ret = skl_reset_pipe(skl, mconfig->pipe);
286
287 if (ret < 0)
288 return ret;
289
290 ret = skl_pcm_host_dma_prepare(dai->dev,
291 mconfig->pipe->p_params);
292 if (ret < 0)
293 return ret;
294 }
295
296 return 0;
297 }
298
skl_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)299 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
300 struct snd_pcm_hw_params *params,
301 struct snd_soc_dai *dai)
302 {
303 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
304 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
305 struct snd_pcm_runtime *runtime = substream->runtime;
306 struct skl_pipe_params p_params = {0};
307 struct skl_module_cfg *m_cfg;
308 int ret, dma_id;
309
310 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
311 ret = skl_substream_alloc_pages(bus, substream,
312 params_buffer_bytes(params));
313 if (ret < 0)
314 return ret;
315
316 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
317 runtime->rate, runtime->channels, runtime->format);
318
319 dma_id = hdac_stream(stream)->stream_tag - 1;
320 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
321
322 p_params.s_fmt = snd_pcm_format_width(params_format(params));
323 p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
324 p_params.ch = params_channels(params);
325 p_params.s_freq = params_rate(params);
326 p_params.host_dma_id = dma_id;
327 p_params.stream = substream->stream;
328 p_params.format = params_format(params);
329 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
330 p_params.host_bps = dai->driver->playback.sig_bits;
331 else
332 p_params.host_bps = dai->driver->capture.sig_bits;
333
334
335 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
336 if (m_cfg)
337 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
338
339 return 0;
340 }
341
skl_pcm_close(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)342 static void skl_pcm_close(struct snd_pcm_substream *substream,
343 struct snd_soc_dai *dai)
344 {
345 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
346 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
347 struct skl_dma_params *dma_params = NULL;
348 struct skl_dev *skl = bus_to_skl(bus);
349 struct skl_module_cfg *mconfig;
350
351 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
352
353 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
354
355 dma_params = snd_soc_dai_get_dma_data(dai, substream);
356 /*
357 * now we should set this to NULL as we are freeing by the
358 * dma_params
359 */
360 snd_soc_dai_set_dma_data(dai, substream, NULL);
361 skl_set_suspend_active(substream, dai, false);
362
363 /*
364 * check if close is for "Reference Pin" and set back the
365 * CGCTL.MISCBDCGE if disabled by driver
366 */
367 if (!strncmp(dai->name, "Reference Pin", 13) &&
368 skl->miscbdcg_disabled) {
369 skl->enable_miscbdcge(dai->dev, true);
370 skl->miscbdcg_disabled = false;
371 }
372
373 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
374 if (mconfig)
375 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
376
377 kfree(dma_params);
378 }
379
skl_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)380 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
381 struct snd_soc_dai *dai)
382 {
383 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
384 struct skl_dev *skl = get_skl_ctx(dai->dev);
385 struct skl_module_cfg *mconfig;
386 int ret;
387
388 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
389
390 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
391
392 if (mconfig) {
393 ret = skl_reset_pipe(skl, mconfig->pipe);
394 if (ret < 0)
395 dev_err(dai->dev, "%s:Reset failed ret =%d",
396 __func__, ret);
397 }
398
399 snd_hdac_stream_cleanup(hdac_stream(stream));
400 hdac_stream(stream)->prepared = 0;
401
402 return 0;
403 }
404
skl_be_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)405 static int skl_be_hw_params(struct snd_pcm_substream *substream,
406 struct snd_pcm_hw_params *params,
407 struct snd_soc_dai *dai)
408 {
409 struct skl_pipe_params p_params = {0};
410
411 p_params.s_fmt = snd_pcm_format_width(params_format(params));
412 p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
413 p_params.ch = params_channels(params);
414 p_params.s_freq = params_rate(params);
415 p_params.stream = substream->stream;
416
417 return skl_tplg_be_update_params(dai, &p_params);
418 }
419
skl_decoupled_trigger(struct snd_pcm_substream * substream,int cmd)420 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
421 int cmd)
422 {
423 struct hdac_bus *bus = get_bus_ctx(substream);
424 struct hdac_ext_stream *stream;
425 int start;
426 unsigned long cookie;
427 struct hdac_stream *hstr;
428
429 stream = get_hdac_ext_stream(substream);
430 hstr = hdac_stream(stream);
431
432 if (!hstr->prepared)
433 return -EPIPE;
434
435 switch (cmd) {
436 case SNDRV_PCM_TRIGGER_START:
437 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
438 case SNDRV_PCM_TRIGGER_RESUME:
439 start = 1;
440 break;
441
442 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
443 case SNDRV_PCM_TRIGGER_SUSPEND:
444 case SNDRV_PCM_TRIGGER_STOP:
445 start = 0;
446 break;
447
448 default:
449 return -EINVAL;
450 }
451
452 spin_lock_irqsave(&bus->reg_lock, cookie);
453
454 if (start) {
455 snd_hdac_stream_start(hdac_stream(stream));
456 snd_hdac_stream_timecounter_init(hstr, 0);
457 } else {
458 snd_hdac_stream_stop(hdac_stream(stream));
459 }
460
461 spin_unlock_irqrestore(&bus->reg_lock, cookie);
462
463 return 0;
464 }
465
skl_pcm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)466 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
467 struct snd_soc_dai *dai)
468 {
469 struct skl_dev *skl = get_skl_ctx(dai->dev);
470 struct skl_module_cfg *mconfig;
471 struct hdac_bus *bus = get_bus_ctx(substream);
472 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
473 struct hdac_stream *hstream = hdac_stream(stream);
474 struct snd_soc_dapm_widget *w;
475 int ret;
476
477 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
478 if (!mconfig)
479 return -EIO;
480
481 w = snd_soc_dai_get_widget(dai, substream->stream);
482
483 switch (cmd) {
484 case SNDRV_PCM_TRIGGER_RESUME:
485 if (!w->ignore_suspend) {
486 /*
487 * enable DMA Resume enable bit for the stream, set the
488 * dpib & lpib position to resume before starting the
489 * DMA
490 */
491 snd_hdac_stream_drsm_enable(bus, true, hstream->index);
492 snd_hdac_stream_set_dpibr(bus, hstream, hstream->lpib);
493 snd_hdac_stream_set_lpib(hstream, hstream->lpib);
494 }
495 fallthrough;
496
497 case SNDRV_PCM_TRIGGER_START:
498 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
499 /*
500 * Start HOST DMA and Start FE Pipe.This is to make sure that
501 * there are no underrun/overrun in the case when the FE
502 * pipeline is started but there is a delay in starting the
503 * DMA channel on the host.
504 */
505 ret = skl_decoupled_trigger(substream, cmd);
506 if (ret < 0)
507 return ret;
508 return skl_run_pipe(skl, mconfig->pipe);
509
510 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
511 case SNDRV_PCM_TRIGGER_SUSPEND:
512 case SNDRV_PCM_TRIGGER_STOP:
513 /*
514 * Stop FE Pipe first and stop DMA. This is to make sure that
515 * there are no underrun/overrun in the case if there is a delay
516 * between the two operations.
517 */
518 ret = skl_stop_pipe(skl, mconfig->pipe);
519 if (ret < 0)
520 return ret;
521
522 ret = skl_decoupled_trigger(substream, cmd);
523 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
524 /* save the dpib and lpib positions */
525 hstream->dpib = readl(bus->remap_addr +
526 AZX_REG_VS_SDXDPIB_XBASE +
527 (AZX_REG_VS_SDXDPIB_XINTERVAL *
528 hstream->index));
529
530 hstream->lpib = snd_hdac_stream_get_pos_lpib(hstream);
531
532 snd_hdac_ext_stream_decouple(bus, stream, false);
533 }
534 break;
535
536 default:
537 return -EINVAL;
538 }
539
540 return 0;
541 }
542
543
skl_link_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)544 static int skl_link_hw_params(struct snd_pcm_substream *substream,
545 struct snd_pcm_hw_params *params,
546 struct snd_soc_dai *dai)
547 {
548 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
549 struct hdac_ext_stream *link_dev;
550 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
551 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
552 struct skl_pipe_params p_params = {0};
553 struct hdac_ext_link *link;
554 int stream_tag;
555
556 link_dev = snd_hdac_ext_stream_assign(bus, substream,
557 HDAC_EXT_STREAM_TYPE_LINK);
558 if (!link_dev)
559 return -EBUSY;
560
561 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
562
563 link = snd_hdac_ext_bus_get_hlink_by_name(bus, codec_dai->component->name);
564 if (!link)
565 return -EINVAL;
566
567 stream_tag = hdac_stream(link_dev)->stream_tag;
568
569 /* set the hdac_stream in the codec dai */
570 snd_soc_dai_set_stream(codec_dai, hdac_stream(link_dev), substream->stream);
571
572 p_params.s_fmt = snd_pcm_format_width(params_format(params));
573 p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
574 p_params.ch = params_channels(params);
575 p_params.s_freq = params_rate(params);
576 p_params.stream = substream->stream;
577 p_params.link_dma_id = stream_tag - 1;
578 p_params.link_index = link->index;
579 p_params.format = params_format(params);
580
581 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
582 p_params.link_bps = codec_dai->driver->playback.sig_bits;
583 else
584 p_params.link_bps = codec_dai->driver->capture.sig_bits;
585
586 return skl_tplg_be_update_params(dai, &p_params);
587 }
588
skl_link_pcm_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)589 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
590 struct snd_soc_dai *dai)
591 {
592 struct skl_dev *skl = get_skl_ctx(dai->dev);
593 struct skl_module_cfg *mconfig = NULL;
594
595 /* In case of XRUN recovery, reset the FW pipe to clean state */
596 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
597 if (mconfig && !mconfig->pipe->passthru &&
598 (substream->runtime->state == SNDRV_PCM_STATE_XRUN))
599 skl_reset_pipe(skl, mconfig->pipe);
600
601 return 0;
602 }
603
skl_link_pcm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)604 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
605 int cmd, struct snd_soc_dai *dai)
606 {
607 struct hdac_ext_stream *link_dev =
608 snd_soc_dai_get_dma_data(dai, substream);
609 struct hdac_bus *bus = get_bus_ctx(substream);
610 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
611
612 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
613 switch (cmd) {
614 case SNDRV_PCM_TRIGGER_RESUME:
615 case SNDRV_PCM_TRIGGER_START:
616 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
617 snd_hdac_ext_stream_start(link_dev);
618 break;
619
620 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
621 case SNDRV_PCM_TRIGGER_SUSPEND:
622 case SNDRV_PCM_TRIGGER_STOP:
623 snd_hdac_ext_stream_clear(link_dev);
624 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
625 snd_hdac_ext_stream_decouple(bus, stream, false);
626 break;
627
628 default:
629 return -EINVAL;
630 }
631 return 0;
632 }
633
skl_link_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)634 static int skl_link_hw_free(struct snd_pcm_substream *substream,
635 struct snd_soc_dai *dai)
636 {
637 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
638 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
639 struct hdac_ext_stream *link_dev =
640 snd_soc_dai_get_dma_data(dai, substream);
641 struct hdac_ext_link *link;
642 unsigned char stream_tag;
643
644 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
645
646 link_dev->link_prepared = 0;
647
648 link = snd_hdac_ext_bus_get_hlink_by_name(bus, asoc_rtd_to_codec(rtd, 0)->component->name);
649 if (!link)
650 return -EINVAL;
651
652 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
653 stream_tag = hdac_stream(link_dev)->stream_tag;
654 snd_hdac_ext_bus_link_clear_stream_id(link, stream_tag);
655 }
656
657 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
658 return 0;
659 }
660
661 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
662 .startup = skl_pcm_open,
663 .shutdown = skl_pcm_close,
664 .prepare = skl_pcm_prepare,
665 .hw_params = skl_pcm_hw_params,
666 .hw_free = skl_pcm_hw_free,
667 .trigger = skl_pcm_trigger,
668 };
669
670 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
671 .hw_params = skl_be_hw_params,
672 };
673
674 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
675 .hw_params = skl_be_hw_params,
676 };
677
678 static const struct snd_soc_dai_ops skl_link_dai_ops = {
679 .prepare = skl_link_pcm_prepare,
680 .hw_params = skl_link_hw_params,
681 .hw_free = skl_link_hw_free,
682 .trigger = skl_link_pcm_trigger,
683 };
684
685 static struct snd_soc_dai_driver skl_fe_dai[] = {
686 {
687 .name = "System Pin",
688 .ops = &skl_pcm_dai_ops,
689 .playback = {
690 .stream_name = "System Playback",
691 .channels_min = HDA_MONO,
692 .channels_max = HDA_STEREO,
693 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
694 .formats = SNDRV_PCM_FMTBIT_S16_LE |
695 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
696 .sig_bits = 32,
697 },
698 .capture = {
699 .stream_name = "System Capture",
700 .channels_min = HDA_MONO,
701 .channels_max = HDA_STEREO,
702 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
703 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
704 .sig_bits = 32,
705 },
706 },
707 {
708 .name = "System Pin2",
709 .ops = &skl_pcm_dai_ops,
710 .playback = {
711 .stream_name = "Headset Playback",
712 .channels_min = HDA_MONO,
713 .channels_max = HDA_STEREO,
714 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
715 SNDRV_PCM_RATE_8000,
716 .formats = SNDRV_PCM_FMTBIT_S16_LE |
717 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
718 },
719 },
720 {
721 .name = "Echoref Pin",
722 .ops = &skl_pcm_dai_ops,
723 .capture = {
724 .stream_name = "Echoreference Capture",
725 .channels_min = HDA_STEREO,
726 .channels_max = HDA_STEREO,
727 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
728 SNDRV_PCM_RATE_8000,
729 .formats = SNDRV_PCM_FMTBIT_S16_LE |
730 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
731 },
732 },
733 {
734 .name = "Reference Pin",
735 .ops = &skl_pcm_dai_ops,
736 .capture = {
737 .stream_name = "Reference Capture",
738 .channels_min = HDA_MONO,
739 .channels_max = HDA_QUAD,
740 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
741 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
742 .sig_bits = 32,
743 },
744 },
745 {
746 .name = "Deepbuffer Pin",
747 .ops = &skl_pcm_dai_ops,
748 .playback = {
749 .stream_name = "Deepbuffer Playback",
750 .channels_min = HDA_STEREO,
751 .channels_max = HDA_STEREO,
752 .rates = SNDRV_PCM_RATE_48000,
753 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
754 .sig_bits = 32,
755 },
756 },
757 {
758 .name = "LowLatency Pin",
759 .ops = &skl_pcm_dai_ops,
760 .playback = {
761 .stream_name = "Low Latency Playback",
762 .channels_min = HDA_STEREO,
763 .channels_max = HDA_STEREO,
764 .rates = SNDRV_PCM_RATE_48000,
765 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
766 .sig_bits = 32,
767 },
768 },
769 {
770 .name = "DMIC Pin",
771 .ops = &skl_pcm_dai_ops,
772 .capture = {
773 .stream_name = "DMIC Capture",
774 .channels_min = HDA_MONO,
775 .channels_max = HDA_QUAD,
776 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
777 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
778 .sig_bits = 32,
779 },
780 },
781 {
782 .name = "HDMI1 Pin",
783 .ops = &skl_pcm_dai_ops,
784 .playback = {
785 .stream_name = "HDMI1 Playback",
786 .channels_min = HDA_STEREO,
787 .channels_max = 8,
788 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
789 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
790 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
791 SNDRV_PCM_RATE_192000,
792 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
793 SNDRV_PCM_FMTBIT_S32_LE,
794 .sig_bits = 32,
795 },
796 },
797 {
798 .name = "HDMI2 Pin",
799 .ops = &skl_pcm_dai_ops,
800 .playback = {
801 .stream_name = "HDMI2 Playback",
802 .channels_min = HDA_STEREO,
803 .channels_max = 8,
804 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
805 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
806 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
807 SNDRV_PCM_RATE_192000,
808 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
809 SNDRV_PCM_FMTBIT_S32_LE,
810 .sig_bits = 32,
811 },
812 },
813 {
814 .name = "HDMI3 Pin",
815 .ops = &skl_pcm_dai_ops,
816 .playback = {
817 .stream_name = "HDMI3 Playback",
818 .channels_min = HDA_STEREO,
819 .channels_max = 8,
820 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
821 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
822 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
823 SNDRV_PCM_RATE_192000,
824 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
825 SNDRV_PCM_FMTBIT_S32_LE,
826 .sig_bits = 32,
827 },
828 },
829 };
830
831 /* BE CPU Dais */
832 static struct snd_soc_dai_driver skl_platform_dai[] = {
833 {
834 .name = "SSP0 Pin",
835 .ops = &skl_be_ssp_dai_ops,
836 .playback = {
837 .stream_name = "ssp0 Tx",
838 .channels_min = HDA_STEREO,
839 .channels_max = HDA_STEREO,
840 .rates = SNDRV_PCM_RATE_48000,
841 .formats = SNDRV_PCM_FMTBIT_S16_LE,
842 },
843 .capture = {
844 .stream_name = "ssp0 Rx",
845 .channels_min = HDA_STEREO,
846 .channels_max = HDA_STEREO,
847 .rates = SNDRV_PCM_RATE_48000,
848 .formats = SNDRV_PCM_FMTBIT_S16_LE,
849 },
850 },
851 {
852 .name = "SSP1 Pin",
853 .ops = &skl_be_ssp_dai_ops,
854 .playback = {
855 .stream_name = "ssp1 Tx",
856 .channels_min = HDA_STEREO,
857 .channels_max = HDA_STEREO,
858 .rates = SNDRV_PCM_RATE_48000,
859 .formats = SNDRV_PCM_FMTBIT_S16_LE,
860 },
861 .capture = {
862 .stream_name = "ssp1 Rx",
863 .channels_min = HDA_STEREO,
864 .channels_max = HDA_STEREO,
865 .rates = SNDRV_PCM_RATE_48000,
866 .formats = SNDRV_PCM_FMTBIT_S16_LE,
867 },
868 },
869 {
870 .name = "SSP2 Pin",
871 .ops = &skl_be_ssp_dai_ops,
872 .playback = {
873 .stream_name = "ssp2 Tx",
874 .channels_min = HDA_STEREO,
875 .channels_max = HDA_STEREO,
876 .rates = SNDRV_PCM_RATE_48000,
877 .formats = SNDRV_PCM_FMTBIT_S16_LE,
878 },
879 .capture = {
880 .stream_name = "ssp2 Rx",
881 .channels_min = HDA_STEREO,
882 .channels_max = HDA_STEREO,
883 .rates = SNDRV_PCM_RATE_48000,
884 .formats = SNDRV_PCM_FMTBIT_S16_LE,
885 },
886 },
887 {
888 .name = "SSP3 Pin",
889 .ops = &skl_be_ssp_dai_ops,
890 .playback = {
891 .stream_name = "ssp3 Tx",
892 .channels_min = HDA_STEREO,
893 .channels_max = HDA_STEREO,
894 .rates = SNDRV_PCM_RATE_48000,
895 .formats = SNDRV_PCM_FMTBIT_S16_LE,
896 },
897 .capture = {
898 .stream_name = "ssp3 Rx",
899 .channels_min = HDA_STEREO,
900 .channels_max = HDA_STEREO,
901 .rates = SNDRV_PCM_RATE_48000,
902 .formats = SNDRV_PCM_FMTBIT_S16_LE,
903 },
904 },
905 {
906 .name = "SSP4 Pin",
907 .ops = &skl_be_ssp_dai_ops,
908 .playback = {
909 .stream_name = "ssp4 Tx",
910 .channels_min = HDA_STEREO,
911 .channels_max = HDA_STEREO,
912 .rates = SNDRV_PCM_RATE_48000,
913 .formats = SNDRV_PCM_FMTBIT_S16_LE,
914 },
915 .capture = {
916 .stream_name = "ssp4 Rx",
917 .channels_min = HDA_STEREO,
918 .channels_max = HDA_STEREO,
919 .rates = SNDRV_PCM_RATE_48000,
920 .formats = SNDRV_PCM_FMTBIT_S16_LE,
921 },
922 },
923 {
924 .name = "SSP5 Pin",
925 .ops = &skl_be_ssp_dai_ops,
926 .playback = {
927 .stream_name = "ssp5 Tx",
928 .channels_min = HDA_STEREO,
929 .channels_max = HDA_STEREO,
930 .rates = SNDRV_PCM_RATE_48000,
931 .formats = SNDRV_PCM_FMTBIT_S16_LE,
932 },
933 .capture = {
934 .stream_name = "ssp5 Rx",
935 .channels_min = HDA_STEREO,
936 .channels_max = HDA_STEREO,
937 .rates = SNDRV_PCM_RATE_48000,
938 .formats = SNDRV_PCM_FMTBIT_S16_LE,
939 },
940 },
941 {
942 .name = "iDisp1 Pin",
943 .ops = &skl_link_dai_ops,
944 .playback = {
945 .stream_name = "iDisp1 Tx",
946 .channels_min = HDA_STEREO,
947 .channels_max = 8,
948 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
949 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
950 SNDRV_PCM_FMTBIT_S24_LE,
951 },
952 },
953 {
954 .name = "iDisp2 Pin",
955 .ops = &skl_link_dai_ops,
956 .playback = {
957 .stream_name = "iDisp2 Tx",
958 .channels_min = HDA_STEREO,
959 .channels_max = 8,
960 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
961 SNDRV_PCM_RATE_48000,
962 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
963 SNDRV_PCM_FMTBIT_S24_LE,
964 },
965 },
966 {
967 .name = "iDisp3 Pin",
968 .ops = &skl_link_dai_ops,
969 .playback = {
970 .stream_name = "iDisp3 Tx",
971 .channels_min = HDA_STEREO,
972 .channels_max = 8,
973 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
974 SNDRV_PCM_RATE_48000,
975 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
976 SNDRV_PCM_FMTBIT_S24_LE,
977 },
978 },
979 {
980 .name = "DMIC01 Pin",
981 .ops = &skl_dmic_dai_ops,
982 .capture = {
983 .stream_name = "DMIC01 Rx",
984 .channels_min = HDA_MONO,
985 .channels_max = HDA_QUAD,
986 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
987 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
988 },
989 },
990 {
991 .name = "DMIC16k Pin",
992 .ops = &skl_dmic_dai_ops,
993 .capture = {
994 .stream_name = "DMIC16k Rx",
995 .channels_min = HDA_MONO,
996 .channels_max = HDA_QUAD,
997 .rates = SNDRV_PCM_RATE_16000,
998 .formats = SNDRV_PCM_FMTBIT_S16_LE,
999 },
1000 },
1001 {
1002 .name = "Analog CPU DAI",
1003 .ops = &skl_link_dai_ops,
1004 .playback = {
1005 .stream_name = "Analog CPU Playback",
1006 .channels_min = HDA_MONO,
1007 .channels_max = HDA_MAX,
1008 .rates = SNDRV_PCM_RATE_8000_192000,
1009 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1010 SNDRV_PCM_FMTBIT_S32_LE,
1011 },
1012 .capture = {
1013 .stream_name = "Analog CPU Capture",
1014 .channels_min = HDA_MONO,
1015 .channels_max = HDA_MAX,
1016 .rates = SNDRV_PCM_RATE_8000_192000,
1017 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1018 SNDRV_PCM_FMTBIT_S32_LE,
1019 },
1020 },
1021 {
1022 .name = "Alt Analog CPU DAI",
1023 .ops = &skl_link_dai_ops,
1024 .playback = {
1025 .stream_name = "Alt Analog CPU Playback",
1026 .channels_min = HDA_MONO,
1027 .channels_max = HDA_MAX,
1028 .rates = SNDRV_PCM_RATE_8000_192000,
1029 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1030 SNDRV_PCM_FMTBIT_S32_LE,
1031 },
1032 .capture = {
1033 .stream_name = "Alt Analog CPU Capture",
1034 .channels_min = HDA_MONO,
1035 .channels_max = HDA_MAX,
1036 .rates = SNDRV_PCM_RATE_8000_192000,
1037 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1038 SNDRV_PCM_FMTBIT_S32_LE,
1039 },
1040 },
1041 {
1042 .name = "Digital CPU DAI",
1043 .ops = &skl_link_dai_ops,
1044 .playback = {
1045 .stream_name = "Digital CPU Playback",
1046 .channels_min = HDA_MONO,
1047 .channels_max = HDA_MAX,
1048 .rates = SNDRV_PCM_RATE_8000_192000,
1049 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1050 SNDRV_PCM_FMTBIT_S32_LE,
1051 },
1052 .capture = {
1053 .stream_name = "Digital CPU Capture",
1054 .channels_min = HDA_MONO,
1055 .channels_max = HDA_MAX,
1056 .rates = SNDRV_PCM_RATE_8000_192000,
1057 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1058 SNDRV_PCM_FMTBIT_S32_LE,
1059 },
1060 },
1061 };
1062
skl_dai_load(struct snd_soc_component * cmp,int index,struct snd_soc_dai_driver * dai_drv,struct snd_soc_tplg_pcm * pcm,struct snd_soc_dai * dai)1063 int skl_dai_load(struct snd_soc_component *cmp, int index,
1064 struct snd_soc_dai_driver *dai_drv,
1065 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1066 {
1067 dai_drv->ops = &skl_pcm_dai_ops;
1068
1069 return 0;
1070 }
1071
skl_platform_soc_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)1072 static int skl_platform_soc_open(struct snd_soc_component *component,
1073 struct snd_pcm_substream *substream)
1074 {
1075 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1076 struct snd_soc_dai_link *dai_link = rtd->dai_link;
1077
1078 dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__,
1079 dai_link->cpus->dai_name);
1080
1081 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1082
1083 return 0;
1084 }
1085
skl_coupled_trigger(struct snd_pcm_substream * substream,int cmd)1086 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1087 int cmd)
1088 {
1089 struct hdac_bus *bus = get_bus_ctx(substream);
1090 struct hdac_ext_stream *stream;
1091 struct snd_pcm_substream *s;
1092 bool start;
1093 int sbits = 0;
1094 unsigned long cookie;
1095 struct hdac_stream *hstr;
1096
1097 stream = get_hdac_ext_stream(substream);
1098 hstr = hdac_stream(stream);
1099
1100 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1101
1102 if (!hstr->prepared)
1103 return -EPIPE;
1104
1105 switch (cmd) {
1106 case SNDRV_PCM_TRIGGER_START:
1107 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1108 case SNDRV_PCM_TRIGGER_RESUME:
1109 start = true;
1110 break;
1111
1112 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1113 case SNDRV_PCM_TRIGGER_SUSPEND:
1114 case SNDRV_PCM_TRIGGER_STOP:
1115 start = false;
1116 break;
1117
1118 default:
1119 return -EINVAL;
1120 }
1121
1122 snd_pcm_group_for_each_entry(s, substream) {
1123 if (s->pcm->card != substream->pcm->card)
1124 continue;
1125 stream = get_hdac_ext_stream(s);
1126 sbits |= 1 << hdac_stream(stream)->index;
1127 snd_pcm_trigger_done(s, substream);
1128 }
1129
1130 spin_lock_irqsave(&bus->reg_lock, cookie);
1131
1132 /* first, set SYNC bits of corresponding streams */
1133 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1134
1135 snd_pcm_group_for_each_entry(s, substream) {
1136 if (s->pcm->card != substream->pcm->card)
1137 continue;
1138 stream = get_hdac_ext_stream(s);
1139 if (start)
1140 snd_hdac_stream_start(hdac_stream(stream));
1141 else
1142 snd_hdac_stream_stop(hdac_stream(stream));
1143 }
1144 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1145
1146 snd_hdac_stream_sync(hstr, start, sbits);
1147
1148 spin_lock_irqsave(&bus->reg_lock, cookie);
1149
1150 /* reset SYNC bits */
1151 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1152 if (start)
1153 snd_hdac_stream_timecounter_init(hstr, sbits);
1154 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1155
1156 return 0;
1157 }
1158
skl_platform_soc_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)1159 static int skl_platform_soc_trigger(struct snd_soc_component *component,
1160 struct snd_pcm_substream *substream,
1161 int cmd)
1162 {
1163 struct hdac_bus *bus = get_bus_ctx(substream);
1164
1165 if (!bus->ppcap)
1166 return skl_coupled_trigger(substream, cmd);
1167
1168 return 0;
1169 }
1170
skl_platform_soc_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)1171 static snd_pcm_uframes_t skl_platform_soc_pointer(
1172 struct snd_soc_component *component,
1173 struct snd_pcm_substream *substream)
1174 {
1175 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1176 struct hdac_bus *bus = get_bus_ctx(substream);
1177 unsigned int pos;
1178
1179 /*
1180 * Use DPIB for Playback stream as the periodic DMA Position-in-
1181 * Buffer Writes may be scheduled at the same time or later than
1182 * the MSI and does not guarantee to reflect the Position of the
1183 * last buffer that was transferred. Whereas DPIB register in
1184 * HAD space reflects the actual data that is transferred.
1185 * Use the position buffer for capture, as DPIB write gets
1186 * completed earlier than the actual data written to the DDR.
1187 *
1188 * For capture stream following workaround is required to fix the
1189 * incorrect position reporting.
1190 *
1191 * 1. Wait for 20us before reading the DMA position in buffer once
1192 * the interrupt is generated for stream completion as update happens
1193 * on the HDA frame boundary i.e. 20.833uSec.
1194 * 2. Read DPIB register to flush the DMA position value. This dummy
1195 * read is required to flush DMA position value.
1196 * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1197 * or greater than period boundary.
1198 */
1199
1200 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1201 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1202 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1203 hdac_stream(hstream)->index));
1204 } else {
1205 udelay(20);
1206 readl(bus->remap_addr +
1207 AZX_REG_VS_SDXDPIB_XBASE +
1208 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1209 hdac_stream(hstream)->index));
1210 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1211 }
1212
1213 if (pos >= hdac_stream(hstream)->bufsize)
1214 pos = 0;
1215
1216 return bytes_to_frames(substream->runtime, pos);
1217 }
1218
skl_adjust_codec_delay(struct snd_pcm_substream * substream,u64 nsec)1219 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1220 u64 nsec)
1221 {
1222 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1223 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
1224 u64 codec_frames, codec_nsecs;
1225
1226 if (!codec_dai->driver->ops->delay)
1227 return nsec;
1228
1229 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1230 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1231 substream->runtime->rate);
1232
1233 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1234 return nsec + codec_nsecs;
1235
1236 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1237 }
1238
skl_platform_soc_get_time_info(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct timespec64 * system_ts,struct timespec64 * audio_ts,struct snd_pcm_audio_tstamp_config * audio_tstamp_config,struct snd_pcm_audio_tstamp_report * audio_tstamp_report)1239 static int skl_platform_soc_get_time_info(
1240 struct snd_soc_component *component,
1241 struct snd_pcm_substream *substream,
1242 struct timespec64 *system_ts, struct timespec64 *audio_ts,
1243 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1244 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1245 {
1246 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1247 struct hdac_stream *hstr = hdac_stream(sstream);
1248 u64 nsec;
1249
1250 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1251 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1252
1253 snd_pcm_gettime(substream->runtime, system_ts);
1254
1255 nsec = timecounter_read(&hstr->tc);
1256 if (audio_tstamp_config->report_delay)
1257 nsec = skl_adjust_codec_delay(substream, nsec);
1258
1259 *audio_ts = ns_to_timespec64(nsec);
1260
1261 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1262 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1263 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1264
1265 } else {
1266 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1267 }
1268
1269 return 0;
1270 }
1271
1272 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
1273
skl_platform_soc_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)1274 static int skl_platform_soc_new(struct snd_soc_component *component,
1275 struct snd_soc_pcm_runtime *rtd)
1276 {
1277 struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
1278 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1279 struct snd_pcm *pcm = rtd->pcm;
1280 unsigned int size;
1281 struct skl_dev *skl = bus_to_skl(bus);
1282
1283 if (dai->driver->playback.channels_min ||
1284 dai->driver->capture.channels_min) {
1285 /* buffer pre-allocation */
1286 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1287 if (size > MAX_PREALLOC_SIZE)
1288 size = MAX_PREALLOC_SIZE;
1289 snd_pcm_set_managed_buffer_all(pcm,
1290 SNDRV_DMA_TYPE_DEV_SG,
1291 &skl->pci->dev,
1292 size, MAX_PREALLOC_SIZE);
1293 }
1294
1295 return 0;
1296 }
1297
skl_get_module_info(struct skl_dev * skl,struct skl_module_cfg * mconfig)1298 static int skl_get_module_info(struct skl_dev *skl,
1299 struct skl_module_cfg *mconfig)
1300 {
1301 struct skl_module_inst_id *pin_id;
1302 guid_t *uuid_mod, *uuid_tplg;
1303 struct skl_module *skl_module;
1304 struct uuid_module *module;
1305 int i, ret = -EIO;
1306
1307 uuid_mod = (guid_t *)mconfig->guid;
1308
1309 if (list_empty(&skl->uuid_list)) {
1310 dev_err(skl->dev, "Module list is empty\n");
1311 return -EIO;
1312 }
1313
1314 for (i = 0; i < skl->nr_modules; i++) {
1315 skl_module = skl->modules[i];
1316 uuid_tplg = &skl_module->uuid;
1317 if (guid_equal(uuid_mod, uuid_tplg)) {
1318 mconfig->module = skl_module;
1319 ret = 0;
1320 break;
1321 }
1322 }
1323
1324 if (skl->nr_modules && ret)
1325 return ret;
1326
1327 ret = -EIO;
1328 list_for_each_entry(module, &skl->uuid_list, list) {
1329 if (guid_equal(uuid_mod, &module->uuid)) {
1330 mconfig->id.module_id = module->id;
1331 mconfig->module->loadable = module->is_loadable;
1332 ret = 0;
1333 }
1334
1335 for (i = 0; i < MAX_IN_QUEUE; i++) {
1336 pin_id = &mconfig->m_in_pin[i].id;
1337 if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1338 pin_id->module_id = module->id;
1339 }
1340
1341 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1342 pin_id = &mconfig->m_out_pin[i].id;
1343 if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1344 pin_id->module_id = module->id;
1345 }
1346 }
1347
1348 return ret;
1349 }
1350
skl_populate_modules(struct skl_dev * skl)1351 static int skl_populate_modules(struct skl_dev *skl)
1352 {
1353 struct skl_pipeline *p;
1354 struct skl_pipe_module *m;
1355 struct snd_soc_dapm_widget *w;
1356 struct skl_module_cfg *mconfig;
1357 int ret = 0;
1358
1359 list_for_each_entry(p, &skl->ppl_list, node) {
1360 list_for_each_entry(m, &p->pipe->w_list, node) {
1361 w = m->w;
1362 mconfig = w->priv;
1363
1364 ret = skl_get_module_info(skl, mconfig);
1365 if (ret < 0) {
1366 dev_err(skl->dev,
1367 "query module info failed\n");
1368 return ret;
1369 }
1370
1371 skl_tplg_add_moduleid_in_bind_params(skl, w);
1372 }
1373 }
1374
1375 return ret;
1376 }
1377
skl_platform_soc_probe(struct snd_soc_component * component)1378 static int skl_platform_soc_probe(struct snd_soc_component *component)
1379 {
1380 struct hdac_bus *bus = dev_get_drvdata(component->dev);
1381 struct skl_dev *skl = bus_to_skl(bus);
1382 const struct skl_dsp_ops *ops;
1383 int ret;
1384
1385 ret = pm_runtime_resume_and_get(component->dev);
1386 if (ret < 0 && ret != -EACCES)
1387 return ret;
1388
1389 if (bus->ppcap) {
1390 skl->component = component;
1391
1392 /* init debugfs */
1393 skl->debugfs = skl_debugfs_init(skl);
1394
1395 ret = skl_tplg_init(component, bus);
1396 if (ret < 0) {
1397 dev_err(component->dev, "Failed to init topology!\n");
1398 return ret;
1399 }
1400
1401 /* load the firmwares, since all is set */
1402 ops = skl_get_dsp_ops(skl->pci->device);
1403 if (!ops)
1404 return -EIO;
1405
1406 /*
1407 * Disable dynamic clock and power gating during firmware
1408 * and library download
1409 */
1410 skl->enable_miscbdcge(component->dev, false);
1411 skl->clock_power_gating(component->dev, false);
1412
1413 ret = ops->init_fw(component->dev, skl);
1414 skl->enable_miscbdcge(component->dev, true);
1415 skl->clock_power_gating(component->dev, true);
1416 if (ret < 0) {
1417 dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1418 return ret;
1419 }
1420 skl_populate_modules(skl);
1421 skl->update_d0i3c = skl_update_d0i3c;
1422
1423 if (skl->cfg.astate_cfg != NULL) {
1424 skl_dsp_set_astate_cfg(skl,
1425 skl->cfg.astate_cfg->count,
1426 skl->cfg.astate_cfg);
1427 }
1428 }
1429 pm_runtime_mark_last_busy(component->dev);
1430 pm_runtime_put_autosuspend(component->dev);
1431
1432 return 0;
1433 }
1434
skl_platform_soc_remove(struct snd_soc_component * component)1435 static void skl_platform_soc_remove(struct snd_soc_component *component)
1436 {
1437 struct hdac_bus *bus = dev_get_drvdata(component->dev);
1438 struct skl_dev *skl = bus_to_skl(bus);
1439
1440 skl_tplg_exit(component, bus);
1441
1442 skl_debugfs_exit(skl);
1443 }
1444
1445 static const struct snd_soc_component_driver skl_component = {
1446 .name = "pcm",
1447 .probe = skl_platform_soc_probe,
1448 .remove = skl_platform_soc_remove,
1449 .open = skl_platform_soc_open,
1450 .trigger = skl_platform_soc_trigger,
1451 .pointer = skl_platform_soc_pointer,
1452 .get_time_info = skl_platform_soc_get_time_info,
1453 .pcm_construct = skl_platform_soc_new,
1454 .module_get_upon_open = 1, /* increment refcount when a pcm is opened */
1455 };
1456
skl_platform_register(struct device * dev)1457 int skl_platform_register(struct device *dev)
1458 {
1459 int ret;
1460 struct snd_soc_dai_driver *dais;
1461 int num_dais = ARRAY_SIZE(skl_platform_dai);
1462 struct hdac_bus *bus = dev_get_drvdata(dev);
1463 struct skl_dev *skl = bus_to_skl(bus);
1464
1465 skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1466 GFP_KERNEL);
1467 if (!skl->dais) {
1468 ret = -ENOMEM;
1469 goto err;
1470 }
1471
1472 if (!skl->use_tplg_pcm) {
1473 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1474 sizeof(skl_platform_dai), GFP_KERNEL);
1475 if (!dais) {
1476 kfree(skl->dais);
1477 ret = -ENOMEM;
1478 goto err;
1479 }
1480
1481 skl->dais = dais;
1482 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1483 sizeof(skl_fe_dai));
1484 num_dais += ARRAY_SIZE(skl_fe_dai);
1485 }
1486
1487 ret = devm_snd_soc_register_component(dev, &skl_component,
1488 skl->dais, num_dais);
1489 if (ret) {
1490 kfree(skl->dais);
1491 dev_err(dev, "soc component registration failed %d\n", ret);
1492 }
1493 err:
1494 return ret;
1495 }
1496
skl_platform_unregister(struct device * dev)1497 int skl_platform_unregister(struct device *dev)
1498 {
1499 struct hdac_bus *bus = dev_get_drvdata(dev);
1500 struct skl_dev *skl = bus_to_skl(bus);
1501 struct skl_module_deferred_bind *modules, *tmp;
1502
1503 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1504 list_del(&modules->node);
1505 kfree(modules);
1506 }
1507
1508 kfree(skl->dais);
1509
1510 return 0;
1511 }
1512