1 /* 2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality 3 * 4 * Copyright (C) 2014-2015 Intel Corp 5 * Author: Jeeja KP <jeeja.kp@intel.com> 6 * 7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 19 * 20 */ 21 22 #include <linux/pci.h> 23 #include <linux/pm_runtime.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include "skl.h" 27 #include "skl-topology.h" 28 #include "skl-sst-dsp.h" 29 #include "skl-sst-ipc.h" 30 31 #define HDA_MONO 1 32 #define HDA_STEREO 2 33 #define HDA_QUAD 4 34 35 static struct snd_pcm_hardware azx_pcm_hw = { 36 .info = (SNDRV_PCM_INFO_MMAP | 37 SNDRV_PCM_INFO_INTERLEAVED | 38 SNDRV_PCM_INFO_BLOCK_TRANSFER | 39 SNDRV_PCM_INFO_MMAP_VALID | 40 SNDRV_PCM_INFO_PAUSE | 41 SNDRV_PCM_INFO_RESUME | 42 SNDRV_PCM_INFO_SYNC_START | 43 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */ 44 SNDRV_PCM_INFO_HAS_LINK_ATIME | 45 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 46 .formats = SNDRV_PCM_FMTBIT_S16_LE | 47 SNDRV_PCM_FMTBIT_S32_LE | 48 SNDRV_PCM_FMTBIT_S24_LE, 49 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 50 SNDRV_PCM_RATE_8000, 51 .rate_min = 8000, 52 .rate_max = 48000, 53 .channels_min = 1, 54 .channels_max = 8, 55 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 56 .period_bytes_min = 128, 57 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 58 .periods_min = 2, 59 .periods_max = AZX_MAX_FRAG, 60 .fifo_size = 0, 61 }; 62 63 static inline 64 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream) 65 { 66 return substream->runtime->private_data; 67 } 68 69 static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream) 70 { 71 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 72 struct hdac_stream *hstream = hdac_stream(stream); 73 struct hdac_bus *bus = hstream->bus; 74 75 return hbus_to_ebus(bus); 76 } 77 78 static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus, 79 struct snd_pcm_substream *substream, 80 size_t size) 81 { 82 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 83 84 hdac_stream(stream)->bufsize = 0; 85 hdac_stream(stream)->period_bytes = 0; 86 hdac_stream(stream)->format_val = 0; 87 88 return snd_pcm_lib_malloc_pages(substream, size); 89 } 90 91 static int skl_substream_free_pages(struct hdac_bus *bus, 92 struct snd_pcm_substream *substream) 93 { 94 return snd_pcm_lib_free_pages(substream); 95 } 96 97 static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus, 98 struct snd_pcm_runtime *runtime) 99 { 100 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 101 102 /* avoid wrap-around with wall-clock */ 103 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, 104 20, 178000000); 105 } 106 107 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus) 108 { 109 if ((ebus_to_hbus(ebus))->ppcap) 110 return HDAC_EXT_STREAM_TYPE_HOST; 111 else 112 return HDAC_EXT_STREAM_TYPE_COUPLED; 113 } 114 115 /* 116 * check if the stream opened is marked as ignore_suspend by machine, if so 117 * then enable suspend_active refcount 118 * 119 * The count supend_active does not need lock as it is used in open/close 120 * and suspend context 121 */ 122 static void skl_set_suspend_active(struct snd_pcm_substream *substream, 123 struct snd_soc_dai *dai, bool enable) 124 { 125 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 126 struct snd_soc_dapm_widget *w; 127 struct skl *skl = ebus_to_skl(ebus); 128 129 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 130 w = dai->playback_widget; 131 else 132 w = dai->capture_widget; 133 134 if (w->ignore_suspend && enable) 135 skl->supend_active++; 136 else if (w->ignore_suspend && !enable) 137 skl->supend_active--; 138 } 139 140 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params) 141 { 142 struct hdac_ext_bus *ebus = dev_get_drvdata(dev); 143 struct hdac_bus *bus = ebus_to_hbus(ebus); 144 unsigned int format_val; 145 struct hdac_stream *hstream; 146 struct hdac_ext_stream *stream; 147 int err; 148 149 hstream = snd_hdac_get_stream(bus, params->stream, 150 params->host_dma_id + 1); 151 if (!hstream) 152 return -EINVAL; 153 154 stream = stream_to_hdac_ext_stream(hstream); 155 snd_hdac_ext_stream_decouple(ebus, stream, true); 156 157 format_val = snd_hdac_calc_stream_format(params->s_freq, 158 params->ch, params->format, 32, 0); 159 160 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n", 161 format_val, params->s_freq, params->ch, params->format); 162 163 snd_hdac_stream_reset(hdac_stream(stream)); 164 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val); 165 if (err < 0) 166 return err; 167 168 err = snd_hdac_stream_setup(hdac_stream(stream)); 169 if (err < 0) 170 return err; 171 172 hdac_stream(stream)->prepared = 1; 173 174 return 0; 175 } 176 177 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params) 178 { 179 struct hdac_ext_bus *ebus = dev_get_drvdata(dev); 180 struct hdac_bus *bus = ebus_to_hbus(ebus); 181 unsigned int format_val; 182 struct hdac_stream *hstream; 183 struct hdac_ext_stream *stream; 184 struct hdac_ext_link *link; 185 186 hstream = snd_hdac_get_stream(bus, params->stream, 187 params->link_dma_id + 1); 188 if (!hstream) 189 return -EINVAL; 190 191 stream = stream_to_hdac_ext_stream(hstream); 192 snd_hdac_ext_stream_decouple(ebus, stream, true); 193 format_val = snd_hdac_calc_stream_format(params->s_freq, 194 params->ch, params->format, 24, 0); 195 196 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n", 197 format_val, params->s_freq, params->ch, params->format); 198 199 snd_hdac_ext_link_stream_reset(stream); 200 201 snd_hdac_ext_link_stream_setup(stream, format_val); 202 203 list_for_each_entry(link, &ebus->hlink_list, list) { 204 if (link->index == params->link_index) 205 snd_hdac_ext_link_set_stream_id(link, 206 hstream->stream_tag); 207 } 208 209 stream->link_prepared = 1; 210 211 return 0; 212 } 213 214 static int skl_pcm_open(struct snd_pcm_substream *substream, 215 struct snd_soc_dai *dai) 216 { 217 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 218 struct hdac_ext_stream *stream; 219 struct snd_pcm_runtime *runtime = substream->runtime; 220 struct skl_dma_params *dma_params; 221 struct skl *skl = get_skl_ctx(dai->dev); 222 struct skl_module_cfg *mconfig; 223 224 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 225 226 stream = snd_hdac_ext_stream_assign(ebus, substream, 227 skl_get_host_stream_type(ebus)); 228 if (stream == NULL) 229 return -EBUSY; 230 231 skl_set_pcm_constrains(ebus, runtime); 232 233 /* 234 * disable WALLCLOCK timestamps for capture streams 235 * until we figure out how to handle digital inputs 236 */ 237 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 238 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */ 239 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME; 240 } 241 242 runtime->private_data = stream; 243 244 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL); 245 if (!dma_params) 246 return -ENOMEM; 247 248 dma_params->stream_tag = hdac_stream(stream)->stream_tag; 249 snd_soc_dai_set_dma_data(dai, substream, dma_params); 250 251 dev_dbg(dai->dev, "stream tag set in dma params=%d\n", 252 dma_params->stream_tag); 253 skl_set_suspend_active(substream, dai, true); 254 snd_pcm_set_sync(substream); 255 256 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 257 if (!mconfig) 258 return -EINVAL; 259 260 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps); 261 262 return 0; 263 } 264 265 static int skl_be_prepare(struct snd_pcm_substream *substream, 266 struct snd_soc_dai *dai) 267 { 268 struct skl *skl = get_skl_ctx(dai->dev); 269 struct skl_sst *ctx = skl->skl_sst; 270 struct skl_module_cfg *mconfig; 271 272 if (dai->playback_widget->power || dai->capture_widget->power) 273 return 0; 274 275 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream); 276 if (mconfig == NULL) 277 return -EINVAL; 278 279 return skl_dsp_set_dma_control(ctx, mconfig); 280 } 281 282 static int skl_pcm_prepare(struct snd_pcm_substream *substream, 283 struct snd_soc_dai *dai) 284 { 285 struct skl *skl = get_skl_ctx(dai->dev); 286 struct skl_module_cfg *mconfig; 287 288 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 289 290 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 291 292 /* In case of XRUN recovery, reset the FW pipe to clean state */ 293 if (mconfig && (substream->runtime->status->state == 294 SNDRV_PCM_STATE_XRUN)) 295 skl_reset_pipe(skl->skl_sst, mconfig->pipe); 296 297 return 0; 298 } 299 300 static int skl_pcm_hw_params(struct snd_pcm_substream *substream, 301 struct snd_pcm_hw_params *params, 302 struct snd_soc_dai *dai) 303 { 304 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 305 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 306 struct snd_pcm_runtime *runtime = substream->runtime; 307 struct skl_pipe_params p_params = {0}; 308 struct skl_module_cfg *m_cfg; 309 int ret, dma_id; 310 311 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 312 ret = skl_substream_alloc_pages(ebus, substream, 313 params_buffer_bytes(params)); 314 if (ret < 0) 315 return ret; 316 317 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n", 318 runtime->rate, runtime->channels, runtime->format); 319 320 dma_id = hdac_stream(stream)->stream_tag - 1; 321 dev_dbg(dai->dev, "dma_id=%d\n", dma_id); 322 323 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 324 p_params.ch = params_channels(params); 325 p_params.s_freq = params_rate(params); 326 p_params.host_dma_id = dma_id; 327 p_params.stream = substream->stream; 328 p_params.format = params_format(params); 329 330 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream); 331 if (m_cfg) 332 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params); 333 334 return 0; 335 } 336 337 static void skl_pcm_close(struct snd_pcm_substream *substream, 338 struct snd_soc_dai *dai) 339 { 340 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 341 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 342 struct skl_dma_params *dma_params = NULL; 343 struct skl *skl = ebus_to_skl(ebus); 344 struct skl_module_cfg *mconfig; 345 346 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 347 348 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus)); 349 350 dma_params = snd_soc_dai_get_dma_data(dai, substream); 351 /* 352 * now we should set this to NULL as we are freeing by the 353 * dma_params 354 */ 355 snd_soc_dai_set_dma_data(dai, substream, NULL); 356 skl_set_suspend_active(substream, dai, false); 357 358 /* 359 * check if close is for "Reference Pin" and set back the 360 * CGCTL.MISCBDCGE if disabled by driver 361 */ 362 if (!strncmp(dai->name, "Reference Pin", 13) && 363 skl->skl_sst->miscbdcg_disabled) { 364 skl->skl_sst->enable_miscbdcge(dai->dev, true); 365 skl->skl_sst->miscbdcg_disabled = false; 366 } 367 368 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 369 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps); 370 371 kfree(dma_params); 372 } 373 374 static int skl_pcm_hw_free(struct snd_pcm_substream *substream, 375 struct snd_soc_dai *dai) 376 { 377 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 378 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 379 380 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 381 382 snd_hdac_stream_cleanup(hdac_stream(stream)); 383 hdac_stream(stream)->prepared = 0; 384 385 return skl_substream_free_pages(ebus_to_hbus(ebus), substream); 386 } 387 388 static int skl_be_hw_params(struct snd_pcm_substream *substream, 389 struct snd_pcm_hw_params *params, 390 struct snd_soc_dai *dai) 391 { 392 struct skl_pipe_params p_params = {0}; 393 394 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 395 p_params.ch = params_channels(params); 396 p_params.s_freq = params_rate(params); 397 p_params.stream = substream->stream; 398 399 return skl_tplg_be_update_params(dai, &p_params); 400 } 401 402 static int skl_decoupled_trigger(struct snd_pcm_substream *substream, 403 int cmd) 404 { 405 struct hdac_ext_bus *ebus = get_bus_ctx(substream); 406 struct hdac_bus *bus = ebus_to_hbus(ebus); 407 struct hdac_ext_stream *stream; 408 int start; 409 unsigned long cookie; 410 struct hdac_stream *hstr; 411 412 stream = get_hdac_ext_stream(substream); 413 hstr = hdac_stream(stream); 414 415 if (!hstr->prepared) 416 return -EPIPE; 417 418 switch (cmd) { 419 case SNDRV_PCM_TRIGGER_START: 420 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 421 case SNDRV_PCM_TRIGGER_RESUME: 422 start = 1; 423 break; 424 425 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 426 case SNDRV_PCM_TRIGGER_SUSPEND: 427 case SNDRV_PCM_TRIGGER_STOP: 428 start = 0; 429 break; 430 431 default: 432 return -EINVAL; 433 } 434 435 spin_lock_irqsave(&bus->reg_lock, cookie); 436 437 if (start) { 438 snd_hdac_stream_start(hdac_stream(stream), true); 439 snd_hdac_stream_timecounter_init(hstr, 0); 440 } else { 441 snd_hdac_stream_stop(hdac_stream(stream)); 442 } 443 444 spin_unlock_irqrestore(&bus->reg_lock, cookie); 445 446 return 0; 447 } 448 449 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 450 struct snd_soc_dai *dai) 451 { 452 struct skl *skl = get_skl_ctx(dai->dev); 453 struct skl_sst *ctx = skl->skl_sst; 454 struct skl_module_cfg *mconfig; 455 struct hdac_ext_bus *ebus = get_bus_ctx(substream); 456 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 457 struct snd_soc_dapm_widget *w; 458 int ret; 459 460 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 461 if (!mconfig) 462 return -EIO; 463 464 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 465 w = dai->playback_widget; 466 else 467 w = dai->capture_widget; 468 469 switch (cmd) { 470 case SNDRV_PCM_TRIGGER_RESUME: 471 if (!w->ignore_suspend) { 472 /* 473 * enable DMA Resume enable bit for the stream, set the 474 * dpib & lpib position to resume before starting the 475 * DMA 476 */ 477 snd_hdac_ext_stream_drsm_enable(ebus, true, 478 hdac_stream(stream)->index); 479 snd_hdac_ext_stream_set_dpibr(ebus, stream, 480 stream->lpib); 481 snd_hdac_ext_stream_set_lpib(stream, stream->lpib); 482 } 483 484 case SNDRV_PCM_TRIGGER_START: 485 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 486 /* 487 * Start HOST DMA and Start FE Pipe.This is to make sure that 488 * there are no underrun/overrun in the case when the FE 489 * pipeline is started but there is a delay in starting the 490 * DMA channel on the host. 491 */ 492 ret = skl_decoupled_trigger(substream, cmd); 493 if (ret < 0) 494 return ret; 495 return skl_run_pipe(ctx, mconfig->pipe); 496 break; 497 498 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 499 case SNDRV_PCM_TRIGGER_SUSPEND: 500 case SNDRV_PCM_TRIGGER_STOP: 501 /* 502 * Stop FE Pipe first and stop DMA. This is to make sure that 503 * there are no underrun/overrun in the case if there is a delay 504 * between the two operations. 505 */ 506 ret = skl_stop_pipe(ctx, mconfig->pipe); 507 if (ret < 0) 508 return ret; 509 510 ret = skl_decoupled_trigger(substream, cmd); 511 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) { 512 /* save the dpib and lpib positions */ 513 stream->dpib = readl(ebus->bus.remap_addr + 514 AZX_REG_VS_SDXDPIB_XBASE + 515 (AZX_REG_VS_SDXDPIB_XINTERVAL * 516 hdac_stream(stream)->index)); 517 518 stream->lpib = snd_hdac_stream_get_pos_lpib( 519 hdac_stream(stream)); 520 snd_hdac_ext_stream_decouple(ebus, stream, false); 521 } 522 break; 523 524 default: 525 return -EINVAL; 526 } 527 528 return 0; 529 } 530 531 static int skl_link_hw_params(struct snd_pcm_substream *substream, 532 struct snd_pcm_hw_params *params, 533 struct snd_soc_dai *dai) 534 { 535 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 536 struct hdac_ext_stream *link_dev; 537 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 538 struct snd_soc_dai *codec_dai = rtd->codec_dai; 539 struct skl_pipe_params p_params = {0}; 540 struct hdac_ext_link *link; 541 int stream_tag; 542 543 link_dev = snd_hdac_ext_stream_assign(ebus, substream, 544 HDAC_EXT_STREAM_TYPE_LINK); 545 if (!link_dev) 546 return -EBUSY; 547 548 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev); 549 550 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name); 551 if (!link) 552 return -EINVAL; 553 554 stream_tag = hdac_stream(link_dev)->stream_tag; 555 556 /* set the stream tag in the codec dai dma params */ 557 snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0); 558 559 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 560 p_params.ch = params_channels(params); 561 p_params.s_freq = params_rate(params); 562 p_params.stream = substream->stream; 563 p_params.link_dma_id = stream_tag - 1; 564 p_params.link_index = link->index; 565 p_params.format = params_format(params); 566 567 return skl_tplg_be_update_params(dai, &p_params); 568 } 569 570 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream, 571 struct snd_soc_dai *dai) 572 { 573 struct skl *skl = get_skl_ctx(dai->dev); 574 struct skl_module_cfg *mconfig = NULL; 575 576 /* In case of XRUN recovery, reset the FW pipe to clean state */ 577 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream); 578 if (mconfig && !mconfig->pipe->passthru && 579 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN)) 580 skl_reset_pipe(skl->skl_sst, mconfig->pipe); 581 582 return 0; 583 } 584 585 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream, 586 int cmd, struct snd_soc_dai *dai) 587 { 588 struct hdac_ext_stream *link_dev = 589 snd_soc_dai_get_dma_data(dai, substream); 590 struct hdac_ext_bus *ebus = get_bus_ctx(substream); 591 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 592 593 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd); 594 switch (cmd) { 595 case SNDRV_PCM_TRIGGER_RESUME: 596 case SNDRV_PCM_TRIGGER_START: 597 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 598 snd_hdac_ext_link_stream_start(link_dev); 599 break; 600 601 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 602 case SNDRV_PCM_TRIGGER_SUSPEND: 603 case SNDRV_PCM_TRIGGER_STOP: 604 snd_hdac_ext_link_stream_clear(link_dev); 605 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND) 606 snd_hdac_ext_stream_decouple(ebus, stream, false); 607 break; 608 609 default: 610 return -EINVAL; 611 } 612 return 0; 613 } 614 615 static int skl_link_hw_free(struct snd_pcm_substream *substream, 616 struct snd_soc_dai *dai) 617 { 618 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 619 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 620 struct hdac_ext_stream *link_dev = 621 snd_soc_dai_get_dma_data(dai, substream); 622 struct hdac_ext_link *link; 623 624 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 625 626 link_dev->link_prepared = 0; 627 628 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name); 629 if (!link) 630 return -EINVAL; 631 632 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag); 633 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK); 634 return 0; 635 } 636 637 static struct snd_soc_dai_ops skl_pcm_dai_ops = { 638 .startup = skl_pcm_open, 639 .shutdown = skl_pcm_close, 640 .prepare = skl_pcm_prepare, 641 .hw_params = skl_pcm_hw_params, 642 .hw_free = skl_pcm_hw_free, 643 .trigger = skl_pcm_trigger, 644 }; 645 646 static struct snd_soc_dai_ops skl_dmic_dai_ops = { 647 .hw_params = skl_be_hw_params, 648 }; 649 650 static struct snd_soc_dai_ops skl_be_ssp_dai_ops = { 651 .hw_params = skl_be_hw_params, 652 .prepare = skl_be_prepare, 653 }; 654 655 static struct snd_soc_dai_ops skl_link_dai_ops = { 656 .prepare = skl_link_pcm_prepare, 657 .hw_params = skl_link_hw_params, 658 .hw_free = skl_link_hw_free, 659 .trigger = skl_link_pcm_trigger, 660 }; 661 662 static struct snd_soc_dai_driver skl_platform_dai[] = { 663 { 664 .name = "System Pin", 665 .ops = &skl_pcm_dai_ops, 666 .playback = { 667 .stream_name = "System Playback", 668 .channels_min = HDA_MONO, 669 .channels_max = HDA_STEREO, 670 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000, 671 .formats = SNDRV_PCM_FMTBIT_S16_LE | 672 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 673 }, 674 .capture = { 675 .stream_name = "System Capture", 676 .channels_min = HDA_MONO, 677 .channels_max = HDA_STEREO, 678 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 679 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 680 }, 681 }, 682 { 683 .name = "Reference Pin", 684 .ops = &skl_pcm_dai_ops, 685 .capture = { 686 .stream_name = "Reference Capture", 687 .channels_min = HDA_MONO, 688 .channels_max = HDA_QUAD, 689 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 690 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 691 }, 692 }, 693 { 694 .name = "Deepbuffer Pin", 695 .ops = &skl_pcm_dai_ops, 696 .playback = { 697 .stream_name = "Deepbuffer Playback", 698 .channels_min = HDA_STEREO, 699 .channels_max = HDA_STEREO, 700 .rates = SNDRV_PCM_RATE_48000, 701 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 702 }, 703 }, 704 { 705 .name = "LowLatency Pin", 706 .ops = &skl_pcm_dai_ops, 707 .playback = { 708 .stream_name = "Low Latency Playback", 709 .channels_min = HDA_STEREO, 710 .channels_max = HDA_STEREO, 711 .rates = SNDRV_PCM_RATE_48000, 712 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 713 }, 714 }, 715 { 716 .name = "DMIC Pin", 717 .ops = &skl_pcm_dai_ops, 718 .capture = { 719 .stream_name = "DMIC Capture", 720 .channels_min = HDA_MONO, 721 .channels_max = HDA_QUAD, 722 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 723 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 724 }, 725 }, 726 { 727 .name = "HDMI1 Pin", 728 .ops = &skl_pcm_dai_ops, 729 .playback = { 730 .stream_name = "HDMI1 Playback", 731 .channels_min = HDA_STEREO, 732 .channels_max = 8, 733 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 734 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 735 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 736 SNDRV_PCM_RATE_192000, 737 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 738 SNDRV_PCM_FMTBIT_S32_LE, 739 }, 740 }, 741 { 742 .name = "HDMI2 Pin", 743 .ops = &skl_pcm_dai_ops, 744 .playback = { 745 .stream_name = "HDMI2 Playback", 746 .channels_min = HDA_STEREO, 747 .channels_max = 8, 748 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 749 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 750 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 751 SNDRV_PCM_RATE_192000, 752 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 753 SNDRV_PCM_FMTBIT_S32_LE, 754 }, 755 }, 756 { 757 .name = "HDMI3 Pin", 758 .ops = &skl_pcm_dai_ops, 759 .playback = { 760 .stream_name = "HDMI3 Playback", 761 .channels_min = HDA_STEREO, 762 .channels_max = 8, 763 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 764 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 765 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 766 SNDRV_PCM_RATE_192000, 767 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 768 SNDRV_PCM_FMTBIT_S32_LE, 769 }, 770 }, 771 772 /* BE CPU Dais */ 773 { 774 .name = "SSP0 Pin", 775 .ops = &skl_be_ssp_dai_ops, 776 .playback = { 777 .stream_name = "ssp0 Tx", 778 .channels_min = HDA_STEREO, 779 .channels_max = HDA_STEREO, 780 .rates = SNDRV_PCM_RATE_48000, 781 .formats = SNDRV_PCM_FMTBIT_S16_LE, 782 }, 783 .capture = { 784 .stream_name = "ssp0 Rx", 785 .channels_min = HDA_STEREO, 786 .channels_max = HDA_STEREO, 787 .rates = SNDRV_PCM_RATE_48000, 788 .formats = SNDRV_PCM_FMTBIT_S16_LE, 789 }, 790 }, 791 { 792 .name = "SSP1 Pin", 793 .ops = &skl_be_ssp_dai_ops, 794 .playback = { 795 .stream_name = "ssp1 Tx", 796 .channels_min = HDA_STEREO, 797 .channels_max = HDA_STEREO, 798 .rates = SNDRV_PCM_RATE_48000, 799 .formats = SNDRV_PCM_FMTBIT_S16_LE, 800 }, 801 .capture = { 802 .stream_name = "ssp1 Rx", 803 .channels_min = HDA_STEREO, 804 .channels_max = HDA_STEREO, 805 .rates = SNDRV_PCM_RATE_48000, 806 .formats = SNDRV_PCM_FMTBIT_S16_LE, 807 }, 808 }, 809 { 810 .name = "SSP2 Pin", 811 .ops = &skl_be_ssp_dai_ops, 812 .playback = { 813 .stream_name = "ssp2 Tx", 814 .channels_min = HDA_STEREO, 815 .channels_max = HDA_STEREO, 816 .rates = SNDRV_PCM_RATE_48000, 817 .formats = SNDRV_PCM_FMTBIT_S16_LE, 818 }, 819 .capture = { 820 .stream_name = "ssp2 Rx", 821 .channels_min = HDA_STEREO, 822 .channels_max = HDA_STEREO, 823 .rates = SNDRV_PCM_RATE_48000, 824 .formats = SNDRV_PCM_FMTBIT_S16_LE, 825 }, 826 }, 827 { 828 .name = "SSP3 Pin", 829 .ops = &skl_be_ssp_dai_ops, 830 .playback = { 831 .stream_name = "ssp3 Tx", 832 .channels_min = HDA_STEREO, 833 .channels_max = HDA_STEREO, 834 .rates = SNDRV_PCM_RATE_48000, 835 .formats = SNDRV_PCM_FMTBIT_S16_LE, 836 }, 837 .capture = { 838 .stream_name = "ssp3 Rx", 839 .channels_min = HDA_STEREO, 840 .channels_max = HDA_STEREO, 841 .rates = SNDRV_PCM_RATE_48000, 842 .formats = SNDRV_PCM_FMTBIT_S16_LE, 843 }, 844 }, 845 { 846 .name = "SSP4 Pin", 847 .ops = &skl_be_ssp_dai_ops, 848 .playback = { 849 .stream_name = "ssp4 Tx", 850 .channels_min = HDA_STEREO, 851 .channels_max = HDA_STEREO, 852 .rates = SNDRV_PCM_RATE_48000, 853 .formats = SNDRV_PCM_FMTBIT_S16_LE, 854 }, 855 .capture = { 856 .stream_name = "ssp4 Rx", 857 .channels_min = HDA_STEREO, 858 .channels_max = HDA_STEREO, 859 .rates = SNDRV_PCM_RATE_48000, 860 .formats = SNDRV_PCM_FMTBIT_S16_LE, 861 }, 862 }, 863 { 864 .name = "SSP5 Pin", 865 .ops = &skl_be_ssp_dai_ops, 866 .playback = { 867 .stream_name = "ssp5 Tx", 868 .channels_min = HDA_STEREO, 869 .channels_max = HDA_STEREO, 870 .rates = SNDRV_PCM_RATE_48000, 871 .formats = SNDRV_PCM_FMTBIT_S16_LE, 872 }, 873 .capture = { 874 .stream_name = "ssp5 Rx", 875 .channels_min = HDA_STEREO, 876 .channels_max = HDA_STEREO, 877 .rates = SNDRV_PCM_RATE_48000, 878 .formats = SNDRV_PCM_FMTBIT_S16_LE, 879 }, 880 }, 881 { 882 .name = "iDisp1 Pin", 883 .ops = &skl_link_dai_ops, 884 .playback = { 885 .stream_name = "iDisp1 Tx", 886 .channels_min = HDA_STEREO, 887 .channels_max = 8, 888 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000, 889 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 890 SNDRV_PCM_FMTBIT_S24_LE, 891 }, 892 }, 893 { 894 .name = "iDisp2 Pin", 895 .ops = &skl_link_dai_ops, 896 .playback = { 897 .stream_name = "iDisp2 Tx", 898 .channels_min = HDA_STEREO, 899 .channels_max = 8, 900 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| 901 SNDRV_PCM_RATE_48000, 902 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 903 SNDRV_PCM_FMTBIT_S24_LE, 904 }, 905 }, 906 { 907 .name = "iDisp3 Pin", 908 .ops = &skl_link_dai_ops, 909 .playback = { 910 .stream_name = "iDisp3 Tx", 911 .channels_min = HDA_STEREO, 912 .channels_max = 8, 913 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| 914 SNDRV_PCM_RATE_48000, 915 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 916 SNDRV_PCM_FMTBIT_S24_LE, 917 }, 918 }, 919 { 920 .name = "DMIC01 Pin", 921 .ops = &skl_dmic_dai_ops, 922 .capture = { 923 .stream_name = "DMIC01 Rx", 924 .channels_min = HDA_MONO, 925 .channels_max = HDA_QUAD, 926 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 927 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 928 }, 929 }, 930 { 931 .name = "HD-Codec Pin", 932 .ops = &skl_link_dai_ops, 933 .playback = { 934 .stream_name = "HD-Codec Tx", 935 .channels_min = HDA_STEREO, 936 .channels_max = HDA_STEREO, 937 .rates = SNDRV_PCM_RATE_48000, 938 .formats = SNDRV_PCM_FMTBIT_S16_LE, 939 }, 940 .capture = { 941 .stream_name = "HD-Codec Rx", 942 .channels_min = HDA_STEREO, 943 .channels_max = HDA_STEREO, 944 .rates = SNDRV_PCM_RATE_48000, 945 .formats = SNDRV_PCM_FMTBIT_S16_LE, 946 }, 947 }, 948 }; 949 950 static int skl_platform_open(struct snd_pcm_substream *substream) 951 { 952 struct snd_pcm_runtime *runtime; 953 struct snd_soc_pcm_runtime *rtd = substream->private_data; 954 struct snd_soc_dai_link *dai_link = rtd->dai_link; 955 956 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__, 957 dai_link->cpu_dai_name); 958 959 runtime = substream->runtime; 960 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw); 961 962 return 0; 963 } 964 965 static int skl_coupled_trigger(struct snd_pcm_substream *substream, 966 int cmd) 967 { 968 struct hdac_ext_bus *ebus = get_bus_ctx(substream); 969 struct hdac_bus *bus = ebus_to_hbus(ebus); 970 struct hdac_ext_stream *stream; 971 struct snd_pcm_substream *s; 972 bool start; 973 int sbits = 0; 974 unsigned long cookie; 975 struct hdac_stream *hstr; 976 977 stream = get_hdac_ext_stream(substream); 978 hstr = hdac_stream(stream); 979 980 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd); 981 982 if (!hstr->prepared) 983 return -EPIPE; 984 985 switch (cmd) { 986 case SNDRV_PCM_TRIGGER_START: 987 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 988 case SNDRV_PCM_TRIGGER_RESUME: 989 start = true; 990 break; 991 992 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 993 case SNDRV_PCM_TRIGGER_SUSPEND: 994 case SNDRV_PCM_TRIGGER_STOP: 995 start = false; 996 break; 997 998 default: 999 return -EINVAL; 1000 } 1001 1002 snd_pcm_group_for_each_entry(s, substream) { 1003 if (s->pcm->card != substream->pcm->card) 1004 continue; 1005 stream = get_hdac_ext_stream(s); 1006 sbits |= 1 << hdac_stream(stream)->index; 1007 snd_pcm_trigger_done(s, substream); 1008 } 1009 1010 spin_lock_irqsave(&bus->reg_lock, cookie); 1011 1012 /* first, set SYNC bits of corresponding streams */ 1013 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC); 1014 1015 snd_pcm_group_for_each_entry(s, substream) { 1016 if (s->pcm->card != substream->pcm->card) 1017 continue; 1018 stream = get_hdac_ext_stream(s); 1019 if (start) 1020 snd_hdac_stream_start(hdac_stream(stream), true); 1021 else 1022 snd_hdac_stream_stop(hdac_stream(stream)); 1023 } 1024 spin_unlock_irqrestore(&bus->reg_lock, cookie); 1025 1026 snd_hdac_stream_sync(hstr, start, sbits); 1027 1028 spin_lock_irqsave(&bus->reg_lock, cookie); 1029 1030 /* reset SYNC bits */ 1031 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC); 1032 if (start) 1033 snd_hdac_stream_timecounter_init(hstr, sbits); 1034 spin_unlock_irqrestore(&bus->reg_lock, cookie); 1035 1036 return 0; 1037 } 1038 1039 static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream, 1040 int cmd) 1041 { 1042 struct hdac_ext_bus *ebus = get_bus_ctx(substream); 1043 1044 if (!(ebus_to_hbus(ebus))->ppcap) 1045 return skl_coupled_trigger(substream, cmd); 1046 1047 return 0; 1048 } 1049 1050 static snd_pcm_uframes_t skl_platform_pcm_pointer 1051 (struct snd_pcm_substream *substream) 1052 { 1053 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream); 1054 struct hdac_ext_bus *ebus = get_bus_ctx(substream); 1055 unsigned int pos; 1056 1057 /* 1058 * Use DPIB for Playback stream as the periodic DMA Position-in- 1059 * Buffer Writes may be scheduled at the same time or later than 1060 * the MSI and does not guarantee to reflect the Position of the 1061 * last buffer that was transferred. Whereas DPIB register in 1062 * HAD space reflects the actual data that is transferred. 1063 * Use the position buffer for capture, as DPIB write gets 1064 * completed earlier than the actual data written to the DDR. 1065 */ 1066 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1067 pos = readl(ebus->bus.remap_addr + AZX_REG_VS_SDXDPIB_XBASE + 1068 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1069 hdac_stream(hstream)->index)); 1070 else 1071 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream)); 1072 1073 if (pos >= hdac_stream(hstream)->bufsize) 1074 pos = 0; 1075 1076 return bytes_to_frames(substream->runtime, pos); 1077 } 1078 1079 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream, 1080 u64 nsec) 1081 { 1082 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 1083 struct snd_soc_dai *codec_dai = rtd->codec_dai; 1084 u64 codec_frames, codec_nsecs; 1085 1086 if (!codec_dai->driver->ops->delay) 1087 return nsec; 1088 1089 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai); 1090 codec_nsecs = div_u64(codec_frames * 1000000000LL, 1091 substream->runtime->rate); 1092 1093 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 1094 return nsec + codec_nsecs; 1095 1096 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; 1097 } 1098 1099 static int skl_get_time_info(struct snd_pcm_substream *substream, 1100 struct timespec *system_ts, struct timespec *audio_ts, 1101 struct snd_pcm_audio_tstamp_config *audio_tstamp_config, 1102 struct snd_pcm_audio_tstamp_report *audio_tstamp_report) 1103 { 1104 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream); 1105 struct hdac_stream *hstr = hdac_stream(sstream); 1106 u64 nsec; 1107 1108 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && 1109 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) { 1110 1111 snd_pcm_gettime(substream->runtime, system_ts); 1112 1113 nsec = timecounter_read(&hstr->tc); 1114 nsec = div_u64(nsec, 3); /* can be optimized */ 1115 if (audio_tstamp_config->report_delay) 1116 nsec = skl_adjust_codec_delay(substream, nsec); 1117 1118 *audio_ts = ns_to_timespec(nsec); 1119 1120 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK; 1121 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */ 1122 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */ 1123 1124 } else { 1125 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; 1126 } 1127 1128 return 0; 1129 } 1130 1131 static const struct snd_pcm_ops skl_platform_ops = { 1132 .open = skl_platform_open, 1133 .ioctl = snd_pcm_lib_ioctl, 1134 .trigger = skl_platform_pcm_trigger, 1135 .pointer = skl_platform_pcm_pointer, 1136 .get_time_info = skl_get_time_info, 1137 .mmap = snd_pcm_lib_default_mmap, 1138 .page = snd_pcm_sgbuf_ops_page, 1139 }; 1140 1141 static void skl_pcm_free(struct snd_pcm *pcm) 1142 { 1143 snd_pcm_lib_preallocate_free_for_all(pcm); 1144 } 1145 1146 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) 1147 1148 static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd) 1149 { 1150 struct snd_soc_dai *dai = rtd->cpu_dai; 1151 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev); 1152 struct snd_pcm *pcm = rtd->pcm; 1153 unsigned int size; 1154 int retval = 0; 1155 struct skl *skl = ebus_to_skl(ebus); 1156 1157 if (dai->driver->playback.channels_min || 1158 dai->driver->capture.channels_min) { 1159 /* buffer pre-allocation */ 1160 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; 1161 if (size > MAX_PREALLOC_SIZE) 1162 size = MAX_PREALLOC_SIZE; 1163 retval = snd_pcm_lib_preallocate_pages_for_all(pcm, 1164 SNDRV_DMA_TYPE_DEV_SG, 1165 snd_dma_pci_data(skl->pci), 1166 size, MAX_PREALLOC_SIZE); 1167 if (retval) { 1168 dev_err(dai->dev, "dma buffer allocationf fail\n"); 1169 return retval; 1170 } 1171 } 1172 1173 return retval; 1174 } 1175 1176 static int skl_populate_modules(struct skl *skl) 1177 { 1178 struct skl_pipeline *p; 1179 struct skl_pipe_module *m; 1180 struct snd_soc_dapm_widget *w; 1181 struct skl_module_cfg *mconfig; 1182 int ret; 1183 1184 list_for_each_entry(p, &skl->ppl_list, node) { 1185 list_for_each_entry(m, &p->pipe->w_list, node) { 1186 1187 w = m->w; 1188 mconfig = w->priv; 1189 1190 ret = snd_skl_get_module_info(skl->skl_sst, mconfig); 1191 if (ret < 0) { 1192 dev_err(skl->skl_sst->dev, 1193 "query module info failed:%d\n", ret); 1194 goto err; 1195 } 1196 } 1197 } 1198 err: 1199 return ret; 1200 } 1201 1202 static int skl_platform_soc_probe(struct snd_soc_platform *platform) 1203 { 1204 struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev); 1205 struct skl *skl = ebus_to_skl(ebus); 1206 const struct skl_dsp_ops *ops; 1207 int ret; 1208 1209 pm_runtime_get_sync(platform->dev); 1210 if ((ebus_to_hbus(ebus))->ppcap) { 1211 ret = skl_tplg_init(platform, ebus); 1212 if (ret < 0) { 1213 dev_err(platform->dev, "Failed to init topology!\n"); 1214 return ret; 1215 } 1216 skl->platform = platform; 1217 1218 /* load the firmwares, since all is set */ 1219 ops = skl_get_dsp_ops(skl->pci->device); 1220 if (!ops) 1221 return -EIO; 1222 1223 if (skl->skl_sst->is_first_boot == false) { 1224 dev_err(platform->dev, "DSP reports first boot done!!!\n"); 1225 return -EIO; 1226 } 1227 1228 ret = ops->init_fw(platform->dev, skl->skl_sst); 1229 if (ret < 0) { 1230 dev_err(platform->dev, "Failed to boot first fw: %d\n", ret); 1231 return ret; 1232 } 1233 skl_populate_modules(skl); 1234 skl->skl_sst->update_d0i3c = skl_update_d0i3c; 1235 } 1236 pm_runtime_mark_last_busy(platform->dev); 1237 pm_runtime_put_autosuspend(platform->dev); 1238 1239 return 0; 1240 } 1241 static struct snd_soc_platform_driver skl_platform_drv = { 1242 .probe = skl_platform_soc_probe, 1243 .ops = &skl_platform_ops, 1244 .pcm_new = skl_pcm_new, 1245 .pcm_free = skl_pcm_free, 1246 }; 1247 1248 static const struct snd_soc_component_driver skl_component = { 1249 .name = "pcm", 1250 }; 1251 1252 int skl_platform_register(struct device *dev) 1253 { 1254 int ret; 1255 struct hdac_ext_bus *ebus = dev_get_drvdata(dev); 1256 struct skl *skl = ebus_to_skl(ebus); 1257 1258 INIT_LIST_HEAD(&skl->ppl_list); 1259 1260 ret = snd_soc_register_platform(dev, &skl_platform_drv); 1261 if (ret) { 1262 dev_err(dev, "soc platform registration failed %d\n", ret); 1263 return ret; 1264 } 1265 ret = snd_soc_register_component(dev, &skl_component, 1266 skl_platform_dai, 1267 ARRAY_SIZE(skl_platform_dai)); 1268 if (ret) { 1269 dev_err(dev, "soc component registration failed %d\n", ret); 1270 snd_soc_unregister_platform(dev); 1271 } 1272 1273 return ret; 1274 1275 } 1276 1277 int skl_platform_unregister(struct device *dev) 1278 { 1279 snd_soc_unregister_component(dev); 1280 snd_soc_unregister_platform(dev); 1281 return 0; 1282 } 1283