1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality 4 * 5 * Copyright (C) 2014-2015 Intel Corp 6 * Author: Jeeja KP <jeeja.kp@intel.com> 7 * 8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 9 * 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 */ 12 13 #include <linux/pci.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/delay.h> 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 #include "skl.h" 19 #include "skl-topology.h" 20 #include "skl-sst-dsp.h" 21 #include "skl-sst-ipc.h" 22 23 #define HDA_MONO 1 24 #define HDA_STEREO 2 25 #define HDA_QUAD 4 26 #define HDA_MAX 8 27 28 static const struct snd_pcm_hardware azx_pcm_hw = { 29 .info = (SNDRV_PCM_INFO_MMAP | 30 SNDRV_PCM_INFO_INTERLEAVED | 31 SNDRV_PCM_INFO_BLOCK_TRANSFER | 32 SNDRV_PCM_INFO_MMAP_VALID | 33 SNDRV_PCM_INFO_PAUSE | 34 SNDRV_PCM_INFO_RESUME | 35 SNDRV_PCM_INFO_SYNC_START | 36 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */ 37 SNDRV_PCM_INFO_HAS_LINK_ATIME | 38 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 39 .formats = SNDRV_PCM_FMTBIT_S16_LE | 40 SNDRV_PCM_FMTBIT_S32_LE | 41 SNDRV_PCM_FMTBIT_S24_LE, 42 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 43 SNDRV_PCM_RATE_8000, 44 .rate_min = 8000, 45 .rate_max = 48000, 46 .channels_min = 1, 47 .channels_max = 8, 48 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 49 .period_bytes_min = 128, 50 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 51 .periods_min = 2, 52 .periods_max = AZX_MAX_FRAG, 53 .fifo_size = 0, 54 }; 55 56 static inline 57 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream) 58 { 59 return substream->runtime->private_data; 60 } 61 62 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream) 63 { 64 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 65 struct hdac_stream *hstream = hdac_stream(stream); 66 struct hdac_bus *bus = hstream->bus; 67 return bus; 68 } 69 70 static int skl_substream_alloc_pages(struct hdac_bus *bus, 71 struct snd_pcm_substream *substream, 72 size_t size) 73 { 74 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 75 76 hdac_stream(stream)->bufsize = 0; 77 hdac_stream(stream)->period_bytes = 0; 78 hdac_stream(stream)->format_val = 0; 79 80 return 0; 81 } 82 83 static void skl_set_pcm_constrains(struct hdac_bus *bus, 84 struct snd_pcm_runtime *runtime) 85 { 86 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 87 88 /* avoid wrap-around with wall-clock */ 89 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, 90 20, 178000000); 91 } 92 93 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus) 94 { 95 if (bus->ppcap) 96 return HDAC_EXT_STREAM_TYPE_HOST; 97 else 98 return HDAC_EXT_STREAM_TYPE_COUPLED; 99 } 100 101 /* 102 * check if the stream opened is marked as ignore_suspend by machine, if so 103 * then enable suspend_active refcount 104 * 105 * The count supend_active does not need lock as it is used in open/close 106 * and suspend context 107 */ 108 static void skl_set_suspend_active(struct snd_pcm_substream *substream, 109 struct snd_soc_dai *dai, bool enable) 110 { 111 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 112 struct snd_soc_dapm_widget *w; 113 struct skl_dev *skl = bus_to_skl(bus); 114 115 w = snd_soc_dai_get_widget(dai, substream->stream); 116 117 if (w->ignore_suspend && enable) 118 skl->supend_active++; 119 else if (w->ignore_suspend && !enable) 120 skl->supend_active--; 121 } 122 123 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params) 124 { 125 struct hdac_bus *bus = dev_get_drvdata(dev); 126 struct skl_dev *skl = bus_to_skl(bus); 127 unsigned int format_val; 128 struct hdac_stream *hstream; 129 struct hdac_ext_stream *stream; 130 int err; 131 132 hstream = snd_hdac_get_stream(bus, params->stream, 133 params->host_dma_id + 1); 134 if (!hstream) 135 return -EINVAL; 136 137 stream = stream_to_hdac_ext_stream(hstream); 138 snd_hdac_ext_stream_decouple(bus, stream, true); 139 140 format_val = snd_hdac_calc_stream_format(params->s_freq, 141 params->ch, params->format, params->host_bps, 0); 142 143 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n", 144 format_val, params->s_freq, params->ch, params->format); 145 146 snd_hdac_stream_reset(hdac_stream(stream)); 147 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val); 148 if (err < 0) 149 return err; 150 151 /* 152 * The recommended SDxFMT programming sequence for BXT 153 * platforms is to couple the stream before writing the format 154 */ 155 if (IS_BXT(skl->pci)) { 156 snd_hdac_ext_stream_decouple(bus, stream, false); 157 err = snd_hdac_stream_setup(hdac_stream(stream)); 158 snd_hdac_ext_stream_decouple(bus, stream, true); 159 } else { 160 err = snd_hdac_stream_setup(hdac_stream(stream)); 161 } 162 163 if (err < 0) 164 return err; 165 166 hdac_stream(stream)->prepared = 1; 167 168 return 0; 169 } 170 171 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params) 172 { 173 struct hdac_bus *bus = dev_get_drvdata(dev); 174 unsigned int format_val; 175 struct hdac_stream *hstream; 176 struct hdac_ext_stream *stream; 177 struct hdac_ext_link *link; 178 unsigned char stream_tag; 179 180 hstream = snd_hdac_get_stream(bus, params->stream, 181 params->link_dma_id + 1); 182 if (!hstream) 183 return -EINVAL; 184 185 stream = stream_to_hdac_ext_stream(hstream); 186 snd_hdac_ext_stream_decouple(bus, stream, true); 187 format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch, 188 params->format, params->link_bps, 0); 189 190 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n", 191 format_val, params->s_freq, params->ch, params->format); 192 193 snd_hdac_ext_link_stream_reset(stream); 194 195 snd_hdac_ext_link_stream_setup(stream, format_val); 196 197 stream_tag = hstream->stream_tag; 198 if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) { 199 list_for_each_entry(link, &bus->hlink_list, list) { 200 if (link->index == params->link_index) 201 snd_hdac_ext_link_set_stream_id(link, 202 stream_tag); 203 } 204 } 205 206 stream->link_prepared = 1; 207 208 return 0; 209 } 210 211 static int skl_pcm_open(struct snd_pcm_substream *substream, 212 struct snd_soc_dai *dai) 213 { 214 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 215 struct hdac_ext_stream *stream; 216 struct snd_pcm_runtime *runtime = substream->runtime; 217 struct skl_dma_params *dma_params; 218 struct skl_dev *skl = get_skl_ctx(dai->dev); 219 struct skl_module_cfg *mconfig; 220 221 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 222 223 stream = snd_hdac_ext_stream_assign(bus, substream, 224 skl_get_host_stream_type(bus)); 225 if (stream == NULL) 226 return -EBUSY; 227 228 skl_set_pcm_constrains(bus, runtime); 229 230 /* 231 * disable WALLCLOCK timestamps for capture streams 232 * until we figure out how to handle digital inputs 233 */ 234 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 235 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */ 236 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME; 237 } 238 239 runtime->private_data = stream; 240 241 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL); 242 if (!dma_params) 243 return -ENOMEM; 244 245 dma_params->stream_tag = hdac_stream(stream)->stream_tag; 246 snd_soc_dai_set_dma_data(dai, substream, dma_params); 247 248 dev_dbg(dai->dev, "stream tag set in dma params=%d\n", 249 dma_params->stream_tag); 250 skl_set_suspend_active(substream, dai, true); 251 snd_pcm_set_sync(substream); 252 253 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 254 if (!mconfig) 255 return -EINVAL; 256 257 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps); 258 259 return 0; 260 } 261 262 static int skl_pcm_prepare(struct snd_pcm_substream *substream, 263 struct snd_soc_dai *dai) 264 { 265 struct skl_dev *skl = get_skl_ctx(dai->dev); 266 struct skl_module_cfg *mconfig; 267 int ret; 268 269 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 270 271 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 272 273 /* 274 * In case of XRUN recovery or in the case when the application 275 * calls prepare another time, reset the FW pipe to clean state 276 */ 277 if (mconfig && 278 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN || 279 mconfig->pipe->state == SKL_PIPE_CREATED || 280 mconfig->pipe->state == SKL_PIPE_PAUSED)) { 281 282 ret = skl_reset_pipe(skl, mconfig->pipe); 283 284 if (ret < 0) 285 return ret; 286 287 ret = skl_pcm_host_dma_prepare(dai->dev, 288 mconfig->pipe->p_params); 289 if (ret < 0) 290 return ret; 291 } 292 293 return 0; 294 } 295 296 static int skl_pcm_hw_params(struct snd_pcm_substream *substream, 297 struct snd_pcm_hw_params *params, 298 struct snd_soc_dai *dai) 299 { 300 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 301 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 302 struct snd_pcm_runtime *runtime = substream->runtime; 303 struct skl_pipe_params p_params = {0}; 304 struct skl_module_cfg *m_cfg; 305 int ret, dma_id; 306 307 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 308 ret = skl_substream_alloc_pages(bus, substream, 309 params_buffer_bytes(params)); 310 if (ret < 0) 311 return ret; 312 313 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n", 314 runtime->rate, runtime->channels, runtime->format); 315 316 dma_id = hdac_stream(stream)->stream_tag - 1; 317 dev_dbg(dai->dev, "dma_id=%d\n", dma_id); 318 319 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 320 p_params.s_cont = snd_pcm_format_physical_width(params_format(params)); 321 p_params.ch = params_channels(params); 322 p_params.s_freq = params_rate(params); 323 p_params.host_dma_id = dma_id; 324 p_params.stream = substream->stream; 325 p_params.format = params_format(params); 326 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 327 p_params.host_bps = dai->driver->playback.sig_bits; 328 else 329 p_params.host_bps = dai->driver->capture.sig_bits; 330 331 332 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream); 333 if (m_cfg) 334 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params); 335 336 return 0; 337 } 338 339 static void skl_pcm_close(struct snd_pcm_substream *substream, 340 struct snd_soc_dai *dai) 341 { 342 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 343 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 344 struct skl_dma_params *dma_params = NULL; 345 struct skl_dev *skl = bus_to_skl(bus); 346 struct skl_module_cfg *mconfig; 347 348 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 349 350 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus)); 351 352 dma_params = snd_soc_dai_get_dma_data(dai, substream); 353 /* 354 * now we should set this to NULL as we are freeing by the 355 * dma_params 356 */ 357 snd_soc_dai_set_dma_data(dai, substream, NULL); 358 skl_set_suspend_active(substream, dai, false); 359 360 /* 361 * check if close is for "Reference Pin" and set back the 362 * CGCTL.MISCBDCGE if disabled by driver 363 */ 364 if (!strncmp(dai->name, "Reference Pin", 13) && 365 skl->miscbdcg_disabled) { 366 skl->enable_miscbdcge(dai->dev, true); 367 skl->miscbdcg_disabled = false; 368 } 369 370 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 371 if (mconfig) 372 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps); 373 374 kfree(dma_params); 375 } 376 377 static int skl_pcm_hw_free(struct snd_pcm_substream *substream, 378 struct snd_soc_dai *dai) 379 { 380 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 381 struct skl_dev *skl = get_skl_ctx(dai->dev); 382 struct skl_module_cfg *mconfig; 383 int ret; 384 385 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 386 387 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 388 389 if (mconfig) { 390 ret = skl_reset_pipe(skl, mconfig->pipe); 391 if (ret < 0) 392 dev_err(dai->dev, "%s:Reset failed ret =%d", 393 __func__, ret); 394 } 395 396 snd_hdac_stream_cleanup(hdac_stream(stream)); 397 hdac_stream(stream)->prepared = 0; 398 399 return 0; 400 } 401 402 static int skl_be_hw_params(struct snd_pcm_substream *substream, 403 struct snd_pcm_hw_params *params, 404 struct snd_soc_dai *dai) 405 { 406 struct skl_pipe_params p_params = {0}; 407 408 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 409 p_params.s_cont = snd_pcm_format_physical_width(params_format(params)); 410 p_params.ch = params_channels(params); 411 p_params.s_freq = params_rate(params); 412 p_params.stream = substream->stream; 413 414 return skl_tplg_be_update_params(dai, &p_params); 415 } 416 417 static int skl_decoupled_trigger(struct snd_pcm_substream *substream, 418 int cmd) 419 { 420 struct hdac_bus *bus = get_bus_ctx(substream); 421 struct hdac_ext_stream *stream; 422 int start; 423 unsigned long cookie; 424 struct hdac_stream *hstr; 425 426 stream = get_hdac_ext_stream(substream); 427 hstr = hdac_stream(stream); 428 429 if (!hstr->prepared) 430 return -EPIPE; 431 432 switch (cmd) { 433 case SNDRV_PCM_TRIGGER_START: 434 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 435 case SNDRV_PCM_TRIGGER_RESUME: 436 start = 1; 437 break; 438 439 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 440 case SNDRV_PCM_TRIGGER_SUSPEND: 441 case SNDRV_PCM_TRIGGER_STOP: 442 start = 0; 443 break; 444 445 default: 446 return -EINVAL; 447 } 448 449 spin_lock_irqsave(&bus->reg_lock, cookie); 450 451 if (start) { 452 snd_hdac_stream_start(hdac_stream(stream), true); 453 snd_hdac_stream_timecounter_init(hstr, 0); 454 } else { 455 snd_hdac_stream_stop(hdac_stream(stream)); 456 } 457 458 spin_unlock_irqrestore(&bus->reg_lock, cookie); 459 460 return 0; 461 } 462 463 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 464 struct snd_soc_dai *dai) 465 { 466 struct skl_dev *skl = get_skl_ctx(dai->dev); 467 struct skl_module_cfg *mconfig; 468 struct hdac_bus *bus = get_bus_ctx(substream); 469 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 470 struct snd_soc_dapm_widget *w; 471 int ret; 472 473 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 474 if (!mconfig) 475 return -EIO; 476 477 w = snd_soc_dai_get_widget(dai, substream->stream); 478 479 switch (cmd) { 480 case SNDRV_PCM_TRIGGER_RESUME: 481 if (!w->ignore_suspend) { 482 /* 483 * enable DMA Resume enable bit for the stream, set the 484 * dpib & lpib position to resume before starting the 485 * DMA 486 */ 487 snd_hdac_ext_stream_drsm_enable(bus, true, 488 hdac_stream(stream)->index); 489 snd_hdac_ext_stream_set_dpibr(bus, stream, 490 stream->lpib); 491 snd_hdac_ext_stream_set_lpib(stream, stream->lpib); 492 } 493 fallthrough; 494 495 case SNDRV_PCM_TRIGGER_START: 496 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 497 /* 498 * Start HOST DMA and Start FE Pipe.This is to make sure that 499 * there are no underrun/overrun in the case when the FE 500 * pipeline is started but there is a delay in starting the 501 * DMA channel on the host. 502 */ 503 ret = skl_decoupled_trigger(substream, cmd); 504 if (ret < 0) 505 return ret; 506 return skl_run_pipe(skl, mconfig->pipe); 507 508 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 509 case SNDRV_PCM_TRIGGER_SUSPEND: 510 case SNDRV_PCM_TRIGGER_STOP: 511 /* 512 * Stop FE Pipe first and stop DMA. This is to make sure that 513 * there are no underrun/overrun in the case if there is a delay 514 * between the two operations. 515 */ 516 ret = skl_stop_pipe(skl, mconfig->pipe); 517 if (ret < 0) 518 return ret; 519 520 ret = skl_decoupled_trigger(substream, cmd); 521 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) { 522 /* save the dpib and lpib positions */ 523 stream->dpib = readl(bus->remap_addr + 524 AZX_REG_VS_SDXDPIB_XBASE + 525 (AZX_REG_VS_SDXDPIB_XINTERVAL * 526 hdac_stream(stream)->index)); 527 528 stream->lpib = snd_hdac_stream_get_pos_lpib( 529 hdac_stream(stream)); 530 snd_hdac_ext_stream_decouple(bus, stream, false); 531 } 532 break; 533 534 default: 535 return -EINVAL; 536 } 537 538 return 0; 539 } 540 541 542 static int skl_link_hw_params(struct snd_pcm_substream *substream, 543 struct snd_pcm_hw_params *params, 544 struct snd_soc_dai *dai) 545 { 546 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 547 struct hdac_ext_stream *link_dev; 548 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 549 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); 550 struct skl_pipe_params p_params = {0}; 551 struct hdac_ext_link *link; 552 int stream_tag; 553 554 link_dev = snd_hdac_ext_stream_assign(bus, substream, 555 HDAC_EXT_STREAM_TYPE_LINK); 556 if (!link_dev) 557 return -EBUSY; 558 559 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev); 560 561 link = snd_hdac_ext_bus_get_link(bus, codec_dai->component->name); 562 if (!link) 563 return -EINVAL; 564 565 stream_tag = hdac_stream(link_dev)->stream_tag; 566 567 /* set the stream tag in the codec dai dma params */ 568 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 569 snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0); 570 else 571 snd_soc_dai_set_tdm_slot(codec_dai, 0, stream_tag, 0, 0); 572 573 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 574 p_params.s_cont = snd_pcm_format_physical_width(params_format(params)); 575 p_params.ch = params_channels(params); 576 p_params.s_freq = params_rate(params); 577 p_params.stream = substream->stream; 578 p_params.link_dma_id = stream_tag - 1; 579 p_params.link_index = link->index; 580 p_params.format = params_format(params); 581 582 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 583 p_params.link_bps = codec_dai->driver->playback.sig_bits; 584 else 585 p_params.link_bps = codec_dai->driver->capture.sig_bits; 586 587 return skl_tplg_be_update_params(dai, &p_params); 588 } 589 590 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream, 591 struct snd_soc_dai *dai) 592 { 593 struct skl_dev *skl = get_skl_ctx(dai->dev); 594 struct skl_module_cfg *mconfig = NULL; 595 596 /* In case of XRUN recovery, reset the FW pipe to clean state */ 597 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream); 598 if (mconfig && !mconfig->pipe->passthru && 599 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN)) 600 skl_reset_pipe(skl, mconfig->pipe); 601 602 return 0; 603 } 604 605 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream, 606 int cmd, struct snd_soc_dai *dai) 607 { 608 struct hdac_ext_stream *link_dev = 609 snd_soc_dai_get_dma_data(dai, substream); 610 struct hdac_bus *bus = get_bus_ctx(substream); 611 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 612 613 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd); 614 switch (cmd) { 615 case SNDRV_PCM_TRIGGER_RESUME: 616 case SNDRV_PCM_TRIGGER_START: 617 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 618 snd_hdac_ext_link_stream_start(link_dev); 619 break; 620 621 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 622 case SNDRV_PCM_TRIGGER_SUSPEND: 623 case SNDRV_PCM_TRIGGER_STOP: 624 snd_hdac_ext_link_stream_clear(link_dev); 625 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND) 626 snd_hdac_ext_stream_decouple(bus, stream, false); 627 break; 628 629 default: 630 return -EINVAL; 631 } 632 return 0; 633 } 634 635 static int skl_link_hw_free(struct snd_pcm_substream *substream, 636 struct snd_soc_dai *dai) 637 { 638 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 639 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 640 struct hdac_ext_stream *link_dev = 641 snd_soc_dai_get_dma_data(dai, substream); 642 struct hdac_ext_link *link; 643 unsigned char stream_tag; 644 645 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 646 647 link_dev->link_prepared = 0; 648 649 link = snd_hdac_ext_bus_get_link(bus, asoc_rtd_to_codec(rtd, 0)->component->name); 650 if (!link) 651 return -EINVAL; 652 653 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 654 stream_tag = hdac_stream(link_dev)->stream_tag; 655 snd_hdac_ext_link_clear_stream_id(link, stream_tag); 656 } 657 658 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK); 659 return 0; 660 } 661 662 static const struct snd_soc_dai_ops skl_pcm_dai_ops = { 663 .startup = skl_pcm_open, 664 .shutdown = skl_pcm_close, 665 .prepare = skl_pcm_prepare, 666 .hw_params = skl_pcm_hw_params, 667 .hw_free = skl_pcm_hw_free, 668 .trigger = skl_pcm_trigger, 669 }; 670 671 static const struct snd_soc_dai_ops skl_dmic_dai_ops = { 672 .hw_params = skl_be_hw_params, 673 }; 674 675 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = { 676 .hw_params = skl_be_hw_params, 677 }; 678 679 static const struct snd_soc_dai_ops skl_link_dai_ops = { 680 .prepare = skl_link_pcm_prepare, 681 .hw_params = skl_link_hw_params, 682 .hw_free = skl_link_hw_free, 683 .trigger = skl_link_pcm_trigger, 684 }; 685 686 static struct snd_soc_dai_driver skl_fe_dai[] = { 687 { 688 .name = "System Pin", 689 .ops = &skl_pcm_dai_ops, 690 .playback = { 691 .stream_name = "System Playback", 692 .channels_min = HDA_MONO, 693 .channels_max = HDA_STEREO, 694 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000, 695 .formats = SNDRV_PCM_FMTBIT_S16_LE | 696 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 697 .sig_bits = 32, 698 }, 699 .capture = { 700 .stream_name = "System Capture", 701 .channels_min = HDA_MONO, 702 .channels_max = HDA_STEREO, 703 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 704 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 705 .sig_bits = 32, 706 }, 707 }, 708 { 709 .name = "System Pin2", 710 .ops = &skl_pcm_dai_ops, 711 .playback = { 712 .stream_name = "Headset Playback", 713 .channels_min = HDA_MONO, 714 .channels_max = HDA_STEREO, 715 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 716 SNDRV_PCM_RATE_8000, 717 .formats = SNDRV_PCM_FMTBIT_S16_LE | 718 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 719 }, 720 }, 721 { 722 .name = "Echoref Pin", 723 .ops = &skl_pcm_dai_ops, 724 .capture = { 725 .stream_name = "Echoreference Capture", 726 .channels_min = HDA_STEREO, 727 .channels_max = HDA_STEREO, 728 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 729 SNDRV_PCM_RATE_8000, 730 .formats = SNDRV_PCM_FMTBIT_S16_LE | 731 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 732 }, 733 }, 734 { 735 .name = "Reference Pin", 736 .ops = &skl_pcm_dai_ops, 737 .capture = { 738 .stream_name = "Reference Capture", 739 .channels_min = HDA_MONO, 740 .channels_max = HDA_QUAD, 741 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 742 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 743 .sig_bits = 32, 744 }, 745 }, 746 { 747 .name = "Deepbuffer Pin", 748 .ops = &skl_pcm_dai_ops, 749 .playback = { 750 .stream_name = "Deepbuffer Playback", 751 .channels_min = HDA_STEREO, 752 .channels_max = HDA_STEREO, 753 .rates = SNDRV_PCM_RATE_48000, 754 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 755 .sig_bits = 32, 756 }, 757 }, 758 { 759 .name = "LowLatency Pin", 760 .ops = &skl_pcm_dai_ops, 761 .playback = { 762 .stream_name = "Low Latency Playback", 763 .channels_min = HDA_STEREO, 764 .channels_max = HDA_STEREO, 765 .rates = SNDRV_PCM_RATE_48000, 766 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 767 .sig_bits = 32, 768 }, 769 }, 770 { 771 .name = "DMIC Pin", 772 .ops = &skl_pcm_dai_ops, 773 .capture = { 774 .stream_name = "DMIC Capture", 775 .channels_min = HDA_MONO, 776 .channels_max = HDA_QUAD, 777 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 778 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 779 .sig_bits = 32, 780 }, 781 }, 782 { 783 .name = "HDMI1 Pin", 784 .ops = &skl_pcm_dai_ops, 785 .playback = { 786 .stream_name = "HDMI1 Playback", 787 .channels_min = HDA_STEREO, 788 .channels_max = 8, 789 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 790 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 791 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 792 SNDRV_PCM_RATE_192000, 793 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 794 SNDRV_PCM_FMTBIT_S32_LE, 795 .sig_bits = 32, 796 }, 797 }, 798 { 799 .name = "HDMI2 Pin", 800 .ops = &skl_pcm_dai_ops, 801 .playback = { 802 .stream_name = "HDMI2 Playback", 803 .channels_min = HDA_STEREO, 804 .channels_max = 8, 805 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 806 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 807 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 808 SNDRV_PCM_RATE_192000, 809 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 810 SNDRV_PCM_FMTBIT_S32_LE, 811 .sig_bits = 32, 812 }, 813 }, 814 { 815 .name = "HDMI3 Pin", 816 .ops = &skl_pcm_dai_ops, 817 .playback = { 818 .stream_name = "HDMI3 Playback", 819 .channels_min = HDA_STEREO, 820 .channels_max = 8, 821 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 822 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 823 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 824 SNDRV_PCM_RATE_192000, 825 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 826 SNDRV_PCM_FMTBIT_S32_LE, 827 .sig_bits = 32, 828 }, 829 }, 830 }; 831 832 /* BE CPU Dais */ 833 static struct snd_soc_dai_driver skl_platform_dai[] = { 834 { 835 .name = "SSP0 Pin", 836 .ops = &skl_be_ssp_dai_ops, 837 .playback = { 838 .stream_name = "ssp0 Tx", 839 .channels_min = HDA_STEREO, 840 .channels_max = HDA_STEREO, 841 .rates = SNDRV_PCM_RATE_48000, 842 .formats = SNDRV_PCM_FMTBIT_S16_LE, 843 }, 844 .capture = { 845 .stream_name = "ssp0 Rx", 846 .channels_min = HDA_STEREO, 847 .channels_max = HDA_STEREO, 848 .rates = SNDRV_PCM_RATE_48000, 849 .formats = SNDRV_PCM_FMTBIT_S16_LE, 850 }, 851 }, 852 { 853 .name = "SSP1 Pin", 854 .ops = &skl_be_ssp_dai_ops, 855 .playback = { 856 .stream_name = "ssp1 Tx", 857 .channels_min = HDA_STEREO, 858 .channels_max = HDA_STEREO, 859 .rates = SNDRV_PCM_RATE_48000, 860 .formats = SNDRV_PCM_FMTBIT_S16_LE, 861 }, 862 .capture = { 863 .stream_name = "ssp1 Rx", 864 .channels_min = HDA_STEREO, 865 .channels_max = HDA_STEREO, 866 .rates = SNDRV_PCM_RATE_48000, 867 .formats = SNDRV_PCM_FMTBIT_S16_LE, 868 }, 869 }, 870 { 871 .name = "SSP2 Pin", 872 .ops = &skl_be_ssp_dai_ops, 873 .playback = { 874 .stream_name = "ssp2 Tx", 875 .channels_min = HDA_STEREO, 876 .channels_max = HDA_STEREO, 877 .rates = SNDRV_PCM_RATE_48000, 878 .formats = SNDRV_PCM_FMTBIT_S16_LE, 879 }, 880 .capture = { 881 .stream_name = "ssp2 Rx", 882 .channels_min = HDA_STEREO, 883 .channels_max = HDA_STEREO, 884 .rates = SNDRV_PCM_RATE_48000, 885 .formats = SNDRV_PCM_FMTBIT_S16_LE, 886 }, 887 }, 888 { 889 .name = "SSP3 Pin", 890 .ops = &skl_be_ssp_dai_ops, 891 .playback = { 892 .stream_name = "ssp3 Tx", 893 .channels_min = HDA_STEREO, 894 .channels_max = HDA_STEREO, 895 .rates = SNDRV_PCM_RATE_48000, 896 .formats = SNDRV_PCM_FMTBIT_S16_LE, 897 }, 898 .capture = { 899 .stream_name = "ssp3 Rx", 900 .channels_min = HDA_STEREO, 901 .channels_max = HDA_STEREO, 902 .rates = SNDRV_PCM_RATE_48000, 903 .formats = SNDRV_PCM_FMTBIT_S16_LE, 904 }, 905 }, 906 { 907 .name = "SSP4 Pin", 908 .ops = &skl_be_ssp_dai_ops, 909 .playback = { 910 .stream_name = "ssp4 Tx", 911 .channels_min = HDA_STEREO, 912 .channels_max = HDA_STEREO, 913 .rates = SNDRV_PCM_RATE_48000, 914 .formats = SNDRV_PCM_FMTBIT_S16_LE, 915 }, 916 .capture = { 917 .stream_name = "ssp4 Rx", 918 .channels_min = HDA_STEREO, 919 .channels_max = HDA_STEREO, 920 .rates = SNDRV_PCM_RATE_48000, 921 .formats = SNDRV_PCM_FMTBIT_S16_LE, 922 }, 923 }, 924 { 925 .name = "SSP5 Pin", 926 .ops = &skl_be_ssp_dai_ops, 927 .playback = { 928 .stream_name = "ssp5 Tx", 929 .channels_min = HDA_STEREO, 930 .channels_max = HDA_STEREO, 931 .rates = SNDRV_PCM_RATE_48000, 932 .formats = SNDRV_PCM_FMTBIT_S16_LE, 933 }, 934 .capture = { 935 .stream_name = "ssp5 Rx", 936 .channels_min = HDA_STEREO, 937 .channels_max = HDA_STEREO, 938 .rates = SNDRV_PCM_RATE_48000, 939 .formats = SNDRV_PCM_FMTBIT_S16_LE, 940 }, 941 }, 942 { 943 .name = "iDisp1 Pin", 944 .ops = &skl_link_dai_ops, 945 .playback = { 946 .stream_name = "iDisp1 Tx", 947 .channels_min = HDA_STEREO, 948 .channels_max = 8, 949 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000, 950 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 951 SNDRV_PCM_FMTBIT_S24_LE, 952 }, 953 }, 954 { 955 .name = "iDisp2 Pin", 956 .ops = &skl_link_dai_ops, 957 .playback = { 958 .stream_name = "iDisp2 Tx", 959 .channels_min = HDA_STEREO, 960 .channels_max = 8, 961 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| 962 SNDRV_PCM_RATE_48000, 963 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 964 SNDRV_PCM_FMTBIT_S24_LE, 965 }, 966 }, 967 { 968 .name = "iDisp3 Pin", 969 .ops = &skl_link_dai_ops, 970 .playback = { 971 .stream_name = "iDisp3 Tx", 972 .channels_min = HDA_STEREO, 973 .channels_max = 8, 974 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| 975 SNDRV_PCM_RATE_48000, 976 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 977 SNDRV_PCM_FMTBIT_S24_LE, 978 }, 979 }, 980 { 981 .name = "DMIC01 Pin", 982 .ops = &skl_dmic_dai_ops, 983 .capture = { 984 .stream_name = "DMIC01 Rx", 985 .channels_min = HDA_MONO, 986 .channels_max = HDA_QUAD, 987 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 988 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 989 }, 990 }, 991 { 992 .name = "DMIC16k Pin", 993 .ops = &skl_dmic_dai_ops, 994 .capture = { 995 .stream_name = "DMIC16k Rx", 996 .channels_min = HDA_MONO, 997 .channels_max = HDA_QUAD, 998 .rates = SNDRV_PCM_RATE_16000, 999 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1000 }, 1001 }, 1002 { 1003 .name = "Analog CPU DAI", 1004 .ops = &skl_link_dai_ops, 1005 .playback = { 1006 .stream_name = "Analog CPU Playback", 1007 .channels_min = HDA_MONO, 1008 .channels_max = HDA_MAX, 1009 .rates = SNDRV_PCM_RATE_8000_192000, 1010 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1011 SNDRV_PCM_FMTBIT_S32_LE, 1012 }, 1013 .capture = { 1014 .stream_name = "Analog CPU Capture", 1015 .channels_min = HDA_MONO, 1016 .channels_max = HDA_MAX, 1017 .rates = SNDRV_PCM_RATE_8000_192000, 1018 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1019 SNDRV_PCM_FMTBIT_S32_LE, 1020 }, 1021 }, 1022 { 1023 .name = "Alt Analog CPU DAI", 1024 .ops = &skl_link_dai_ops, 1025 .playback = { 1026 .stream_name = "Alt Analog CPU Playback", 1027 .channels_min = HDA_MONO, 1028 .channels_max = HDA_MAX, 1029 .rates = SNDRV_PCM_RATE_8000_192000, 1030 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1031 SNDRV_PCM_FMTBIT_S32_LE, 1032 }, 1033 .capture = { 1034 .stream_name = "Alt Analog CPU Capture", 1035 .channels_min = HDA_MONO, 1036 .channels_max = HDA_MAX, 1037 .rates = SNDRV_PCM_RATE_8000_192000, 1038 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1039 SNDRV_PCM_FMTBIT_S32_LE, 1040 }, 1041 }, 1042 { 1043 .name = "Digital CPU DAI", 1044 .ops = &skl_link_dai_ops, 1045 .playback = { 1046 .stream_name = "Digital CPU Playback", 1047 .channels_min = HDA_MONO, 1048 .channels_max = HDA_MAX, 1049 .rates = SNDRV_PCM_RATE_8000_192000, 1050 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1051 SNDRV_PCM_FMTBIT_S32_LE, 1052 }, 1053 .capture = { 1054 .stream_name = "Digital CPU Capture", 1055 .channels_min = HDA_MONO, 1056 .channels_max = HDA_MAX, 1057 .rates = SNDRV_PCM_RATE_8000_192000, 1058 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1059 SNDRV_PCM_FMTBIT_S32_LE, 1060 }, 1061 }, 1062 }; 1063 1064 int skl_dai_load(struct snd_soc_component *cmp, int index, 1065 struct snd_soc_dai_driver *dai_drv, 1066 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai) 1067 { 1068 dai_drv->ops = &skl_pcm_dai_ops; 1069 1070 return 0; 1071 } 1072 1073 static int skl_platform_soc_open(struct snd_soc_component *component, 1074 struct snd_pcm_substream *substream) 1075 { 1076 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 1077 struct snd_soc_dai_link *dai_link = rtd->dai_link; 1078 1079 dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__, 1080 dai_link->cpus->dai_name); 1081 1082 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw); 1083 1084 return 0; 1085 } 1086 1087 static int skl_coupled_trigger(struct snd_pcm_substream *substream, 1088 int cmd) 1089 { 1090 struct hdac_bus *bus = get_bus_ctx(substream); 1091 struct hdac_ext_stream *stream; 1092 struct snd_pcm_substream *s; 1093 bool start; 1094 int sbits = 0; 1095 unsigned long cookie; 1096 struct hdac_stream *hstr; 1097 1098 stream = get_hdac_ext_stream(substream); 1099 hstr = hdac_stream(stream); 1100 1101 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd); 1102 1103 if (!hstr->prepared) 1104 return -EPIPE; 1105 1106 switch (cmd) { 1107 case SNDRV_PCM_TRIGGER_START: 1108 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1109 case SNDRV_PCM_TRIGGER_RESUME: 1110 start = true; 1111 break; 1112 1113 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1114 case SNDRV_PCM_TRIGGER_SUSPEND: 1115 case SNDRV_PCM_TRIGGER_STOP: 1116 start = false; 1117 break; 1118 1119 default: 1120 return -EINVAL; 1121 } 1122 1123 snd_pcm_group_for_each_entry(s, substream) { 1124 if (s->pcm->card != substream->pcm->card) 1125 continue; 1126 stream = get_hdac_ext_stream(s); 1127 sbits |= 1 << hdac_stream(stream)->index; 1128 snd_pcm_trigger_done(s, substream); 1129 } 1130 1131 spin_lock_irqsave(&bus->reg_lock, cookie); 1132 1133 /* first, set SYNC bits of corresponding streams */ 1134 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC); 1135 1136 snd_pcm_group_for_each_entry(s, substream) { 1137 if (s->pcm->card != substream->pcm->card) 1138 continue; 1139 stream = get_hdac_ext_stream(s); 1140 if (start) 1141 snd_hdac_stream_start(hdac_stream(stream), true); 1142 else 1143 snd_hdac_stream_stop(hdac_stream(stream)); 1144 } 1145 spin_unlock_irqrestore(&bus->reg_lock, cookie); 1146 1147 snd_hdac_stream_sync(hstr, start, sbits); 1148 1149 spin_lock_irqsave(&bus->reg_lock, cookie); 1150 1151 /* reset SYNC bits */ 1152 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC); 1153 if (start) 1154 snd_hdac_stream_timecounter_init(hstr, sbits); 1155 spin_unlock_irqrestore(&bus->reg_lock, cookie); 1156 1157 return 0; 1158 } 1159 1160 static int skl_platform_soc_trigger(struct snd_soc_component *component, 1161 struct snd_pcm_substream *substream, 1162 int cmd) 1163 { 1164 struct hdac_bus *bus = get_bus_ctx(substream); 1165 1166 if (!bus->ppcap) 1167 return skl_coupled_trigger(substream, cmd); 1168 1169 return 0; 1170 } 1171 1172 static snd_pcm_uframes_t skl_platform_soc_pointer( 1173 struct snd_soc_component *component, 1174 struct snd_pcm_substream *substream) 1175 { 1176 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream); 1177 struct hdac_bus *bus = get_bus_ctx(substream); 1178 unsigned int pos; 1179 1180 /* 1181 * Use DPIB for Playback stream as the periodic DMA Position-in- 1182 * Buffer Writes may be scheduled at the same time or later than 1183 * the MSI and does not guarantee to reflect the Position of the 1184 * last buffer that was transferred. Whereas DPIB register in 1185 * HAD space reflects the actual data that is transferred. 1186 * Use the position buffer for capture, as DPIB write gets 1187 * completed earlier than the actual data written to the DDR. 1188 * 1189 * For capture stream following workaround is required to fix the 1190 * incorrect position reporting. 1191 * 1192 * 1. Wait for 20us before reading the DMA position in buffer once 1193 * the interrupt is generated for stream completion as update happens 1194 * on the HDA frame boundary i.e. 20.833uSec. 1195 * 2. Read DPIB register to flush the DMA position value. This dummy 1196 * read is required to flush DMA position value. 1197 * 3. Read the DMA Position-in-Buffer. This value now will be equal to 1198 * or greater than period boundary. 1199 */ 1200 1201 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1202 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE + 1203 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1204 hdac_stream(hstream)->index)); 1205 } else { 1206 udelay(20); 1207 readl(bus->remap_addr + 1208 AZX_REG_VS_SDXDPIB_XBASE + 1209 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1210 hdac_stream(hstream)->index)); 1211 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream)); 1212 } 1213 1214 if (pos >= hdac_stream(hstream)->bufsize) 1215 pos = 0; 1216 1217 return bytes_to_frames(substream->runtime, pos); 1218 } 1219 1220 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream, 1221 u64 nsec) 1222 { 1223 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 1224 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); 1225 u64 codec_frames, codec_nsecs; 1226 1227 if (!codec_dai->driver->ops->delay) 1228 return nsec; 1229 1230 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai); 1231 codec_nsecs = div_u64(codec_frames * 1000000000LL, 1232 substream->runtime->rate); 1233 1234 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 1235 return nsec + codec_nsecs; 1236 1237 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; 1238 } 1239 1240 static int skl_platform_soc_get_time_info( 1241 struct snd_soc_component *component, 1242 struct snd_pcm_substream *substream, 1243 struct timespec64 *system_ts, struct timespec64 *audio_ts, 1244 struct snd_pcm_audio_tstamp_config *audio_tstamp_config, 1245 struct snd_pcm_audio_tstamp_report *audio_tstamp_report) 1246 { 1247 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream); 1248 struct hdac_stream *hstr = hdac_stream(sstream); 1249 u64 nsec; 1250 1251 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && 1252 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) { 1253 1254 snd_pcm_gettime(substream->runtime, system_ts); 1255 1256 nsec = timecounter_read(&hstr->tc); 1257 if (audio_tstamp_config->report_delay) 1258 nsec = skl_adjust_codec_delay(substream, nsec); 1259 1260 *audio_ts = ns_to_timespec64(nsec); 1261 1262 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK; 1263 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */ 1264 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */ 1265 1266 } else { 1267 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; 1268 } 1269 1270 return 0; 1271 } 1272 1273 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) 1274 1275 static int skl_platform_soc_new(struct snd_soc_component *component, 1276 struct snd_soc_pcm_runtime *rtd) 1277 { 1278 struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0); 1279 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 1280 struct snd_pcm *pcm = rtd->pcm; 1281 unsigned int size; 1282 struct skl_dev *skl = bus_to_skl(bus); 1283 1284 if (dai->driver->playback.channels_min || 1285 dai->driver->capture.channels_min) { 1286 /* buffer pre-allocation */ 1287 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; 1288 if (size > MAX_PREALLOC_SIZE) 1289 size = MAX_PREALLOC_SIZE; 1290 snd_pcm_set_managed_buffer_all(pcm, 1291 SNDRV_DMA_TYPE_DEV_SG, 1292 &skl->pci->dev, 1293 size, MAX_PREALLOC_SIZE); 1294 } 1295 1296 return 0; 1297 } 1298 1299 static int skl_get_module_info(struct skl_dev *skl, 1300 struct skl_module_cfg *mconfig) 1301 { 1302 struct skl_module_inst_id *pin_id; 1303 guid_t *uuid_mod, *uuid_tplg; 1304 struct skl_module *skl_module; 1305 struct uuid_module *module; 1306 int i, ret = -EIO; 1307 1308 uuid_mod = (guid_t *)mconfig->guid; 1309 1310 if (list_empty(&skl->uuid_list)) { 1311 dev_err(skl->dev, "Module list is empty\n"); 1312 return -EIO; 1313 } 1314 1315 for (i = 0; i < skl->nr_modules; i++) { 1316 skl_module = skl->modules[i]; 1317 uuid_tplg = &skl_module->uuid; 1318 if (guid_equal(uuid_mod, uuid_tplg)) { 1319 mconfig->module = skl_module; 1320 ret = 0; 1321 break; 1322 } 1323 } 1324 1325 if (skl->nr_modules && ret) 1326 return ret; 1327 1328 ret = -EIO; 1329 list_for_each_entry(module, &skl->uuid_list, list) { 1330 if (guid_equal(uuid_mod, &module->uuid)) { 1331 mconfig->id.module_id = module->id; 1332 mconfig->module->loadable = module->is_loadable; 1333 ret = 0; 1334 } 1335 1336 for (i = 0; i < MAX_IN_QUEUE; i++) { 1337 pin_id = &mconfig->m_in_pin[i].id; 1338 if (guid_equal(&pin_id->mod_uuid, &module->uuid)) 1339 pin_id->module_id = module->id; 1340 } 1341 1342 for (i = 0; i < MAX_OUT_QUEUE; i++) { 1343 pin_id = &mconfig->m_out_pin[i].id; 1344 if (guid_equal(&pin_id->mod_uuid, &module->uuid)) 1345 pin_id->module_id = module->id; 1346 } 1347 } 1348 1349 return ret; 1350 } 1351 1352 static int skl_populate_modules(struct skl_dev *skl) 1353 { 1354 struct skl_pipeline *p; 1355 struct skl_pipe_module *m; 1356 struct snd_soc_dapm_widget *w; 1357 struct skl_module_cfg *mconfig; 1358 int ret = 0; 1359 1360 list_for_each_entry(p, &skl->ppl_list, node) { 1361 list_for_each_entry(m, &p->pipe->w_list, node) { 1362 w = m->w; 1363 mconfig = w->priv; 1364 1365 ret = skl_get_module_info(skl, mconfig); 1366 if (ret < 0) { 1367 dev_err(skl->dev, 1368 "query module info failed\n"); 1369 return ret; 1370 } 1371 1372 skl_tplg_add_moduleid_in_bind_params(skl, w); 1373 } 1374 } 1375 1376 return ret; 1377 } 1378 1379 static int skl_platform_soc_probe(struct snd_soc_component *component) 1380 { 1381 struct hdac_bus *bus = dev_get_drvdata(component->dev); 1382 struct skl_dev *skl = bus_to_skl(bus); 1383 const struct skl_dsp_ops *ops; 1384 int ret; 1385 1386 pm_runtime_get_sync(component->dev); 1387 if (bus->ppcap) { 1388 skl->component = component; 1389 1390 /* init debugfs */ 1391 skl->debugfs = skl_debugfs_init(skl); 1392 1393 ret = skl_tplg_init(component, bus); 1394 if (ret < 0) { 1395 dev_err(component->dev, "Failed to init topology!\n"); 1396 return ret; 1397 } 1398 1399 /* load the firmwares, since all is set */ 1400 ops = skl_get_dsp_ops(skl->pci->device); 1401 if (!ops) 1402 return -EIO; 1403 1404 /* 1405 * Disable dynamic clock and power gating during firmware 1406 * and library download 1407 */ 1408 skl->enable_miscbdcge(component->dev, false); 1409 skl->clock_power_gating(component->dev, false); 1410 1411 ret = ops->init_fw(component->dev, skl); 1412 skl->enable_miscbdcge(component->dev, true); 1413 skl->clock_power_gating(component->dev, true); 1414 if (ret < 0) { 1415 dev_err(component->dev, "Failed to boot first fw: %d\n", ret); 1416 return ret; 1417 } 1418 skl_populate_modules(skl); 1419 skl->update_d0i3c = skl_update_d0i3c; 1420 1421 if (skl->cfg.astate_cfg != NULL) { 1422 skl_dsp_set_astate_cfg(skl, 1423 skl->cfg.astate_cfg->count, 1424 skl->cfg.astate_cfg); 1425 } 1426 } 1427 pm_runtime_mark_last_busy(component->dev); 1428 pm_runtime_put_autosuspend(component->dev); 1429 1430 return 0; 1431 } 1432 1433 static void skl_platform_soc_remove(struct snd_soc_component *component) 1434 { 1435 struct hdac_bus *bus = dev_get_drvdata(component->dev); 1436 struct skl_dev *skl = bus_to_skl(bus); 1437 1438 skl_tplg_exit(component, bus); 1439 1440 skl_debugfs_exit(skl); 1441 } 1442 1443 static const struct snd_soc_component_driver skl_component = { 1444 .name = "pcm", 1445 .probe = skl_platform_soc_probe, 1446 .remove = skl_platform_soc_remove, 1447 .open = skl_platform_soc_open, 1448 .trigger = skl_platform_soc_trigger, 1449 .pointer = skl_platform_soc_pointer, 1450 .get_time_info = skl_platform_soc_get_time_info, 1451 .pcm_construct = skl_platform_soc_new, 1452 .module_get_upon_open = 1, /* increment refcount when a pcm is opened */ 1453 }; 1454 1455 int skl_platform_register(struct device *dev) 1456 { 1457 int ret; 1458 struct snd_soc_dai_driver *dais; 1459 int num_dais = ARRAY_SIZE(skl_platform_dai); 1460 struct hdac_bus *bus = dev_get_drvdata(dev); 1461 struct skl_dev *skl = bus_to_skl(bus); 1462 1463 skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai), 1464 GFP_KERNEL); 1465 if (!skl->dais) { 1466 ret = -ENOMEM; 1467 goto err; 1468 } 1469 1470 if (!skl->use_tplg_pcm) { 1471 dais = krealloc(skl->dais, sizeof(skl_fe_dai) + 1472 sizeof(skl_platform_dai), GFP_KERNEL); 1473 if (!dais) { 1474 ret = -ENOMEM; 1475 goto err; 1476 } 1477 1478 skl->dais = dais; 1479 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai, 1480 sizeof(skl_fe_dai)); 1481 num_dais += ARRAY_SIZE(skl_fe_dai); 1482 } 1483 1484 ret = devm_snd_soc_register_component(dev, &skl_component, 1485 skl->dais, num_dais); 1486 if (ret) 1487 dev_err(dev, "soc component registration failed %d\n", ret); 1488 err: 1489 return ret; 1490 } 1491 1492 int skl_platform_unregister(struct device *dev) 1493 { 1494 struct hdac_bus *bus = dev_get_drvdata(dev); 1495 struct skl_dev *skl = bus_to_skl(bus); 1496 struct skl_module_deferred_bind *modules, *tmp; 1497 1498 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) { 1499 list_del(&modules->node); 1500 kfree(modules); 1501 } 1502 1503 kfree(skl->dais); 1504 1505 return 0; 1506 } 1507