1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality 4 * 5 * Copyright (C) 2014-2015 Intel Corp 6 * Author: Jeeja KP <jeeja.kp@intel.com> 7 * 8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 9 * 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 */ 12 13 #include <linux/pci.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/delay.h> 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 #include "skl.h" 19 #include "skl-topology.h" 20 #include "skl-sst-dsp.h" 21 #include "skl-sst-ipc.h" 22 23 #define HDA_MONO 1 24 #define HDA_STEREO 2 25 #define HDA_QUAD 4 26 #define HDA_MAX 8 27 28 static const struct snd_pcm_hardware azx_pcm_hw = { 29 .info = (SNDRV_PCM_INFO_MMAP | 30 SNDRV_PCM_INFO_INTERLEAVED | 31 SNDRV_PCM_INFO_BLOCK_TRANSFER | 32 SNDRV_PCM_INFO_MMAP_VALID | 33 SNDRV_PCM_INFO_PAUSE | 34 SNDRV_PCM_INFO_RESUME | 35 SNDRV_PCM_INFO_SYNC_START | 36 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */ 37 SNDRV_PCM_INFO_HAS_LINK_ATIME | 38 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 39 .formats = SNDRV_PCM_FMTBIT_S16_LE | 40 SNDRV_PCM_FMTBIT_S32_LE | 41 SNDRV_PCM_FMTBIT_S24_LE, 42 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 43 SNDRV_PCM_RATE_8000, 44 .rate_min = 8000, 45 .rate_max = 48000, 46 .channels_min = 1, 47 .channels_max = 8, 48 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 49 .period_bytes_min = 128, 50 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 51 .periods_min = 2, 52 .periods_max = AZX_MAX_FRAG, 53 .fifo_size = 0, 54 }; 55 56 static inline 57 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream) 58 { 59 return substream->runtime->private_data; 60 } 61 62 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream) 63 { 64 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 65 struct hdac_stream *hstream = hdac_stream(stream); 66 struct hdac_bus *bus = hstream->bus; 67 return bus; 68 } 69 70 static int skl_substream_alloc_pages(struct hdac_bus *bus, 71 struct snd_pcm_substream *substream, 72 size_t size) 73 { 74 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 75 76 hdac_stream(stream)->bufsize = 0; 77 hdac_stream(stream)->period_bytes = 0; 78 hdac_stream(stream)->format_val = 0; 79 80 return snd_pcm_lib_malloc_pages(substream, size); 81 } 82 83 static int skl_substream_free_pages(struct hdac_bus *bus, 84 struct snd_pcm_substream *substream) 85 { 86 return snd_pcm_lib_free_pages(substream); 87 } 88 89 static void skl_set_pcm_constrains(struct hdac_bus *bus, 90 struct snd_pcm_runtime *runtime) 91 { 92 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 93 94 /* avoid wrap-around with wall-clock */ 95 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, 96 20, 178000000); 97 } 98 99 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus) 100 { 101 if (bus->ppcap) 102 return HDAC_EXT_STREAM_TYPE_HOST; 103 else 104 return HDAC_EXT_STREAM_TYPE_COUPLED; 105 } 106 107 /* 108 * check if the stream opened is marked as ignore_suspend by machine, if so 109 * then enable suspend_active refcount 110 * 111 * The count supend_active does not need lock as it is used in open/close 112 * and suspend context 113 */ 114 static void skl_set_suspend_active(struct snd_pcm_substream *substream, 115 struct snd_soc_dai *dai, bool enable) 116 { 117 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 118 struct snd_soc_dapm_widget *w; 119 struct skl *skl = bus_to_skl(bus); 120 121 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 122 w = dai->playback_widget; 123 else 124 w = dai->capture_widget; 125 126 if (w->ignore_suspend && enable) 127 skl->supend_active++; 128 else if (w->ignore_suspend && !enable) 129 skl->supend_active--; 130 } 131 132 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params) 133 { 134 struct hdac_bus *bus = dev_get_drvdata(dev); 135 unsigned int format_val; 136 struct hdac_stream *hstream; 137 struct hdac_ext_stream *stream; 138 int err; 139 140 hstream = snd_hdac_get_stream(bus, params->stream, 141 params->host_dma_id + 1); 142 if (!hstream) 143 return -EINVAL; 144 145 stream = stream_to_hdac_ext_stream(hstream); 146 snd_hdac_ext_stream_decouple(bus, stream, true); 147 148 format_val = snd_hdac_calc_stream_format(params->s_freq, 149 params->ch, params->format, params->host_bps, 0); 150 151 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n", 152 format_val, params->s_freq, params->ch, params->format); 153 154 snd_hdac_stream_reset(hdac_stream(stream)); 155 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val); 156 if (err < 0) 157 return err; 158 159 err = snd_hdac_stream_setup(hdac_stream(stream)); 160 if (err < 0) 161 return err; 162 163 hdac_stream(stream)->prepared = 1; 164 165 return 0; 166 } 167 168 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params) 169 { 170 struct hdac_bus *bus = dev_get_drvdata(dev); 171 unsigned int format_val; 172 struct hdac_stream *hstream; 173 struct hdac_ext_stream *stream; 174 struct hdac_ext_link *link; 175 unsigned char stream_tag; 176 177 hstream = snd_hdac_get_stream(bus, params->stream, 178 params->link_dma_id + 1); 179 if (!hstream) 180 return -EINVAL; 181 182 stream = stream_to_hdac_ext_stream(hstream); 183 snd_hdac_ext_stream_decouple(bus, stream, true); 184 format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch, 185 params->format, params->link_bps, 0); 186 187 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n", 188 format_val, params->s_freq, params->ch, params->format); 189 190 snd_hdac_ext_link_stream_reset(stream); 191 192 snd_hdac_ext_link_stream_setup(stream, format_val); 193 194 stream_tag = hstream->stream_tag; 195 if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) { 196 list_for_each_entry(link, &bus->hlink_list, list) { 197 if (link->index == params->link_index) 198 snd_hdac_ext_link_set_stream_id(link, 199 stream_tag); 200 } 201 } 202 203 stream->link_prepared = 1; 204 205 return 0; 206 } 207 208 static int skl_pcm_open(struct snd_pcm_substream *substream, 209 struct snd_soc_dai *dai) 210 { 211 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 212 struct hdac_ext_stream *stream; 213 struct snd_pcm_runtime *runtime = substream->runtime; 214 struct skl_dma_params *dma_params; 215 struct skl *skl = get_skl_ctx(dai->dev); 216 struct skl_module_cfg *mconfig; 217 218 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 219 220 stream = snd_hdac_ext_stream_assign(bus, substream, 221 skl_get_host_stream_type(bus)); 222 if (stream == NULL) 223 return -EBUSY; 224 225 skl_set_pcm_constrains(bus, runtime); 226 227 /* 228 * disable WALLCLOCK timestamps for capture streams 229 * until we figure out how to handle digital inputs 230 */ 231 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 232 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */ 233 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME; 234 } 235 236 runtime->private_data = stream; 237 238 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL); 239 if (!dma_params) 240 return -ENOMEM; 241 242 dma_params->stream_tag = hdac_stream(stream)->stream_tag; 243 snd_soc_dai_set_dma_data(dai, substream, dma_params); 244 245 dev_dbg(dai->dev, "stream tag set in dma params=%d\n", 246 dma_params->stream_tag); 247 skl_set_suspend_active(substream, dai, true); 248 snd_pcm_set_sync(substream); 249 250 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 251 if (!mconfig) 252 return -EINVAL; 253 254 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps); 255 256 return 0; 257 } 258 259 static int skl_pcm_prepare(struct snd_pcm_substream *substream, 260 struct snd_soc_dai *dai) 261 { 262 struct skl *skl = get_skl_ctx(dai->dev); 263 struct skl_module_cfg *mconfig; 264 int ret; 265 266 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 267 268 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 269 270 /* 271 * In case of XRUN recovery or in the case when the application 272 * calls prepare another time, reset the FW pipe to clean state 273 */ 274 if (mconfig && 275 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN || 276 mconfig->pipe->state == SKL_PIPE_CREATED || 277 mconfig->pipe->state == SKL_PIPE_PAUSED)) { 278 279 ret = skl_reset_pipe(skl->skl_sst, mconfig->pipe); 280 281 if (ret < 0) 282 return ret; 283 284 ret = skl_pcm_host_dma_prepare(dai->dev, 285 mconfig->pipe->p_params); 286 if (ret < 0) 287 return ret; 288 } 289 290 return 0; 291 } 292 293 static int skl_pcm_hw_params(struct snd_pcm_substream *substream, 294 struct snd_pcm_hw_params *params, 295 struct snd_soc_dai *dai) 296 { 297 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 298 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 299 struct snd_pcm_runtime *runtime = substream->runtime; 300 struct skl_pipe_params p_params = {0}; 301 struct skl_module_cfg *m_cfg; 302 int ret, dma_id; 303 304 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 305 ret = skl_substream_alloc_pages(bus, substream, 306 params_buffer_bytes(params)); 307 if (ret < 0) 308 return ret; 309 310 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n", 311 runtime->rate, runtime->channels, runtime->format); 312 313 dma_id = hdac_stream(stream)->stream_tag - 1; 314 dev_dbg(dai->dev, "dma_id=%d\n", dma_id); 315 316 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 317 p_params.ch = params_channels(params); 318 p_params.s_freq = params_rate(params); 319 p_params.host_dma_id = dma_id; 320 p_params.stream = substream->stream; 321 p_params.format = params_format(params); 322 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 323 p_params.host_bps = dai->driver->playback.sig_bits; 324 else 325 p_params.host_bps = dai->driver->capture.sig_bits; 326 327 328 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream); 329 if (m_cfg) 330 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params); 331 332 return 0; 333 } 334 335 static void skl_pcm_close(struct snd_pcm_substream *substream, 336 struct snd_soc_dai *dai) 337 { 338 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 339 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 340 struct skl_dma_params *dma_params = NULL; 341 struct skl *skl = bus_to_skl(bus); 342 struct skl_module_cfg *mconfig; 343 344 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 345 346 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus)); 347 348 dma_params = snd_soc_dai_get_dma_data(dai, substream); 349 /* 350 * now we should set this to NULL as we are freeing by the 351 * dma_params 352 */ 353 snd_soc_dai_set_dma_data(dai, substream, NULL); 354 skl_set_suspend_active(substream, dai, false); 355 356 /* 357 * check if close is for "Reference Pin" and set back the 358 * CGCTL.MISCBDCGE if disabled by driver 359 */ 360 if (!strncmp(dai->name, "Reference Pin", 13) && 361 skl->skl_sst->miscbdcg_disabled) { 362 skl->skl_sst->enable_miscbdcge(dai->dev, true); 363 skl->skl_sst->miscbdcg_disabled = false; 364 } 365 366 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 367 if (mconfig) 368 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps); 369 370 kfree(dma_params); 371 } 372 373 static int skl_pcm_hw_free(struct snd_pcm_substream *substream, 374 struct snd_soc_dai *dai) 375 { 376 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 377 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 378 struct skl *skl = get_skl_ctx(dai->dev); 379 struct skl_module_cfg *mconfig; 380 int ret; 381 382 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 383 384 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 385 386 if (mconfig) { 387 ret = skl_reset_pipe(skl->skl_sst, mconfig->pipe); 388 if (ret < 0) 389 dev_err(dai->dev, "%s:Reset failed ret =%d", 390 __func__, ret); 391 } 392 393 snd_hdac_stream_cleanup(hdac_stream(stream)); 394 hdac_stream(stream)->prepared = 0; 395 396 return skl_substream_free_pages(bus, substream); 397 } 398 399 static int skl_be_hw_params(struct snd_pcm_substream *substream, 400 struct snd_pcm_hw_params *params, 401 struct snd_soc_dai *dai) 402 { 403 struct skl_pipe_params p_params = {0}; 404 405 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 406 p_params.ch = params_channels(params); 407 p_params.s_freq = params_rate(params); 408 p_params.stream = substream->stream; 409 410 return skl_tplg_be_update_params(dai, &p_params); 411 } 412 413 static int skl_decoupled_trigger(struct snd_pcm_substream *substream, 414 int cmd) 415 { 416 struct hdac_bus *bus = get_bus_ctx(substream); 417 struct hdac_ext_stream *stream; 418 int start; 419 unsigned long cookie; 420 struct hdac_stream *hstr; 421 422 stream = get_hdac_ext_stream(substream); 423 hstr = hdac_stream(stream); 424 425 if (!hstr->prepared) 426 return -EPIPE; 427 428 switch (cmd) { 429 case SNDRV_PCM_TRIGGER_START: 430 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 431 case SNDRV_PCM_TRIGGER_RESUME: 432 start = 1; 433 break; 434 435 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 436 case SNDRV_PCM_TRIGGER_SUSPEND: 437 case SNDRV_PCM_TRIGGER_STOP: 438 start = 0; 439 break; 440 441 default: 442 return -EINVAL; 443 } 444 445 spin_lock_irqsave(&bus->reg_lock, cookie); 446 447 if (start) { 448 snd_hdac_stream_start(hdac_stream(stream), true); 449 snd_hdac_stream_timecounter_init(hstr, 0); 450 } else { 451 snd_hdac_stream_stop(hdac_stream(stream)); 452 } 453 454 spin_unlock_irqrestore(&bus->reg_lock, cookie); 455 456 return 0; 457 } 458 459 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 460 struct snd_soc_dai *dai) 461 { 462 struct skl *skl = get_skl_ctx(dai->dev); 463 struct skl_sst *ctx = skl->skl_sst; 464 struct skl_module_cfg *mconfig; 465 struct hdac_bus *bus = get_bus_ctx(substream); 466 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 467 struct snd_soc_dapm_widget *w; 468 int ret; 469 470 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 471 if (!mconfig) 472 return -EIO; 473 474 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 475 w = dai->playback_widget; 476 else 477 w = dai->capture_widget; 478 479 switch (cmd) { 480 case SNDRV_PCM_TRIGGER_RESUME: 481 if (!w->ignore_suspend) { 482 /* 483 * enable DMA Resume enable bit for the stream, set the 484 * dpib & lpib position to resume before starting the 485 * DMA 486 */ 487 snd_hdac_ext_stream_drsm_enable(bus, true, 488 hdac_stream(stream)->index); 489 snd_hdac_ext_stream_set_dpibr(bus, stream, 490 stream->lpib); 491 snd_hdac_ext_stream_set_lpib(stream, stream->lpib); 492 } 493 /* fall through */ 494 495 case SNDRV_PCM_TRIGGER_START: 496 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 497 /* 498 * Start HOST DMA and Start FE Pipe.This is to make sure that 499 * there are no underrun/overrun in the case when the FE 500 * pipeline is started but there is a delay in starting the 501 * DMA channel on the host. 502 */ 503 ret = skl_decoupled_trigger(substream, cmd); 504 if (ret < 0) 505 return ret; 506 return skl_run_pipe(ctx, mconfig->pipe); 507 break; 508 509 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 510 case SNDRV_PCM_TRIGGER_SUSPEND: 511 case SNDRV_PCM_TRIGGER_STOP: 512 /* 513 * Stop FE Pipe first and stop DMA. This is to make sure that 514 * there are no underrun/overrun in the case if there is a delay 515 * between the two operations. 516 */ 517 ret = skl_stop_pipe(ctx, mconfig->pipe); 518 if (ret < 0) 519 return ret; 520 521 ret = skl_decoupled_trigger(substream, cmd); 522 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) { 523 /* save the dpib and lpib positions */ 524 stream->dpib = readl(bus->remap_addr + 525 AZX_REG_VS_SDXDPIB_XBASE + 526 (AZX_REG_VS_SDXDPIB_XINTERVAL * 527 hdac_stream(stream)->index)); 528 529 stream->lpib = snd_hdac_stream_get_pos_lpib( 530 hdac_stream(stream)); 531 snd_hdac_ext_stream_decouple(bus, stream, false); 532 } 533 break; 534 535 default: 536 return -EINVAL; 537 } 538 539 return 0; 540 } 541 542 543 static int skl_link_hw_params(struct snd_pcm_substream *substream, 544 struct snd_pcm_hw_params *params, 545 struct snd_soc_dai *dai) 546 { 547 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 548 struct hdac_ext_stream *link_dev; 549 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 550 struct snd_soc_dai *codec_dai = rtd->codec_dai; 551 struct skl_pipe_params p_params = {0}; 552 struct hdac_ext_link *link; 553 int stream_tag; 554 555 link_dev = snd_hdac_ext_stream_assign(bus, substream, 556 HDAC_EXT_STREAM_TYPE_LINK); 557 if (!link_dev) 558 return -EBUSY; 559 560 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev); 561 562 link = snd_hdac_ext_bus_get_link(bus, codec_dai->component->name); 563 if (!link) 564 return -EINVAL; 565 566 stream_tag = hdac_stream(link_dev)->stream_tag; 567 568 /* set the stream tag in the codec dai dma params */ 569 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 570 snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0); 571 else 572 snd_soc_dai_set_tdm_slot(codec_dai, 0, stream_tag, 0, 0); 573 574 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 575 p_params.ch = params_channels(params); 576 p_params.s_freq = params_rate(params); 577 p_params.stream = substream->stream; 578 p_params.link_dma_id = stream_tag - 1; 579 p_params.link_index = link->index; 580 p_params.format = params_format(params); 581 582 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 583 p_params.link_bps = codec_dai->driver->playback.sig_bits; 584 else 585 p_params.link_bps = codec_dai->driver->capture.sig_bits; 586 587 return skl_tplg_be_update_params(dai, &p_params); 588 } 589 590 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream, 591 struct snd_soc_dai *dai) 592 { 593 struct skl *skl = get_skl_ctx(dai->dev); 594 struct skl_module_cfg *mconfig = NULL; 595 596 /* In case of XRUN recovery, reset the FW pipe to clean state */ 597 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream); 598 if (mconfig && !mconfig->pipe->passthru && 599 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN)) 600 skl_reset_pipe(skl->skl_sst, mconfig->pipe); 601 602 return 0; 603 } 604 605 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream, 606 int cmd, struct snd_soc_dai *dai) 607 { 608 struct hdac_ext_stream *link_dev = 609 snd_soc_dai_get_dma_data(dai, substream); 610 struct hdac_bus *bus = get_bus_ctx(substream); 611 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 612 613 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd); 614 switch (cmd) { 615 case SNDRV_PCM_TRIGGER_RESUME: 616 case SNDRV_PCM_TRIGGER_START: 617 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 618 snd_hdac_ext_link_stream_start(link_dev); 619 break; 620 621 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 622 case SNDRV_PCM_TRIGGER_SUSPEND: 623 case SNDRV_PCM_TRIGGER_STOP: 624 snd_hdac_ext_link_stream_clear(link_dev); 625 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND) 626 snd_hdac_ext_stream_decouple(bus, stream, false); 627 break; 628 629 default: 630 return -EINVAL; 631 } 632 return 0; 633 } 634 635 static int skl_link_hw_free(struct snd_pcm_substream *substream, 636 struct snd_soc_dai *dai) 637 { 638 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 639 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 640 struct hdac_ext_stream *link_dev = 641 snd_soc_dai_get_dma_data(dai, substream); 642 struct hdac_ext_link *link; 643 unsigned char stream_tag; 644 645 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 646 647 link_dev->link_prepared = 0; 648 649 link = snd_hdac_ext_bus_get_link(bus, rtd->codec_dai->component->name); 650 if (!link) 651 return -EINVAL; 652 653 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 654 stream_tag = hdac_stream(link_dev)->stream_tag; 655 snd_hdac_ext_link_clear_stream_id(link, stream_tag); 656 } 657 658 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK); 659 return 0; 660 } 661 662 static const struct snd_soc_dai_ops skl_pcm_dai_ops = { 663 .startup = skl_pcm_open, 664 .shutdown = skl_pcm_close, 665 .prepare = skl_pcm_prepare, 666 .hw_params = skl_pcm_hw_params, 667 .hw_free = skl_pcm_hw_free, 668 .trigger = skl_pcm_trigger, 669 }; 670 671 static const struct snd_soc_dai_ops skl_dmic_dai_ops = { 672 .hw_params = skl_be_hw_params, 673 }; 674 675 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = { 676 .hw_params = skl_be_hw_params, 677 }; 678 679 static const struct snd_soc_dai_ops skl_link_dai_ops = { 680 .prepare = skl_link_pcm_prepare, 681 .hw_params = skl_link_hw_params, 682 .hw_free = skl_link_hw_free, 683 .trigger = skl_link_pcm_trigger, 684 }; 685 686 static struct snd_soc_dai_driver skl_fe_dai[] = { 687 { 688 .name = "System Pin", 689 .ops = &skl_pcm_dai_ops, 690 .playback = { 691 .stream_name = "System Playback", 692 .channels_min = HDA_MONO, 693 .channels_max = HDA_STEREO, 694 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000, 695 .formats = SNDRV_PCM_FMTBIT_S16_LE | 696 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 697 .sig_bits = 32, 698 }, 699 .capture = { 700 .stream_name = "System Capture", 701 .channels_min = HDA_MONO, 702 .channels_max = HDA_STEREO, 703 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 704 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 705 .sig_bits = 32, 706 }, 707 }, 708 { 709 .name = "System Pin2", 710 .ops = &skl_pcm_dai_ops, 711 .playback = { 712 .stream_name = "Headset Playback", 713 .channels_min = HDA_MONO, 714 .channels_max = HDA_STEREO, 715 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 716 SNDRV_PCM_RATE_8000, 717 .formats = SNDRV_PCM_FMTBIT_S16_LE | 718 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 719 }, 720 }, 721 { 722 .name = "Echoref Pin", 723 .ops = &skl_pcm_dai_ops, 724 .capture = { 725 .stream_name = "Echoreference Capture", 726 .channels_min = HDA_STEREO, 727 .channels_max = HDA_STEREO, 728 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 729 SNDRV_PCM_RATE_8000, 730 .formats = SNDRV_PCM_FMTBIT_S16_LE | 731 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 732 }, 733 }, 734 { 735 .name = "Reference Pin", 736 .ops = &skl_pcm_dai_ops, 737 .capture = { 738 .stream_name = "Reference Capture", 739 .channels_min = HDA_MONO, 740 .channels_max = HDA_QUAD, 741 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 742 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 743 .sig_bits = 32, 744 }, 745 }, 746 { 747 .name = "Deepbuffer Pin", 748 .ops = &skl_pcm_dai_ops, 749 .playback = { 750 .stream_name = "Deepbuffer Playback", 751 .channels_min = HDA_STEREO, 752 .channels_max = HDA_STEREO, 753 .rates = SNDRV_PCM_RATE_48000, 754 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 755 .sig_bits = 32, 756 }, 757 }, 758 { 759 .name = "LowLatency Pin", 760 .ops = &skl_pcm_dai_ops, 761 .playback = { 762 .stream_name = "Low Latency Playback", 763 .channels_min = HDA_STEREO, 764 .channels_max = HDA_STEREO, 765 .rates = SNDRV_PCM_RATE_48000, 766 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 767 .sig_bits = 32, 768 }, 769 }, 770 { 771 .name = "DMIC Pin", 772 .ops = &skl_pcm_dai_ops, 773 .capture = { 774 .stream_name = "DMIC Capture", 775 .channels_min = HDA_MONO, 776 .channels_max = HDA_QUAD, 777 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 778 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 779 .sig_bits = 32, 780 }, 781 }, 782 { 783 .name = "HDMI1 Pin", 784 .ops = &skl_pcm_dai_ops, 785 .playback = { 786 .stream_name = "HDMI1 Playback", 787 .channels_min = HDA_STEREO, 788 .channels_max = 8, 789 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 790 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 791 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 792 SNDRV_PCM_RATE_192000, 793 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 794 SNDRV_PCM_FMTBIT_S32_LE, 795 .sig_bits = 32, 796 }, 797 }, 798 { 799 .name = "HDMI2 Pin", 800 .ops = &skl_pcm_dai_ops, 801 .playback = { 802 .stream_name = "HDMI2 Playback", 803 .channels_min = HDA_STEREO, 804 .channels_max = 8, 805 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 806 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 807 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 808 SNDRV_PCM_RATE_192000, 809 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 810 SNDRV_PCM_FMTBIT_S32_LE, 811 .sig_bits = 32, 812 }, 813 }, 814 { 815 .name = "HDMI3 Pin", 816 .ops = &skl_pcm_dai_ops, 817 .playback = { 818 .stream_name = "HDMI3 Playback", 819 .channels_min = HDA_STEREO, 820 .channels_max = 8, 821 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 822 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 823 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 824 SNDRV_PCM_RATE_192000, 825 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 826 SNDRV_PCM_FMTBIT_S32_LE, 827 .sig_bits = 32, 828 }, 829 }, 830 }; 831 832 /* BE CPU Dais */ 833 static struct snd_soc_dai_driver skl_platform_dai[] = { 834 { 835 .name = "SSP0 Pin", 836 .ops = &skl_be_ssp_dai_ops, 837 .playback = { 838 .stream_name = "ssp0 Tx", 839 .channels_min = HDA_STEREO, 840 .channels_max = HDA_STEREO, 841 .rates = SNDRV_PCM_RATE_48000, 842 .formats = SNDRV_PCM_FMTBIT_S16_LE, 843 }, 844 .capture = { 845 .stream_name = "ssp0 Rx", 846 .channels_min = HDA_STEREO, 847 .channels_max = HDA_STEREO, 848 .rates = SNDRV_PCM_RATE_48000, 849 .formats = SNDRV_PCM_FMTBIT_S16_LE, 850 }, 851 }, 852 { 853 .name = "SSP1 Pin", 854 .ops = &skl_be_ssp_dai_ops, 855 .playback = { 856 .stream_name = "ssp1 Tx", 857 .channels_min = HDA_STEREO, 858 .channels_max = HDA_STEREO, 859 .rates = SNDRV_PCM_RATE_48000, 860 .formats = SNDRV_PCM_FMTBIT_S16_LE, 861 }, 862 .capture = { 863 .stream_name = "ssp1 Rx", 864 .channels_min = HDA_STEREO, 865 .channels_max = HDA_STEREO, 866 .rates = SNDRV_PCM_RATE_48000, 867 .formats = SNDRV_PCM_FMTBIT_S16_LE, 868 }, 869 }, 870 { 871 .name = "SSP2 Pin", 872 .ops = &skl_be_ssp_dai_ops, 873 .playback = { 874 .stream_name = "ssp2 Tx", 875 .channels_min = HDA_STEREO, 876 .channels_max = HDA_STEREO, 877 .rates = SNDRV_PCM_RATE_48000, 878 .formats = SNDRV_PCM_FMTBIT_S16_LE, 879 }, 880 .capture = { 881 .stream_name = "ssp2 Rx", 882 .channels_min = HDA_STEREO, 883 .channels_max = HDA_STEREO, 884 .rates = SNDRV_PCM_RATE_48000, 885 .formats = SNDRV_PCM_FMTBIT_S16_LE, 886 }, 887 }, 888 { 889 .name = "SSP3 Pin", 890 .ops = &skl_be_ssp_dai_ops, 891 .playback = { 892 .stream_name = "ssp3 Tx", 893 .channels_min = HDA_STEREO, 894 .channels_max = HDA_STEREO, 895 .rates = SNDRV_PCM_RATE_48000, 896 .formats = SNDRV_PCM_FMTBIT_S16_LE, 897 }, 898 .capture = { 899 .stream_name = "ssp3 Rx", 900 .channels_min = HDA_STEREO, 901 .channels_max = HDA_STEREO, 902 .rates = SNDRV_PCM_RATE_48000, 903 .formats = SNDRV_PCM_FMTBIT_S16_LE, 904 }, 905 }, 906 { 907 .name = "SSP4 Pin", 908 .ops = &skl_be_ssp_dai_ops, 909 .playback = { 910 .stream_name = "ssp4 Tx", 911 .channels_min = HDA_STEREO, 912 .channels_max = HDA_STEREO, 913 .rates = SNDRV_PCM_RATE_48000, 914 .formats = SNDRV_PCM_FMTBIT_S16_LE, 915 }, 916 .capture = { 917 .stream_name = "ssp4 Rx", 918 .channels_min = HDA_STEREO, 919 .channels_max = HDA_STEREO, 920 .rates = SNDRV_PCM_RATE_48000, 921 .formats = SNDRV_PCM_FMTBIT_S16_LE, 922 }, 923 }, 924 { 925 .name = "SSP5 Pin", 926 .ops = &skl_be_ssp_dai_ops, 927 .playback = { 928 .stream_name = "ssp5 Tx", 929 .channels_min = HDA_STEREO, 930 .channels_max = HDA_STEREO, 931 .rates = SNDRV_PCM_RATE_48000, 932 .formats = SNDRV_PCM_FMTBIT_S16_LE, 933 }, 934 .capture = { 935 .stream_name = "ssp5 Rx", 936 .channels_min = HDA_STEREO, 937 .channels_max = HDA_STEREO, 938 .rates = SNDRV_PCM_RATE_48000, 939 .formats = SNDRV_PCM_FMTBIT_S16_LE, 940 }, 941 }, 942 { 943 .name = "iDisp1 Pin", 944 .ops = &skl_link_dai_ops, 945 .playback = { 946 .stream_name = "iDisp1 Tx", 947 .channels_min = HDA_STEREO, 948 .channels_max = 8, 949 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000, 950 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 951 SNDRV_PCM_FMTBIT_S24_LE, 952 }, 953 }, 954 { 955 .name = "iDisp2 Pin", 956 .ops = &skl_link_dai_ops, 957 .playback = { 958 .stream_name = "iDisp2 Tx", 959 .channels_min = HDA_STEREO, 960 .channels_max = 8, 961 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| 962 SNDRV_PCM_RATE_48000, 963 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 964 SNDRV_PCM_FMTBIT_S24_LE, 965 }, 966 }, 967 { 968 .name = "iDisp3 Pin", 969 .ops = &skl_link_dai_ops, 970 .playback = { 971 .stream_name = "iDisp3 Tx", 972 .channels_min = HDA_STEREO, 973 .channels_max = 8, 974 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| 975 SNDRV_PCM_RATE_48000, 976 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 977 SNDRV_PCM_FMTBIT_S24_LE, 978 }, 979 }, 980 { 981 .name = "DMIC01 Pin", 982 .ops = &skl_dmic_dai_ops, 983 .capture = { 984 .stream_name = "DMIC01 Rx", 985 .channels_min = HDA_MONO, 986 .channels_max = HDA_QUAD, 987 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 988 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 989 }, 990 }, 991 { 992 .name = "DMIC16k Pin", 993 .ops = &skl_dmic_dai_ops, 994 .capture = { 995 .stream_name = "DMIC16k Rx", 996 .channels_min = HDA_MONO, 997 .channels_max = HDA_QUAD, 998 .rates = SNDRV_PCM_RATE_16000, 999 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1000 }, 1001 }, 1002 { 1003 .name = "Analog CPU DAI", 1004 .ops = &skl_link_dai_ops, 1005 .playback = { 1006 .stream_name = "Analog CPU Playback", 1007 .channels_min = HDA_MONO, 1008 .channels_max = HDA_MAX, 1009 .rates = SNDRV_PCM_RATE_8000_192000, 1010 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1011 SNDRV_PCM_FMTBIT_S32_LE, 1012 }, 1013 .capture = { 1014 .stream_name = "Analog CPU Capture", 1015 .channels_min = HDA_MONO, 1016 .channels_max = HDA_MAX, 1017 .rates = SNDRV_PCM_RATE_8000_192000, 1018 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1019 SNDRV_PCM_FMTBIT_S32_LE, 1020 }, 1021 }, 1022 { 1023 .name = "Alt Analog CPU DAI", 1024 .ops = &skl_link_dai_ops, 1025 .playback = { 1026 .stream_name = "Alt Analog CPU Playback", 1027 .channels_min = HDA_MONO, 1028 .channels_max = HDA_MAX, 1029 .rates = SNDRV_PCM_RATE_8000_192000, 1030 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1031 SNDRV_PCM_FMTBIT_S32_LE, 1032 }, 1033 .capture = { 1034 .stream_name = "Alt Analog CPU Capture", 1035 .channels_min = HDA_MONO, 1036 .channels_max = HDA_MAX, 1037 .rates = SNDRV_PCM_RATE_8000_192000, 1038 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1039 SNDRV_PCM_FMTBIT_S32_LE, 1040 }, 1041 }, 1042 { 1043 .name = "Digital CPU DAI", 1044 .ops = &skl_link_dai_ops, 1045 .playback = { 1046 .stream_name = "Digital CPU Playback", 1047 .channels_min = HDA_MONO, 1048 .channels_max = HDA_MAX, 1049 .rates = SNDRV_PCM_RATE_8000_192000, 1050 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1051 SNDRV_PCM_FMTBIT_S32_LE, 1052 }, 1053 .capture = { 1054 .stream_name = "Digital CPU Capture", 1055 .channels_min = HDA_MONO, 1056 .channels_max = HDA_MAX, 1057 .rates = SNDRV_PCM_RATE_8000_192000, 1058 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1059 SNDRV_PCM_FMTBIT_S32_LE, 1060 }, 1061 }, 1062 }; 1063 1064 int skl_dai_load(struct snd_soc_component *cmp, int index, 1065 struct snd_soc_dai_driver *dai_drv, 1066 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai) 1067 { 1068 dai_drv->ops = &skl_pcm_dai_ops; 1069 1070 return 0; 1071 } 1072 1073 static int skl_platform_open(struct snd_pcm_substream *substream) 1074 { 1075 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1076 struct snd_soc_dai_link *dai_link = rtd->dai_link; 1077 1078 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__, 1079 dai_link->cpu_dai_name); 1080 1081 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw); 1082 1083 return 0; 1084 } 1085 1086 static int skl_coupled_trigger(struct snd_pcm_substream *substream, 1087 int cmd) 1088 { 1089 struct hdac_bus *bus = get_bus_ctx(substream); 1090 struct hdac_ext_stream *stream; 1091 struct snd_pcm_substream *s; 1092 bool start; 1093 int sbits = 0; 1094 unsigned long cookie; 1095 struct hdac_stream *hstr; 1096 1097 stream = get_hdac_ext_stream(substream); 1098 hstr = hdac_stream(stream); 1099 1100 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd); 1101 1102 if (!hstr->prepared) 1103 return -EPIPE; 1104 1105 switch (cmd) { 1106 case SNDRV_PCM_TRIGGER_START: 1107 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1108 case SNDRV_PCM_TRIGGER_RESUME: 1109 start = true; 1110 break; 1111 1112 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1113 case SNDRV_PCM_TRIGGER_SUSPEND: 1114 case SNDRV_PCM_TRIGGER_STOP: 1115 start = false; 1116 break; 1117 1118 default: 1119 return -EINVAL; 1120 } 1121 1122 snd_pcm_group_for_each_entry(s, substream) { 1123 if (s->pcm->card != substream->pcm->card) 1124 continue; 1125 stream = get_hdac_ext_stream(s); 1126 sbits |= 1 << hdac_stream(stream)->index; 1127 snd_pcm_trigger_done(s, substream); 1128 } 1129 1130 spin_lock_irqsave(&bus->reg_lock, cookie); 1131 1132 /* first, set SYNC bits of corresponding streams */ 1133 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC); 1134 1135 snd_pcm_group_for_each_entry(s, substream) { 1136 if (s->pcm->card != substream->pcm->card) 1137 continue; 1138 stream = get_hdac_ext_stream(s); 1139 if (start) 1140 snd_hdac_stream_start(hdac_stream(stream), true); 1141 else 1142 snd_hdac_stream_stop(hdac_stream(stream)); 1143 } 1144 spin_unlock_irqrestore(&bus->reg_lock, cookie); 1145 1146 snd_hdac_stream_sync(hstr, start, sbits); 1147 1148 spin_lock_irqsave(&bus->reg_lock, cookie); 1149 1150 /* reset SYNC bits */ 1151 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC); 1152 if (start) 1153 snd_hdac_stream_timecounter_init(hstr, sbits); 1154 spin_unlock_irqrestore(&bus->reg_lock, cookie); 1155 1156 return 0; 1157 } 1158 1159 static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream, 1160 int cmd) 1161 { 1162 struct hdac_bus *bus = get_bus_ctx(substream); 1163 1164 if (!bus->ppcap) 1165 return skl_coupled_trigger(substream, cmd); 1166 1167 return 0; 1168 } 1169 1170 static snd_pcm_uframes_t skl_platform_pcm_pointer 1171 (struct snd_pcm_substream *substream) 1172 { 1173 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream); 1174 struct hdac_bus *bus = get_bus_ctx(substream); 1175 unsigned int pos; 1176 1177 /* 1178 * Use DPIB for Playback stream as the periodic DMA Position-in- 1179 * Buffer Writes may be scheduled at the same time or later than 1180 * the MSI and does not guarantee to reflect the Position of the 1181 * last buffer that was transferred. Whereas DPIB register in 1182 * HAD space reflects the actual data that is transferred. 1183 * Use the position buffer for capture, as DPIB write gets 1184 * completed earlier than the actual data written to the DDR. 1185 * 1186 * For capture stream following workaround is required to fix the 1187 * incorrect position reporting. 1188 * 1189 * 1. Wait for 20us before reading the DMA position in buffer once 1190 * the interrupt is generated for stream completion as update happens 1191 * on the HDA frame boundary i.e. 20.833uSec. 1192 * 2. Read DPIB register to flush the DMA position value. This dummy 1193 * read is required to flush DMA position value. 1194 * 3. Read the DMA Position-in-Buffer. This value now will be equal to 1195 * or greater than period boundary. 1196 */ 1197 1198 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1199 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE + 1200 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1201 hdac_stream(hstream)->index)); 1202 } else { 1203 udelay(20); 1204 readl(bus->remap_addr + 1205 AZX_REG_VS_SDXDPIB_XBASE + 1206 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1207 hdac_stream(hstream)->index)); 1208 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream)); 1209 } 1210 1211 if (pos >= hdac_stream(hstream)->bufsize) 1212 pos = 0; 1213 1214 return bytes_to_frames(substream->runtime, pos); 1215 } 1216 1217 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream, 1218 u64 nsec) 1219 { 1220 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 1221 struct snd_soc_dai *codec_dai = rtd->codec_dai; 1222 u64 codec_frames, codec_nsecs; 1223 1224 if (!codec_dai->driver->ops->delay) 1225 return nsec; 1226 1227 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai); 1228 codec_nsecs = div_u64(codec_frames * 1000000000LL, 1229 substream->runtime->rate); 1230 1231 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 1232 return nsec + codec_nsecs; 1233 1234 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; 1235 } 1236 1237 static int skl_get_time_info(struct snd_pcm_substream *substream, 1238 struct timespec *system_ts, struct timespec *audio_ts, 1239 struct snd_pcm_audio_tstamp_config *audio_tstamp_config, 1240 struct snd_pcm_audio_tstamp_report *audio_tstamp_report) 1241 { 1242 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream); 1243 struct hdac_stream *hstr = hdac_stream(sstream); 1244 u64 nsec; 1245 1246 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && 1247 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) { 1248 1249 snd_pcm_gettime(substream->runtime, system_ts); 1250 1251 nsec = timecounter_read(&hstr->tc); 1252 nsec = div_u64(nsec, 3); /* can be optimized */ 1253 if (audio_tstamp_config->report_delay) 1254 nsec = skl_adjust_codec_delay(substream, nsec); 1255 1256 *audio_ts = ns_to_timespec(nsec); 1257 1258 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK; 1259 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */ 1260 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */ 1261 1262 } else { 1263 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; 1264 } 1265 1266 return 0; 1267 } 1268 1269 static const struct snd_pcm_ops skl_platform_ops = { 1270 .open = skl_platform_open, 1271 .ioctl = snd_pcm_lib_ioctl, 1272 .trigger = skl_platform_pcm_trigger, 1273 .pointer = skl_platform_pcm_pointer, 1274 .get_time_info = skl_get_time_info, 1275 .mmap = snd_pcm_lib_default_mmap, 1276 .page = snd_pcm_sgbuf_ops_page, 1277 }; 1278 1279 static void skl_pcm_free(struct snd_pcm *pcm) 1280 { 1281 snd_pcm_lib_preallocate_free_for_all(pcm); 1282 } 1283 1284 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) 1285 1286 static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd) 1287 { 1288 struct snd_soc_dai *dai = rtd->cpu_dai; 1289 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 1290 struct snd_pcm *pcm = rtd->pcm; 1291 unsigned int size; 1292 struct skl *skl = bus_to_skl(bus); 1293 1294 if (dai->driver->playback.channels_min || 1295 dai->driver->capture.channels_min) { 1296 /* buffer pre-allocation */ 1297 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; 1298 if (size > MAX_PREALLOC_SIZE) 1299 size = MAX_PREALLOC_SIZE; 1300 snd_pcm_lib_preallocate_pages_for_all(pcm, 1301 SNDRV_DMA_TYPE_DEV_SG, 1302 snd_dma_pci_data(skl->pci), 1303 size, MAX_PREALLOC_SIZE); 1304 } 1305 1306 return 0; 1307 } 1308 1309 static int skl_get_module_info(struct skl *skl, struct skl_module_cfg *mconfig) 1310 { 1311 struct skl_sst *ctx = skl->skl_sst; 1312 struct skl_module_inst_id *pin_id; 1313 uuid_le *uuid_mod, *uuid_tplg; 1314 struct skl_module *skl_module; 1315 struct uuid_module *module; 1316 int i, ret = -EIO; 1317 1318 uuid_mod = (uuid_le *)mconfig->guid; 1319 1320 if (list_empty(&ctx->uuid_list)) { 1321 dev_err(ctx->dev, "Module list is empty\n"); 1322 return -EIO; 1323 } 1324 1325 list_for_each_entry(module, &ctx->uuid_list, list) { 1326 if (uuid_le_cmp(*uuid_mod, module->uuid) == 0) { 1327 mconfig->id.module_id = module->id; 1328 if (mconfig->module) 1329 mconfig->module->loadable = module->is_loadable; 1330 ret = 0; 1331 break; 1332 } 1333 } 1334 1335 if (ret) 1336 return ret; 1337 1338 uuid_mod = &module->uuid; 1339 ret = -EIO; 1340 for (i = 0; i < skl->nr_modules; i++) { 1341 skl_module = skl->modules[i]; 1342 uuid_tplg = &skl_module->uuid; 1343 if (!uuid_le_cmp(*uuid_mod, *uuid_tplg)) { 1344 mconfig->module = skl_module; 1345 ret = 0; 1346 break; 1347 } 1348 } 1349 if (skl->nr_modules && ret) 1350 return ret; 1351 1352 list_for_each_entry(module, &ctx->uuid_list, list) { 1353 for (i = 0; i < MAX_IN_QUEUE; i++) { 1354 pin_id = &mconfig->m_in_pin[i].id; 1355 if (!uuid_le_cmp(pin_id->mod_uuid, module->uuid)) 1356 pin_id->module_id = module->id; 1357 } 1358 1359 for (i = 0; i < MAX_OUT_QUEUE; i++) { 1360 pin_id = &mconfig->m_out_pin[i].id; 1361 if (!uuid_le_cmp(pin_id->mod_uuid, module->uuid)) 1362 pin_id->module_id = module->id; 1363 } 1364 } 1365 1366 return 0; 1367 } 1368 1369 static int skl_populate_modules(struct skl *skl) 1370 { 1371 struct skl_pipeline *p; 1372 struct skl_pipe_module *m; 1373 struct snd_soc_dapm_widget *w; 1374 struct skl_module_cfg *mconfig; 1375 int ret = 0; 1376 1377 list_for_each_entry(p, &skl->ppl_list, node) { 1378 list_for_each_entry(m, &p->pipe->w_list, node) { 1379 w = m->w; 1380 mconfig = w->priv; 1381 1382 ret = skl_get_module_info(skl, mconfig); 1383 if (ret < 0) { 1384 dev_err(skl->skl_sst->dev, 1385 "query module info failed\n"); 1386 return ret; 1387 } 1388 1389 skl_tplg_add_moduleid_in_bind_params(skl, w); 1390 } 1391 } 1392 1393 return ret; 1394 } 1395 1396 static int skl_platform_soc_probe(struct snd_soc_component *component) 1397 { 1398 struct hdac_bus *bus = dev_get_drvdata(component->dev); 1399 struct skl *skl = bus_to_skl(bus); 1400 const struct skl_dsp_ops *ops; 1401 int ret; 1402 1403 pm_runtime_get_sync(component->dev); 1404 if (bus->ppcap) { 1405 skl->component = component; 1406 1407 /* init debugfs */ 1408 skl->debugfs = skl_debugfs_init(skl); 1409 1410 ret = skl_tplg_init(component, bus); 1411 if (ret < 0) { 1412 dev_err(component->dev, "Failed to init topology!\n"); 1413 return ret; 1414 } 1415 1416 /* load the firmwares, since all is set */ 1417 ops = skl_get_dsp_ops(skl->pci->device); 1418 if (!ops) 1419 return -EIO; 1420 1421 if (!skl->skl_sst->is_first_boot) { 1422 dev_err(component->dev, "DSP reports first boot done!!!\n"); 1423 return -EIO; 1424 } 1425 1426 /* 1427 * Disable dynamic clock and power gating during firmware 1428 * and library download 1429 */ 1430 skl->skl_sst->enable_miscbdcge(component->dev, false); 1431 skl->skl_sst->clock_power_gating(component->dev, false); 1432 1433 ret = ops->init_fw(component->dev, skl->skl_sst); 1434 skl->skl_sst->enable_miscbdcge(component->dev, true); 1435 skl->skl_sst->clock_power_gating(component->dev, true); 1436 if (ret < 0) { 1437 dev_err(component->dev, "Failed to boot first fw: %d\n", ret); 1438 return ret; 1439 } 1440 skl_populate_modules(skl); 1441 skl->skl_sst->update_d0i3c = skl_update_d0i3c; 1442 skl_dsp_enable_notification(skl->skl_sst, false); 1443 1444 if (skl->cfg.astate_cfg != NULL) { 1445 skl_dsp_set_astate_cfg(skl->skl_sst, 1446 skl->cfg.astate_cfg->count, 1447 skl->cfg.astate_cfg); 1448 } 1449 } 1450 pm_runtime_mark_last_busy(component->dev); 1451 pm_runtime_put_autosuspend(component->dev); 1452 1453 return 0; 1454 } 1455 1456 static void skl_pcm_remove(struct snd_soc_component *component) 1457 { 1458 /* remove topology */ 1459 snd_soc_tplg_component_remove(component, SND_SOC_TPLG_INDEX_ALL); 1460 } 1461 1462 static const struct snd_soc_component_driver skl_component = { 1463 .name = "pcm", 1464 .probe = skl_platform_soc_probe, 1465 .remove = skl_pcm_remove, 1466 .ops = &skl_platform_ops, 1467 .pcm_new = skl_pcm_new, 1468 .pcm_free = skl_pcm_free, 1469 .module_get_upon_open = 1, /* increment refcount when a pcm is opened */ 1470 }; 1471 1472 int skl_platform_register(struct device *dev) 1473 { 1474 int ret; 1475 struct snd_soc_dai_driver *dais; 1476 int num_dais = ARRAY_SIZE(skl_platform_dai); 1477 struct hdac_bus *bus = dev_get_drvdata(dev); 1478 struct skl *skl = bus_to_skl(bus); 1479 1480 INIT_LIST_HEAD(&skl->ppl_list); 1481 INIT_LIST_HEAD(&skl->bind_list); 1482 1483 skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai), 1484 GFP_KERNEL); 1485 if (!skl->dais) { 1486 ret = -ENOMEM; 1487 goto err; 1488 } 1489 1490 if (!skl->use_tplg_pcm) { 1491 dais = krealloc(skl->dais, sizeof(skl_fe_dai) + 1492 sizeof(skl_platform_dai), GFP_KERNEL); 1493 if (!dais) { 1494 ret = -ENOMEM; 1495 goto err; 1496 } 1497 1498 skl->dais = dais; 1499 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai, 1500 sizeof(skl_fe_dai)); 1501 num_dais += ARRAY_SIZE(skl_fe_dai); 1502 } 1503 1504 ret = devm_snd_soc_register_component(dev, &skl_component, 1505 skl->dais, num_dais); 1506 if (ret) 1507 dev_err(dev, "soc component registration failed %d\n", ret); 1508 err: 1509 return ret; 1510 } 1511 1512 int skl_platform_unregister(struct device *dev) 1513 { 1514 struct hdac_bus *bus = dev_get_drvdata(dev); 1515 struct skl *skl = bus_to_skl(bus); 1516 struct skl_module_deferred_bind *modules, *tmp; 1517 1518 if (!list_empty(&skl->bind_list)) { 1519 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) { 1520 list_del(&modules->node); 1521 kfree(modules); 1522 } 1523 } 1524 1525 kfree(skl->dais); 1526 1527 return 0; 1528 } 1529