1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality 4 * 5 * Copyright (C) 2014-2015 Intel Corp 6 * Author: Jeeja KP <jeeja.kp@intel.com> 7 * 8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 9 * 10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 */ 12 13 #include <linux/pci.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/delay.h> 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 #include "skl.h" 19 #include "skl-topology.h" 20 #include "skl-sst-dsp.h" 21 #include "skl-sst-ipc.h" 22 23 #define HDA_MONO 1 24 #define HDA_STEREO 2 25 #define HDA_QUAD 4 26 #define HDA_MAX 8 27 28 static const struct snd_pcm_hardware azx_pcm_hw = { 29 .info = (SNDRV_PCM_INFO_MMAP | 30 SNDRV_PCM_INFO_INTERLEAVED | 31 SNDRV_PCM_INFO_BLOCK_TRANSFER | 32 SNDRV_PCM_INFO_MMAP_VALID | 33 SNDRV_PCM_INFO_PAUSE | 34 SNDRV_PCM_INFO_RESUME | 35 SNDRV_PCM_INFO_SYNC_START | 36 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */ 37 SNDRV_PCM_INFO_HAS_LINK_ATIME | 38 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 39 .formats = SNDRV_PCM_FMTBIT_S16_LE | 40 SNDRV_PCM_FMTBIT_S32_LE | 41 SNDRV_PCM_FMTBIT_S24_LE, 42 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 43 SNDRV_PCM_RATE_8000, 44 .rate_min = 8000, 45 .rate_max = 48000, 46 .channels_min = 1, 47 .channels_max = 8, 48 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 49 .period_bytes_min = 128, 50 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 51 .periods_min = 2, 52 .periods_max = AZX_MAX_FRAG, 53 .fifo_size = 0, 54 }; 55 56 static inline 57 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream) 58 { 59 return substream->runtime->private_data; 60 } 61 62 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream) 63 { 64 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 65 struct hdac_stream *hstream = hdac_stream(stream); 66 struct hdac_bus *bus = hstream->bus; 67 return bus; 68 } 69 70 static int skl_substream_alloc_pages(struct hdac_bus *bus, 71 struct snd_pcm_substream *substream, 72 size_t size) 73 { 74 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 75 76 hdac_stream(stream)->bufsize = 0; 77 hdac_stream(stream)->period_bytes = 0; 78 hdac_stream(stream)->format_val = 0; 79 80 return 0; 81 } 82 83 static void skl_set_pcm_constrains(struct hdac_bus *bus, 84 struct snd_pcm_runtime *runtime) 85 { 86 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 87 88 /* avoid wrap-around with wall-clock */ 89 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, 90 20, 178000000); 91 } 92 93 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus) 94 { 95 if (bus->ppcap) 96 return HDAC_EXT_STREAM_TYPE_HOST; 97 else 98 return HDAC_EXT_STREAM_TYPE_COUPLED; 99 } 100 101 /* 102 * check if the stream opened is marked as ignore_suspend by machine, if so 103 * then enable suspend_active refcount 104 * 105 * The count supend_active does not need lock as it is used in open/close 106 * and suspend context 107 */ 108 static void skl_set_suspend_active(struct snd_pcm_substream *substream, 109 struct snd_soc_dai *dai, bool enable) 110 { 111 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 112 struct snd_soc_dapm_widget *w; 113 struct skl_dev *skl = bus_to_skl(bus); 114 115 w = snd_soc_dai_get_widget(dai, substream->stream); 116 117 if (w->ignore_suspend && enable) 118 skl->supend_active++; 119 else if (w->ignore_suspend && !enable) 120 skl->supend_active--; 121 } 122 123 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params) 124 { 125 struct hdac_bus *bus = dev_get_drvdata(dev); 126 struct skl_dev *skl = bus_to_skl(bus); 127 unsigned int format_val; 128 struct hdac_stream *hstream; 129 struct hdac_ext_stream *stream; 130 int err; 131 132 hstream = snd_hdac_get_stream(bus, params->stream, 133 params->host_dma_id + 1); 134 if (!hstream) 135 return -EINVAL; 136 137 stream = stream_to_hdac_ext_stream(hstream); 138 snd_hdac_ext_stream_decouple(bus, stream, true); 139 140 format_val = snd_hdac_calc_stream_format(params->s_freq, 141 params->ch, params->format, params->host_bps, 0); 142 143 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n", 144 format_val, params->s_freq, params->ch, params->format); 145 146 snd_hdac_stream_reset(hdac_stream(stream)); 147 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val); 148 if (err < 0) 149 return err; 150 151 /* 152 * The recommended SDxFMT programming sequence for BXT 153 * platforms is to couple the stream before writing the format 154 */ 155 if (IS_BXT(skl->pci)) { 156 snd_hdac_ext_stream_decouple(bus, stream, false); 157 err = snd_hdac_stream_setup(hdac_stream(stream)); 158 snd_hdac_ext_stream_decouple(bus, stream, true); 159 } else { 160 err = snd_hdac_stream_setup(hdac_stream(stream)); 161 } 162 163 if (err < 0) 164 return err; 165 166 hdac_stream(stream)->prepared = 1; 167 168 return 0; 169 } 170 171 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params) 172 { 173 struct hdac_bus *bus = dev_get_drvdata(dev); 174 unsigned int format_val; 175 struct hdac_stream *hstream; 176 struct hdac_ext_stream *stream; 177 struct hdac_ext_link *link; 178 unsigned char stream_tag; 179 180 hstream = snd_hdac_get_stream(bus, params->stream, 181 params->link_dma_id + 1); 182 if (!hstream) 183 return -EINVAL; 184 185 stream = stream_to_hdac_ext_stream(hstream); 186 snd_hdac_ext_stream_decouple(bus, stream, true); 187 format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch, 188 params->format, params->link_bps, 0); 189 190 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n", 191 format_val, params->s_freq, params->ch, params->format); 192 193 snd_hdac_ext_link_stream_reset(stream); 194 195 snd_hdac_ext_link_stream_setup(stream, format_val); 196 197 stream_tag = hstream->stream_tag; 198 if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) { 199 list_for_each_entry(link, &bus->hlink_list, list) { 200 if (link->index == params->link_index) 201 snd_hdac_ext_link_set_stream_id(link, 202 stream_tag); 203 } 204 } 205 206 stream->link_prepared = 1; 207 208 return 0; 209 } 210 211 static int skl_pcm_open(struct snd_pcm_substream *substream, 212 struct snd_soc_dai *dai) 213 { 214 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 215 struct hdac_ext_stream *stream; 216 struct snd_pcm_runtime *runtime = substream->runtime; 217 struct skl_dma_params *dma_params; 218 struct skl_dev *skl = get_skl_ctx(dai->dev); 219 struct skl_module_cfg *mconfig; 220 221 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 222 223 stream = snd_hdac_ext_stream_assign(bus, substream, 224 skl_get_host_stream_type(bus)); 225 if (stream == NULL) 226 return -EBUSY; 227 228 skl_set_pcm_constrains(bus, runtime); 229 230 /* 231 * disable WALLCLOCK timestamps for capture streams 232 * until we figure out how to handle digital inputs 233 */ 234 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 235 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */ 236 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME; 237 } 238 239 runtime->private_data = stream; 240 241 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL); 242 if (!dma_params) 243 return -ENOMEM; 244 245 dma_params->stream_tag = hdac_stream(stream)->stream_tag; 246 snd_soc_dai_set_dma_data(dai, substream, dma_params); 247 248 dev_dbg(dai->dev, "stream tag set in dma params=%d\n", 249 dma_params->stream_tag); 250 skl_set_suspend_active(substream, dai, true); 251 snd_pcm_set_sync(substream); 252 253 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 254 if (!mconfig) 255 return -EINVAL; 256 257 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps); 258 259 return 0; 260 } 261 262 static int skl_pcm_prepare(struct snd_pcm_substream *substream, 263 struct snd_soc_dai *dai) 264 { 265 struct skl_dev *skl = get_skl_ctx(dai->dev); 266 struct skl_module_cfg *mconfig; 267 int ret; 268 269 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 270 271 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 272 273 /* 274 * In case of XRUN recovery or in the case when the application 275 * calls prepare another time, reset the FW pipe to clean state 276 */ 277 if (mconfig && 278 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN || 279 mconfig->pipe->state == SKL_PIPE_CREATED || 280 mconfig->pipe->state == SKL_PIPE_PAUSED)) { 281 282 ret = skl_reset_pipe(skl, mconfig->pipe); 283 284 if (ret < 0) 285 return ret; 286 287 ret = skl_pcm_host_dma_prepare(dai->dev, 288 mconfig->pipe->p_params); 289 if (ret < 0) 290 return ret; 291 } 292 293 return 0; 294 } 295 296 static int skl_pcm_hw_params(struct snd_pcm_substream *substream, 297 struct snd_pcm_hw_params *params, 298 struct snd_soc_dai *dai) 299 { 300 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 301 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 302 struct snd_pcm_runtime *runtime = substream->runtime; 303 struct skl_pipe_params p_params = {0}; 304 struct skl_module_cfg *m_cfg; 305 int ret, dma_id; 306 307 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 308 ret = skl_substream_alloc_pages(bus, substream, 309 params_buffer_bytes(params)); 310 if (ret < 0) 311 return ret; 312 313 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n", 314 runtime->rate, runtime->channels, runtime->format); 315 316 dma_id = hdac_stream(stream)->stream_tag - 1; 317 dev_dbg(dai->dev, "dma_id=%d\n", dma_id); 318 319 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 320 p_params.ch = params_channels(params); 321 p_params.s_freq = params_rate(params); 322 p_params.host_dma_id = dma_id; 323 p_params.stream = substream->stream; 324 p_params.format = params_format(params); 325 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 326 p_params.host_bps = dai->driver->playback.sig_bits; 327 else 328 p_params.host_bps = dai->driver->capture.sig_bits; 329 330 331 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream); 332 if (m_cfg) 333 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params); 334 335 return 0; 336 } 337 338 static void skl_pcm_close(struct snd_pcm_substream *substream, 339 struct snd_soc_dai *dai) 340 { 341 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 342 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 343 struct skl_dma_params *dma_params = NULL; 344 struct skl_dev *skl = bus_to_skl(bus); 345 struct skl_module_cfg *mconfig; 346 347 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 348 349 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus)); 350 351 dma_params = snd_soc_dai_get_dma_data(dai, substream); 352 /* 353 * now we should set this to NULL as we are freeing by the 354 * dma_params 355 */ 356 snd_soc_dai_set_dma_data(dai, substream, NULL); 357 skl_set_suspend_active(substream, dai, false); 358 359 /* 360 * check if close is for "Reference Pin" and set back the 361 * CGCTL.MISCBDCGE if disabled by driver 362 */ 363 if (!strncmp(dai->name, "Reference Pin", 13) && 364 skl->miscbdcg_disabled) { 365 skl->enable_miscbdcge(dai->dev, true); 366 skl->miscbdcg_disabled = false; 367 } 368 369 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 370 if (mconfig) 371 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps); 372 373 kfree(dma_params); 374 } 375 376 static int skl_pcm_hw_free(struct snd_pcm_substream *substream, 377 struct snd_soc_dai *dai) 378 { 379 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 380 struct skl_dev *skl = get_skl_ctx(dai->dev); 381 struct skl_module_cfg *mconfig; 382 int ret; 383 384 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 385 386 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 387 388 if (mconfig) { 389 ret = skl_reset_pipe(skl, mconfig->pipe); 390 if (ret < 0) 391 dev_err(dai->dev, "%s:Reset failed ret =%d", 392 __func__, ret); 393 } 394 395 snd_hdac_stream_cleanup(hdac_stream(stream)); 396 hdac_stream(stream)->prepared = 0; 397 398 return 0; 399 } 400 401 static int skl_be_hw_params(struct snd_pcm_substream *substream, 402 struct snd_pcm_hw_params *params, 403 struct snd_soc_dai *dai) 404 { 405 struct skl_pipe_params p_params = {0}; 406 407 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 408 p_params.ch = params_channels(params); 409 p_params.s_freq = params_rate(params); 410 p_params.stream = substream->stream; 411 412 return skl_tplg_be_update_params(dai, &p_params); 413 } 414 415 static int skl_decoupled_trigger(struct snd_pcm_substream *substream, 416 int cmd) 417 { 418 struct hdac_bus *bus = get_bus_ctx(substream); 419 struct hdac_ext_stream *stream; 420 int start; 421 unsigned long cookie; 422 struct hdac_stream *hstr; 423 424 stream = get_hdac_ext_stream(substream); 425 hstr = hdac_stream(stream); 426 427 if (!hstr->prepared) 428 return -EPIPE; 429 430 switch (cmd) { 431 case SNDRV_PCM_TRIGGER_START: 432 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 433 case SNDRV_PCM_TRIGGER_RESUME: 434 start = 1; 435 break; 436 437 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 438 case SNDRV_PCM_TRIGGER_SUSPEND: 439 case SNDRV_PCM_TRIGGER_STOP: 440 start = 0; 441 break; 442 443 default: 444 return -EINVAL; 445 } 446 447 spin_lock_irqsave(&bus->reg_lock, cookie); 448 449 if (start) { 450 snd_hdac_stream_start(hdac_stream(stream), true); 451 snd_hdac_stream_timecounter_init(hstr, 0); 452 } else { 453 snd_hdac_stream_stop(hdac_stream(stream)); 454 } 455 456 spin_unlock_irqrestore(&bus->reg_lock, cookie); 457 458 return 0; 459 } 460 461 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 462 struct snd_soc_dai *dai) 463 { 464 struct skl_dev *skl = get_skl_ctx(dai->dev); 465 struct skl_module_cfg *mconfig; 466 struct hdac_bus *bus = get_bus_ctx(substream); 467 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 468 struct snd_soc_dapm_widget *w; 469 int ret; 470 471 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream); 472 if (!mconfig) 473 return -EIO; 474 475 w = snd_soc_dai_get_widget(dai, substream->stream); 476 477 switch (cmd) { 478 case SNDRV_PCM_TRIGGER_RESUME: 479 if (!w->ignore_suspend) { 480 /* 481 * enable DMA Resume enable bit for the stream, set the 482 * dpib & lpib position to resume before starting the 483 * DMA 484 */ 485 snd_hdac_ext_stream_drsm_enable(bus, true, 486 hdac_stream(stream)->index); 487 snd_hdac_ext_stream_set_dpibr(bus, stream, 488 stream->lpib); 489 snd_hdac_ext_stream_set_lpib(stream, stream->lpib); 490 } 491 /* fall through */ 492 493 case SNDRV_PCM_TRIGGER_START: 494 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 495 /* 496 * Start HOST DMA and Start FE Pipe.This is to make sure that 497 * there are no underrun/overrun in the case when the FE 498 * pipeline is started but there is a delay in starting the 499 * DMA channel on the host. 500 */ 501 ret = skl_decoupled_trigger(substream, cmd); 502 if (ret < 0) 503 return ret; 504 return skl_run_pipe(skl, mconfig->pipe); 505 break; 506 507 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 508 case SNDRV_PCM_TRIGGER_SUSPEND: 509 case SNDRV_PCM_TRIGGER_STOP: 510 /* 511 * Stop FE Pipe first and stop DMA. This is to make sure that 512 * there are no underrun/overrun in the case if there is a delay 513 * between the two operations. 514 */ 515 ret = skl_stop_pipe(skl, mconfig->pipe); 516 if (ret < 0) 517 return ret; 518 519 ret = skl_decoupled_trigger(substream, cmd); 520 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) { 521 /* save the dpib and lpib positions */ 522 stream->dpib = readl(bus->remap_addr + 523 AZX_REG_VS_SDXDPIB_XBASE + 524 (AZX_REG_VS_SDXDPIB_XINTERVAL * 525 hdac_stream(stream)->index)); 526 527 stream->lpib = snd_hdac_stream_get_pos_lpib( 528 hdac_stream(stream)); 529 snd_hdac_ext_stream_decouple(bus, stream, false); 530 } 531 break; 532 533 default: 534 return -EINVAL; 535 } 536 537 return 0; 538 } 539 540 541 static int skl_link_hw_params(struct snd_pcm_substream *substream, 542 struct snd_pcm_hw_params *params, 543 struct snd_soc_dai *dai) 544 { 545 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 546 struct hdac_ext_stream *link_dev; 547 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 548 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); 549 struct skl_pipe_params p_params = {0}; 550 struct hdac_ext_link *link; 551 int stream_tag; 552 553 link_dev = snd_hdac_ext_stream_assign(bus, substream, 554 HDAC_EXT_STREAM_TYPE_LINK); 555 if (!link_dev) 556 return -EBUSY; 557 558 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev); 559 560 link = snd_hdac_ext_bus_get_link(bus, codec_dai->component->name); 561 if (!link) 562 return -EINVAL; 563 564 stream_tag = hdac_stream(link_dev)->stream_tag; 565 566 /* set the stream tag in the codec dai dma params */ 567 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 568 snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0); 569 else 570 snd_soc_dai_set_tdm_slot(codec_dai, 0, stream_tag, 0, 0); 571 572 p_params.s_fmt = snd_pcm_format_width(params_format(params)); 573 p_params.ch = params_channels(params); 574 p_params.s_freq = params_rate(params); 575 p_params.stream = substream->stream; 576 p_params.link_dma_id = stream_tag - 1; 577 p_params.link_index = link->index; 578 p_params.format = params_format(params); 579 580 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 581 p_params.link_bps = codec_dai->driver->playback.sig_bits; 582 else 583 p_params.link_bps = codec_dai->driver->capture.sig_bits; 584 585 return skl_tplg_be_update_params(dai, &p_params); 586 } 587 588 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream, 589 struct snd_soc_dai *dai) 590 { 591 struct skl_dev *skl = get_skl_ctx(dai->dev); 592 struct skl_module_cfg *mconfig = NULL; 593 594 /* In case of XRUN recovery, reset the FW pipe to clean state */ 595 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream); 596 if (mconfig && !mconfig->pipe->passthru && 597 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN)) 598 skl_reset_pipe(skl, mconfig->pipe); 599 600 return 0; 601 } 602 603 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream, 604 int cmd, struct snd_soc_dai *dai) 605 { 606 struct hdac_ext_stream *link_dev = 607 snd_soc_dai_get_dma_data(dai, substream); 608 struct hdac_bus *bus = get_bus_ctx(substream); 609 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream); 610 611 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd); 612 switch (cmd) { 613 case SNDRV_PCM_TRIGGER_RESUME: 614 case SNDRV_PCM_TRIGGER_START: 615 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 616 snd_hdac_ext_link_stream_start(link_dev); 617 break; 618 619 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 620 case SNDRV_PCM_TRIGGER_SUSPEND: 621 case SNDRV_PCM_TRIGGER_STOP: 622 snd_hdac_ext_link_stream_clear(link_dev); 623 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND) 624 snd_hdac_ext_stream_decouple(bus, stream, false); 625 break; 626 627 default: 628 return -EINVAL; 629 } 630 return 0; 631 } 632 633 static int skl_link_hw_free(struct snd_pcm_substream *substream, 634 struct snd_soc_dai *dai) 635 { 636 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 637 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 638 struct hdac_ext_stream *link_dev = 639 snd_soc_dai_get_dma_data(dai, substream); 640 struct hdac_ext_link *link; 641 unsigned char stream_tag; 642 643 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name); 644 645 link_dev->link_prepared = 0; 646 647 link = snd_hdac_ext_bus_get_link(bus, asoc_rtd_to_codec(rtd, 0)->component->name); 648 if (!link) 649 return -EINVAL; 650 651 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 652 stream_tag = hdac_stream(link_dev)->stream_tag; 653 snd_hdac_ext_link_clear_stream_id(link, stream_tag); 654 } 655 656 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK); 657 return 0; 658 } 659 660 static const struct snd_soc_dai_ops skl_pcm_dai_ops = { 661 .startup = skl_pcm_open, 662 .shutdown = skl_pcm_close, 663 .prepare = skl_pcm_prepare, 664 .hw_params = skl_pcm_hw_params, 665 .hw_free = skl_pcm_hw_free, 666 .trigger = skl_pcm_trigger, 667 }; 668 669 static const struct snd_soc_dai_ops skl_dmic_dai_ops = { 670 .hw_params = skl_be_hw_params, 671 }; 672 673 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = { 674 .hw_params = skl_be_hw_params, 675 }; 676 677 static const struct snd_soc_dai_ops skl_link_dai_ops = { 678 .prepare = skl_link_pcm_prepare, 679 .hw_params = skl_link_hw_params, 680 .hw_free = skl_link_hw_free, 681 .trigger = skl_link_pcm_trigger, 682 }; 683 684 static struct snd_soc_dai_driver skl_fe_dai[] = { 685 { 686 .name = "System Pin", 687 .ops = &skl_pcm_dai_ops, 688 .playback = { 689 .stream_name = "System Playback", 690 .channels_min = HDA_MONO, 691 .channels_max = HDA_STEREO, 692 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000, 693 .formats = SNDRV_PCM_FMTBIT_S16_LE | 694 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 695 .sig_bits = 32, 696 }, 697 .capture = { 698 .stream_name = "System Capture", 699 .channels_min = HDA_MONO, 700 .channels_max = HDA_STEREO, 701 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 702 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 703 .sig_bits = 32, 704 }, 705 }, 706 { 707 .name = "System Pin2", 708 .ops = &skl_pcm_dai_ops, 709 .playback = { 710 .stream_name = "Headset Playback", 711 .channels_min = HDA_MONO, 712 .channels_max = HDA_STEREO, 713 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 714 SNDRV_PCM_RATE_8000, 715 .formats = SNDRV_PCM_FMTBIT_S16_LE | 716 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 717 }, 718 }, 719 { 720 .name = "Echoref Pin", 721 .ops = &skl_pcm_dai_ops, 722 .capture = { 723 .stream_name = "Echoreference Capture", 724 .channels_min = HDA_STEREO, 725 .channels_max = HDA_STEREO, 726 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | 727 SNDRV_PCM_RATE_8000, 728 .formats = SNDRV_PCM_FMTBIT_S16_LE | 729 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 730 }, 731 }, 732 { 733 .name = "Reference Pin", 734 .ops = &skl_pcm_dai_ops, 735 .capture = { 736 .stream_name = "Reference Capture", 737 .channels_min = HDA_MONO, 738 .channels_max = HDA_QUAD, 739 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 740 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 741 .sig_bits = 32, 742 }, 743 }, 744 { 745 .name = "Deepbuffer Pin", 746 .ops = &skl_pcm_dai_ops, 747 .playback = { 748 .stream_name = "Deepbuffer Playback", 749 .channels_min = HDA_STEREO, 750 .channels_max = HDA_STEREO, 751 .rates = SNDRV_PCM_RATE_48000, 752 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 753 .sig_bits = 32, 754 }, 755 }, 756 { 757 .name = "LowLatency Pin", 758 .ops = &skl_pcm_dai_ops, 759 .playback = { 760 .stream_name = "Low Latency Playback", 761 .channels_min = HDA_STEREO, 762 .channels_max = HDA_STEREO, 763 .rates = SNDRV_PCM_RATE_48000, 764 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 765 .sig_bits = 32, 766 }, 767 }, 768 { 769 .name = "DMIC Pin", 770 .ops = &skl_pcm_dai_ops, 771 .capture = { 772 .stream_name = "DMIC Capture", 773 .channels_min = HDA_MONO, 774 .channels_max = HDA_QUAD, 775 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 776 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 777 .sig_bits = 32, 778 }, 779 }, 780 { 781 .name = "HDMI1 Pin", 782 .ops = &skl_pcm_dai_ops, 783 .playback = { 784 .stream_name = "HDMI1 Playback", 785 .channels_min = HDA_STEREO, 786 .channels_max = 8, 787 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 788 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 789 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 790 SNDRV_PCM_RATE_192000, 791 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 792 SNDRV_PCM_FMTBIT_S32_LE, 793 .sig_bits = 32, 794 }, 795 }, 796 { 797 .name = "HDMI2 Pin", 798 .ops = &skl_pcm_dai_ops, 799 .playback = { 800 .stream_name = "HDMI2 Playback", 801 .channels_min = HDA_STEREO, 802 .channels_max = 8, 803 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 804 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 805 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 806 SNDRV_PCM_RATE_192000, 807 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 808 SNDRV_PCM_FMTBIT_S32_LE, 809 .sig_bits = 32, 810 }, 811 }, 812 { 813 .name = "HDMI3 Pin", 814 .ops = &skl_pcm_dai_ops, 815 .playback = { 816 .stream_name = "HDMI3 Playback", 817 .channels_min = HDA_STEREO, 818 .channels_max = 8, 819 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 820 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 821 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 822 SNDRV_PCM_RATE_192000, 823 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 824 SNDRV_PCM_FMTBIT_S32_LE, 825 .sig_bits = 32, 826 }, 827 }, 828 }; 829 830 /* BE CPU Dais */ 831 static struct snd_soc_dai_driver skl_platform_dai[] = { 832 { 833 .name = "SSP0 Pin", 834 .ops = &skl_be_ssp_dai_ops, 835 .playback = { 836 .stream_name = "ssp0 Tx", 837 .channels_min = HDA_STEREO, 838 .channels_max = HDA_STEREO, 839 .rates = SNDRV_PCM_RATE_48000, 840 .formats = SNDRV_PCM_FMTBIT_S16_LE, 841 }, 842 .capture = { 843 .stream_name = "ssp0 Rx", 844 .channels_min = HDA_STEREO, 845 .channels_max = HDA_STEREO, 846 .rates = SNDRV_PCM_RATE_48000, 847 .formats = SNDRV_PCM_FMTBIT_S16_LE, 848 }, 849 }, 850 { 851 .name = "SSP1 Pin", 852 .ops = &skl_be_ssp_dai_ops, 853 .playback = { 854 .stream_name = "ssp1 Tx", 855 .channels_min = HDA_STEREO, 856 .channels_max = HDA_STEREO, 857 .rates = SNDRV_PCM_RATE_48000, 858 .formats = SNDRV_PCM_FMTBIT_S16_LE, 859 }, 860 .capture = { 861 .stream_name = "ssp1 Rx", 862 .channels_min = HDA_STEREO, 863 .channels_max = HDA_STEREO, 864 .rates = SNDRV_PCM_RATE_48000, 865 .formats = SNDRV_PCM_FMTBIT_S16_LE, 866 }, 867 }, 868 { 869 .name = "SSP2 Pin", 870 .ops = &skl_be_ssp_dai_ops, 871 .playback = { 872 .stream_name = "ssp2 Tx", 873 .channels_min = HDA_STEREO, 874 .channels_max = HDA_STEREO, 875 .rates = SNDRV_PCM_RATE_48000, 876 .formats = SNDRV_PCM_FMTBIT_S16_LE, 877 }, 878 .capture = { 879 .stream_name = "ssp2 Rx", 880 .channels_min = HDA_STEREO, 881 .channels_max = HDA_STEREO, 882 .rates = SNDRV_PCM_RATE_48000, 883 .formats = SNDRV_PCM_FMTBIT_S16_LE, 884 }, 885 }, 886 { 887 .name = "SSP3 Pin", 888 .ops = &skl_be_ssp_dai_ops, 889 .playback = { 890 .stream_name = "ssp3 Tx", 891 .channels_min = HDA_STEREO, 892 .channels_max = HDA_STEREO, 893 .rates = SNDRV_PCM_RATE_48000, 894 .formats = SNDRV_PCM_FMTBIT_S16_LE, 895 }, 896 .capture = { 897 .stream_name = "ssp3 Rx", 898 .channels_min = HDA_STEREO, 899 .channels_max = HDA_STEREO, 900 .rates = SNDRV_PCM_RATE_48000, 901 .formats = SNDRV_PCM_FMTBIT_S16_LE, 902 }, 903 }, 904 { 905 .name = "SSP4 Pin", 906 .ops = &skl_be_ssp_dai_ops, 907 .playback = { 908 .stream_name = "ssp4 Tx", 909 .channels_min = HDA_STEREO, 910 .channels_max = HDA_STEREO, 911 .rates = SNDRV_PCM_RATE_48000, 912 .formats = SNDRV_PCM_FMTBIT_S16_LE, 913 }, 914 .capture = { 915 .stream_name = "ssp4 Rx", 916 .channels_min = HDA_STEREO, 917 .channels_max = HDA_STEREO, 918 .rates = SNDRV_PCM_RATE_48000, 919 .formats = SNDRV_PCM_FMTBIT_S16_LE, 920 }, 921 }, 922 { 923 .name = "SSP5 Pin", 924 .ops = &skl_be_ssp_dai_ops, 925 .playback = { 926 .stream_name = "ssp5 Tx", 927 .channels_min = HDA_STEREO, 928 .channels_max = HDA_STEREO, 929 .rates = SNDRV_PCM_RATE_48000, 930 .formats = SNDRV_PCM_FMTBIT_S16_LE, 931 }, 932 .capture = { 933 .stream_name = "ssp5 Rx", 934 .channels_min = HDA_STEREO, 935 .channels_max = HDA_STEREO, 936 .rates = SNDRV_PCM_RATE_48000, 937 .formats = SNDRV_PCM_FMTBIT_S16_LE, 938 }, 939 }, 940 { 941 .name = "iDisp1 Pin", 942 .ops = &skl_link_dai_ops, 943 .playback = { 944 .stream_name = "iDisp1 Tx", 945 .channels_min = HDA_STEREO, 946 .channels_max = 8, 947 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000, 948 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 949 SNDRV_PCM_FMTBIT_S24_LE, 950 }, 951 }, 952 { 953 .name = "iDisp2 Pin", 954 .ops = &skl_link_dai_ops, 955 .playback = { 956 .stream_name = "iDisp2 Tx", 957 .channels_min = HDA_STEREO, 958 .channels_max = 8, 959 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| 960 SNDRV_PCM_RATE_48000, 961 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 962 SNDRV_PCM_FMTBIT_S24_LE, 963 }, 964 }, 965 { 966 .name = "iDisp3 Pin", 967 .ops = &skl_link_dai_ops, 968 .playback = { 969 .stream_name = "iDisp3 Tx", 970 .channels_min = HDA_STEREO, 971 .channels_max = 8, 972 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000| 973 SNDRV_PCM_RATE_48000, 974 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE | 975 SNDRV_PCM_FMTBIT_S24_LE, 976 }, 977 }, 978 { 979 .name = "DMIC01 Pin", 980 .ops = &skl_dmic_dai_ops, 981 .capture = { 982 .stream_name = "DMIC01 Rx", 983 .channels_min = HDA_MONO, 984 .channels_max = HDA_QUAD, 985 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000, 986 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 987 }, 988 }, 989 { 990 .name = "DMIC16k Pin", 991 .ops = &skl_dmic_dai_ops, 992 .capture = { 993 .stream_name = "DMIC16k Rx", 994 .channels_min = HDA_MONO, 995 .channels_max = HDA_QUAD, 996 .rates = SNDRV_PCM_RATE_16000, 997 .formats = SNDRV_PCM_FMTBIT_S16_LE, 998 }, 999 }, 1000 { 1001 .name = "Analog CPU DAI", 1002 .ops = &skl_link_dai_ops, 1003 .playback = { 1004 .stream_name = "Analog CPU Playback", 1005 .channels_min = HDA_MONO, 1006 .channels_max = HDA_MAX, 1007 .rates = SNDRV_PCM_RATE_8000_192000, 1008 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1009 SNDRV_PCM_FMTBIT_S32_LE, 1010 }, 1011 .capture = { 1012 .stream_name = "Analog CPU Capture", 1013 .channels_min = HDA_MONO, 1014 .channels_max = HDA_MAX, 1015 .rates = SNDRV_PCM_RATE_8000_192000, 1016 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1017 SNDRV_PCM_FMTBIT_S32_LE, 1018 }, 1019 }, 1020 { 1021 .name = "Alt Analog CPU DAI", 1022 .ops = &skl_link_dai_ops, 1023 .playback = { 1024 .stream_name = "Alt Analog CPU Playback", 1025 .channels_min = HDA_MONO, 1026 .channels_max = HDA_MAX, 1027 .rates = SNDRV_PCM_RATE_8000_192000, 1028 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1029 SNDRV_PCM_FMTBIT_S32_LE, 1030 }, 1031 .capture = { 1032 .stream_name = "Alt Analog CPU Capture", 1033 .channels_min = HDA_MONO, 1034 .channels_max = HDA_MAX, 1035 .rates = SNDRV_PCM_RATE_8000_192000, 1036 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1037 SNDRV_PCM_FMTBIT_S32_LE, 1038 }, 1039 }, 1040 { 1041 .name = "Digital CPU DAI", 1042 .ops = &skl_link_dai_ops, 1043 .playback = { 1044 .stream_name = "Digital CPU Playback", 1045 .channels_min = HDA_MONO, 1046 .channels_max = HDA_MAX, 1047 .rates = SNDRV_PCM_RATE_8000_192000, 1048 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1049 SNDRV_PCM_FMTBIT_S32_LE, 1050 }, 1051 .capture = { 1052 .stream_name = "Digital CPU Capture", 1053 .channels_min = HDA_MONO, 1054 .channels_max = HDA_MAX, 1055 .rates = SNDRV_PCM_RATE_8000_192000, 1056 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1057 SNDRV_PCM_FMTBIT_S32_LE, 1058 }, 1059 }, 1060 }; 1061 1062 int skl_dai_load(struct snd_soc_component *cmp, int index, 1063 struct snd_soc_dai_driver *dai_drv, 1064 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai) 1065 { 1066 dai_drv->ops = &skl_pcm_dai_ops; 1067 1068 return 0; 1069 } 1070 1071 static int skl_platform_soc_open(struct snd_soc_component *component, 1072 struct snd_pcm_substream *substream) 1073 { 1074 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1075 struct snd_soc_dai_link *dai_link = rtd->dai_link; 1076 1077 dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__, 1078 dai_link->cpus->dai_name); 1079 1080 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw); 1081 1082 return 0; 1083 } 1084 1085 static int skl_coupled_trigger(struct snd_pcm_substream *substream, 1086 int cmd) 1087 { 1088 struct hdac_bus *bus = get_bus_ctx(substream); 1089 struct hdac_ext_stream *stream; 1090 struct snd_pcm_substream *s; 1091 bool start; 1092 int sbits = 0; 1093 unsigned long cookie; 1094 struct hdac_stream *hstr; 1095 1096 stream = get_hdac_ext_stream(substream); 1097 hstr = hdac_stream(stream); 1098 1099 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd); 1100 1101 if (!hstr->prepared) 1102 return -EPIPE; 1103 1104 switch (cmd) { 1105 case SNDRV_PCM_TRIGGER_START: 1106 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1107 case SNDRV_PCM_TRIGGER_RESUME: 1108 start = true; 1109 break; 1110 1111 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1112 case SNDRV_PCM_TRIGGER_SUSPEND: 1113 case SNDRV_PCM_TRIGGER_STOP: 1114 start = false; 1115 break; 1116 1117 default: 1118 return -EINVAL; 1119 } 1120 1121 snd_pcm_group_for_each_entry(s, substream) { 1122 if (s->pcm->card != substream->pcm->card) 1123 continue; 1124 stream = get_hdac_ext_stream(s); 1125 sbits |= 1 << hdac_stream(stream)->index; 1126 snd_pcm_trigger_done(s, substream); 1127 } 1128 1129 spin_lock_irqsave(&bus->reg_lock, cookie); 1130 1131 /* first, set SYNC bits of corresponding streams */ 1132 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC); 1133 1134 snd_pcm_group_for_each_entry(s, substream) { 1135 if (s->pcm->card != substream->pcm->card) 1136 continue; 1137 stream = get_hdac_ext_stream(s); 1138 if (start) 1139 snd_hdac_stream_start(hdac_stream(stream), true); 1140 else 1141 snd_hdac_stream_stop(hdac_stream(stream)); 1142 } 1143 spin_unlock_irqrestore(&bus->reg_lock, cookie); 1144 1145 snd_hdac_stream_sync(hstr, start, sbits); 1146 1147 spin_lock_irqsave(&bus->reg_lock, cookie); 1148 1149 /* reset SYNC bits */ 1150 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC); 1151 if (start) 1152 snd_hdac_stream_timecounter_init(hstr, sbits); 1153 spin_unlock_irqrestore(&bus->reg_lock, cookie); 1154 1155 return 0; 1156 } 1157 1158 static int skl_platform_soc_trigger(struct snd_soc_component *component, 1159 struct snd_pcm_substream *substream, 1160 int cmd) 1161 { 1162 struct hdac_bus *bus = get_bus_ctx(substream); 1163 1164 if (!bus->ppcap) 1165 return skl_coupled_trigger(substream, cmd); 1166 1167 return 0; 1168 } 1169 1170 static snd_pcm_uframes_t skl_platform_soc_pointer( 1171 struct snd_soc_component *component, 1172 struct snd_pcm_substream *substream) 1173 { 1174 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream); 1175 struct hdac_bus *bus = get_bus_ctx(substream); 1176 unsigned int pos; 1177 1178 /* 1179 * Use DPIB for Playback stream as the periodic DMA Position-in- 1180 * Buffer Writes may be scheduled at the same time or later than 1181 * the MSI and does not guarantee to reflect the Position of the 1182 * last buffer that was transferred. Whereas DPIB register in 1183 * HAD space reflects the actual data that is transferred. 1184 * Use the position buffer for capture, as DPIB write gets 1185 * completed earlier than the actual data written to the DDR. 1186 * 1187 * For capture stream following workaround is required to fix the 1188 * incorrect position reporting. 1189 * 1190 * 1. Wait for 20us before reading the DMA position in buffer once 1191 * the interrupt is generated for stream completion as update happens 1192 * on the HDA frame boundary i.e. 20.833uSec. 1193 * 2. Read DPIB register to flush the DMA position value. This dummy 1194 * read is required to flush DMA position value. 1195 * 3. Read the DMA Position-in-Buffer. This value now will be equal to 1196 * or greater than period boundary. 1197 */ 1198 1199 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1200 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE + 1201 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1202 hdac_stream(hstream)->index)); 1203 } else { 1204 udelay(20); 1205 readl(bus->remap_addr + 1206 AZX_REG_VS_SDXDPIB_XBASE + 1207 (AZX_REG_VS_SDXDPIB_XINTERVAL * 1208 hdac_stream(hstream)->index)); 1209 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream)); 1210 } 1211 1212 if (pos >= hdac_stream(hstream)->bufsize) 1213 pos = 0; 1214 1215 return bytes_to_frames(substream->runtime, pos); 1216 } 1217 1218 static int skl_platform_soc_mmap(struct snd_soc_component *component, 1219 struct snd_pcm_substream *substream, 1220 struct vm_area_struct *area) 1221 { 1222 return snd_pcm_lib_default_mmap(substream, area); 1223 } 1224 1225 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream, 1226 u64 nsec) 1227 { 1228 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); 1229 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); 1230 u64 codec_frames, codec_nsecs; 1231 1232 if (!codec_dai->driver->ops->delay) 1233 return nsec; 1234 1235 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai); 1236 codec_nsecs = div_u64(codec_frames * 1000000000LL, 1237 substream->runtime->rate); 1238 1239 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 1240 return nsec + codec_nsecs; 1241 1242 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; 1243 } 1244 1245 static int skl_platform_soc_get_time_info( 1246 struct snd_soc_component *component, 1247 struct snd_pcm_substream *substream, 1248 struct timespec64 *system_ts, struct timespec64 *audio_ts, 1249 struct snd_pcm_audio_tstamp_config *audio_tstamp_config, 1250 struct snd_pcm_audio_tstamp_report *audio_tstamp_report) 1251 { 1252 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream); 1253 struct hdac_stream *hstr = hdac_stream(sstream); 1254 u64 nsec; 1255 1256 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && 1257 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) { 1258 1259 snd_pcm_gettime(substream->runtime, system_ts); 1260 1261 nsec = timecounter_read(&hstr->tc); 1262 nsec = div_u64(nsec, 3); /* can be optimized */ 1263 if (audio_tstamp_config->report_delay) 1264 nsec = skl_adjust_codec_delay(substream, nsec); 1265 1266 *audio_ts = ns_to_timespec64(nsec); 1267 1268 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK; 1269 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */ 1270 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */ 1271 1272 } else { 1273 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; 1274 } 1275 1276 return 0; 1277 } 1278 1279 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) 1280 1281 static int skl_platform_soc_new(struct snd_soc_component *component, 1282 struct snd_soc_pcm_runtime *rtd) 1283 { 1284 struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0); 1285 struct hdac_bus *bus = dev_get_drvdata(dai->dev); 1286 struct snd_pcm *pcm = rtd->pcm; 1287 unsigned int size; 1288 struct skl_dev *skl = bus_to_skl(bus); 1289 1290 if (dai->driver->playback.channels_min || 1291 dai->driver->capture.channels_min) { 1292 /* buffer pre-allocation */ 1293 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; 1294 if (size > MAX_PREALLOC_SIZE) 1295 size = MAX_PREALLOC_SIZE; 1296 snd_pcm_set_managed_buffer_all(pcm, 1297 SNDRV_DMA_TYPE_DEV_SG, 1298 &skl->pci->dev, 1299 size, MAX_PREALLOC_SIZE); 1300 } 1301 1302 return 0; 1303 } 1304 1305 static int skl_get_module_info(struct skl_dev *skl, 1306 struct skl_module_cfg *mconfig) 1307 { 1308 struct skl_module_inst_id *pin_id; 1309 guid_t *uuid_mod, *uuid_tplg; 1310 struct skl_module *skl_module; 1311 struct uuid_module *module; 1312 int i, ret = -EIO; 1313 1314 uuid_mod = (guid_t *)mconfig->guid; 1315 1316 if (list_empty(&skl->uuid_list)) { 1317 dev_err(skl->dev, "Module list is empty\n"); 1318 return -EIO; 1319 } 1320 1321 list_for_each_entry(module, &skl->uuid_list, list) { 1322 if (guid_equal(uuid_mod, &module->uuid)) { 1323 mconfig->id.module_id = module->id; 1324 if (mconfig->module) 1325 mconfig->module->loadable = module->is_loadable; 1326 ret = 0; 1327 break; 1328 } 1329 } 1330 1331 if (ret) 1332 return ret; 1333 1334 uuid_mod = &module->uuid; 1335 ret = -EIO; 1336 for (i = 0; i < skl->nr_modules; i++) { 1337 skl_module = skl->modules[i]; 1338 uuid_tplg = &skl_module->uuid; 1339 if (guid_equal(uuid_mod, uuid_tplg)) { 1340 mconfig->module = skl_module; 1341 ret = 0; 1342 break; 1343 } 1344 } 1345 if (skl->nr_modules && ret) 1346 return ret; 1347 1348 list_for_each_entry(module, &skl->uuid_list, list) { 1349 for (i = 0; i < MAX_IN_QUEUE; i++) { 1350 pin_id = &mconfig->m_in_pin[i].id; 1351 if (guid_equal(&pin_id->mod_uuid, &module->uuid)) 1352 pin_id->module_id = module->id; 1353 } 1354 1355 for (i = 0; i < MAX_OUT_QUEUE; i++) { 1356 pin_id = &mconfig->m_out_pin[i].id; 1357 if (guid_equal(&pin_id->mod_uuid, &module->uuid)) 1358 pin_id->module_id = module->id; 1359 } 1360 } 1361 1362 return 0; 1363 } 1364 1365 static int skl_populate_modules(struct skl_dev *skl) 1366 { 1367 struct skl_pipeline *p; 1368 struct skl_pipe_module *m; 1369 struct snd_soc_dapm_widget *w; 1370 struct skl_module_cfg *mconfig; 1371 int ret = 0; 1372 1373 list_for_each_entry(p, &skl->ppl_list, node) { 1374 list_for_each_entry(m, &p->pipe->w_list, node) { 1375 w = m->w; 1376 mconfig = w->priv; 1377 1378 ret = skl_get_module_info(skl, mconfig); 1379 if (ret < 0) { 1380 dev_err(skl->dev, 1381 "query module info failed\n"); 1382 return ret; 1383 } 1384 1385 skl_tplg_add_moduleid_in_bind_params(skl, w); 1386 } 1387 } 1388 1389 return ret; 1390 } 1391 1392 static int skl_platform_soc_probe(struct snd_soc_component *component) 1393 { 1394 struct hdac_bus *bus = dev_get_drvdata(component->dev); 1395 struct skl_dev *skl = bus_to_skl(bus); 1396 const struct skl_dsp_ops *ops; 1397 int ret; 1398 1399 pm_runtime_get_sync(component->dev); 1400 if (bus->ppcap) { 1401 skl->component = component; 1402 1403 /* init debugfs */ 1404 skl->debugfs = skl_debugfs_init(skl); 1405 1406 ret = skl_tplg_init(component, bus); 1407 if (ret < 0) { 1408 dev_err(component->dev, "Failed to init topology!\n"); 1409 return ret; 1410 } 1411 1412 /* load the firmwares, since all is set */ 1413 ops = skl_get_dsp_ops(skl->pci->device); 1414 if (!ops) 1415 return -EIO; 1416 1417 /* 1418 * Disable dynamic clock and power gating during firmware 1419 * and library download 1420 */ 1421 skl->enable_miscbdcge(component->dev, false); 1422 skl->clock_power_gating(component->dev, false); 1423 1424 ret = ops->init_fw(component->dev, skl); 1425 skl->enable_miscbdcge(component->dev, true); 1426 skl->clock_power_gating(component->dev, true); 1427 if (ret < 0) { 1428 dev_err(component->dev, "Failed to boot first fw: %d\n", ret); 1429 return ret; 1430 } 1431 skl_populate_modules(skl); 1432 skl->update_d0i3c = skl_update_d0i3c; 1433 1434 if (skl->cfg.astate_cfg != NULL) { 1435 skl_dsp_set_astate_cfg(skl, 1436 skl->cfg.astate_cfg->count, 1437 skl->cfg.astate_cfg); 1438 } 1439 } 1440 pm_runtime_mark_last_busy(component->dev); 1441 pm_runtime_put_autosuspend(component->dev); 1442 1443 return 0; 1444 } 1445 1446 static void skl_platform_soc_remove(struct snd_soc_component *component) 1447 { 1448 struct hdac_bus *bus = dev_get_drvdata(component->dev); 1449 struct skl_dev *skl = bus_to_skl(bus); 1450 1451 skl_tplg_exit(component, bus); 1452 1453 skl_debugfs_exit(skl); 1454 } 1455 1456 static const struct snd_soc_component_driver skl_component = { 1457 .name = "pcm", 1458 .probe = skl_platform_soc_probe, 1459 .remove = skl_platform_soc_remove, 1460 .open = skl_platform_soc_open, 1461 .trigger = skl_platform_soc_trigger, 1462 .pointer = skl_platform_soc_pointer, 1463 .get_time_info = skl_platform_soc_get_time_info, 1464 .mmap = skl_platform_soc_mmap, 1465 .pcm_construct = skl_platform_soc_new, 1466 .module_get_upon_open = 1, /* increment refcount when a pcm is opened */ 1467 }; 1468 1469 int skl_platform_register(struct device *dev) 1470 { 1471 int ret; 1472 struct snd_soc_dai_driver *dais; 1473 int num_dais = ARRAY_SIZE(skl_platform_dai); 1474 struct hdac_bus *bus = dev_get_drvdata(dev); 1475 struct skl_dev *skl = bus_to_skl(bus); 1476 1477 skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai), 1478 GFP_KERNEL); 1479 if (!skl->dais) { 1480 ret = -ENOMEM; 1481 goto err; 1482 } 1483 1484 if (!skl->use_tplg_pcm) { 1485 dais = krealloc(skl->dais, sizeof(skl_fe_dai) + 1486 sizeof(skl_platform_dai), GFP_KERNEL); 1487 if (!dais) { 1488 ret = -ENOMEM; 1489 goto err; 1490 } 1491 1492 skl->dais = dais; 1493 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai, 1494 sizeof(skl_fe_dai)); 1495 num_dais += ARRAY_SIZE(skl_fe_dai); 1496 } 1497 1498 ret = devm_snd_soc_register_component(dev, &skl_component, 1499 skl->dais, num_dais); 1500 if (ret) 1501 dev_err(dev, "soc component registration failed %d\n", ret); 1502 err: 1503 return ret; 1504 } 1505 1506 int skl_platform_unregister(struct device *dev) 1507 { 1508 struct hdac_bus *bus = dev_get_drvdata(dev); 1509 struct skl_dev *skl = bus_to_skl(bus); 1510 struct skl_module_deferred_bind *modules, *tmp; 1511 1512 if (!list_empty(&skl->bind_list)) { 1513 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) { 1514 list_del(&modules->node); 1515 kfree(modules); 1516 } 1517 } 1518 1519 kfree(skl->dais); 1520 1521 return 0; 1522 } 1523