xref: /openbmc/linux/sound/soc/fsl/fsl_sai.c (revision f20c7d91)
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
4 //
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
6 
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/slab.h>
16 #include <linux/time.h>
17 #include <sound/core.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm_params.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
22 
23 #include "fsl_sai.h"
24 #include "imx-pcm.h"
25 
26 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
27 		       FSL_SAI_CSR_FEIE)
28 
29 static const unsigned int fsl_sai_rates[] = {
30 	8000, 11025, 12000, 16000, 22050,
31 	24000, 32000, 44100, 48000, 64000,
32 	88200, 96000, 176400, 192000
33 };
34 
35 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
36 	.count = ARRAY_SIZE(fsl_sai_rates),
37 	.list = fsl_sai_rates,
38 };
39 
40 static irqreturn_t fsl_sai_isr(int irq, void *devid)
41 {
42 	struct fsl_sai *sai = (struct fsl_sai *)devid;
43 	unsigned int ofs = sai->soc_data->reg_offset;
44 	struct device *dev = &sai->pdev->dev;
45 	u32 flags, xcsr, mask;
46 	bool irq_none = true;
47 
48 	/*
49 	 * Both IRQ status bits and IRQ mask bits are in the xCSR but
50 	 * different shifts. And we here create a mask only for those
51 	 * IRQs that we activated.
52 	 */
53 	mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
54 
55 	/* Tx IRQ */
56 	regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
57 	flags = xcsr & mask;
58 
59 	if (flags)
60 		irq_none = false;
61 	else
62 		goto irq_rx;
63 
64 	if (flags & FSL_SAI_CSR_WSF)
65 		dev_dbg(dev, "isr: Start of Tx word detected\n");
66 
67 	if (flags & FSL_SAI_CSR_SEF)
68 		dev_dbg(dev, "isr: Tx Frame sync error detected\n");
69 
70 	if (flags & FSL_SAI_CSR_FEF) {
71 		dev_dbg(dev, "isr: Transmit underrun detected\n");
72 		/* FIFO reset for safety */
73 		xcsr |= FSL_SAI_CSR_FR;
74 	}
75 
76 	if (flags & FSL_SAI_CSR_FWF)
77 		dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
78 
79 	if (flags & FSL_SAI_CSR_FRF)
80 		dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
81 
82 	flags &= FSL_SAI_CSR_xF_W_MASK;
83 	xcsr &= ~FSL_SAI_CSR_xF_MASK;
84 
85 	if (flags)
86 		regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
87 
88 irq_rx:
89 	/* Rx IRQ */
90 	regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
91 	flags = xcsr & mask;
92 
93 	if (flags)
94 		irq_none = false;
95 	else
96 		goto out;
97 
98 	if (flags & FSL_SAI_CSR_WSF)
99 		dev_dbg(dev, "isr: Start of Rx word detected\n");
100 
101 	if (flags & FSL_SAI_CSR_SEF)
102 		dev_dbg(dev, "isr: Rx Frame sync error detected\n");
103 
104 	if (flags & FSL_SAI_CSR_FEF) {
105 		dev_dbg(dev, "isr: Receive overflow detected\n");
106 		/* FIFO reset for safety */
107 		xcsr |= FSL_SAI_CSR_FR;
108 	}
109 
110 	if (flags & FSL_SAI_CSR_FWF)
111 		dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
112 
113 	if (flags & FSL_SAI_CSR_FRF)
114 		dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
115 
116 	flags &= FSL_SAI_CSR_xF_W_MASK;
117 	xcsr &= ~FSL_SAI_CSR_xF_MASK;
118 
119 	if (flags)
120 		regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
121 
122 out:
123 	if (irq_none)
124 		return IRQ_NONE;
125 	else
126 		return IRQ_HANDLED;
127 }
128 
129 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
130 				u32 rx_mask, int slots, int slot_width)
131 {
132 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
133 
134 	sai->slots = slots;
135 	sai->slot_width = slot_width;
136 
137 	return 0;
138 }
139 
140 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
141 				      unsigned int ratio)
142 {
143 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
144 
145 	sai->bclk_ratio = ratio;
146 
147 	return 0;
148 }
149 
150 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
151 		int clk_id, unsigned int freq, int fsl_dir)
152 {
153 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
154 	unsigned int ofs = sai->soc_data->reg_offset;
155 	bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
156 	u32 val_cr2 = 0;
157 
158 	switch (clk_id) {
159 	case FSL_SAI_CLK_BUS:
160 		val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
161 		break;
162 	case FSL_SAI_CLK_MAST1:
163 		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
164 		break;
165 	case FSL_SAI_CLK_MAST2:
166 		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
167 		break;
168 	case FSL_SAI_CLK_MAST3:
169 		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
170 		break;
171 	default:
172 		return -EINVAL;
173 	}
174 
175 	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
176 			   FSL_SAI_CR2_MSEL_MASK, val_cr2);
177 
178 	return 0;
179 }
180 
181 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
182 		int clk_id, unsigned int freq, int dir)
183 {
184 	int ret;
185 
186 	if (dir == SND_SOC_CLOCK_IN)
187 		return 0;
188 
189 	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
190 					FSL_FMT_TRANSMITTER);
191 	if (ret) {
192 		dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
193 		return ret;
194 	}
195 
196 	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
197 					FSL_FMT_RECEIVER);
198 	if (ret)
199 		dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
200 
201 	return ret;
202 }
203 
204 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
205 				unsigned int fmt, int fsl_dir)
206 {
207 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
208 	unsigned int ofs = sai->soc_data->reg_offset;
209 	bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
210 	u32 val_cr2 = 0, val_cr4 = 0;
211 
212 	if (!sai->is_lsb_first)
213 		val_cr4 |= FSL_SAI_CR4_MF;
214 
215 	/* DAI mode */
216 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
217 	case SND_SOC_DAIFMT_I2S:
218 		/*
219 		 * Frame low, 1clk before data, one word length for frame sync,
220 		 * frame sync starts one serial clock cycle earlier,
221 		 * that is, together with the last bit of the previous
222 		 * data word.
223 		 */
224 		val_cr2 |= FSL_SAI_CR2_BCP;
225 		val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
226 		break;
227 	case SND_SOC_DAIFMT_LEFT_J:
228 		/*
229 		 * Frame high, one word length for frame sync,
230 		 * frame sync asserts with the first bit of the frame.
231 		 */
232 		val_cr2 |= FSL_SAI_CR2_BCP;
233 		break;
234 	case SND_SOC_DAIFMT_DSP_A:
235 		/*
236 		 * Frame high, 1clk before data, one bit for frame sync,
237 		 * frame sync starts one serial clock cycle earlier,
238 		 * that is, together with the last bit of the previous
239 		 * data word.
240 		 */
241 		val_cr2 |= FSL_SAI_CR2_BCP;
242 		val_cr4 |= FSL_SAI_CR4_FSE;
243 		sai->is_dsp_mode = true;
244 		break;
245 	case SND_SOC_DAIFMT_DSP_B:
246 		/*
247 		 * Frame high, one bit for frame sync,
248 		 * frame sync asserts with the first bit of the frame.
249 		 */
250 		val_cr2 |= FSL_SAI_CR2_BCP;
251 		sai->is_dsp_mode = true;
252 		break;
253 	case SND_SOC_DAIFMT_RIGHT_J:
254 		/* To be done */
255 	default:
256 		return -EINVAL;
257 	}
258 
259 	/* DAI clock inversion */
260 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
261 	case SND_SOC_DAIFMT_IB_IF:
262 		/* Invert both clocks */
263 		val_cr2 ^= FSL_SAI_CR2_BCP;
264 		val_cr4 ^= FSL_SAI_CR4_FSP;
265 		break;
266 	case SND_SOC_DAIFMT_IB_NF:
267 		/* Invert bit clock */
268 		val_cr2 ^= FSL_SAI_CR2_BCP;
269 		break;
270 	case SND_SOC_DAIFMT_NB_IF:
271 		/* Invert frame clock */
272 		val_cr4 ^= FSL_SAI_CR4_FSP;
273 		break;
274 	case SND_SOC_DAIFMT_NB_NF:
275 		/* Nothing to do for both normal cases */
276 		break;
277 	default:
278 		return -EINVAL;
279 	}
280 
281 	/* DAI clock master masks */
282 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
283 	case SND_SOC_DAIFMT_CBS_CFS:
284 		val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
285 		val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
286 		sai->is_slave_mode = false;
287 		break;
288 	case SND_SOC_DAIFMT_CBM_CFM:
289 		sai->is_slave_mode = true;
290 		break;
291 	case SND_SOC_DAIFMT_CBS_CFM:
292 		val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
293 		sai->is_slave_mode = false;
294 		break;
295 	case SND_SOC_DAIFMT_CBM_CFS:
296 		val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
297 		sai->is_slave_mode = true;
298 		break;
299 	default:
300 		return -EINVAL;
301 	}
302 
303 	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
304 			   FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
305 	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
306 			   FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
307 			   FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
308 
309 	return 0;
310 }
311 
312 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
313 {
314 	int ret;
315 
316 	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
317 	if (ret) {
318 		dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
319 		return ret;
320 	}
321 
322 	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
323 	if (ret)
324 		dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
325 
326 	return ret;
327 }
328 
329 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
330 {
331 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
332 	unsigned int ofs = sai->soc_data->reg_offset;
333 	unsigned long clk_rate;
334 	u32 savediv = 0, ratio, savesub = freq;
335 	u32 id;
336 	int ret = 0;
337 
338 	/* Don't apply to slave mode */
339 	if (sai->is_slave_mode)
340 		return 0;
341 
342 	for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
343 		clk_rate = clk_get_rate(sai->mclk_clk[id]);
344 		if (!clk_rate)
345 			continue;
346 
347 		ratio = clk_rate / freq;
348 
349 		ret = clk_rate - ratio * freq;
350 
351 		/*
352 		 * Drop the source that can not be
353 		 * divided into the required rate.
354 		 */
355 		if (ret != 0 && clk_rate / ret < 1000)
356 			continue;
357 
358 		dev_dbg(dai->dev,
359 			"ratio %d for freq %dHz based on clock %ldHz\n",
360 			ratio, freq, clk_rate);
361 
362 		if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
363 			ratio /= 2;
364 		else
365 			continue;
366 
367 		if (ret < savesub) {
368 			savediv = ratio;
369 			sai->mclk_id[tx] = id;
370 			savesub = ret;
371 		}
372 
373 		if (ret == 0)
374 			break;
375 	}
376 
377 	if (savediv == 0) {
378 		dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
379 				tx ? 'T' : 'R', freq);
380 		return -EINVAL;
381 	}
382 
383 	/*
384 	 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
385 	 *    set TCR2 register for playback.
386 	 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
387 	 *    and capture.
388 	 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
389 	 *    and capture.
390 	 * 4) For Tx and Rx are both Synchronous with another SAI, we just
391 	 *    ignore it.
392 	 */
393 	if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
394 	    (!tx && !sai->synchronous[RX])) {
395 		regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
396 				   FSL_SAI_CR2_MSEL_MASK,
397 				   FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
398 		regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
399 				   FSL_SAI_CR2_DIV_MASK, savediv - 1);
400 	} else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
401 		   (tx && !sai->synchronous[TX])) {
402 		regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
403 				   FSL_SAI_CR2_MSEL_MASK,
404 				   FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
405 		regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
406 				   FSL_SAI_CR2_DIV_MASK, savediv - 1);
407 	}
408 
409 	dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
410 			sai->mclk_id[tx], savediv, savesub);
411 
412 	return 0;
413 }
414 
415 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
416 		struct snd_pcm_hw_params *params,
417 		struct snd_soc_dai *cpu_dai)
418 {
419 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
420 	unsigned int ofs = sai->soc_data->reg_offset;
421 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
422 	unsigned int channels = params_channels(params);
423 	u32 word_width = params_width(params);
424 	u32 val_cr4 = 0, val_cr5 = 0;
425 	u32 slots = (channels == 1) ? 2 : channels;
426 	u32 slot_width = word_width;
427 	int ret;
428 
429 	if (sai->slots)
430 		slots = sai->slots;
431 
432 	if (sai->slot_width)
433 		slot_width = sai->slot_width;
434 
435 	if (!sai->is_slave_mode) {
436 		if (sai->bclk_ratio)
437 			ret = fsl_sai_set_bclk(cpu_dai, tx,
438 					       sai->bclk_ratio *
439 					       params_rate(params));
440 		else
441 			ret = fsl_sai_set_bclk(cpu_dai, tx,
442 					       slots * slot_width *
443 					       params_rate(params));
444 		if (ret)
445 			return ret;
446 
447 		/* Do not enable the clock if it is already enabled */
448 		if (!(sai->mclk_streams & BIT(substream->stream))) {
449 			ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
450 			if (ret)
451 				return ret;
452 
453 			sai->mclk_streams |= BIT(substream->stream);
454 		}
455 	}
456 
457 	if (!sai->is_dsp_mode)
458 		val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
459 
460 	val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
461 	val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
462 
463 	if (sai->is_lsb_first)
464 		val_cr5 |= FSL_SAI_CR5_FBT(0);
465 	else
466 		val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
467 
468 	val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
469 
470 	/*
471 	 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
472 	 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
473 	 * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
474 	 * error.
475 	 */
476 
477 	if (!sai->is_slave_mode) {
478 		if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
479 			regmap_update_bits(sai->regmap, FSL_SAI_TCR4(ofs),
480 				FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
481 				val_cr4);
482 			regmap_update_bits(sai->regmap, FSL_SAI_TCR5(ofs),
483 				FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
484 				FSL_SAI_CR5_FBT_MASK, val_cr5);
485 			regmap_write(sai->regmap, FSL_SAI_TMR,
486 				~0UL - ((1 << channels) - 1));
487 		} else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
488 			regmap_update_bits(sai->regmap, FSL_SAI_RCR4(ofs),
489 				FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
490 				val_cr4);
491 			regmap_update_bits(sai->regmap, FSL_SAI_RCR5(ofs),
492 				FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
493 				FSL_SAI_CR5_FBT_MASK, val_cr5);
494 			regmap_write(sai->regmap, FSL_SAI_RMR,
495 				~0UL - ((1 << channels) - 1));
496 		}
497 	}
498 
499 	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
500 			   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
501 			   val_cr4);
502 	regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
503 			   FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
504 			   FSL_SAI_CR5_FBT_MASK, val_cr5);
505 	regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
506 
507 	return 0;
508 }
509 
510 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
511 		struct snd_soc_dai *cpu_dai)
512 {
513 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
514 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
515 
516 	if (!sai->is_slave_mode &&
517 			sai->mclk_streams & BIT(substream->stream)) {
518 		clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
519 		sai->mclk_streams &= ~BIT(substream->stream);
520 	}
521 
522 	return 0;
523 }
524 
525 
526 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
527 		struct snd_soc_dai *cpu_dai)
528 {
529 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
530 	unsigned int ofs = sai->soc_data->reg_offset;
531 
532 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
533 	u32 xcsr, count = 100;
534 
535 	/*
536 	 * Asynchronous mode: Clear SYNC for both Tx and Rx.
537 	 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
538 	 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
539 	 */
540 	regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
541 			   sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
542 	regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
543 			   sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
544 
545 	/*
546 	 * It is recommended that the transmitter is the last enabled
547 	 * and the first disabled.
548 	 */
549 	switch (cmd) {
550 	case SNDRV_PCM_TRIGGER_START:
551 	case SNDRV_PCM_TRIGGER_RESUME:
552 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
553 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
554 				   FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
555 
556 		regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
557 				   FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
558 		regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
559 				   FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
560 
561 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
562 				   FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
563 		break;
564 	case SNDRV_PCM_TRIGGER_STOP:
565 	case SNDRV_PCM_TRIGGER_SUSPEND:
566 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
567 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
568 				   FSL_SAI_CSR_FRDE, 0);
569 		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
570 				   FSL_SAI_CSR_xIE_MASK, 0);
571 
572 		/* Check if the opposite FRDE is also disabled */
573 		regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
574 		if (!(xcsr & FSL_SAI_CSR_FRDE)) {
575 			/* Disable both directions and reset their FIFOs */
576 			regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
577 					   FSL_SAI_CSR_TERE, 0);
578 			regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
579 					   FSL_SAI_CSR_TERE, 0);
580 
581 			/* TERE will remain set till the end of current frame */
582 			do {
583 				udelay(10);
584 				regmap_read(sai->regmap,
585 					    FSL_SAI_xCSR(tx, ofs), &xcsr);
586 			} while (--count && xcsr & FSL_SAI_CSR_TERE);
587 
588 			regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
589 					   FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
590 			regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
591 					   FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
592 
593 			/*
594 			 * For sai master mode, after several open/close sai,
595 			 * there will be no frame clock, and can't recover
596 			 * anymore. Add software reset to fix this issue.
597 			 * This is a hardware bug, and will be fix in the
598 			 * next sai version.
599 			 */
600 			if (!sai->is_slave_mode) {
601 				/* Software Reset for both Tx and Rx */
602 				regmap_write(sai->regmap, FSL_SAI_TCSR(ofs),
603 					     FSL_SAI_CSR_SR);
604 				regmap_write(sai->regmap, FSL_SAI_RCSR(ofs),
605 					     FSL_SAI_CSR_SR);
606 				/* Clear SR bit to finish the reset */
607 				regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
608 				regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
609 			}
610 		}
611 		break;
612 	default:
613 		return -EINVAL;
614 	}
615 
616 	return 0;
617 }
618 
619 static int fsl_sai_startup(struct snd_pcm_substream *substream,
620 		struct snd_soc_dai *cpu_dai)
621 {
622 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
623 	unsigned int ofs = sai->soc_data->reg_offset;
624 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
625 	int ret;
626 
627 	regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
628 			   FSL_SAI_CR3_TRCE_MASK,
629 			   FSL_SAI_CR3_TRCE);
630 
631 	/*
632 	 * EDMA controller needs period size to be a multiple of
633 	 * tx/rx maxburst
634 	 */
635 	if (sai->soc_data->use_edma)
636 		snd_pcm_hw_constraint_step(substream->runtime, 0,
637 					   SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
638 					   tx ? sai->dma_params_tx.maxburst :
639 					   sai->dma_params_rx.maxburst);
640 
641 	ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
642 			SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
643 
644 	return ret;
645 }
646 
647 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
648 		struct snd_soc_dai *cpu_dai)
649 {
650 	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
651 	unsigned int ofs = sai->soc_data->reg_offset;
652 	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
653 
654 	regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
655 			   FSL_SAI_CR3_TRCE_MASK, 0);
656 }
657 
658 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
659 	.set_bclk_ratio	= fsl_sai_set_dai_bclk_ratio,
660 	.set_sysclk	= fsl_sai_set_dai_sysclk,
661 	.set_fmt	= fsl_sai_set_dai_fmt,
662 	.set_tdm_slot	= fsl_sai_set_dai_tdm_slot,
663 	.hw_params	= fsl_sai_hw_params,
664 	.hw_free	= fsl_sai_hw_free,
665 	.trigger	= fsl_sai_trigger,
666 	.startup	= fsl_sai_startup,
667 	.shutdown	= fsl_sai_shutdown,
668 };
669 
670 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
671 {
672 	struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
673 	unsigned int ofs = sai->soc_data->reg_offset;
674 
675 	/* Software Reset for both Tx and Rx */
676 	regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
677 	regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
678 	/* Clear SR bit to finish the reset */
679 	regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
680 	regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
681 
682 	regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
683 			   FSL_SAI_CR1_RFW_MASK,
684 			   sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX);
685 	regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
686 			   FSL_SAI_CR1_RFW_MASK, FSL_SAI_MAXBURST_RX - 1);
687 
688 	snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
689 				&sai->dma_params_rx);
690 
691 	snd_soc_dai_set_drvdata(cpu_dai, sai);
692 
693 	return 0;
694 }
695 
696 static struct snd_soc_dai_driver fsl_sai_dai = {
697 	.probe = fsl_sai_dai_probe,
698 	.playback = {
699 		.stream_name = "CPU-Playback",
700 		.channels_min = 1,
701 		.channels_max = 32,
702 		.rate_min = 8000,
703 		.rate_max = 192000,
704 		.rates = SNDRV_PCM_RATE_KNOT,
705 		.formats = FSL_SAI_FORMATS,
706 	},
707 	.capture = {
708 		.stream_name = "CPU-Capture",
709 		.channels_min = 1,
710 		.channels_max = 32,
711 		.rate_min = 8000,
712 		.rate_max = 192000,
713 		.rates = SNDRV_PCM_RATE_KNOT,
714 		.formats = FSL_SAI_FORMATS,
715 	},
716 	.ops = &fsl_sai_pcm_dai_ops,
717 };
718 
719 static const struct snd_soc_component_driver fsl_component = {
720 	.name           = "fsl-sai",
721 };
722 
723 static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
724 	{FSL_SAI_TCR1(0), 0},
725 	{FSL_SAI_TCR2(0), 0},
726 	{FSL_SAI_TCR3(0), 0},
727 	{FSL_SAI_TCR4(0), 0},
728 	{FSL_SAI_TCR5(0), 0},
729 	{FSL_SAI_TDR0, 0},
730 	{FSL_SAI_TDR1, 0},
731 	{FSL_SAI_TDR2, 0},
732 	{FSL_SAI_TDR3, 0},
733 	{FSL_SAI_TDR4, 0},
734 	{FSL_SAI_TDR5, 0},
735 	{FSL_SAI_TDR6, 0},
736 	{FSL_SAI_TDR7, 0},
737 	{FSL_SAI_TMR, 0},
738 	{FSL_SAI_RCR1(0), 0},
739 	{FSL_SAI_RCR2(0), 0},
740 	{FSL_SAI_RCR3(0), 0},
741 	{FSL_SAI_RCR4(0), 0},
742 	{FSL_SAI_RCR5(0), 0},
743 	{FSL_SAI_RMR, 0},
744 };
745 
746 static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
747 	{FSL_SAI_TCR1(8), 0},
748 	{FSL_SAI_TCR2(8), 0},
749 	{FSL_SAI_TCR3(8), 0},
750 	{FSL_SAI_TCR4(8), 0},
751 	{FSL_SAI_TCR5(8), 0},
752 	{FSL_SAI_TDR0, 0},
753 	{FSL_SAI_TDR1, 0},
754 	{FSL_SAI_TDR2, 0},
755 	{FSL_SAI_TDR3, 0},
756 	{FSL_SAI_TDR4, 0},
757 	{FSL_SAI_TDR5, 0},
758 	{FSL_SAI_TDR6, 0},
759 	{FSL_SAI_TDR7, 0},
760 	{FSL_SAI_TMR, 0},
761 	{FSL_SAI_RCR1(8), 0},
762 	{FSL_SAI_RCR2(8), 0},
763 	{FSL_SAI_RCR3(8), 0},
764 	{FSL_SAI_RCR4(8), 0},
765 	{FSL_SAI_RCR5(8), 0},
766 	{FSL_SAI_RMR, 0},
767 };
768 
769 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
770 {
771 	struct fsl_sai *sai = dev_get_drvdata(dev);
772 	unsigned int ofs = sai->soc_data->reg_offset;
773 
774 	if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
775 		return true;
776 
777 	if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
778 		return true;
779 
780 	switch (reg) {
781 	case FSL_SAI_TFR0:
782 	case FSL_SAI_TFR1:
783 	case FSL_SAI_TFR2:
784 	case FSL_SAI_TFR3:
785 	case FSL_SAI_TFR4:
786 	case FSL_SAI_TFR5:
787 	case FSL_SAI_TFR6:
788 	case FSL_SAI_TFR7:
789 	case FSL_SAI_TMR:
790 	case FSL_SAI_RDR0:
791 	case FSL_SAI_RDR1:
792 	case FSL_SAI_RDR2:
793 	case FSL_SAI_RDR3:
794 	case FSL_SAI_RDR4:
795 	case FSL_SAI_RDR5:
796 	case FSL_SAI_RDR6:
797 	case FSL_SAI_RDR7:
798 	case FSL_SAI_RFR0:
799 	case FSL_SAI_RFR1:
800 	case FSL_SAI_RFR2:
801 	case FSL_SAI_RFR3:
802 	case FSL_SAI_RFR4:
803 	case FSL_SAI_RFR5:
804 	case FSL_SAI_RFR6:
805 	case FSL_SAI_RFR7:
806 	case FSL_SAI_RMR:
807 		return true;
808 	default:
809 		return false;
810 	}
811 }
812 
813 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
814 {
815 	struct fsl_sai *sai = dev_get_drvdata(dev);
816 	unsigned int ofs = sai->soc_data->reg_offset;
817 
818 	if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
819 		return true;
820 
821 	switch (reg) {
822 	case FSL_SAI_TFR0:
823 	case FSL_SAI_TFR1:
824 	case FSL_SAI_TFR2:
825 	case FSL_SAI_TFR3:
826 	case FSL_SAI_TFR4:
827 	case FSL_SAI_TFR5:
828 	case FSL_SAI_TFR6:
829 	case FSL_SAI_TFR7:
830 	case FSL_SAI_RFR0:
831 	case FSL_SAI_RFR1:
832 	case FSL_SAI_RFR2:
833 	case FSL_SAI_RFR3:
834 	case FSL_SAI_RFR4:
835 	case FSL_SAI_RFR5:
836 	case FSL_SAI_RFR6:
837 	case FSL_SAI_RFR7:
838 	case FSL_SAI_RDR0:
839 	case FSL_SAI_RDR1:
840 	case FSL_SAI_RDR2:
841 	case FSL_SAI_RDR3:
842 	case FSL_SAI_RDR4:
843 	case FSL_SAI_RDR5:
844 	case FSL_SAI_RDR6:
845 	case FSL_SAI_RDR7:
846 		return true;
847 	default:
848 		return false;
849 	}
850 }
851 
852 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
853 {
854 	struct fsl_sai *sai = dev_get_drvdata(dev);
855 	unsigned int ofs = sai->soc_data->reg_offset;
856 
857 	if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
858 		return true;
859 
860 	if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
861 		return true;
862 
863 	switch (reg) {
864 	case FSL_SAI_TDR0:
865 	case FSL_SAI_TDR1:
866 	case FSL_SAI_TDR2:
867 	case FSL_SAI_TDR3:
868 	case FSL_SAI_TDR4:
869 	case FSL_SAI_TDR5:
870 	case FSL_SAI_TDR6:
871 	case FSL_SAI_TDR7:
872 	case FSL_SAI_TMR:
873 	case FSL_SAI_RMR:
874 		return true;
875 	default:
876 		return false;
877 	}
878 }
879 
880 static struct regmap_config fsl_sai_regmap_config = {
881 	.reg_bits = 32,
882 	.reg_stride = 4,
883 	.val_bits = 32,
884 	.fast_io = true,
885 
886 	.max_register = FSL_SAI_RMR,
887 	.reg_defaults = fsl_sai_reg_defaults_ofs0,
888 	.num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
889 	.readable_reg = fsl_sai_readable_reg,
890 	.volatile_reg = fsl_sai_volatile_reg,
891 	.writeable_reg = fsl_sai_writeable_reg,
892 	.cache_type = REGCACHE_FLAT,
893 };
894 
895 static int fsl_sai_probe(struct platform_device *pdev)
896 {
897 	struct device_node *np = pdev->dev.of_node;
898 	struct fsl_sai *sai;
899 	struct regmap *gpr;
900 	struct resource *res;
901 	void __iomem *base;
902 	char tmp[8];
903 	int irq, ret, i;
904 	int index;
905 
906 	sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
907 	if (!sai)
908 		return -ENOMEM;
909 
910 	sai->pdev = pdev;
911 	sai->soc_data = of_device_get_match_data(&pdev->dev);
912 
913 	sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
914 
915 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
916 	base = devm_ioremap_resource(&pdev->dev, res);
917 	if (IS_ERR(base))
918 		return PTR_ERR(base);
919 
920 	if (sai->soc_data->reg_offset == 8) {
921 		fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
922 		fsl_sai_regmap_config.num_reg_defaults =
923 			ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
924 	}
925 
926 	sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
927 			"bus", base, &fsl_sai_regmap_config);
928 
929 	/* Compatible with old DTB cases */
930 	if (IS_ERR(sai->regmap))
931 		sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
932 				"sai", base, &fsl_sai_regmap_config);
933 	if (IS_ERR(sai->regmap)) {
934 		dev_err(&pdev->dev, "regmap init failed\n");
935 		return PTR_ERR(sai->regmap);
936 	}
937 
938 	/* No error out for old DTB cases but only mark the clock NULL */
939 	sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
940 	if (IS_ERR(sai->bus_clk)) {
941 		dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
942 				PTR_ERR(sai->bus_clk));
943 		sai->bus_clk = NULL;
944 	}
945 
946 	sai->mclk_clk[0] = sai->bus_clk;
947 	for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
948 		sprintf(tmp, "mclk%d", i);
949 		sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
950 		if (IS_ERR(sai->mclk_clk[i])) {
951 			dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
952 					i + 1, PTR_ERR(sai->mclk_clk[i]));
953 			sai->mclk_clk[i] = NULL;
954 		}
955 	}
956 
957 	irq = platform_get_irq(pdev, 0);
958 	if (irq < 0)
959 		return irq;
960 
961 	ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, IRQF_SHARED,
962 			       np->name, sai);
963 	if (ret) {
964 		dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
965 		return ret;
966 	}
967 
968 	/* Sync Tx with Rx as default by following old DT binding */
969 	sai->synchronous[RX] = true;
970 	sai->synchronous[TX] = false;
971 	fsl_sai_dai.symmetric_rates = 1;
972 	fsl_sai_dai.symmetric_channels = 1;
973 	fsl_sai_dai.symmetric_samplebits = 1;
974 
975 	if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
976 	    of_find_property(np, "fsl,sai-asynchronous", NULL)) {
977 		/* error out if both synchronous and asynchronous are present */
978 		dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
979 		return -EINVAL;
980 	}
981 
982 	if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
983 		/* Sync Rx with Tx */
984 		sai->synchronous[RX] = false;
985 		sai->synchronous[TX] = true;
986 	} else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
987 		/* Discard all settings for asynchronous mode */
988 		sai->synchronous[RX] = false;
989 		sai->synchronous[TX] = false;
990 		fsl_sai_dai.symmetric_rates = 0;
991 		fsl_sai_dai.symmetric_channels = 0;
992 		fsl_sai_dai.symmetric_samplebits = 0;
993 	}
994 
995 	if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
996 	    of_device_is_compatible(np, "fsl,imx6ul-sai")) {
997 		gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
998 		if (IS_ERR(gpr)) {
999 			dev_err(&pdev->dev, "cannot find iomuxc registers\n");
1000 			return PTR_ERR(gpr);
1001 		}
1002 
1003 		index = of_alias_get_id(np, "sai");
1004 		if (index < 0)
1005 			return index;
1006 
1007 		regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
1008 				   MCLK_DIR(index));
1009 	}
1010 
1011 	sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0;
1012 	sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0;
1013 	sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
1014 	sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
1015 
1016 	platform_set_drvdata(pdev, sai);
1017 
1018 	pm_runtime_enable(&pdev->dev);
1019 
1020 	ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
1021 			&fsl_sai_dai, 1);
1022 	if (ret)
1023 		goto err_pm_disable;
1024 
1025 	if (sai->soc_data->use_imx_pcm) {
1026 		ret = imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
1027 		if (ret)
1028 			goto err_pm_disable;
1029 	} else {
1030 		ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1031 		if (ret)
1032 			goto err_pm_disable;
1033 	}
1034 
1035 	return ret;
1036 
1037 err_pm_disable:
1038 	pm_runtime_disable(&pdev->dev);
1039 
1040 	return ret;
1041 }
1042 
1043 static int fsl_sai_remove(struct platform_device *pdev)
1044 {
1045 	pm_runtime_disable(&pdev->dev);
1046 
1047 	return 0;
1048 }
1049 
1050 static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
1051 	.use_imx_pcm = false,
1052 	.use_edma = false,
1053 	.fifo_depth = 32,
1054 	.reg_offset = 0,
1055 };
1056 
1057 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
1058 	.use_imx_pcm = true,
1059 	.use_edma = false,
1060 	.fifo_depth = 32,
1061 	.reg_offset = 0,
1062 };
1063 
1064 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
1065 	.use_imx_pcm = true,
1066 	.use_edma = false,
1067 	.fifo_depth = 16,
1068 	.reg_offset = 8,
1069 };
1070 
1071 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
1072 	.use_imx_pcm = true,
1073 	.use_edma = false,
1074 	.fifo_depth = 128,
1075 	.reg_offset = 8,
1076 };
1077 
1078 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
1079 	.use_imx_pcm = true,
1080 	.use_edma = true,
1081 	.fifo_depth = 64,
1082 	.reg_offset = 0,
1083 };
1084 
1085 static const struct of_device_id fsl_sai_ids[] = {
1086 	{ .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1087 	{ .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1088 	{ .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1089 	{ .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1090 	{ .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1091 	{ .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1092 	{ /* sentinel */ }
1093 };
1094 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
1095 
1096 #ifdef CONFIG_PM
1097 static int fsl_sai_runtime_suspend(struct device *dev)
1098 {
1099 	struct fsl_sai *sai = dev_get_drvdata(dev);
1100 
1101 	if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1102 		clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1103 
1104 	if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1105 		clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1106 
1107 	clk_disable_unprepare(sai->bus_clk);
1108 
1109 	regcache_cache_only(sai->regmap, true);
1110 	regcache_mark_dirty(sai->regmap);
1111 
1112 	return 0;
1113 }
1114 
1115 static int fsl_sai_runtime_resume(struct device *dev)
1116 {
1117 	struct fsl_sai *sai = dev_get_drvdata(dev);
1118 	unsigned int ofs = sai->soc_data->reg_offset;
1119 	int ret;
1120 
1121 	ret = clk_prepare_enable(sai->bus_clk);
1122 	if (ret) {
1123 		dev_err(dev, "failed to enable bus clock: %d\n", ret);
1124 		return ret;
1125 	}
1126 
1127 	if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
1128 		ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
1129 		if (ret)
1130 			goto disable_bus_clk;
1131 	}
1132 
1133 	if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
1134 		ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
1135 		if (ret)
1136 			goto disable_tx_clk;
1137 	}
1138 
1139 	regcache_cache_only(sai->regmap, false);
1140 	regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
1141 	regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
1142 	usleep_range(1000, 2000);
1143 	regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
1144 	regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
1145 
1146 	ret = regcache_sync(sai->regmap);
1147 	if (ret)
1148 		goto disable_rx_clk;
1149 
1150 	return 0;
1151 
1152 disable_rx_clk:
1153 	if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1154 		clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1155 disable_tx_clk:
1156 	if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1157 		clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1158 disable_bus_clk:
1159 	clk_disable_unprepare(sai->bus_clk);
1160 
1161 	return ret;
1162 }
1163 #endif /* CONFIG_PM */
1164 
1165 static const struct dev_pm_ops fsl_sai_pm_ops = {
1166 	SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
1167 			   fsl_sai_runtime_resume, NULL)
1168 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1169 				pm_runtime_force_resume)
1170 };
1171 
1172 static struct platform_driver fsl_sai_driver = {
1173 	.probe = fsl_sai_probe,
1174 	.remove = fsl_sai_remove,
1175 	.driver = {
1176 		.name = "fsl-sai",
1177 		.pm = &fsl_sai_pm_ops,
1178 		.of_match_table = fsl_sai_ids,
1179 	},
1180 };
1181 module_platform_driver(fsl_sai_driver);
1182 
1183 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
1184 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
1185 MODULE_ALIAS("platform:fsl-sai");
1186 MODULE_LICENSE("GPL");
1187