1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/pm_qos.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/time.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 24 25 #include "fsl_sai.h" 26 #include "fsl_utils.h" 27 #include "imx-pcm.h" 28 29 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 30 FSL_SAI_CSR_FEIE) 31 32 static const unsigned int fsl_sai_rates[] = { 33 8000, 11025, 12000, 16000, 22050, 34 24000, 32000, 44100, 48000, 64000, 35 88200, 96000, 176400, 192000, 352800, 36 384000, 705600, 768000, 1411200, 2822400, 37 }; 38 39 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 40 .count = ARRAY_SIZE(fsl_sai_rates), 41 .list = fsl_sai_rates, 42 }; 43 44 /** 45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 46 * 47 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 48 * or Receiver's for both streams. This function is used to check if clocks of 49 * the stream's are synced by the opposite stream. 50 * 51 * @sai: SAI context 52 * @dir: stream direction 53 */ 54 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 55 { 56 int adir = (dir == TX) ? RX : TX; 57 58 /* current dir in async mode while opposite dir in sync mode */ 59 return !sai->synchronous[dir] && sai->synchronous[adir]; 60 } 61 62 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 63 { 64 struct pinctrl_state *state = NULL; 65 66 if (sai->is_pdm_mode) { 67 /* DSD512@44.1kHz, DSD512@48kHz */ 68 if (bclk >= 22579200) 69 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 70 71 /* Get default DSD state */ 72 if (IS_ERR_OR_NULL(state)) 73 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 74 } else { 75 /* 706k32b2c, 768k32b2c, etc */ 76 if (bclk >= 45158400) 77 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 78 } 79 80 /* Get default state */ 81 if (IS_ERR_OR_NULL(state)) 82 state = pinctrl_lookup_state(sai->pinctrl, "default"); 83 84 return state; 85 } 86 87 static irqreturn_t fsl_sai_isr(int irq, void *devid) 88 { 89 struct fsl_sai *sai = (struct fsl_sai *)devid; 90 unsigned int ofs = sai->soc_data->reg_offset; 91 struct device *dev = &sai->pdev->dev; 92 u32 flags, xcsr, mask; 93 irqreturn_t iret = IRQ_NONE; 94 95 /* 96 * Both IRQ status bits and IRQ mask bits are in the xCSR but 97 * different shifts. And we here create a mask only for those 98 * IRQs that we activated. 99 */ 100 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 101 102 /* Tx IRQ */ 103 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 104 flags = xcsr & mask; 105 106 if (flags) 107 iret = IRQ_HANDLED; 108 else 109 goto irq_rx; 110 111 if (flags & FSL_SAI_CSR_WSF) 112 dev_dbg(dev, "isr: Start of Tx word detected\n"); 113 114 if (flags & FSL_SAI_CSR_SEF) 115 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 116 117 if (flags & FSL_SAI_CSR_FEF) 118 dev_dbg(dev, "isr: Transmit underrun detected\n"); 119 120 if (flags & FSL_SAI_CSR_FWF) 121 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 122 123 if (flags & FSL_SAI_CSR_FRF) 124 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 125 126 flags &= FSL_SAI_CSR_xF_W_MASK; 127 xcsr &= ~FSL_SAI_CSR_xF_MASK; 128 129 if (flags) 130 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 131 132 irq_rx: 133 /* Rx IRQ */ 134 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 135 flags = xcsr & mask; 136 137 if (flags) 138 iret = IRQ_HANDLED; 139 else 140 goto out; 141 142 if (flags & FSL_SAI_CSR_WSF) 143 dev_dbg(dev, "isr: Start of Rx word detected\n"); 144 145 if (flags & FSL_SAI_CSR_SEF) 146 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 147 148 if (flags & FSL_SAI_CSR_FEF) 149 dev_dbg(dev, "isr: Receive overflow detected\n"); 150 151 if (flags & FSL_SAI_CSR_FWF) 152 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 153 154 if (flags & FSL_SAI_CSR_FRF) 155 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 156 157 flags &= FSL_SAI_CSR_xF_W_MASK; 158 xcsr &= ~FSL_SAI_CSR_xF_MASK; 159 160 if (flags) 161 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 162 163 out: 164 return iret; 165 } 166 167 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 168 u32 rx_mask, int slots, int slot_width) 169 { 170 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 171 172 sai->slots = slots; 173 sai->slot_width = slot_width; 174 175 return 0; 176 } 177 178 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 179 unsigned int ratio) 180 { 181 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 182 183 sai->bclk_ratio = ratio; 184 185 return 0; 186 } 187 188 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 189 int clk_id, unsigned int freq, bool tx) 190 { 191 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 192 unsigned int ofs = sai->soc_data->reg_offset; 193 u32 val_cr2 = 0; 194 195 switch (clk_id) { 196 case FSL_SAI_CLK_BUS: 197 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 198 break; 199 case FSL_SAI_CLK_MAST1: 200 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 201 break; 202 case FSL_SAI_CLK_MAST2: 203 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 204 break; 205 case FSL_SAI_CLK_MAST3: 206 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 207 break; 208 default: 209 return -EINVAL; 210 } 211 212 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 213 FSL_SAI_CR2_MSEL_MASK, val_cr2); 214 215 return 0; 216 } 217 218 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 219 { 220 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 221 int ret; 222 223 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 224 sai->pll8k_clk, sai->pll11k_clk, freq); 225 226 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 227 if (ret < 0) 228 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 229 230 return ret; 231 } 232 233 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 234 int clk_id, unsigned int freq, int dir) 235 { 236 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 237 int ret; 238 239 if (dir == SND_SOC_CLOCK_IN) 240 return 0; 241 242 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) { 243 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 244 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 245 return -EINVAL; 246 } 247 248 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 249 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 250 return -EINVAL; 251 } 252 253 if (sai->mclk_streams == 0) { 254 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq); 255 if (ret < 0) 256 return ret; 257 } 258 } 259 260 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 261 if (ret) { 262 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 263 return ret; 264 } 265 266 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 267 if (ret) 268 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 269 270 return ret; 271 } 272 273 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 274 unsigned int fmt, bool tx) 275 { 276 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 277 unsigned int ofs = sai->soc_data->reg_offset; 278 u32 val_cr2 = 0, val_cr4 = 0; 279 280 if (!sai->is_lsb_first) 281 val_cr4 |= FSL_SAI_CR4_MF; 282 283 sai->is_pdm_mode = false; 284 sai->is_dsp_mode = false; 285 /* DAI mode */ 286 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 287 case SND_SOC_DAIFMT_I2S: 288 /* 289 * Frame low, 1clk before data, one word length for frame sync, 290 * frame sync starts one serial clock cycle earlier, 291 * that is, together with the last bit of the previous 292 * data word. 293 */ 294 val_cr2 |= FSL_SAI_CR2_BCP; 295 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 296 break; 297 case SND_SOC_DAIFMT_LEFT_J: 298 /* 299 * Frame high, one word length for frame sync, 300 * frame sync asserts with the first bit of the frame. 301 */ 302 val_cr2 |= FSL_SAI_CR2_BCP; 303 break; 304 case SND_SOC_DAIFMT_DSP_A: 305 /* 306 * Frame high, 1clk before data, one bit for frame sync, 307 * frame sync starts one serial clock cycle earlier, 308 * that is, together with the last bit of the previous 309 * data word. 310 */ 311 val_cr2 |= FSL_SAI_CR2_BCP; 312 val_cr4 |= FSL_SAI_CR4_FSE; 313 sai->is_dsp_mode = true; 314 break; 315 case SND_SOC_DAIFMT_DSP_B: 316 /* 317 * Frame high, one bit for frame sync, 318 * frame sync asserts with the first bit of the frame. 319 */ 320 val_cr2 |= FSL_SAI_CR2_BCP; 321 sai->is_dsp_mode = true; 322 break; 323 case SND_SOC_DAIFMT_PDM: 324 val_cr2 |= FSL_SAI_CR2_BCP; 325 val_cr4 &= ~FSL_SAI_CR4_MF; 326 sai->is_pdm_mode = true; 327 break; 328 case SND_SOC_DAIFMT_RIGHT_J: 329 /* To be done */ 330 default: 331 return -EINVAL; 332 } 333 334 /* DAI clock inversion */ 335 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 336 case SND_SOC_DAIFMT_IB_IF: 337 /* Invert both clocks */ 338 val_cr2 ^= FSL_SAI_CR2_BCP; 339 val_cr4 ^= FSL_SAI_CR4_FSP; 340 break; 341 case SND_SOC_DAIFMT_IB_NF: 342 /* Invert bit clock */ 343 val_cr2 ^= FSL_SAI_CR2_BCP; 344 break; 345 case SND_SOC_DAIFMT_NB_IF: 346 /* Invert frame clock */ 347 val_cr4 ^= FSL_SAI_CR4_FSP; 348 break; 349 case SND_SOC_DAIFMT_NB_NF: 350 /* Nothing to do for both normal cases */ 351 break; 352 default: 353 return -EINVAL; 354 } 355 356 /* DAI clock provider masks */ 357 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 358 case SND_SOC_DAIFMT_BP_FP: 359 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 360 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 361 sai->is_consumer_mode = false; 362 break; 363 case SND_SOC_DAIFMT_BC_FC: 364 sai->is_consumer_mode = true; 365 break; 366 case SND_SOC_DAIFMT_BP_FC: 367 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 368 sai->is_consumer_mode = false; 369 break; 370 case SND_SOC_DAIFMT_BC_FP: 371 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 372 sai->is_consumer_mode = true; 373 break; 374 default: 375 return -EINVAL; 376 } 377 378 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 379 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 380 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 381 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 382 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 383 384 return 0; 385 } 386 387 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 388 { 389 int ret; 390 391 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 392 if (ret) { 393 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 394 return ret; 395 } 396 397 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 398 if (ret) 399 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 400 401 return ret; 402 } 403 404 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 405 { 406 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 407 unsigned int reg, ofs = sai->soc_data->reg_offset; 408 unsigned long clk_rate; 409 u32 savediv = 0, ratio, bestdiff = freq; 410 int adir = tx ? RX : TX; 411 int dir = tx ? TX : RX; 412 u32 id; 413 bool support_1_1_ratio = sai->verid.version >= 0x0301; 414 415 /* Don't apply to consumer mode */ 416 if (sai->is_consumer_mode) 417 return 0; 418 419 /* 420 * There is no point in polling MCLK0 if it is identical to MCLK1. 421 * And given that MQS use case has to use MCLK1 though two clocks 422 * are the same, we simply skip MCLK0 and start to find from MCLK1. 423 */ 424 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 425 426 for (; id < FSL_SAI_MCLK_MAX; id++) { 427 int diff; 428 429 clk_rate = clk_get_rate(sai->mclk_clk[id]); 430 if (!clk_rate) 431 continue; 432 433 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 434 if (!ratio || ratio > 512) 435 continue; 436 if (ratio == 1 && !support_1_1_ratio) 437 continue; 438 if ((ratio & 1) && ratio > 1) 439 continue; 440 441 diff = abs((long)clk_rate - ratio * freq); 442 443 /* 444 * Drop the source that can not be 445 * divided into the required rate. 446 */ 447 if (diff != 0 && clk_rate / diff < 1000) 448 continue; 449 450 dev_dbg(dai->dev, 451 "ratio %d for freq %dHz based on clock %ldHz\n", 452 ratio, freq, clk_rate); 453 454 455 if (diff < bestdiff) { 456 savediv = ratio; 457 sai->mclk_id[tx] = id; 458 bestdiff = diff; 459 } 460 461 if (diff == 0) 462 break; 463 } 464 465 if (savediv == 0) { 466 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 467 tx ? 'T' : 'R', freq); 468 return -EINVAL; 469 } 470 471 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 472 sai->mclk_id[tx], savediv, bestdiff); 473 474 /* 475 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 476 * set TCR2 register for playback. 477 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 478 * and capture. 479 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 480 * and capture. 481 * 4) For Tx and Rx are both Synchronous with another SAI, we just 482 * ignore it. 483 */ 484 if (fsl_sai_dir_is_synced(sai, adir)) 485 reg = FSL_SAI_xCR2(!tx, ofs); 486 else if (!sai->synchronous[dir]) 487 reg = FSL_SAI_xCR2(tx, ofs); 488 else 489 return 0; 490 491 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 492 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 493 494 if (savediv == 1) { 495 regmap_update_bits(sai->regmap, reg, 496 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 497 FSL_SAI_CR2_BYP); 498 if (fsl_sai_dir_is_synced(sai, adir)) 499 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 500 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI); 501 else 502 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 503 FSL_SAI_CR2_BCI, 0); 504 } else { 505 regmap_update_bits(sai->regmap, reg, 506 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 507 savediv / 2 - 1); 508 } 509 510 return 0; 511 } 512 513 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 514 struct snd_pcm_hw_params *params, 515 struct snd_soc_dai *cpu_dai) 516 { 517 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 518 unsigned int ofs = sai->soc_data->reg_offset; 519 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 520 unsigned int channels = params_channels(params); 521 struct snd_dmaengine_dai_dma_data *dma_params; 522 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 523 u32 word_width = params_width(params); 524 int trce_mask = 0, dl_cfg_idx = 0; 525 int dl_cfg_cnt = sai->dl_cfg_cnt; 526 u32 dl_type = FSL_SAI_DL_I2S; 527 u32 val_cr4 = 0, val_cr5 = 0; 528 u32 slots = (channels == 1) ? 2 : channels; 529 u32 slot_width = word_width; 530 int adir = tx ? RX : TX; 531 u32 pins, bclk; 532 u32 watermark; 533 int ret, i; 534 535 if (sai->slot_width) 536 slot_width = sai->slot_width; 537 538 if (sai->slots) 539 slots = sai->slots; 540 else if (sai->bclk_ratio) 541 slots = sai->bclk_ratio / slot_width; 542 543 pins = DIV_ROUND_UP(channels, slots); 544 545 /* 546 * PDM mode, channels are independent 547 * each channels are on one dataline/FIFO. 548 */ 549 if (sai->is_pdm_mode) { 550 pins = channels; 551 dl_type = FSL_SAI_DL_PDM; 552 } 553 554 for (i = 0; i < dl_cfg_cnt; i++) { 555 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 556 dl_cfg_idx = i; 557 break; 558 } 559 } 560 561 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 562 dev_err(cpu_dai->dev, "channel not supported\n"); 563 return -EINVAL; 564 } 565 566 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 567 568 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 569 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 570 if (!IS_ERR_OR_NULL(sai->pins_state)) { 571 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 572 if (ret) { 573 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 574 return ret; 575 } 576 } 577 } 578 579 if (!sai->is_consumer_mode) { 580 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 581 if (ret) 582 return ret; 583 584 /* Do not enable the clock if it is already enabled */ 585 if (!(sai->mclk_streams & BIT(substream->stream))) { 586 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 587 if (ret) 588 return ret; 589 590 sai->mclk_streams |= BIT(substream->stream); 591 } 592 } 593 594 if (!sai->is_dsp_mode && !sai->is_pdm_mode) 595 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 596 597 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 598 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 599 600 if (sai->is_lsb_first || sai->is_pdm_mode) 601 val_cr5 |= FSL_SAI_CR5_FBT(0); 602 else 603 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 604 605 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 606 607 /* Set to avoid channel swap */ 608 val_cr4 |= FSL_SAI_CR4_FCONT; 609 610 /* Set to output mode to avoid tri-stated data pins */ 611 if (tx) 612 val_cr4 |= FSL_SAI_CR4_CHMOD; 613 614 /* 615 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 616 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 617 * RCR5(TCR5) for playback(capture), or there will be sync error. 618 */ 619 620 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { 621 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 622 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 623 FSL_SAI_CR4_CHMOD_MASK, 624 val_cr4); 625 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 626 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 627 FSL_SAI_CR5_FBT_MASK, val_cr5); 628 } 629 630 /* 631 * Combine mode has limation: 632 * - Can't used for singel dataline/FIFO case except the FIFO0 633 * - Can't used for multi dataline/FIFO case except the enabled FIFOs 634 * are successive and start from FIFO0 635 * 636 * So for common usage, all multi fifo case disable the combine mode. 637 */ 638 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) 639 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 640 FSL_SAI_CR4_FCOMB_MASK, 0); 641 else 642 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 643 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 644 645 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 646 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 647 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 648 649 if (sai->is_multi_fifo_dma) { 650 sai->audio_config[tx].words_per_fifo = min(slots, channels); 651 if (tx) { 652 sai->audio_config[tx].n_fifos_dst = pins; 653 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; 654 } else { 655 sai->audio_config[tx].n_fifos_src = pins; 656 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; 657 } 658 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; 659 dma_params->peripheral_config = &sai->audio_config[tx]; 660 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); 661 662 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : 663 (dma_params->maxburst - 1); 664 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), 665 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 666 watermark); 667 } 668 669 /* Find a proper tcre setting */ 670 for (i = 0; i < sai->soc_data->pins; i++) { 671 trce_mask = (1 << (i + 1)) - 1; 672 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 673 break; 674 } 675 676 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 677 FSL_SAI_CR3_TRCE_MASK, 678 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 679 680 /* 681 * When the TERE and FSD_MSTR enabled before configuring the word width 682 * There will be no frame sync clock issue, because word width impact 683 * the generation of frame sync clock. 684 * 685 * TERE enabled earlier only for i.MX8MP case for the hardware limitation, 686 * We need to disable FSD_MSTR before configuring word width, then enable 687 * FSD_MSTR bit for this specific case. 688 */ 689 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 690 !sai->is_consumer_mode) 691 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 692 FSL_SAI_CR4_FSD_MSTR, 0); 693 694 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 695 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 696 FSL_SAI_CR4_CHMOD_MASK | FSL_SAI_CR4_FCONT_MASK, 697 val_cr4); 698 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 699 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 700 FSL_SAI_CR5_FBT_MASK, val_cr5); 701 702 /* Enable FSD_MSTR after configuring word width */ 703 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 704 !sai->is_consumer_mode) 705 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 706 FSL_SAI_CR4_FSD_MSTR, FSL_SAI_CR4_FSD_MSTR); 707 708 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 709 ~0UL - ((1 << min(channels, slots)) - 1)); 710 711 return 0; 712 } 713 714 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 715 struct snd_soc_dai *cpu_dai) 716 { 717 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 718 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 719 unsigned int ofs = sai->soc_data->reg_offset; 720 721 /* Clear xMR to avoid channel swap with mclk_with_tere enabled case */ 722 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0); 723 724 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 725 FSL_SAI_CR3_TRCE_MASK, 0); 726 727 if (!sai->is_consumer_mode && 728 sai->mclk_streams & BIT(substream->stream)) { 729 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 730 sai->mclk_streams &= ~BIT(substream->stream); 731 } 732 733 return 0; 734 } 735 736 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 737 { 738 unsigned int ofs = sai->soc_data->reg_offset; 739 bool tx = dir == TX; 740 u32 xcsr, count = 100, mask; 741 742 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 743 mask = FSL_SAI_CSR_TERE; 744 else 745 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE; 746 747 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 748 mask, 0); 749 750 /* TERE will remain set till the end of current frame */ 751 do { 752 udelay(10); 753 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 754 } while (--count && xcsr & FSL_SAI_CSR_TERE); 755 756 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 757 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 758 759 /* 760 * For sai master mode, after several open/close sai, 761 * there will be no frame clock, and can't recover 762 * anymore. Add software reset to fix this issue. 763 * This is a hardware bug, and will be fix in the 764 * next sai version. 765 */ 766 if (!sai->is_consumer_mode) { 767 /* Software Reset */ 768 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 769 /* Clear SR bit to finish the reset */ 770 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 771 } 772 } 773 774 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 775 struct snd_soc_dai *cpu_dai) 776 { 777 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 778 unsigned int ofs = sai->soc_data->reg_offset; 779 780 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 781 int adir = tx ? RX : TX; 782 int dir = tx ? TX : RX; 783 u32 xcsr; 784 785 /* 786 * Asynchronous mode: Clear SYNC for both Tx and Rx. 787 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 788 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 789 */ 790 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 791 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 792 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 793 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 794 795 /* 796 * It is recommended that the transmitter is the last enabled 797 * and the first disabled. 798 */ 799 switch (cmd) { 800 case SNDRV_PCM_TRIGGER_START: 801 case SNDRV_PCM_TRIGGER_RESUME: 802 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 803 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 804 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 805 806 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 807 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 808 /* 809 * Enable the opposite direction for synchronous mode 810 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 811 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 812 * 813 * RM recommends to enable RE after TE for case 1 and to enable 814 * TE after RE for case 2, but we here may not always guarantee 815 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 816 * TE after RE, which is against what RM recommends but should 817 * be safe to do, judging by years of testing results. 818 */ 819 if (fsl_sai_dir_is_synced(sai, adir)) 820 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 821 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 822 823 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 824 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 825 break; 826 case SNDRV_PCM_TRIGGER_STOP: 827 case SNDRV_PCM_TRIGGER_SUSPEND: 828 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 829 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 830 FSL_SAI_CSR_FRDE, 0); 831 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 832 FSL_SAI_CSR_xIE_MASK, 0); 833 834 /* Check if the opposite FRDE is also disabled */ 835 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 836 837 /* 838 * If opposite stream provides clocks for synchronous mode and 839 * it is inactive, disable it before disabling the current one 840 */ 841 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 842 fsl_sai_config_disable(sai, adir); 843 844 /* 845 * Disable current stream if either of: 846 * 1. current stream doesn't provide clocks for synchronous mode 847 * 2. current stream provides clocks for synchronous mode but no 848 * more stream is active. 849 */ 850 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 851 fsl_sai_config_disable(sai, dir); 852 853 break; 854 default: 855 return -EINVAL; 856 } 857 858 return 0; 859 } 860 861 static int fsl_sai_startup(struct snd_pcm_substream *substream, 862 struct snd_soc_dai *cpu_dai) 863 { 864 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 865 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 866 int ret; 867 868 /* 869 * EDMA controller needs period size to be a multiple of 870 * tx/rx maxburst 871 */ 872 if (sai->soc_data->use_edma) 873 snd_pcm_hw_constraint_step(substream->runtime, 0, 874 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 875 tx ? sai->dma_params_tx.maxburst : 876 sai->dma_params_rx.maxburst); 877 878 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 879 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 880 881 return ret; 882 } 883 884 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 885 { 886 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 887 unsigned int ofs = sai->soc_data->reg_offset; 888 889 /* Software Reset for both Tx and Rx */ 890 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 891 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 892 /* Clear SR bit to finish the reset */ 893 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 894 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 895 896 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 897 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 898 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst); 899 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 900 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 901 sai->dma_params_rx.maxburst - 1); 902 903 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 904 &sai->dma_params_rx); 905 906 return 0; 907 } 908 909 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 910 .probe = fsl_sai_dai_probe, 911 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 912 .set_sysclk = fsl_sai_set_dai_sysclk, 913 .set_fmt = fsl_sai_set_dai_fmt, 914 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 915 .hw_params = fsl_sai_hw_params, 916 .hw_free = fsl_sai_hw_free, 917 .trigger = fsl_sai_trigger, 918 .startup = fsl_sai_startup, 919 }; 920 921 static int fsl_sai_dai_resume(struct snd_soc_component *component) 922 { 923 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 924 struct device *dev = &sai->pdev->dev; 925 int ret; 926 927 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 928 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 929 if (ret) { 930 dev_err(dev, "failed to set proper pins state: %d\n", ret); 931 return ret; 932 } 933 } 934 935 return 0; 936 } 937 938 static struct snd_soc_dai_driver fsl_sai_dai_template = { 939 .playback = { 940 .stream_name = "CPU-Playback", 941 .channels_min = 1, 942 .channels_max = 32, 943 .rate_min = 8000, 944 .rate_max = 2822400, 945 .rates = SNDRV_PCM_RATE_KNOT, 946 .formats = FSL_SAI_FORMATS, 947 }, 948 .capture = { 949 .stream_name = "CPU-Capture", 950 .channels_min = 1, 951 .channels_max = 32, 952 .rate_min = 8000, 953 .rate_max = 2822400, 954 .rates = SNDRV_PCM_RATE_KNOT, 955 .formats = FSL_SAI_FORMATS, 956 }, 957 .ops = &fsl_sai_pcm_dai_ops, 958 }; 959 960 static const struct snd_soc_component_driver fsl_component = { 961 .name = "fsl-sai", 962 .resume = fsl_sai_dai_resume, 963 .legacy_dai_naming = 1, 964 }; 965 966 static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 967 {FSL_SAI_TCR1(0), 0}, 968 {FSL_SAI_TCR2(0), 0}, 969 {FSL_SAI_TCR3(0), 0}, 970 {FSL_SAI_TCR4(0), 0}, 971 {FSL_SAI_TCR5(0), 0}, 972 {FSL_SAI_TDR0, 0}, 973 {FSL_SAI_TDR1, 0}, 974 {FSL_SAI_TDR2, 0}, 975 {FSL_SAI_TDR3, 0}, 976 {FSL_SAI_TDR4, 0}, 977 {FSL_SAI_TDR5, 0}, 978 {FSL_SAI_TDR6, 0}, 979 {FSL_SAI_TDR7, 0}, 980 {FSL_SAI_TMR, 0}, 981 {FSL_SAI_RCR1(0), 0}, 982 {FSL_SAI_RCR2(0), 0}, 983 {FSL_SAI_RCR3(0), 0}, 984 {FSL_SAI_RCR4(0), 0}, 985 {FSL_SAI_RCR5(0), 0}, 986 {FSL_SAI_RMR, 0}, 987 }; 988 989 static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 990 {FSL_SAI_TCR1(8), 0}, 991 {FSL_SAI_TCR2(8), 0}, 992 {FSL_SAI_TCR3(8), 0}, 993 {FSL_SAI_TCR4(8), 0}, 994 {FSL_SAI_TCR5(8), 0}, 995 {FSL_SAI_TDR0, 0}, 996 {FSL_SAI_TDR1, 0}, 997 {FSL_SAI_TDR2, 0}, 998 {FSL_SAI_TDR3, 0}, 999 {FSL_SAI_TDR4, 0}, 1000 {FSL_SAI_TDR5, 0}, 1001 {FSL_SAI_TDR6, 0}, 1002 {FSL_SAI_TDR7, 0}, 1003 {FSL_SAI_TMR, 0}, 1004 {FSL_SAI_RCR1(8), 0}, 1005 {FSL_SAI_RCR2(8), 0}, 1006 {FSL_SAI_RCR3(8), 0}, 1007 {FSL_SAI_RCR4(8), 0}, 1008 {FSL_SAI_RCR5(8), 0}, 1009 {FSL_SAI_RMR, 0}, 1010 {FSL_SAI_MCTL, 0}, 1011 {FSL_SAI_MDIV, 0}, 1012 }; 1013 1014 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 1015 { 1016 struct fsl_sai *sai = dev_get_drvdata(dev); 1017 unsigned int ofs = sai->soc_data->reg_offset; 1018 1019 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1020 return true; 1021 1022 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1023 return true; 1024 1025 switch (reg) { 1026 case FSL_SAI_TFR0: 1027 case FSL_SAI_TFR1: 1028 case FSL_SAI_TFR2: 1029 case FSL_SAI_TFR3: 1030 case FSL_SAI_TFR4: 1031 case FSL_SAI_TFR5: 1032 case FSL_SAI_TFR6: 1033 case FSL_SAI_TFR7: 1034 case FSL_SAI_TMR: 1035 case FSL_SAI_RDR0: 1036 case FSL_SAI_RDR1: 1037 case FSL_SAI_RDR2: 1038 case FSL_SAI_RDR3: 1039 case FSL_SAI_RDR4: 1040 case FSL_SAI_RDR5: 1041 case FSL_SAI_RDR6: 1042 case FSL_SAI_RDR7: 1043 case FSL_SAI_RFR0: 1044 case FSL_SAI_RFR1: 1045 case FSL_SAI_RFR2: 1046 case FSL_SAI_RFR3: 1047 case FSL_SAI_RFR4: 1048 case FSL_SAI_RFR5: 1049 case FSL_SAI_RFR6: 1050 case FSL_SAI_RFR7: 1051 case FSL_SAI_RMR: 1052 case FSL_SAI_MCTL: 1053 case FSL_SAI_MDIV: 1054 case FSL_SAI_VERID: 1055 case FSL_SAI_PARAM: 1056 case FSL_SAI_TTCTN: 1057 case FSL_SAI_RTCTN: 1058 case FSL_SAI_TTCTL: 1059 case FSL_SAI_TBCTN: 1060 case FSL_SAI_TTCAP: 1061 case FSL_SAI_RTCTL: 1062 case FSL_SAI_RBCTN: 1063 case FSL_SAI_RTCAP: 1064 return true; 1065 default: 1066 return false; 1067 } 1068 } 1069 1070 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1071 { 1072 struct fsl_sai *sai = dev_get_drvdata(dev); 1073 unsigned int ofs = sai->soc_data->reg_offset; 1074 1075 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1076 return true; 1077 1078 /* Set VERID and PARAM be volatile for reading value in probe */ 1079 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1080 return true; 1081 1082 switch (reg) { 1083 case FSL_SAI_TFR0: 1084 case FSL_SAI_TFR1: 1085 case FSL_SAI_TFR2: 1086 case FSL_SAI_TFR3: 1087 case FSL_SAI_TFR4: 1088 case FSL_SAI_TFR5: 1089 case FSL_SAI_TFR6: 1090 case FSL_SAI_TFR7: 1091 case FSL_SAI_RFR0: 1092 case FSL_SAI_RFR1: 1093 case FSL_SAI_RFR2: 1094 case FSL_SAI_RFR3: 1095 case FSL_SAI_RFR4: 1096 case FSL_SAI_RFR5: 1097 case FSL_SAI_RFR6: 1098 case FSL_SAI_RFR7: 1099 case FSL_SAI_RDR0: 1100 case FSL_SAI_RDR1: 1101 case FSL_SAI_RDR2: 1102 case FSL_SAI_RDR3: 1103 case FSL_SAI_RDR4: 1104 case FSL_SAI_RDR5: 1105 case FSL_SAI_RDR6: 1106 case FSL_SAI_RDR7: 1107 return true; 1108 default: 1109 return false; 1110 } 1111 } 1112 1113 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1114 { 1115 struct fsl_sai *sai = dev_get_drvdata(dev); 1116 unsigned int ofs = sai->soc_data->reg_offset; 1117 1118 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1119 return true; 1120 1121 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1122 return true; 1123 1124 switch (reg) { 1125 case FSL_SAI_TDR0: 1126 case FSL_SAI_TDR1: 1127 case FSL_SAI_TDR2: 1128 case FSL_SAI_TDR3: 1129 case FSL_SAI_TDR4: 1130 case FSL_SAI_TDR5: 1131 case FSL_SAI_TDR6: 1132 case FSL_SAI_TDR7: 1133 case FSL_SAI_TMR: 1134 case FSL_SAI_RMR: 1135 case FSL_SAI_MCTL: 1136 case FSL_SAI_MDIV: 1137 case FSL_SAI_TTCTL: 1138 case FSL_SAI_RTCTL: 1139 return true; 1140 default: 1141 return false; 1142 } 1143 } 1144 1145 static struct regmap_config fsl_sai_regmap_config = { 1146 .reg_bits = 32, 1147 .reg_stride = 4, 1148 .val_bits = 32, 1149 .fast_io = true, 1150 1151 .max_register = FSL_SAI_RMR, 1152 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1153 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1154 .readable_reg = fsl_sai_readable_reg, 1155 .volatile_reg = fsl_sai_volatile_reg, 1156 .writeable_reg = fsl_sai_writeable_reg, 1157 .cache_type = REGCACHE_FLAT, 1158 }; 1159 1160 static int fsl_sai_check_version(struct device *dev) 1161 { 1162 struct fsl_sai *sai = dev_get_drvdata(dev); 1163 unsigned char ofs = sai->soc_data->reg_offset; 1164 unsigned int val; 1165 int ret; 1166 1167 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1168 return 0; 1169 1170 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1171 if (ret < 0) 1172 return ret; 1173 1174 dev_dbg(dev, "VERID: 0x%016X\n", val); 1175 1176 sai->verid.version = val & 1177 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1178 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT; 1179 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1180 1181 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1182 if (ret < 0) 1183 return ret; 1184 1185 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1186 1187 /* Max slots per frame, power of 2 */ 1188 sai->param.slot_num = 1 << 1189 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1190 1191 /* Words per fifo, power of 2 */ 1192 sai->param.fifo_depth = 1 << 1193 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1194 1195 /* Number of datalines implemented */ 1196 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1197 1198 return 0; 1199 } 1200 1201 /* 1202 * Calculate the offset between first two datalines, don't 1203 * different offset in one case. 1204 */ 1205 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1206 { 1207 int fbidx, nbidx, offset; 1208 1209 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1210 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1211 offset = nbidx - fbidx - 1; 1212 1213 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1214 } 1215 1216 /* 1217 * read the fsl,dataline property from dts file. 1218 * It has 3 value for each configuration, first one means the type: 1219 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1220 * dataline mask for 'tx'. for example 1221 * 1222 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1223 * 1224 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1225 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1226 * 1227 */ 1228 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1229 { 1230 struct platform_device *pdev = sai->pdev; 1231 struct device_node *np = pdev->dev.of_node; 1232 struct device *dev = &pdev->dev; 1233 int ret, elems, i, index, num_cfg; 1234 char *propname = "fsl,dataline"; 1235 struct fsl_sai_dl_cfg *cfg; 1236 unsigned long dl_mask; 1237 unsigned int soc_dl; 1238 u32 rx, tx, type; 1239 1240 elems = of_property_count_u32_elems(np, propname); 1241 1242 if (elems <= 0) { 1243 elems = 0; 1244 } else if (elems % 3) { 1245 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1246 return -EINVAL; 1247 } 1248 1249 num_cfg = elems / 3; 1250 /* Add one more for default value */ 1251 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL); 1252 if (!cfg) 1253 return -ENOMEM; 1254 1255 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1256 soc_dl = BIT(sai->soc_data->pins) - 1; 1257 cfg[0].type = FSL_SAI_DL_DEFAULT; 1258 cfg[0].pins[0] = sai->soc_data->pins; 1259 cfg[0].mask[0] = soc_dl; 1260 cfg[0].start_off[0] = 0; 1261 cfg[0].next_off[0] = 0; 1262 1263 cfg[0].pins[1] = sai->soc_data->pins; 1264 cfg[0].mask[1] = soc_dl; 1265 cfg[0].start_off[1] = 0; 1266 cfg[0].next_off[1] = 0; 1267 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1268 /* 1269 * type of dataline 1270 * 0 means default mode 1271 * 1 means I2S mode 1272 * 2 means PDM mode 1273 */ 1274 ret = of_property_read_u32_index(np, propname, index++, &type); 1275 if (ret) 1276 return -EINVAL; 1277 1278 ret = of_property_read_u32_index(np, propname, index++, &rx); 1279 if (ret) 1280 return -EINVAL; 1281 1282 ret = of_property_read_u32_index(np, propname, index++, &tx); 1283 if (ret) 1284 return -EINVAL; 1285 1286 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1287 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1288 return -EINVAL; 1289 } 1290 1291 rx = rx & soc_dl; 1292 tx = tx & soc_dl; 1293 1294 cfg[i].type = type; 1295 cfg[i].pins[0] = hweight8(rx); 1296 cfg[i].mask[0] = rx; 1297 dl_mask = rx; 1298 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1299 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1300 1301 cfg[i].pins[1] = hweight8(tx); 1302 cfg[i].mask[1] = tx; 1303 dl_mask = tx; 1304 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1305 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1306 } 1307 1308 sai->dl_cfg = cfg; 1309 sai->dl_cfg_cnt = num_cfg + 1; 1310 return 0; 1311 } 1312 1313 static int fsl_sai_runtime_suspend(struct device *dev); 1314 static int fsl_sai_runtime_resume(struct device *dev); 1315 1316 static int fsl_sai_probe(struct platform_device *pdev) 1317 { 1318 struct device_node *np = pdev->dev.of_node; 1319 struct device *dev = &pdev->dev; 1320 struct fsl_sai *sai; 1321 struct regmap *gpr; 1322 void __iomem *base; 1323 char tmp[8]; 1324 int irq, ret, i; 1325 int index; 1326 u32 dmas[4]; 1327 1328 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1329 if (!sai) 1330 return -ENOMEM; 1331 1332 sai->pdev = pdev; 1333 sai->soc_data = of_device_get_match_data(dev); 1334 1335 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1336 1337 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1338 if (IS_ERR(base)) 1339 return PTR_ERR(base); 1340 1341 if (sai->soc_data->reg_offset == 8) { 1342 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1343 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1344 fsl_sai_regmap_config.num_reg_defaults = 1345 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1346 } 1347 1348 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1349 if (IS_ERR(sai->regmap)) { 1350 dev_err(dev, "regmap init failed\n"); 1351 return PTR_ERR(sai->regmap); 1352 } 1353 1354 sai->bus_clk = devm_clk_get(dev, "bus"); 1355 /* Compatible with old DTB cases */ 1356 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1357 sai->bus_clk = devm_clk_get(dev, "sai"); 1358 if (IS_ERR(sai->bus_clk)) { 1359 dev_err(dev, "failed to get bus clock: %ld\n", 1360 PTR_ERR(sai->bus_clk)); 1361 /* -EPROBE_DEFER */ 1362 return PTR_ERR(sai->bus_clk); 1363 } 1364 1365 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1366 sprintf(tmp, "mclk%d", i); 1367 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1368 if (IS_ERR(sai->mclk_clk[i])) { 1369 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1370 i, PTR_ERR(sai->mclk_clk[i])); 1371 sai->mclk_clk[i] = NULL; 1372 } 1373 } 1374 1375 if (sai->soc_data->mclk0_is_mclk1) 1376 sai->mclk_clk[0] = sai->mclk_clk[1]; 1377 else 1378 sai->mclk_clk[0] = sai->bus_clk; 1379 1380 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1381 &sai->pll11k_clk); 1382 1383 /* Use Multi FIFO mode depending on the support from SDMA script */ 1384 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1385 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) 1386 sai->is_multi_fifo_dma = true; 1387 1388 /* read dataline mask for rx and tx*/ 1389 ret = fsl_sai_read_dlcfg(sai); 1390 if (ret < 0) { 1391 dev_err(dev, "failed to read dlcfg %d\n", ret); 1392 return ret; 1393 } 1394 1395 irq = platform_get_irq(pdev, 0); 1396 if (irq < 0) 1397 return irq; 1398 1399 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1400 np->name, sai); 1401 if (ret) { 1402 dev_err(dev, "failed to claim irq %u\n", irq); 1403 return ret; 1404 } 1405 1406 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1407 sizeof(fsl_sai_dai_template)); 1408 1409 /* Sync Tx with Rx as default by following old DT binding */ 1410 sai->synchronous[RX] = true; 1411 sai->synchronous[TX] = false; 1412 sai->cpu_dai_drv.symmetric_rate = 1; 1413 sai->cpu_dai_drv.symmetric_channels = 1; 1414 sai->cpu_dai_drv.symmetric_sample_bits = 1; 1415 1416 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") && 1417 of_property_read_bool(np, "fsl,sai-asynchronous")) { 1418 /* error out if both synchronous and asynchronous are present */ 1419 dev_err(dev, "invalid binding for synchronous mode\n"); 1420 return -EINVAL; 1421 } 1422 1423 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) { 1424 /* Sync Rx with Tx */ 1425 sai->synchronous[RX] = false; 1426 sai->synchronous[TX] = true; 1427 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) { 1428 /* Discard all settings for asynchronous mode */ 1429 sai->synchronous[RX] = false; 1430 sai->synchronous[TX] = false; 1431 sai->cpu_dai_drv.symmetric_rate = 0; 1432 sai->cpu_dai_drv.symmetric_channels = 0; 1433 sai->cpu_dai_drv.symmetric_sample_bits = 0; 1434 } 1435 1436 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output"); 1437 1438 if (sai->mclk_direction_output && 1439 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1440 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1441 if (IS_ERR(gpr)) { 1442 dev_err(dev, "cannot find iomuxc registers\n"); 1443 return PTR_ERR(gpr); 1444 } 1445 1446 index = of_alias_get_id(np, "sai"); 1447 if (index < 0) 1448 return index; 1449 1450 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1451 MCLK_DIR(index)); 1452 } 1453 1454 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1455 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1456 sai->dma_params_rx.maxburst = 1457 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX; 1458 sai->dma_params_tx.maxburst = 1459 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX; 1460 1461 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1462 1463 platform_set_drvdata(pdev, sai); 1464 pm_runtime_enable(dev); 1465 if (!pm_runtime_enabled(dev)) { 1466 ret = fsl_sai_runtime_resume(dev); 1467 if (ret) 1468 goto err_pm_disable; 1469 } 1470 1471 ret = pm_runtime_resume_and_get(dev); 1472 if (ret < 0) 1473 goto err_pm_get_sync; 1474 1475 /* Get sai version */ 1476 ret = fsl_sai_check_version(dev); 1477 if (ret < 0) 1478 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1479 1480 /* Select MCLK direction */ 1481 if (sai->mclk_direction_output && 1482 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1483 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1484 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1485 } 1486 1487 ret = pm_runtime_put_sync(dev); 1488 if (ret < 0 && ret != -ENOSYS) 1489 goto err_pm_get_sync; 1490 1491 /* 1492 * Register platform component before registering cpu dai for there 1493 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1494 */ 1495 if (sai->soc_data->use_imx_pcm) { 1496 ret = imx_pcm_dma_init(pdev); 1497 if (ret) { 1498 dev_err_probe(dev, ret, "PCM DMA init failed\n"); 1499 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1500 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1501 goto err_pm_get_sync; 1502 } 1503 } else { 1504 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1505 if (ret) { 1506 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n"); 1507 goto err_pm_get_sync; 1508 } 1509 } 1510 1511 ret = devm_snd_soc_register_component(dev, &fsl_component, 1512 &sai->cpu_dai_drv, 1); 1513 if (ret) 1514 goto err_pm_get_sync; 1515 1516 return ret; 1517 1518 err_pm_get_sync: 1519 if (!pm_runtime_status_suspended(dev)) 1520 fsl_sai_runtime_suspend(dev); 1521 err_pm_disable: 1522 pm_runtime_disable(dev); 1523 1524 return ret; 1525 } 1526 1527 static void fsl_sai_remove(struct platform_device *pdev) 1528 { 1529 pm_runtime_disable(&pdev->dev); 1530 if (!pm_runtime_status_suspended(&pdev->dev)) 1531 fsl_sai_runtime_suspend(&pdev->dev); 1532 } 1533 1534 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1535 .use_imx_pcm = false, 1536 .use_edma = false, 1537 .fifo_depth = 32, 1538 .pins = 1, 1539 .reg_offset = 0, 1540 .mclk0_is_mclk1 = false, 1541 .flags = 0, 1542 .max_register = FSL_SAI_RMR, 1543 }; 1544 1545 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1546 .use_imx_pcm = true, 1547 .use_edma = false, 1548 .fifo_depth = 32, 1549 .pins = 1, 1550 .reg_offset = 0, 1551 .mclk0_is_mclk1 = true, 1552 .flags = 0, 1553 .max_register = FSL_SAI_RMR, 1554 }; 1555 1556 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1557 .use_imx_pcm = true, 1558 .use_edma = false, 1559 .fifo_depth = 16, 1560 .pins = 2, 1561 .reg_offset = 8, 1562 .mclk0_is_mclk1 = false, 1563 .flags = PMQOS_CPU_LATENCY, 1564 .max_register = FSL_SAI_RMR, 1565 }; 1566 1567 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1568 .use_imx_pcm = true, 1569 .use_edma = false, 1570 .fifo_depth = 128, 1571 .pins = 8, 1572 .reg_offset = 8, 1573 .mclk0_is_mclk1 = false, 1574 .flags = 0, 1575 .max_register = FSL_SAI_RMR, 1576 }; 1577 1578 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1579 .use_imx_pcm = true, 1580 .use_edma = true, 1581 .fifo_depth = 64, 1582 .pins = 4, 1583 .reg_offset = 0, 1584 .mclk0_is_mclk1 = false, 1585 .flags = 0, 1586 .max_register = FSL_SAI_RMR, 1587 }; 1588 1589 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1590 .use_imx_pcm = true, 1591 .use_edma = false, 1592 .fifo_depth = 128, 1593 .reg_offset = 8, 1594 .mclk0_is_mclk1 = false, 1595 .pins = 8, 1596 .flags = 0, 1597 .max_register = FSL_SAI_MCTL, 1598 }; 1599 1600 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = { 1601 .use_imx_pcm = true, 1602 .use_edma = false, 1603 .fifo_depth = 128, 1604 .reg_offset = 8, 1605 .mclk0_is_mclk1 = false, 1606 .pins = 8, 1607 .flags = 0, 1608 .max_register = FSL_SAI_MDIV, 1609 }; 1610 1611 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1612 .use_imx_pcm = true, 1613 .use_edma = false, 1614 .fifo_depth = 128, 1615 .reg_offset = 8, 1616 .mclk0_is_mclk1 = false, 1617 .pins = 8, 1618 .flags = 0, 1619 .max_register = FSL_SAI_MDIV, 1620 .mclk_with_tere = true, 1621 }; 1622 1623 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1624 .use_imx_pcm = true, 1625 .use_edma = true, 1626 .fifo_depth = 16, 1627 .reg_offset = 8, 1628 .mclk0_is_mclk1 = false, 1629 .pins = 4, 1630 .flags = PMQOS_CPU_LATENCY, 1631 .max_register = FSL_SAI_RTCAP, 1632 }; 1633 1634 static const struct fsl_sai_soc_data fsl_sai_imx93_data = { 1635 .use_imx_pcm = true, 1636 .use_edma = true, 1637 .fifo_depth = 128, 1638 .reg_offset = 8, 1639 .mclk0_is_mclk1 = false, 1640 .pins = 4, 1641 .flags = 0, 1642 .max_register = FSL_SAI_MCTL, 1643 .max_burst = {8, 8}, 1644 }; 1645 1646 static const struct of_device_id fsl_sai_ids[] = { 1647 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1648 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1649 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1650 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1651 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1652 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1653 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1654 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1655 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1656 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data }, 1657 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data }, 1658 { /* sentinel */ } 1659 }; 1660 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1661 1662 static int fsl_sai_runtime_suspend(struct device *dev) 1663 { 1664 struct fsl_sai *sai = dev_get_drvdata(dev); 1665 1666 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1667 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1668 1669 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1670 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1671 1672 clk_disable_unprepare(sai->bus_clk); 1673 1674 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1675 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1676 1677 regcache_cache_only(sai->regmap, true); 1678 1679 return 0; 1680 } 1681 1682 static int fsl_sai_runtime_resume(struct device *dev) 1683 { 1684 struct fsl_sai *sai = dev_get_drvdata(dev); 1685 unsigned int ofs = sai->soc_data->reg_offset; 1686 int ret; 1687 1688 ret = clk_prepare_enable(sai->bus_clk); 1689 if (ret) { 1690 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1691 return ret; 1692 } 1693 1694 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1695 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1696 if (ret) 1697 goto disable_bus_clk; 1698 } 1699 1700 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1701 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1702 if (ret) 1703 goto disable_tx_clk; 1704 } 1705 1706 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1707 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1708 1709 regcache_cache_only(sai->regmap, false); 1710 regcache_mark_dirty(sai->regmap); 1711 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1712 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1713 usleep_range(1000, 2000); 1714 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1715 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1716 1717 ret = regcache_sync(sai->regmap); 1718 if (ret) 1719 goto disable_rx_clk; 1720 1721 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 1722 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), 1723 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 1724 1725 return 0; 1726 1727 disable_rx_clk: 1728 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1729 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1730 disable_tx_clk: 1731 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1732 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1733 disable_bus_clk: 1734 clk_disable_unprepare(sai->bus_clk); 1735 1736 return ret; 1737 } 1738 1739 static const struct dev_pm_ops fsl_sai_pm_ops = { 1740 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1741 fsl_sai_runtime_resume, NULL) 1742 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1743 pm_runtime_force_resume) 1744 }; 1745 1746 static struct platform_driver fsl_sai_driver = { 1747 .probe = fsl_sai_probe, 1748 .remove_new = fsl_sai_remove, 1749 .driver = { 1750 .name = "fsl-sai", 1751 .pm = &fsl_sai_pm_ops, 1752 .of_match_table = fsl_sai_ids, 1753 }, 1754 }; 1755 module_platform_driver(fsl_sai_driver); 1756 1757 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1758 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1759 MODULE_ALIAS("platform:fsl-sai"); 1760 MODULE_LICENSE("GPL"); 1761