1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/pm_qos.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/time.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 24 25 #include "fsl_sai.h" 26 #include "fsl_utils.h" 27 #include "imx-pcm.h" 28 29 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 30 FSL_SAI_CSR_FEIE) 31 32 static const unsigned int fsl_sai_rates[] = { 33 8000, 11025, 12000, 16000, 22050, 34 24000, 32000, 44100, 48000, 64000, 35 88200, 96000, 176400, 192000, 352800, 36 384000, 705600, 768000, 1411200, 2822400, 37 }; 38 39 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 40 .count = ARRAY_SIZE(fsl_sai_rates), 41 .list = fsl_sai_rates, 42 }; 43 44 /** 45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 46 * 47 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 48 * or Receiver's for both streams. This function is used to check if clocks of 49 * the stream's are synced by the opposite stream. 50 * 51 * @sai: SAI context 52 * @dir: stream direction 53 */ 54 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 55 { 56 int adir = (dir == TX) ? RX : TX; 57 58 /* current dir in async mode while opposite dir in sync mode */ 59 return !sai->synchronous[dir] && sai->synchronous[adir]; 60 } 61 62 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 63 { 64 struct pinctrl_state *state = NULL; 65 66 if (sai->is_pdm_mode) { 67 /* DSD512@44.1kHz, DSD512@48kHz */ 68 if (bclk >= 22579200) 69 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 70 71 /* Get default DSD state */ 72 if (IS_ERR_OR_NULL(state)) 73 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 74 } else { 75 /* 706k32b2c, 768k32b2c, etc */ 76 if (bclk >= 45158400) 77 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 78 } 79 80 /* Get default state */ 81 if (IS_ERR_OR_NULL(state)) 82 state = pinctrl_lookup_state(sai->pinctrl, "default"); 83 84 return state; 85 } 86 87 static irqreturn_t fsl_sai_isr(int irq, void *devid) 88 { 89 struct fsl_sai *sai = (struct fsl_sai *)devid; 90 unsigned int ofs = sai->soc_data->reg_offset; 91 struct device *dev = &sai->pdev->dev; 92 u32 flags, xcsr, mask; 93 irqreturn_t iret = IRQ_NONE; 94 95 /* 96 * Both IRQ status bits and IRQ mask bits are in the xCSR but 97 * different shifts. And we here create a mask only for those 98 * IRQs that we activated. 99 */ 100 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 101 102 /* Tx IRQ */ 103 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 104 flags = xcsr & mask; 105 106 if (flags) 107 iret = IRQ_HANDLED; 108 else 109 goto irq_rx; 110 111 if (flags & FSL_SAI_CSR_WSF) 112 dev_dbg(dev, "isr: Start of Tx word detected\n"); 113 114 if (flags & FSL_SAI_CSR_SEF) 115 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 116 117 if (flags & FSL_SAI_CSR_FEF) 118 dev_dbg(dev, "isr: Transmit underrun detected\n"); 119 120 if (flags & FSL_SAI_CSR_FWF) 121 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 122 123 if (flags & FSL_SAI_CSR_FRF) 124 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 125 126 flags &= FSL_SAI_CSR_xF_W_MASK; 127 xcsr &= ~FSL_SAI_CSR_xF_MASK; 128 129 if (flags) 130 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 131 132 irq_rx: 133 /* Rx IRQ */ 134 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 135 flags = xcsr & mask; 136 137 if (flags) 138 iret = IRQ_HANDLED; 139 else 140 goto out; 141 142 if (flags & FSL_SAI_CSR_WSF) 143 dev_dbg(dev, "isr: Start of Rx word detected\n"); 144 145 if (flags & FSL_SAI_CSR_SEF) 146 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 147 148 if (flags & FSL_SAI_CSR_FEF) 149 dev_dbg(dev, "isr: Receive overflow detected\n"); 150 151 if (flags & FSL_SAI_CSR_FWF) 152 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 153 154 if (flags & FSL_SAI_CSR_FRF) 155 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 156 157 flags &= FSL_SAI_CSR_xF_W_MASK; 158 xcsr &= ~FSL_SAI_CSR_xF_MASK; 159 160 if (flags) 161 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 162 163 out: 164 return iret; 165 } 166 167 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 168 u32 rx_mask, int slots, int slot_width) 169 { 170 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 171 172 sai->slots = slots; 173 sai->slot_width = slot_width; 174 175 return 0; 176 } 177 178 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 179 unsigned int ratio) 180 { 181 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 182 183 sai->bclk_ratio = ratio; 184 185 return 0; 186 } 187 188 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 189 int clk_id, unsigned int freq, bool tx) 190 { 191 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 192 unsigned int ofs = sai->soc_data->reg_offset; 193 u32 val_cr2 = 0; 194 195 switch (clk_id) { 196 case FSL_SAI_CLK_BUS: 197 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 198 break; 199 case FSL_SAI_CLK_MAST1: 200 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 201 break; 202 case FSL_SAI_CLK_MAST2: 203 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 204 break; 205 case FSL_SAI_CLK_MAST3: 206 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 207 break; 208 default: 209 return -EINVAL; 210 } 211 212 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 213 FSL_SAI_CR2_MSEL_MASK, val_cr2); 214 215 return 0; 216 } 217 218 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 219 { 220 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 221 int ret; 222 223 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 224 sai->pll8k_clk, sai->pll11k_clk, freq); 225 226 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 227 if (ret < 0) 228 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 229 230 return ret; 231 } 232 233 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 234 int clk_id, unsigned int freq, int dir) 235 { 236 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 237 int ret; 238 239 if (dir == SND_SOC_CLOCK_IN) 240 return 0; 241 242 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) { 243 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 244 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 245 return -EINVAL; 246 } 247 248 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 249 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 250 return -EINVAL; 251 } 252 253 if (sai->mclk_streams == 0) { 254 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq); 255 if (ret < 0) 256 return ret; 257 } 258 } 259 260 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 261 if (ret) { 262 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 263 return ret; 264 } 265 266 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 267 if (ret) 268 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 269 270 return ret; 271 } 272 273 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 274 unsigned int fmt, bool tx) 275 { 276 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 277 unsigned int ofs = sai->soc_data->reg_offset; 278 u32 val_cr2 = 0, val_cr4 = 0; 279 280 if (!sai->is_lsb_first) 281 val_cr4 |= FSL_SAI_CR4_MF; 282 283 sai->is_pdm_mode = false; 284 sai->is_dsp_mode = false; 285 /* DAI mode */ 286 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 287 case SND_SOC_DAIFMT_I2S: 288 /* 289 * Frame low, 1clk before data, one word length for frame sync, 290 * frame sync starts one serial clock cycle earlier, 291 * that is, together with the last bit of the previous 292 * data word. 293 */ 294 val_cr2 |= FSL_SAI_CR2_BCP; 295 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 296 break; 297 case SND_SOC_DAIFMT_LEFT_J: 298 /* 299 * Frame high, one word length for frame sync, 300 * frame sync asserts with the first bit of the frame. 301 */ 302 val_cr2 |= FSL_SAI_CR2_BCP; 303 break; 304 case SND_SOC_DAIFMT_DSP_A: 305 /* 306 * Frame high, 1clk before data, one bit for frame sync, 307 * frame sync starts one serial clock cycle earlier, 308 * that is, together with the last bit of the previous 309 * data word. 310 */ 311 val_cr2 |= FSL_SAI_CR2_BCP; 312 val_cr4 |= FSL_SAI_CR4_FSE; 313 sai->is_dsp_mode = true; 314 break; 315 case SND_SOC_DAIFMT_DSP_B: 316 /* 317 * Frame high, one bit for frame sync, 318 * frame sync asserts with the first bit of the frame. 319 */ 320 val_cr2 |= FSL_SAI_CR2_BCP; 321 sai->is_dsp_mode = true; 322 break; 323 case SND_SOC_DAIFMT_PDM: 324 val_cr2 |= FSL_SAI_CR2_BCP; 325 val_cr4 &= ~FSL_SAI_CR4_MF; 326 sai->is_pdm_mode = true; 327 break; 328 case SND_SOC_DAIFMT_RIGHT_J: 329 /* To be done */ 330 default: 331 return -EINVAL; 332 } 333 334 /* DAI clock inversion */ 335 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 336 case SND_SOC_DAIFMT_IB_IF: 337 /* Invert both clocks */ 338 val_cr2 ^= FSL_SAI_CR2_BCP; 339 val_cr4 ^= FSL_SAI_CR4_FSP; 340 break; 341 case SND_SOC_DAIFMT_IB_NF: 342 /* Invert bit clock */ 343 val_cr2 ^= FSL_SAI_CR2_BCP; 344 break; 345 case SND_SOC_DAIFMT_NB_IF: 346 /* Invert frame clock */ 347 val_cr4 ^= FSL_SAI_CR4_FSP; 348 break; 349 case SND_SOC_DAIFMT_NB_NF: 350 /* Nothing to do for both normal cases */ 351 break; 352 default: 353 return -EINVAL; 354 } 355 356 /* DAI clock provider masks */ 357 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 358 case SND_SOC_DAIFMT_BP_FP: 359 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 360 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 361 sai->is_consumer_mode = false; 362 break; 363 case SND_SOC_DAIFMT_BC_FC: 364 sai->is_consumer_mode = true; 365 break; 366 case SND_SOC_DAIFMT_BP_FC: 367 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 368 sai->is_consumer_mode = false; 369 break; 370 case SND_SOC_DAIFMT_BC_FP: 371 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 372 sai->is_consumer_mode = true; 373 break; 374 default: 375 return -EINVAL; 376 } 377 378 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 379 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 380 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 381 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 382 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 383 384 return 0; 385 } 386 387 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 388 { 389 int ret; 390 391 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 392 if (ret) { 393 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 394 return ret; 395 } 396 397 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 398 if (ret) 399 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 400 401 return ret; 402 } 403 404 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 405 { 406 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 407 unsigned int reg, ofs = sai->soc_data->reg_offset; 408 unsigned long clk_rate; 409 u32 savediv = 0, ratio, bestdiff = freq; 410 int adir = tx ? RX : TX; 411 int dir = tx ? TX : RX; 412 u32 id; 413 bool support_1_1_ratio = sai->verid.version >= 0x0301; 414 415 /* Don't apply to consumer mode */ 416 if (sai->is_consumer_mode) 417 return 0; 418 419 /* 420 * There is no point in polling MCLK0 if it is identical to MCLK1. 421 * And given that MQS use case has to use MCLK1 though two clocks 422 * are the same, we simply skip MCLK0 and start to find from MCLK1. 423 */ 424 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 425 426 for (; id < FSL_SAI_MCLK_MAX; id++) { 427 int diff; 428 429 clk_rate = clk_get_rate(sai->mclk_clk[id]); 430 if (!clk_rate) 431 continue; 432 433 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 434 if (!ratio || ratio > 512) 435 continue; 436 if (ratio == 1 && !support_1_1_ratio) 437 continue; 438 if ((ratio & 1) && ratio > 1) 439 continue; 440 441 diff = abs((long)clk_rate - ratio * freq); 442 443 /* 444 * Drop the source that can not be 445 * divided into the required rate. 446 */ 447 if (diff != 0 && clk_rate / diff < 1000) 448 continue; 449 450 dev_dbg(dai->dev, 451 "ratio %d for freq %dHz based on clock %ldHz\n", 452 ratio, freq, clk_rate); 453 454 455 if (diff < bestdiff) { 456 savediv = ratio; 457 sai->mclk_id[tx] = id; 458 bestdiff = diff; 459 } 460 461 if (diff == 0) 462 break; 463 } 464 465 if (savediv == 0) { 466 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 467 tx ? 'T' : 'R', freq); 468 return -EINVAL; 469 } 470 471 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 472 sai->mclk_id[tx], savediv, bestdiff); 473 474 /* 475 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 476 * set TCR2 register for playback. 477 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 478 * and capture. 479 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 480 * and capture. 481 * 4) For Tx and Rx are both Synchronous with another SAI, we just 482 * ignore it. 483 */ 484 if (fsl_sai_dir_is_synced(sai, adir)) 485 reg = FSL_SAI_xCR2(!tx, ofs); 486 else if (!sai->synchronous[dir]) 487 reg = FSL_SAI_xCR2(tx, ofs); 488 else 489 return 0; 490 491 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 492 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 493 494 if (savediv == 1) { 495 regmap_update_bits(sai->regmap, reg, 496 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 497 FSL_SAI_CR2_BYP); 498 if (fsl_sai_dir_is_synced(sai, adir)) 499 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 500 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI); 501 else 502 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 503 FSL_SAI_CR2_BCI, 0); 504 } else { 505 regmap_update_bits(sai->regmap, reg, 506 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 507 savediv / 2 - 1); 508 } 509 510 return 0; 511 } 512 513 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 514 struct snd_pcm_hw_params *params, 515 struct snd_soc_dai *cpu_dai) 516 { 517 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 518 unsigned int ofs = sai->soc_data->reg_offset; 519 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 520 unsigned int channels = params_channels(params); 521 struct snd_dmaengine_dai_dma_data *dma_params; 522 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 523 u32 word_width = params_width(params); 524 int trce_mask = 0, dl_cfg_idx = 0; 525 int dl_cfg_cnt = sai->dl_cfg_cnt; 526 u32 dl_type = FSL_SAI_DL_I2S; 527 u32 val_cr4 = 0, val_cr5 = 0; 528 u32 slots = (channels == 1) ? 2 : channels; 529 u32 slot_width = word_width; 530 int adir = tx ? RX : TX; 531 u32 pins, bclk; 532 u32 watermark; 533 int ret, i; 534 535 if (sai->slot_width) 536 slot_width = sai->slot_width; 537 538 if (sai->slots) 539 slots = sai->slots; 540 else if (sai->bclk_ratio) 541 slots = sai->bclk_ratio / slot_width; 542 543 pins = DIV_ROUND_UP(channels, slots); 544 545 /* 546 * PDM mode, channels are independent 547 * each channels are on one dataline/FIFO. 548 */ 549 if (sai->is_pdm_mode) { 550 pins = channels; 551 dl_type = FSL_SAI_DL_PDM; 552 } 553 554 for (i = 0; i < dl_cfg_cnt; i++) { 555 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 556 dl_cfg_idx = i; 557 break; 558 } 559 } 560 561 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 562 dev_err(cpu_dai->dev, "channel not supported\n"); 563 return -EINVAL; 564 } 565 566 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 567 568 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 569 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 570 if (!IS_ERR_OR_NULL(sai->pins_state)) { 571 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 572 if (ret) { 573 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 574 return ret; 575 } 576 } 577 } 578 579 if (!sai->is_consumer_mode) { 580 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 581 if (ret) 582 return ret; 583 584 /* Do not enable the clock if it is already enabled */ 585 if (!(sai->mclk_streams & BIT(substream->stream))) { 586 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 587 if (ret) 588 return ret; 589 590 sai->mclk_streams |= BIT(substream->stream); 591 } 592 } 593 594 if (!sai->is_dsp_mode && !sai->is_pdm_mode) 595 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 596 597 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 598 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 599 600 if (sai->is_lsb_first || sai->is_pdm_mode) 601 val_cr5 |= FSL_SAI_CR5_FBT(0); 602 else 603 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 604 605 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 606 607 /* Set to output mode to avoid tri-stated data pins */ 608 if (tx) 609 val_cr4 |= FSL_SAI_CR4_CHMOD; 610 611 /* 612 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 613 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 614 * RCR5(TCR5) for playback(capture), or there will be sync error. 615 */ 616 617 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { 618 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 619 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 620 FSL_SAI_CR4_CHMOD_MASK, 621 val_cr4); 622 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 623 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 624 FSL_SAI_CR5_FBT_MASK, val_cr5); 625 } 626 627 /* 628 * Combine mode has limation: 629 * - Can't used for singel dataline/FIFO case except the FIFO0 630 * - Can't used for multi dataline/FIFO case except the enabled FIFOs 631 * are successive and start from FIFO0 632 * 633 * So for common usage, all multi fifo case disable the combine mode. 634 */ 635 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) 636 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 637 FSL_SAI_CR4_FCOMB_MASK, 0); 638 else 639 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 640 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 641 642 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 643 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 644 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 645 646 if (sai->is_multi_fifo_dma) { 647 sai->audio_config[tx].words_per_fifo = min(slots, channels); 648 if (tx) { 649 sai->audio_config[tx].n_fifos_dst = pins; 650 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; 651 } else { 652 sai->audio_config[tx].n_fifos_src = pins; 653 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; 654 } 655 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; 656 dma_params->peripheral_config = &sai->audio_config[tx]; 657 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); 658 659 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : 660 (dma_params->maxburst - 1); 661 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), 662 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 663 watermark); 664 } 665 666 /* Find a proper tcre setting */ 667 for (i = 0; i < sai->soc_data->pins; i++) { 668 trce_mask = (1 << (i + 1)) - 1; 669 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 670 break; 671 } 672 673 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 674 FSL_SAI_CR3_TRCE_MASK, 675 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 676 677 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 678 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 679 FSL_SAI_CR4_CHMOD_MASK, 680 val_cr4); 681 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 682 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 683 FSL_SAI_CR5_FBT_MASK, val_cr5); 684 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 685 ~0UL - ((1 << min(channels, slots)) - 1)); 686 687 return 0; 688 } 689 690 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 691 struct snd_soc_dai *cpu_dai) 692 { 693 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 694 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 695 unsigned int ofs = sai->soc_data->reg_offset; 696 697 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 698 FSL_SAI_CR3_TRCE_MASK, 0); 699 700 if (!sai->is_consumer_mode && 701 sai->mclk_streams & BIT(substream->stream)) { 702 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 703 sai->mclk_streams &= ~BIT(substream->stream); 704 } 705 706 return 0; 707 } 708 709 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 710 { 711 unsigned int ofs = sai->soc_data->reg_offset; 712 bool tx = dir == TX; 713 u32 xcsr, count = 100; 714 715 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 716 FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE, 0); 717 718 /* TERE will remain set till the end of current frame */ 719 do { 720 udelay(10); 721 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 722 } while (--count && xcsr & FSL_SAI_CSR_TERE); 723 724 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 725 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 726 727 /* 728 * For sai master mode, after several open/close sai, 729 * there will be no frame clock, and can't recover 730 * anymore. Add software reset to fix this issue. 731 * This is a hardware bug, and will be fix in the 732 * next sai version. 733 */ 734 if (!sai->is_consumer_mode) { 735 /* Software Reset */ 736 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 737 /* Clear SR bit to finish the reset */ 738 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 739 } 740 } 741 742 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 743 struct snd_soc_dai *cpu_dai) 744 { 745 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 746 unsigned int ofs = sai->soc_data->reg_offset; 747 748 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 749 int adir = tx ? RX : TX; 750 int dir = tx ? TX : RX; 751 u32 xcsr; 752 753 /* 754 * Asynchronous mode: Clear SYNC for both Tx and Rx. 755 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 756 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 757 */ 758 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 759 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 760 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 761 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 762 763 /* 764 * It is recommended that the transmitter is the last enabled 765 * and the first disabled. 766 */ 767 switch (cmd) { 768 case SNDRV_PCM_TRIGGER_START: 769 case SNDRV_PCM_TRIGGER_RESUME: 770 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 771 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 772 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 773 774 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 775 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 776 /* 777 * Enable the opposite direction for synchronous mode 778 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 779 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 780 * 781 * RM recommends to enable RE after TE for case 1 and to enable 782 * TE after RE for case 2, but we here may not always guarantee 783 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 784 * TE after RE, which is against what RM recommends but should 785 * be safe to do, judging by years of testing results. 786 */ 787 if (fsl_sai_dir_is_synced(sai, adir)) 788 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 789 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 790 791 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 792 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 793 break; 794 case SNDRV_PCM_TRIGGER_STOP: 795 case SNDRV_PCM_TRIGGER_SUSPEND: 796 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 797 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 798 FSL_SAI_CSR_FRDE, 0); 799 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 800 FSL_SAI_CSR_xIE_MASK, 0); 801 802 /* Check if the opposite FRDE is also disabled */ 803 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 804 805 /* 806 * If opposite stream provides clocks for synchronous mode and 807 * it is inactive, disable it before disabling the current one 808 */ 809 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 810 fsl_sai_config_disable(sai, adir); 811 812 /* 813 * Disable current stream if either of: 814 * 1. current stream doesn't provide clocks for synchronous mode 815 * 2. current stream provides clocks for synchronous mode but no 816 * more stream is active. 817 */ 818 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 819 fsl_sai_config_disable(sai, dir); 820 821 break; 822 default: 823 return -EINVAL; 824 } 825 826 return 0; 827 } 828 829 static int fsl_sai_startup(struct snd_pcm_substream *substream, 830 struct snd_soc_dai *cpu_dai) 831 { 832 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 833 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 834 int ret; 835 836 /* 837 * EDMA controller needs period size to be a multiple of 838 * tx/rx maxburst 839 */ 840 if (sai->soc_data->use_edma) 841 snd_pcm_hw_constraint_step(substream->runtime, 0, 842 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 843 tx ? sai->dma_params_tx.maxburst : 844 sai->dma_params_rx.maxburst); 845 846 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 847 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 848 849 return ret; 850 } 851 852 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 853 { 854 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 855 unsigned int ofs = sai->soc_data->reg_offset; 856 857 /* Software Reset for both Tx and Rx */ 858 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 859 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 860 /* Clear SR bit to finish the reset */ 861 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 862 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 863 864 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 865 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 866 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst); 867 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 868 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 869 sai->dma_params_rx.maxburst - 1); 870 871 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 872 &sai->dma_params_rx); 873 874 return 0; 875 } 876 877 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 878 .probe = fsl_sai_dai_probe, 879 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 880 .set_sysclk = fsl_sai_set_dai_sysclk, 881 .set_fmt = fsl_sai_set_dai_fmt, 882 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 883 .hw_params = fsl_sai_hw_params, 884 .hw_free = fsl_sai_hw_free, 885 .trigger = fsl_sai_trigger, 886 .startup = fsl_sai_startup, 887 }; 888 889 static int fsl_sai_dai_resume(struct snd_soc_component *component) 890 { 891 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 892 struct device *dev = &sai->pdev->dev; 893 int ret; 894 895 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 896 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 897 if (ret) { 898 dev_err(dev, "failed to set proper pins state: %d\n", ret); 899 return ret; 900 } 901 } 902 903 return 0; 904 } 905 906 static struct snd_soc_dai_driver fsl_sai_dai_template = { 907 .playback = { 908 .stream_name = "CPU-Playback", 909 .channels_min = 1, 910 .channels_max = 32, 911 .rate_min = 8000, 912 .rate_max = 2822400, 913 .rates = SNDRV_PCM_RATE_KNOT, 914 .formats = FSL_SAI_FORMATS, 915 }, 916 .capture = { 917 .stream_name = "CPU-Capture", 918 .channels_min = 1, 919 .channels_max = 32, 920 .rate_min = 8000, 921 .rate_max = 2822400, 922 .rates = SNDRV_PCM_RATE_KNOT, 923 .formats = FSL_SAI_FORMATS, 924 }, 925 .ops = &fsl_sai_pcm_dai_ops, 926 }; 927 928 static const struct snd_soc_component_driver fsl_component = { 929 .name = "fsl-sai", 930 .resume = fsl_sai_dai_resume, 931 .legacy_dai_naming = 1, 932 }; 933 934 static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 935 {FSL_SAI_TCR1(0), 0}, 936 {FSL_SAI_TCR2(0), 0}, 937 {FSL_SAI_TCR3(0), 0}, 938 {FSL_SAI_TCR4(0), 0}, 939 {FSL_SAI_TCR5(0), 0}, 940 {FSL_SAI_TDR0, 0}, 941 {FSL_SAI_TDR1, 0}, 942 {FSL_SAI_TDR2, 0}, 943 {FSL_SAI_TDR3, 0}, 944 {FSL_SAI_TDR4, 0}, 945 {FSL_SAI_TDR5, 0}, 946 {FSL_SAI_TDR6, 0}, 947 {FSL_SAI_TDR7, 0}, 948 {FSL_SAI_TMR, 0}, 949 {FSL_SAI_RCR1(0), 0}, 950 {FSL_SAI_RCR2(0), 0}, 951 {FSL_SAI_RCR3(0), 0}, 952 {FSL_SAI_RCR4(0), 0}, 953 {FSL_SAI_RCR5(0), 0}, 954 {FSL_SAI_RMR, 0}, 955 }; 956 957 static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 958 {FSL_SAI_TCR1(8), 0}, 959 {FSL_SAI_TCR2(8), 0}, 960 {FSL_SAI_TCR3(8), 0}, 961 {FSL_SAI_TCR4(8), 0}, 962 {FSL_SAI_TCR5(8), 0}, 963 {FSL_SAI_TDR0, 0}, 964 {FSL_SAI_TDR1, 0}, 965 {FSL_SAI_TDR2, 0}, 966 {FSL_SAI_TDR3, 0}, 967 {FSL_SAI_TDR4, 0}, 968 {FSL_SAI_TDR5, 0}, 969 {FSL_SAI_TDR6, 0}, 970 {FSL_SAI_TDR7, 0}, 971 {FSL_SAI_TMR, 0}, 972 {FSL_SAI_RCR1(8), 0}, 973 {FSL_SAI_RCR2(8), 0}, 974 {FSL_SAI_RCR3(8), 0}, 975 {FSL_SAI_RCR4(8), 0}, 976 {FSL_SAI_RCR5(8), 0}, 977 {FSL_SAI_RMR, 0}, 978 {FSL_SAI_MCTL, 0}, 979 {FSL_SAI_MDIV, 0}, 980 }; 981 982 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 983 { 984 struct fsl_sai *sai = dev_get_drvdata(dev); 985 unsigned int ofs = sai->soc_data->reg_offset; 986 987 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 988 return true; 989 990 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 991 return true; 992 993 switch (reg) { 994 case FSL_SAI_TFR0: 995 case FSL_SAI_TFR1: 996 case FSL_SAI_TFR2: 997 case FSL_SAI_TFR3: 998 case FSL_SAI_TFR4: 999 case FSL_SAI_TFR5: 1000 case FSL_SAI_TFR6: 1001 case FSL_SAI_TFR7: 1002 case FSL_SAI_TMR: 1003 case FSL_SAI_RDR0: 1004 case FSL_SAI_RDR1: 1005 case FSL_SAI_RDR2: 1006 case FSL_SAI_RDR3: 1007 case FSL_SAI_RDR4: 1008 case FSL_SAI_RDR5: 1009 case FSL_SAI_RDR6: 1010 case FSL_SAI_RDR7: 1011 case FSL_SAI_RFR0: 1012 case FSL_SAI_RFR1: 1013 case FSL_SAI_RFR2: 1014 case FSL_SAI_RFR3: 1015 case FSL_SAI_RFR4: 1016 case FSL_SAI_RFR5: 1017 case FSL_SAI_RFR6: 1018 case FSL_SAI_RFR7: 1019 case FSL_SAI_RMR: 1020 case FSL_SAI_MCTL: 1021 case FSL_SAI_MDIV: 1022 case FSL_SAI_VERID: 1023 case FSL_SAI_PARAM: 1024 case FSL_SAI_TTCTN: 1025 case FSL_SAI_RTCTN: 1026 case FSL_SAI_TTCTL: 1027 case FSL_SAI_TBCTN: 1028 case FSL_SAI_TTCAP: 1029 case FSL_SAI_RTCTL: 1030 case FSL_SAI_RBCTN: 1031 case FSL_SAI_RTCAP: 1032 return true; 1033 default: 1034 return false; 1035 } 1036 } 1037 1038 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1039 { 1040 struct fsl_sai *sai = dev_get_drvdata(dev); 1041 unsigned int ofs = sai->soc_data->reg_offset; 1042 1043 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1044 return true; 1045 1046 /* Set VERID and PARAM be volatile for reading value in probe */ 1047 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1048 return true; 1049 1050 switch (reg) { 1051 case FSL_SAI_TFR0: 1052 case FSL_SAI_TFR1: 1053 case FSL_SAI_TFR2: 1054 case FSL_SAI_TFR3: 1055 case FSL_SAI_TFR4: 1056 case FSL_SAI_TFR5: 1057 case FSL_SAI_TFR6: 1058 case FSL_SAI_TFR7: 1059 case FSL_SAI_RFR0: 1060 case FSL_SAI_RFR1: 1061 case FSL_SAI_RFR2: 1062 case FSL_SAI_RFR3: 1063 case FSL_SAI_RFR4: 1064 case FSL_SAI_RFR5: 1065 case FSL_SAI_RFR6: 1066 case FSL_SAI_RFR7: 1067 case FSL_SAI_RDR0: 1068 case FSL_SAI_RDR1: 1069 case FSL_SAI_RDR2: 1070 case FSL_SAI_RDR3: 1071 case FSL_SAI_RDR4: 1072 case FSL_SAI_RDR5: 1073 case FSL_SAI_RDR6: 1074 case FSL_SAI_RDR7: 1075 return true; 1076 default: 1077 return false; 1078 } 1079 } 1080 1081 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1082 { 1083 struct fsl_sai *sai = dev_get_drvdata(dev); 1084 unsigned int ofs = sai->soc_data->reg_offset; 1085 1086 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1087 return true; 1088 1089 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1090 return true; 1091 1092 switch (reg) { 1093 case FSL_SAI_TDR0: 1094 case FSL_SAI_TDR1: 1095 case FSL_SAI_TDR2: 1096 case FSL_SAI_TDR3: 1097 case FSL_SAI_TDR4: 1098 case FSL_SAI_TDR5: 1099 case FSL_SAI_TDR6: 1100 case FSL_SAI_TDR7: 1101 case FSL_SAI_TMR: 1102 case FSL_SAI_RMR: 1103 case FSL_SAI_MCTL: 1104 case FSL_SAI_MDIV: 1105 case FSL_SAI_TTCTL: 1106 case FSL_SAI_RTCTL: 1107 return true; 1108 default: 1109 return false; 1110 } 1111 } 1112 1113 static struct regmap_config fsl_sai_regmap_config = { 1114 .reg_bits = 32, 1115 .reg_stride = 4, 1116 .val_bits = 32, 1117 .fast_io = true, 1118 1119 .max_register = FSL_SAI_RMR, 1120 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1121 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1122 .readable_reg = fsl_sai_readable_reg, 1123 .volatile_reg = fsl_sai_volatile_reg, 1124 .writeable_reg = fsl_sai_writeable_reg, 1125 .cache_type = REGCACHE_FLAT, 1126 }; 1127 1128 static int fsl_sai_check_version(struct device *dev) 1129 { 1130 struct fsl_sai *sai = dev_get_drvdata(dev); 1131 unsigned char ofs = sai->soc_data->reg_offset; 1132 unsigned int val; 1133 int ret; 1134 1135 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1136 return 0; 1137 1138 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1139 if (ret < 0) 1140 return ret; 1141 1142 dev_dbg(dev, "VERID: 0x%016X\n", val); 1143 1144 sai->verid.version = val & 1145 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1146 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT; 1147 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1148 1149 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1150 if (ret < 0) 1151 return ret; 1152 1153 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1154 1155 /* Max slots per frame, power of 2 */ 1156 sai->param.slot_num = 1 << 1157 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1158 1159 /* Words per fifo, power of 2 */ 1160 sai->param.fifo_depth = 1 << 1161 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1162 1163 /* Number of datalines implemented */ 1164 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1165 1166 return 0; 1167 } 1168 1169 /* 1170 * Calculate the offset between first two datalines, don't 1171 * different offset in one case. 1172 */ 1173 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1174 { 1175 int fbidx, nbidx, offset; 1176 1177 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1178 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1179 offset = nbidx - fbidx - 1; 1180 1181 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1182 } 1183 1184 /* 1185 * read the fsl,dataline property from dts file. 1186 * It has 3 value for each configuration, first one means the type: 1187 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1188 * dataline mask for 'tx'. for example 1189 * 1190 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1191 * 1192 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1193 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1194 * 1195 */ 1196 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1197 { 1198 struct platform_device *pdev = sai->pdev; 1199 struct device_node *np = pdev->dev.of_node; 1200 struct device *dev = &pdev->dev; 1201 int ret, elems, i, index, num_cfg; 1202 char *propname = "fsl,dataline"; 1203 struct fsl_sai_dl_cfg *cfg; 1204 unsigned long dl_mask; 1205 unsigned int soc_dl; 1206 u32 rx, tx, type; 1207 1208 elems = of_property_count_u32_elems(np, propname); 1209 1210 if (elems <= 0) { 1211 elems = 0; 1212 } else if (elems % 3) { 1213 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1214 return -EINVAL; 1215 } 1216 1217 num_cfg = elems / 3; 1218 /* Add one more for default value */ 1219 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL); 1220 if (!cfg) 1221 return -ENOMEM; 1222 1223 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1224 soc_dl = BIT(sai->soc_data->pins) - 1; 1225 cfg[0].type = FSL_SAI_DL_DEFAULT; 1226 cfg[0].pins[0] = sai->soc_data->pins; 1227 cfg[0].mask[0] = soc_dl; 1228 cfg[0].start_off[0] = 0; 1229 cfg[0].next_off[0] = 0; 1230 1231 cfg[0].pins[1] = sai->soc_data->pins; 1232 cfg[0].mask[1] = soc_dl; 1233 cfg[0].start_off[1] = 0; 1234 cfg[0].next_off[1] = 0; 1235 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1236 /* 1237 * type of dataline 1238 * 0 means default mode 1239 * 1 means I2S mode 1240 * 2 means PDM mode 1241 */ 1242 ret = of_property_read_u32_index(np, propname, index++, &type); 1243 if (ret) 1244 return -EINVAL; 1245 1246 ret = of_property_read_u32_index(np, propname, index++, &rx); 1247 if (ret) 1248 return -EINVAL; 1249 1250 ret = of_property_read_u32_index(np, propname, index++, &tx); 1251 if (ret) 1252 return -EINVAL; 1253 1254 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1255 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1256 return -EINVAL; 1257 } 1258 1259 rx = rx & soc_dl; 1260 tx = tx & soc_dl; 1261 1262 cfg[i].type = type; 1263 cfg[i].pins[0] = hweight8(rx); 1264 cfg[i].mask[0] = rx; 1265 dl_mask = rx; 1266 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1267 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1268 1269 cfg[i].pins[1] = hweight8(tx); 1270 cfg[i].mask[1] = tx; 1271 dl_mask = tx; 1272 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1273 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1274 } 1275 1276 sai->dl_cfg = cfg; 1277 sai->dl_cfg_cnt = num_cfg + 1; 1278 return 0; 1279 } 1280 1281 static int fsl_sai_runtime_suspend(struct device *dev); 1282 static int fsl_sai_runtime_resume(struct device *dev); 1283 1284 static int fsl_sai_probe(struct platform_device *pdev) 1285 { 1286 struct device_node *np = pdev->dev.of_node; 1287 struct device *dev = &pdev->dev; 1288 struct fsl_sai *sai; 1289 struct regmap *gpr; 1290 void __iomem *base; 1291 char tmp[8]; 1292 int irq, ret, i; 1293 int index; 1294 u32 dmas[4]; 1295 1296 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1297 if (!sai) 1298 return -ENOMEM; 1299 1300 sai->pdev = pdev; 1301 sai->soc_data = of_device_get_match_data(dev); 1302 1303 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1304 1305 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1306 if (IS_ERR(base)) 1307 return PTR_ERR(base); 1308 1309 if (sai->soc_data->reg_offset == 8) { 1310 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1311 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1312 fsl_sai_regmap_config.num_reg_defaults = 1313 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1314 } 1315 1316 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1317 if (IS_ERR(sai->regmap)) { 1318 dev_err(dev, "regmap init failed\n"); 1319 return PTR_ERR(sai->regmap); 1320 } 1321 1322 sai->bus_clk = devm_clk_get(dev, "bus"); 1323 /* Compatible with old DTB cases */ 1324 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1325 sai->bus_clk = devm_clk_get(dev, "sai"); 1326 if (IS_ERR(sai->bus_clk)) { 1327 dev_err(dev, "failed to get bus clock: %ld\n", 1328 PTR_ERR(sai->bus_clk)); 1329 /* -EPROBE_DEFER */ 1330 return PTR_ERR(sai->bus_clk); 1331 } 1332 1333 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1334 sprintf(tmp, "mclk%d", i); 1335 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1336 if (IS_ERR(sai->mclk_clk[i])) { 1337 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1338 i, PTR_ERR(sai->mclk_clk[i])); 1339 sai->mclk_clk[i] = NULL; 1340 } 1341 } 1342 1343 if (sai->soc_data->mclk0_is_mclk1) 1344 sai->mclk_clk[0] = sai->mclk_clk[1]; 1345 else 1346 sai->mclk_clk[0] = sai->bus_clk; 1347 1348 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1349 &sai->pll11k_clk); 1350 1351 /* Use Multi FIFO mode depending on the support from SDMA script */ 1352 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1353 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) 1354 sai->is_multi_fifo_dma = true; 1355 1356 /* read dataline mask for rx and tx*/ 1357 ret = fsl_sai_read_dlcfg(sai); 1358 if (ret < 0) { 1359 dev_err(dev, "failed to read dlcfg %d\n", ret); 1360 return ret; 1361 } 1362 1363 irq = platform_get_irq(pdev, 0); 1364 if (irq < 0) 1365 return irq; 1366 1367 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1368 np->name, sai); 1369 if (ret) { 1370 dev_err(dev, "failed to claim irq %u\n", irq); 1371 return ret; 1372 } 1373 1374 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1375 sizeof(fsl_sai_dai_template)); 1376 1377 /* Sync Tx with Rx as default by following old DT binding */ 1378 sai->synchronous[RX] = true; 1379 sai->synchronous[TX] = false; 1380 sai->cpu_dai_drv.symmetric_rate = 1; 1381 sai->cpu_dai_drv.symmetric_channels = 1; 1382 sai->cpu_dai_drv.symmetric_sample_bits = 1; 1383 1384 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") && 1385 of_property_read_bool(np, "fsl,sai-asynchronous")) { 1386 /* error out if both synchronous and asynchronous are present */ 1387 dev_err(dev, "invalid binding for synchronous mode\n"); 1388 return -EINVAL; 1389 } 1390 1391 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) { 1392 /* Sync Rx with Tx */ 1393 sai->synchronous[RX] = false; 1394 sai->synchronous[TX] = true; 1395 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) { 1396 /* Discard all settings for asynchronous mode */ 1397 sai->synchronous[RX] = false; 1398 sai->synchronous[TX] = false; 1399 sai->cpu_dai_drv.symmetric_rate = 0; 1400 sai->cpu_dai_drv.symmetric_channels = 0; 1401 sai->cpu_dai_drv.symmetric_sample_bits = 0; 1402 } 1403 1404 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output"); 1405 1406 if (sai->mclk_direction_output && 1407 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1408 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1409 if (IS_ERR(gpr)) { 1410 dev_err(dev, "cannot find iomuxc registers\n"); 1411 return PTR_ERR(gpr); 1412 } 1413 1414 index = of_alias_get_id(np, "sai"); 1415 if (index < 0) 1416 return index; 1417 1418 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1419 MCLK_DIR(index)); 1420 } 1421 1422 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1423 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1424 sai->dma_params_rx.maxburst = 1425 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX; 1426 sai->dma_params_tx.maxburst = 1427 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX; 1428 1429 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1430 1431 platform_set_drvdata(pdev, sai); 1432 pm_runtime_enable(dev); 1433 if (!pm_runtime_enabled(dev)) { 1434 ret = fsl_sai_runtime_resume(dev); 1435 if (ret) 1436 goto err_pm_disable; 1437 } 1438 1439 ret = pm_runtime_resume_and_get(dev); 1440 if (ret < 0) 1441 goto err_pm_get_sync; 1442 1443 /* Get sai version */ 1444 ret = fsl_sai_check_version(dev); 1445 if (ret < 0) 1446 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1447 1448 /* Select MCLK direction */ 1449 if (sai->mclk_direction_output && 1450 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1451 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1452 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1453 } 1454 1455 ret = pm_runtime_put_sync(dev); 1456 if (ret < 0 && ret != -ENOSYS) 1457 goto err_pm_get_sync; 1458 1459 /* 1460 * Register platform component before registering cpu dai for there 1461 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1462 */ 1463 if (sai->soc_data->use_imx_pcm) { 1464 ret = imx_pcm_dma_init(pdev); 1465 if (ret) { 1466 dev_err_probe(dev, ret, "PCM DMA init failed\n"); 1467 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1468 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1469 goto err_pm_get_sync; 1470 } 1471 } else { 1472 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1473 if (ret) { 1474 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n"); 1475 goto err_pm_get_sync; 1476 } 1477 } 1478 1479 ret = devm_snd_soc_register_component(dev, &fsl_component, 1480 &sai->cpu_dai_drv, 1); 1481 if (ret) 1482 goto err_pm_get_sync; 1483 1484 return ret; 1485 1486 err_pm_get_sync: 1487 if (!pm_runtime_status_suspended(dev)) 1488 fsl_sai_runtime_suspend(dev); 1489 err_pm_disable: 1490 pm_runtime_disable(dev); 1491 1492 return ret; 1493 } 1494 1495 static void fsl_sai_remove(struct platform_device *pdev) 1496 { 1497 pm_runtime_disable(&pdev->dev); 1498 if (!pm_runtime_status_suspended(&pdev->dev)) 1499 fsl_sai_runtime_suspend(&pdev->dev); 1500 } 1501 1502 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1503 .use_imx_pcm = false, 1504 .use_edma = false, 1505 .fifo_depth = 32, 1506 .pins = 1, 1507 .reg_offset = 0, 1508 .mclk0_is_mclk1 = false, 1509 .flags = 0, 1510 .max_register = FSL_SAI_RMR, 1511 }; 1512 1513 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1514 .use_imx_pcm = true, 1515 .use_edma = false, 1516 .fifo_depth = 32, 1517 .pins = 1, 1518 .reg_offset = 0, 1519 .mclk0_is_mclk1 = true, 1520 .flags = 0, 1521 .max_register = FSL_SAI_RMR, 1522 }; 1523 1524 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1525 .use_imx_pcm = true, 1526 .use_edma = false, 1527 .fifo_depth = 16, 1528 .pins = 2, 1529 .reg_offset = 8, 1530 .mclk0_is_mclk1 = false, 1531 .flags = PMQOS_CPU_LATENCY, 1532 .max_register = FSL_SAI_RMR, 1533 }; 1534 1535 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1536 .use_imx_pcm = true, 1537 .use_edma = false, 1538 .fifo_depth = 128, 1539 .pins = 8, 1540 .reg_offset = 8, 1541 .mclk0_is_mclk1 = false, 1542 .flags = 0, 1543 .max_register = FSL_SAI_RMR, 1544 }; 1545 1546 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1547 .use_imx_pcm = true, 1548 .use_edma = true, 1549 .fifo_depth = 64, 1550 .pins = 4, 1551 .reg_offset = 0, 1552 .mclk0_is_mclk1 = false, 1553 .flags = 0, 1554 .max_register = FSL_SAI_RMR, 1555 }; 1556 1557 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1558 .use_imx_pcm = true, 1559 .use_edma = false, 1560 .fifo_depth = 128, 1561 .reg_offset = 8, 1562 .mclk0_is_mclk1 = false, 1563 .pins = 8, 1564 .flags = 0, 1565 .max_register = FSL_SAI_MCTL, 1566 }; 1567 1568 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = { 1569 .use_imx_pcm = true, 1570 .use_edma = false, 1571 .fifo_depth = 128, 1572 .reg_offset = 8, 1573 .mclk0_is_mclk1 = false, 1574 .pins = 8, 1575 .flags = 0, 1576 .max_register = FSL_SAI_MDIV, 1577 }; 1578 1579 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1580 .use_imx_pcm = true, 1581 .use_edma = false, 1582 .fifo_depth = 128, 1583 .reg_offset = 8, 1584 .mclk0_is_mclk1 = false, 1585 .pins = 8, 1586 .flags = 0, 1587 .max_register = FSL_SAI_MDIV, 1588 .mclk_with_tere = true, 1589 }; 1590 1591 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1592 .use_imx_pcm = true, 1593 .use_edma = true, 1594 .fifo_depth = 16, 1595 .reg_offset = 8, 1596 .mclk0_is_mclk1 = false, 1597 .pins = 4, 1598 .flags = PMQOS_CPU_LATENCY, 1599 .max_register = FSL_SAI_RTCAP, 1600 }; 1601 1602 static const struct fsl_sai_soc_data fsl_sai_imx93_data = { 1603 .use_imx_pcm = true, 1604 .use_edma = true, 1605 .fifo_depth = 128, 1606 .reg_offset = 8, 1607 .mclk0_is_mclk1 = false, 1608 .pins = 4, 1609 .flags = 0, 1610 .max_register = FSL_SAI_MCTL, 1611 .max_burst = {8, 8}, 1612 }; 1613 1614 static const struct of_device_id fsl_sai_ids[] = { 1615 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1616 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1617 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1618 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1619 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1620 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1621 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1622 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1623 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1624 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data }, 1625 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data }, 1626 { /* sentinel */ } 1627 }; 1628 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1629 1630 static int fsl_sai_runtime_suspend(struct device *dev) 1631 { 1632 struct fsl_sai *sai = dev_get_drvdata(dev); 1633 1634 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1635 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1636 1637 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1638 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1639 1640 clk_disable_unprepare(sai->bus_clk); 1641 1642 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1643 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1644 1645 regcache_cache_only(sai->regmap, true); 1646 1647 return 0; 1648 } 1649 1650 static int fsl_sai_runtime_resume(struct device *dev) 1651 { 1652 struct fsl_sai *sai = dev_get_drvdata(dev); 1653 unsigned int ofs = sai->soc_data->reg_offset; 1654 int ret; 1655 1656 ret = clk_prepare_enable(sai->bus_clk); 1657 if (ret) { 1658 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1659 return ret; 1660 } 1661 1662 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1663 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1664 if (ret) 1665 goto disable_bus_clk; 1666 } 1667 1668 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1669 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1670 if (ret) 1671 goto disable_tx_clk; 1672 } 1673 1674 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1675 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1676 1677 regcache_cache_only(sai->regmap, false); 1678 regcache_mark_dirty(sai->regmap); 1679 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1680 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1681 usleep_range(1000, 2000); 1682 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1683 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1684 1685 ret = regcache_sync(sai->regmap); 1686 if (ret) 1687 goto disable_rx_clk; 1688 1689 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 1690 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), 1691 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 1692 1693 return 0; 1694 1695 disable_rx_clk: 1696 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1697 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1698 disable_tx_clk: 1699 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1700 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1701 disable_bus_clk: 1702 clk_disable_unprepare(sai->bus_clk); 1703 1704 return ret; 1705 } 1706 1707 static const struct dev_pm_ops fsl_sai_pm_ops = { 1708 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1709 fsl_sai_runtime_resume, NULL) 1710 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1711 pm_runtime_force_resume) 1712 }; 1713 1714 static struct platform_driver fsl_sai_driver = { 1715 .probe = fsl_sai_probe, 1716 .remove_new = fsl_sai_remove, 1717 .driver = { 1718 .name = "fsl-sai", 1719 .pm = &fsl_sai_pm_ops, 1720 .of_match_table = fsl_sai_ids, 1721 }, 1722 }; 1723 module_platform_driver(fsl_sai_driver); 1724 1725 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1726 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1727 MODULE_ALIAS("platform:fsl-sai"); 1728 MODULE_LICENSE("GPL"); 1729