1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/slab.h> 16 #include <linux/time.h> 17 #include <sound/core.h> 18 #include <sound/dmaengine_pcm.h> 19 #include <sound/pcm_params.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 22 23 #include "fsl_sai.h" 24 #include "imx-pcm.h" 25 26 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 27 FSL_SAI_CSR_FEIE) 28 29 static const unsigned int fsl_sai_rates[] = { 30 8000, 11025, 12000, 16000, 22050, 31 24000, 32000, 44100, 48000, 64000, 32 88200, 96000, 176400, 192000 33 }; 34 35 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 36 .count = ARRAY_SIZE(fsl_sai_rates), 37 .list = fsl_sai_rates, 38 }; 39 40 static irqreturn_t fsl_sai_isr(int irq, void *devid) 41 { 42 struct fsl_sai *sai = (struct fsl_sai *)devid; 43 struct device *dev = &sai->pdev->dev; 44 u32 flags, xcsr, mask; 45 bool irq_none = true; 46 47 /* 48 * Both IRQ status bits and IRQ mask bits are in the xCSR but 49 * different shifts. And we here create a mask only for those 50 * IRQs that we activated. 51 */ 52 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 53 54 /* Tx IRQ */ 55 regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr); 56 flags = xcsr & mask; 57 58 if (flags) 59 irq_none = false; 60 else 61 goto irq_rx; 62 63 if (flags & FSL_SAI_CSR_WSF) 64 dev_dbg(dev, "isr: Start of Tx word detected\n"); 65 66 if (flags & FSL_SAI_CSR_SEF) 67 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 68 69 if (flags & FSL_SAI_CSR_FEF) { 70 dev_dbg(dev, "isr: Transmit underrun detected\n"); 71 /* FIFO reset for safety */ 72 xcsr |= FSL_SAI_CSR_FR; 73 } 74 75 if (flags & FSL_SAI_CSR_FWF) 76 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 77 78 if (flags & FSL_SAI_CSR_FRF) 79 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 80 81 flags &= FSL_SAI_CSR_xF_W_MASK; 82 xcsr &= ~FSL_SAI_CSR_xF_MASK; 83 84 if (flags) 85 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr); 86 87 irq_rx: 88 /* Rx IRQ */ 89 regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr); 90 flags = xcsr & mask; 91 92 if (flags) 93 irq_none = false; 94 else 95 goto out; 96 97 if (flags & FSL_SAI_CSR_WSF) 98 dev_dbg(dev, "isr: Start of Rx word detected\n"); 99 100 if (flags & FSL_SAI_CSR_SEF) 101 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 102 103 if (flags & FSL_SAI_CSR_FEF) { 104 dev_dbg(dev, "isr: Receive overflow detected\n"); 105 /* FIFO reset for safety */ 106 xcsr |= FSL_SAI_CSR_FR; 107 } 108 109 if (flags & FSL_SAI_CSR_FWF) 110 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 111 112 if (flags & FSL_SAI_CSR_FRF) 113 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 114 115 flags &= FSL_SAI_CSR_xF_W_MASK; 116 xcsr &= ~FSL_SAI_CSR_xF_MASK; 117 118 if (flags) 119 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr); 120 121 out: 122 if (irq_none) 123 return IRQ_NONE; 124 else 125 return IRQ_HANDLED; 126 } 127 128 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 129 u32 rx_mask, int slots, int slot_width) 130 { 131 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 132 133 sai->slots = slots; 134 sai->slot_width = slot_width; 135 136 return 0; 137 } 138 139 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 140 int clk_id, unsigned int freq, int fsl_dir) 141 { 142 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 143 bool tx = fsl_dir == FSL_FMT_TRANSMITTER; 144 u32 val_cr2 = 0; 145 146 switch (clk_id) { 147 case FSL_SAI_CLK_BUS: 148 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 149 break; 150 case FSL_SAI_CLK_MAST1: 151 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 152 break; 153 case FSL_SAI_CLK_MAST2: 154 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 155 break; 156 case FSL_SAI_CLK_MAST3: 157 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 158 break; 159 default: 160 return -EINVAL; 161 } 162 163 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), 164 FSL_SAI_CR2_MSEL_MASK, val_cr2); 165 166 return 0; 167 } 168 169 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 170 int clk_id, unsigned int freq, int dir) 171 { 172 int ret; 173 174 if (dir == SND_SOC_CLOCK_IN) 175 return 0; 176 177 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, 178 FSL_FMT_TRANSMITTER); 179 if (ret) { 180 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 181 return ret; 182 } 183 184 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, 185 FSL_FMT_RECEIVER); 186 if (ret) 187 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 188 189 return ret; 190 } 191 192 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 193 unsigned int fmt, int fsl_dir) 194 { 195 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 196 bool tx = fsl_dir == FSL_FMT_TRANSMITTER; 197 u32 val_cr2 = 0, val_cr4 = 0; 198 199 if (!sai->is_lsb_first) 200 val_cr4 |= FSL_SAI_CR4_MF; 201 202 /* DAI mode */ 203 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 204 case SND_SOC_DAIFMT_I2S: 205 /* 206 * Frame low, 1clk before data, one word length for frame sync, 207 * frame sync starts one serial clock cycle earlier, 208 * that is, together with the last bit of the previous 209 * data word. 210 */ 211 val_cr2 |= FSL_SAI_CR2_BCP; 212 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 213 break; 214 case SND_SOC_DAIFMT_LEFT_J: 215 /* 216 * Frame high, one word length for frame sync, 217 * frame sync asserts with the first bit of the frame. 218 */ 219 val_cr2 |= FSL_SAI_CR2_BCP; 220 break; 221 case SND_SOC_DAIFMT_DSP_A: 222 /* 223 * Frame high, 1clk before data, one bit for frame sync, 224 * frame sync starts one serial clock cycle earlier, 225 * that is, together with the last bit of the previous 226 * data word. 227 */ 228 val_cr2 |= FSL_SAI_CR2_BCP; 229 val_cr4 |= FSL_SAI_CR4_FSE; 230 sai->is_dsp_mode = true; 231 break; 232 case SND_SOC_DAIFMT_DSP_B: 233 /* 234 * Frame high, one bit for frame sync, 235 * frame sync asserts with the first bit of the frame. 236 */ 237 val_cr2 |= FSL_SAI_CR2_BCP; 238 sai->is_dsp_mode = true; 239 break; 240 case SND_SOC_DAIFMT_RIGHT_J: 241 /* To be done */ 242 default: 243 return -EINVAL; 244 } 245 246 /* DAI clock inversion */ 247 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 248 case SND_SOC_DAIFMT_IB_IF: 249 /* Invert both clocks */ 250 val_cr2 ^= FSL_SAI_CR2_BCP; 251 val_cr4 ^= FSL_SAI_CR4_FSP; 252 break; 253 case SND_SOC_DAIFMT_IB_NF: 254 /* Invert bit clock */ 255 val_cr2 ^= FSL_SAI_CR2_BCP; 256 break; 257 case SND_SOC_DAIFMT_NB_IF: 258 /* Invert frame clock */ 259 val_cr4 ^= FSL_SAI_CR4_FSP; 260 break; 261 case SND_SOC_DAIFMT_NB_NF: 262 /* Nothing to do for both normal cases */ 263 break; 264 default: 265 return -EINVAL; 266 } 267 268 /* DAI clock master masks */ 269 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 270 case SND_SOC_DAIFMT_CBS_CFS: 271 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 272 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 273 sai->is_slave_mode = false; 274 break; 275 case SND_SOC_DAIFMT_CBM_CFM: 276 sai->is_slave_mode = true; 277 break; 278 case SND_SOC_DAIFMT_CBS_CFM: 279 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 280 sai->is_slave_mode = false; 281 break; 282 case SND_SOC_DAIFMT_CBM_CFS: 283 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 284 sai->is_slave_mode = true; 285 break; 286 default: 287 return -EINVAL; 288 } 289 290 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), 291 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 292 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), 293 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 294 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 295 296 return 0; 297 } 298 299 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 300 { 301 int ret; 302 303 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER); 304 if (ret) { 305 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 306 return ret; 307 } 308 309 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER); 310 if (ret) 311 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 312 313 return ret; 314 } 315 316 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 317 { 318 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 319 unsigned long clk_rate; 320 u32 savediv = 0, ratio, savesub = freq; 321 u32 id; 322 int ret = 0; 323 324 /* Don't apply to slave mode */ 325 if (sai->is_slave_mode) 326 return 0; 327 328 for (id = 0; id < FSL_SAI_MCLK_MAX; id++) { 329 clk_rate = clk_get_rate(sai->mclk_clk[id]); 330 if (!clk_rate) 331 continue; 332 333 ratio = clk_rate / freq; 334 335 ret = clk_rate - ratio * freq; 336 337 /* 338 * Drop the source that can not be 339 * divided into the required rate. 340 */ 341 if (ret != 0 && clk_rate / ret < 1000) 342 continue; 343 344 dev_dbg(dai->dev, 345 "ratio %d for freq %dHz based on clock %ldHz\n", 346 ratio, freq, clk_rate); 347 348 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512) 349 ratio /= 2; 350 else 351 continue; 352 353 if (ret < savesub) { 354 savediv = ratio; 355 sai->mclk_id[tx] = id; 356 savesub = ret; 357 } 358 359 if (ret == 0) 360 break; 361 } 362 363 if (savediv == 0) { 364 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 365 tx ? 'T' : 'R', freq); 366 return -EINVAL; 367 } 368 369 /* 370 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 371 * set TCR2 register for playback. 372 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 373 * and capture. 374 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 375 * and capture. 376 * 4) For Tx and Rx are both Synchronous with another SAI, we just 377 * ignore it. 378 */ 379 if ((sai->synchronous[TX] && !sai->synchronous[RX]) || 380 (!tx && !sai->synchronous[RX])) { 381 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, 382 FSL_SAI_CR2_MSEL_MASK, 383 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 384 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, 385 FSL_SAI_CR2_DIV_MASK, savediv - 1); 386 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) || 387 (tx && !sai->synchronous[TX])) { 388 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, 389 FSL_SAI_CR2_MSEL_MASK, 390 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 391 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, 392 FSL_SAI_CR2_DIV_MASK, savediv - 1); 393 } 394 395 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 396 sai->mclk_id[tx], savediv, savesub); 397 398 return 0; 399 } 400 401 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 402 struct snd_pcm_hw_params *params, 403 struct snd_soc_dai *cpu_dai) 404 { 405 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 406 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 407 unsigned int channels = params_channels(params); 408 u32 word_width = params_width(params); 409 u32 val_cr4 = 0, val_cr5 = 0; 410 u32 slots = (channels == 1) ? 2 : channels; 411 u32 slot_width = word_width; 412 int ret; 413 414 if (sai->slots) 415 slots = sai->slots; 416 417 if (sai->slot_width) 418 slot_width = sai->slot_width; 419 420 if (!sai->is_slave_mode) { 421 ret = fsl_sai_set_bclk(cpu_dai, tx, 422 slots * slot_width * params_rate(params)); 423 if (ret) 424 return ret; 425 426 /* Do not enable the clock if it is already enabled */ 427 if (!(sai->mclk_streams & BIT(substream->stream))) { 428 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 429 if (ret) 430 return ret; 431 432 sai->mclk_streams |= BIT(substream->stream); 433 } 434 } 435 436 if (!sai->is_dsp_mode) 437 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 438 439 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 440 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 441 442 if (sai->is_lsb_first) 443 val_cr5 |= FSL_SAI_CR5_FBT(0); 444 else 445 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 446 447 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 448 449 /* 450 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 451 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 452 * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync 453 * error. 454 */ 455 456 if (!sai->is_slave_mode) { 457 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { 458 regmap_update_bits(sai->regmap, FSL_SAI_TCR4, 459 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, 460 val_cr4); 461 regmap_update_bits(sai->regmap, FSL_SAI_TCR5, 462 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 463 FSL_SAI_CR5_FBT_MASK, val_cr5); 464 regmap_write(sai->regmap, FSL_SAI_TMR, 465 ~0UL - ((1 << channels) - 1)); 466 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { 467 regmap_update_bits(sai->regmap, FSL_SAI_RCR4, 468 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, 469 val_cr4); 470 regmap_update_bits(sai->regmap, FSL_SAI_RCR5, 471 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 472 FSL_SAI_CR5_FBT_MASK, val_cr5); 473 regmap_write(sai->regmap, FSL_SAI_RMR, 474 ~0UL - ((1 << channels) - 1)); 475 } 476 } 477 478 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), 479 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, 480 val_cr4); 481 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx), 482 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 483 FSL_SAI_CR5_FBT_MASK, val_cr5); 484 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1)); 485 486 return 0; 487 } 488 489 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 490 struct snd_soc_dai *cpu_dai) 491 { 492 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 493 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 494 495 if (!sai->is_slave_mode && 496 sai->mclk_streams & BIT(substream->stream)) { 497 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 498 sai->mclk_streams &= ~BIT(substream->stream); 499 } 500 501 return 0; 502 } 503 504 505 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 506 struct snd_soc_dai *cpu_dai) 507 { 508 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 509 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 510 u32 xcsr, count = 100; 511 512 /* 513 * Asynchronous mode: Clear SYNC for both Tx and Rx. 514 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 515 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 516 */ 517 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, 518 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 519 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC, 520 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 521 522 /* 523 * It is recommended that the transmitter is the last enabled 524 * and the first disabled. 525 */ 526 switch (cmd) { 527 case SNDRV_PCM_TRIGGER_START: 528 case SNDRV_PCM_TRIGGER_RESUME: 529 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 530 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), 531 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 532 533 regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 534 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 535 regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 536 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 537 538 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), 539 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 540 break; 541 case SNDRV_PCM_TRIGGER_STOP: 542 case SNDRV_PCM_TRIGGER_SUSPEND: 543 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 544 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), 545 FSL_SAI_CSR_FRDE, 0); 546 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), 547 FSL_SAI_CSR_xIE_MASK, 0); 548 549 /* Check if the opposite FRDE is also disabled */ 550 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr); 551 if (!(xcsr & FSL_SAI_CSR_FRDE)) { 552 /* Disable both directions and reset their FIFOs */ 553 regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 554 FSL_SAI_CSR_TERE, 0); 555 regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 556 FSL_SAI_CSR_TERE, 0); 557 558 /* TERE will remain set till the end of current frame */ 559 do { 560 udelay(10); 561 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr); 562 } while (--count && xcsr & FSL_SAI_CSR_TERE); 563 564 regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 565 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 566 regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 567 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 568 569 /* 570 * For sai master mode, after several open/close sai, 571 * there will be no frame clock, and can't recover 572 * anymore. Add software reset to fix this issue. 573 * This is a hardware bug, and will be fix in the 574 * next sai version. 575 */ 576 if (!sai->is_slave_mode) { 577 /* Software Reset for both Tx and Rx */ 578 regmap_write(sai->regmap, 579 FSL_SAI_TCSR, FSL_SAI_CSR_SR); 580 regmap_write(sai->regmap, 581 FSL_SAI_RCSR, FSL_SAI_CSR_SR); 582 /* Clear SR bit to finish the reset */ 583 regmap_write(sai->regmap, FSL_SAI_TCSR, 0); 584 regmap_write(sai->regmap, FSL_SAI_RCSR, 0); 585 } 586 } 587 break; 588 default: 589 return -EINVAL; 590 } 591 592 return 0; 593 } 594 595 static int fsl_sai_startup(struct snd_pcm_substream *substream, 596 struct snd_soc_dai *cpu_dai) 597 { 598 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 599 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 600 int ret; 601 602 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 603 FSL_SAI_CR3_TRCE); 604 605 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 606 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 607 608 return ret; 609 } 610 611 static void fsl_sai_shutdown(struct snd_pcm_substream *substream, 612 struct snd_soc_dai *cpu_dai) 613 { 614 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 615 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 616 617 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0); 618 } 619 620 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 621 .set_sysclk = fsl_sai_set_dai_sysclk, 622 .set_fmt = fsl_sai_set_dai_fmt, 623 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 624 .hw_params = fsl_sai_hw_params, 625 .hw_free = fsl_sai_hw_free, 626 .trigger = fsl_sai_trigger, 627 .startup = fsl_sai_startup, 628 .shutdown = fsl_sai_shutdown, 629 }; 630 631 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 632 { 633 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 634 635 /* Software Reset for both Tx and Rx */ 636 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); 637 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); 638 /* Clear SR bit to finish the reset */ 639 regmap_write(sai->regmap, FSL_SAI_TCSR, 0); 640 regmap_write(sai->regmap, FSL_SAI_RCSR, 0); 641 642 regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK, 643 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); 644 regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK, 645 FSL_SAI_MAXBURST_RX - 1); 646 647 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 648 &sai->dma_params_rx); 649 650 snd_soc_dai_set_drvdata(cpu_dai, sai); 651 652 return 0; 653 } 654 655 static struct snd_soc_dai_driver fsl_sai_dai = { 656 .probe = fsl_sai_dai_probe, 657 .playback = { 658 .stream_name = "CPU-Playback", 659 .channels_min = 1, 660 .channels_max = 32, 661 .rate_min = 8000, 662 .rate_max = 192000, 663 .rates = SNDRV_PCM_RATE_KNOT, 664 .formats = FSL_SAI_FORMATS, 665 }, 666 .capture = { 667 .stream_name = "CPU-Capture", 668 .channels_min = 1, 669 .channels_max = 32, 670 .rate_min = 8000, 671 .rate_max = 192000, 672 .rates = SNDRV_PCM_RATE_KNOT, 673 .formats = FSL_SAI_FORMATS, 674 }, 675 .ops = &fsl_sai_pcm_dai_ops, 676 }; 677 678 static const struct snd_soc_component_driver fsl_component = { 679 .name = "fsl-sai", 680 }; 681 682 static struct reg_default fsl_sai_reg_defaults[] = { 683 {FSL_SAI_TCR1, 0}, 684 {FSL_SAI_TCR2, 0}, 685 {FSL_SAI_TCR3, 0}, 686 {FSL_SAI_TCR4, 0}, 687 {FSL_SAI_TCR5, 0}, 688 {FSL_SAI_TDR, 0}, 689 {FSL_SAI_TMR, 0}, 690 {FSL_SAI_RCR1, 0}, 691 {FSL_SAI_RCR2, 0}, 692 {FSL_SAI_RCR3, 0}, 693 {FSL_SAI_RCR4, 0}, 694 {FSL_SAI_RCR5, 0}, 695 {FSL_SAI_RMR, 0}, 696 }; 697 698 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 699 { 700 switch (reg) { 701 case FSL_SAI_TCSR: 702 case FSL_SAI_TCR1: 703 case FSL_SAI_TCR2: 704 case FSL_SAI_TCR3: 705 case FSL_SAI_TCR4: 706 case FSL_SAI_TCR5: 707 case FSL_SAI_TFR: 708 case FSL_SAI_TMR: 709 case FSL_SAI_RCSR: 710 case FSL_SAI_RCR1: 711 case FSL_SAI_RCR2: 712 case FSL_SAI_RCR3: 713 case FSL_SAI_RCR4: 714 case FSL_SAI_RCR5: 715 case FSL_SAI_RDR: 716 case FSL_SAI_RFR: 717 case FSL_SAI_RMR: 718 return true; 719 default: 720 return false; 721 } 722 } 723 724 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 725 { 726 switch (reg) { 727 case FSL_SAI_TCSR: 728 case FSL_SAI_RCSR: 729 case FSL_SAI_TFR: 730 case FSL_SAI_RFR: 731 case FSL_SAI_RDR: 732 return true; 733 default: 734 return false; 735 } 736 } 737 738 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 739 { 740 switch (reg) { 741 case FSL_SAI_TCSR: 742 case FSL_SAI_TCR1: 743 case FSL_SAI_TCR2: 744 case FSL_SAI_TCR3: 745 case FSL_SAI_TCR4: 746 case FSL_SAI_TCR5: 747 case FSL_SAI_TDR: 748 case FSL_SAI_TMR: 749 case FSL_SAI_RCSR: 750 case FSL_SAI_RCR1: 751 case FSL_SAI_RCR2: 752 case FSL_SAI_RCR3: 753 case FSL_SAI_RCR4: 754 case FSL_SAI_RCR5: 755 case FSL_SAI_RMR: 756 return true; 757 default: 758 return false; 759 } 760 } 761 762 static const struct regmap_config fsl_sai_regmap_config = { 763 .reg_bits = 32, 764 .reg_stride = 4, 765 .val_bits = 32, 766 .fast_io = true, 767 768 .max_register = FSL_SAI_RMR, 769 .reg_defaults = fsl_sai_reg_defaults, 770 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults), 771 .readable_reg = fsl_sai_readable_reg, 772 .volatile_reg = fsl_sai_volatile_reg, 773 .writeable_reg = fsl_sai_writeable_reg, 774 .cache_type = REGCACHE_FLAT, 775 }; 776 777 static int fsl_sai_probe(struct platform_device *pdev) 778 { 779 struct device_node *np = pdev->dev.of_node; 780 struct fsl_sai *sai; 781 struct regmap *gpr; 782 struct resource *res; 783 void __iomem *base; 784 char tmp[8]; 785 int irq, ret, i; 786 int index; 787 788 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 789 if (!sai) 790 return -ENOMEM; 791 792 sai->pdev = pdev; 793 sai->soc_data = of_device_get_match_data(&pdev->dev); 794 795 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 796 797 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 798 base = devm_ioremap_resource(&pdev->dev, res); 799 if (IS_ERR(base)) 800 return PTR_ERR(base); 801 802 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 803 "bus", base, &fsl_sai_regmap_config); 804 805 /* Compatible with old DTB cases */ 806 if (IS_ERR(sai->regmap)) 807 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 808 "sai", base, &fsl_sai_regmap_config); 809 if (IS_ERR(sai->regmap)) { 810 dev_err(&pdev->dev, "regmap init failed\n"); 811 return PTR_ERR(sai->regmap); 812 } 813 814 /* No error out for old DTB cases but only mark the clock NULL */ 815 sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); 816 if (IS_ERR(sai->bus_clk)) { 817 dev_err(&pdev->dev, "failed to get bus clock: %ld\n", 818 PTR_ERR(sai->bus_clk)); 819 sai->bus_clk = NULL; 820 } 821 822 sai->mclk_clk[0] = sai->bus_clk; 823 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 824 sprintf(tmp, "mclk%d", i); 825 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); 826 if (IS_ERR(sai->mclk_clk[i])) { 827 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n", 828 i + 1, PTR_ERR(sai->mclk_clk[i])); 829 sai->mclk_clk[i] = NULL; 830 } 831 } 832 833 irq = platform_get_irq(pdev, 0); 834 if (irq < 0) 835 return irq; 836 837 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai); 838 if (ret) { 839 dev_err(&pdev->dev, "failed to claim irq %u\n", irq); 840 return ret; 841 } 842 843 /* Sync Tx with Rx as default by following old DT binding */ 844 sai->synchronous[RX] = true; 845 sai->synchronous[TX] = false; 846 fsl_sai_dai.symmetric_rates = 1; 847 fsl_sai_dai.symmetric_channels = 1; 848 fsl_sai_dai.symmetric_samplebits = 1; 849 850 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && 851 of_find_property(np, "fsl,sai-asynchronous", NULL)) { 852 /* error out if both synchronous and asynchronous are present */ 853 dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); 854 return -EINVAL; 855 } 856 857 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { 858 /* Sync Rx with Tx */ 859 sai->synchronous[RX] = false; 860 sai->synchronous[TX] = true; 861 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { 862 /* Discard all settings for asynchronous mode */ 863 sai->synchronous[RX] = false; 864 sai->synchronous[TX] = false; 865 fsl_sai_dai.symmetric_rates = 0; 866 fsl_sai_dai.symmetric_channels = 0; 867 fsl_sai_dai.symmetric_samplebits = 0; 868 } 869 870 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 871 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 872 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 873 if (IS_ERR(gpr)) { 874 dev_err(&pdev->dev, "cannot find iomuxc registers\n"); 875 return PTR_ERR(gpr); 876 } 877 878 index = of_alias_get_id(np, "sai"); 879 if (index < 0) 880 return index; 881 882 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 883 MCLK_DIR(index)); 884 } 885 886 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR; 887 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR; 888 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; 889 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; 890 891 platform_set_drvdata(pdev, sai); 892 893 pm_runtime_enable(&pdev->dev); 894 895 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, 896 &fsl_sai_dai, 1); 897 if (ret) 898 return ret; 899 900 if (sai->soc_data->use_imx_pcm) 901 return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE); 902 else 903 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 904 } 905 906 static int fsl_sai_remove(struct platform_device *pdev) 907 { 908 pm_runtime_disable(&pdev->dev); 909 910 return 0; 911 } 912 913 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 914 .use_imx_pcm = false, 915 .fifo_depth = 32, 916 }; 917 918 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 919 .use_imx_pcm = true, 920 .fifo_depth = 32, 921 }; 922 923 static const struct of_device_id fsl_sai_ids[] = { 924 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 925 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 926 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 927 { /* sentinel */ } 928 }; 929 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 930 931 #ifdef CONFIG_PM 932 static int fsl_sai_runtime_suspend(struct device *dev) 933 { 934 struct fsl_sai *sai = dev_get_drvdata(dev); 935 936 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 937 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 938 939 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 940 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 941 942 clk_disable_unprepare(sai->bus_clk); 943 944 regcache_cache_only(sai->regmap, true); 945 regcache_mark_dirty(sai->regmap); 946 947 return 0; 948 } 949 950 static int fsl_sai_runtime_resume(struct device *dev) 951 { 952 struct fsl_sai *sai = dev_get_drvdata(dev); 953 int ret; 954 955 ret = clk_prepare_enable(sai->bus_clk); 956 if (ret) { 957 dev_err(dev, "failed to enable bus clock: %d\n", ret); 958 return ret; 959 } 960 961 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 962 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 963 if (ret) 964 goto disable_bus_clk; 965 } 966 967 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 968 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 969 if (ret) 970 goto disable_tx_clk; 971 } 972 973 regcache_cache_only(sai->regmap, false); 974 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); 975 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); 976 usleep_range(1000, 2000); 977 regmap_write(sai->regmap, FSL_SAI_TCSR, 0); 978 regmap_write(sai->regmap, FSL_SAI_RCSR, 0); 979 980 ret = regcache_sync(sai->regmap); 981 if (ret) 982 goto disable_rx_clk; 983 984 return 0; 985 986 disable_rx_clk: 987 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 988 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 989 disable_tx_clk: 990 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 991 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 992 disable_bus_clk: 993 clk_disable_unprepare(sai->bus_clk); 994 995 return ret; 996 } 997 #endif /* CONFIG_PM */ 998 999 static const struct dev_pm_ops fsl_sai_pm_ops = { 1000 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1001 fsl_sai_runtime_resume, NULL) 1002 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1003 pm_runtime_force_resume) 1004 }; 1005 1006 static struct platform_driver fsl_sai_driver = { 1007 .probe = fsl_sai_probe, 1008 .remove = fsl_sai_remove, 1009 .driver = { 1010 .name = "fsl-sai", 1011 .pm = &fsl_sai_pm_ops, 1012 .of_match_table = fsl_sai_ids, 1013 }, 1014 }; 1015 module_platform_driver(fsl_sai_driver); 1016 1017 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1018 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1019 MODULE_ALIAS("platform:fsl-sai"); 1020 MODULE_LICENSE("GPL"); 1021