1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/slab.h> 16 #include <linux/time.h> 17 #include <sound/core.h> 18 #include <sound/dmaengine_pcm.h> 19 #include <sound/pcm_params.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 22 23 #include "fsl_sai.h" 24 #include "imx-pcm.h" 25 26 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 27 FSL_SAI_CSR_FEIE) 28 29 static const unsigned int fsl_sai_rates[] = { 30 8000, 11025, 12000, 16000, 22050, 31 24000, 32000, 44100, 48000, 64000, 32 88200, 96000, 176400, 192000 33 }; 34 35 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 36 .count = ARRAY_SIZE(fsl_sai_rates), 37 .list = fsl_sai_rates, 38 }; 39 40 /** 41 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 42 * 43 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 44 * or Receiver's for both streams. This function is used to check if clocks of 45 * the stream's are synced by the opposite stream. 46 * 47 * @sai: SAI context 48 * @dir: stream direction 49 */ 50 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 51 { 52 int adir = (dir == TX) ? RX : TX; 53 54 /* current dir in async mode while opposite dir in sync mode */ 55 return !sai->synchronous[dir] && sai->synchronous[adir]; 56 } 57 58 static irqreturn_t fsl_sai_isr(int irq, void *devid) 59 { 60 struct fsl_sai *sai = (struct fsl_sai *)devid; 61 unsigned int ofs = sai->soc_data->reg_offset; 62 struct device *dev = &sai->pdev->dev; 63 u32 flags, xcsr, mask; 64 bool irq_none = true; 65 66 /* 67 * Both IRQ status bits and IRQ mask bits are in the xCSR but 68 * different shifts. And we here create a mask only for those 69 * IRQs that we activated. 70 */ 71 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 72 73 /* Tx IRQ */ 74 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 75 flags = xcsr & mask; 76 77 if (flags) 78 irq_none = false; 79 else 80 goto irq_rx; 81 82 if (flags & FSL_SAI_CSR_WSF) 83 dev_dbg(dev, "isr: Start of Tx word detected\n"); 84 85 if (flags & FSL_SAI_CSR_SEF) 86 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 87 88 if (flags & FSL_SAI_CSR_FEF) { 89 dev_dbg(dev, "isr: Transmit underrun detected\n"); 90 /* FIFO reset for safety */ 91 xcsr |= FSL_SAI_CSR_FR; 92 } 93 94 if (flags & FSL_SAI_CSR_FWF) 95 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 96 97 if (flags & FSL_SAI_CSR_FRF) 98 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 99 100 flags &= FSL_SAI_CSR_xF_W_MASK; 101 xcsr &= ~FSL_SAI_CSR_xF_MASK; 102 103 if (flags) 104 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 105 106 irq_rx: 107 /* Rx IRQ */ 108 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 109 flags = xcsr & mask; 110 111 if (flags) 112 irq_none = false; 113 else 114 goto out; 115 116 if (flags & FSL_SAI_CSR_WSF) 117 dev_dbg(dev, "isr: Start of Rx word detected\n"); 118 119 if (flags & FSL_SAI_CSR_SEF) 120 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 121 122 if (flags & FSL_SAI_CSR_FEF) { 123 dev_dbg(dev, "isr: Receive overflow detected\n"); 124 /* FIFO reset for safety */ 125 xcsr |= FSL_SAI_CSR_FR; 126 } 127 128 if (flags & FSL_SAI_CSR_FWF) 129 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 130 131 if (flags & FSL_SAI_CSR_FRF) 132 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 133 134 flags &= FSL_SAI_CSR_xF_W_MASK; 135 xcsr &= ~FSL_SAI_CSR_xF_MASK; 136 137 if (flags) 138 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 139 140 out: 141 if (irq_none) 142 return IRQ_NONE; 143 else 144 return IRQ_HANDLED; 145 } 146 147 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 148 u32 rx_mask, int slots, int slot_width) 149 { 150 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 151 152 sai->slots = slots; 153 sai->slot_width = slot_width; 154 155 return 0; 156 } 157 158 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 159 unsigned int ratio) 160 { 161 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 162 163 sai->bclk_ratio = ratio; 164 165 return 0; 166 } 167 168 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 169 int clk_id, unsigned int freq, int fsl_dir) 170 { 171 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 172 unsigned int ofs = sai->soc_data->reg_offset; 173 bool tx = fsl_dir == FSL_FMT_TRANSMITTER; 174 u32 val_cr2 = 0; 175 176 switch (clk_id) { 177 case FSL_SAI_CLK_BUS: 178 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 179 break; 180 case FSL_SAI_CLK_MAST1: 181 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 182 break; 183 case FSL_SAI_CLK_MAST2: 184 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 185 break; 186 case FSL_SAI_CLK_MAST3: 187 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 188 break; 189 default: 190 return -EINVAL; 191 } 192 193 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 194 FSL_SAI_CR2_MSEL_MASK, val_cr2); 195 196 return 0; 197 } 198 199 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 200 int clk_id, unsigned int freq, int dir) 201 { 202 int ret; 203 204 if (dir == SND_SOC_CLOCK_IN) 205 return 0; 206 207 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, 208 FSL_FMT_TRANSMITTER); 209 if (ret) { 210 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 211 return ret; 212 } 213 214 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, 215 FSL_FMT_RECEIVER); 216 if (ret) 217 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 218 219 return ret; 220 } 221 222 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 223 unsigned int fmt, int fsl_dir) 224 { 225 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 226 unsigned int ofs = sai->soc_data->reg_offset; 227 bool tx = fsl_dir == FSL_FMT_TRANSMITTER; 228 u32 val_cr2 = 0, val_cr4 = 0; 229 230 if (!sai->is_lsb_first) 231 val_cr4 |= FSL_SAI_CR4_MF; 232 233 /* DAI mode */ 234 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 235 case SND_SOC_DAIFMT_I2S: 236 /* 237 * Frame low, 1clk before data, one word length for frame sync, 238 * frame sync starts one serial clock cycle earlier, 239 * that is, together with the last bit of the previous 240 * data word. 241 */ 242 val_cr2 |= FSL_SAI_CR2_BCP; 243 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 244 break; 245 case SND_SOC_DAIFMT_LEFT_J: 246 /* 247 * Frame high, one word length for frame sync, 248 * frame sync asserts with the first bit of the frame. 249 */ 250 val_cr2 |= FSL_SAI_CR2_BCP; 251 break; 252 case SND_SOC_DAIFMT_DSP_A: 253 /* 254 * Frame high, 1clk before data, one bit for frame sync, 255 * frame sync starts one serial clock cycle earlier, 256 * that is, together with the last bit of the previous 257 * data word. 258 */ 259 val_cr2 |= FSL_SAI_CR2_BCP; 260 val_cr4 |= FSL_SAI_CR4_FSE; 261 sai->is_dsp_mode = true; 262 break; 263 case SND_SOC_DAIFMT_DSP_B: 264 /* 265 * Frame high, one bit for frame sync, 266 * frame sync asserts with the first bit of the frame. 267 */ 268 val_cr2 |= FSL_SAI_CR2_BCP; 269 sai->is_dsp_mode = true; 270 break; 271 case SND_SOC_DAIFMT_RIGHT_J: 272 /* To be done */ 273 default: 274 return -EINVAL; 275 } 276 277 /* DAI clock inversion */ 278 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 279 case SND_SOC_DAIFMT_IB_IF: 280 /* Invert both clocks */ 281 val_cr2 ^= FSL_SAI_CR2_BCP; 282 val_cr4 ^= FSL_SAI_CR4_FSP; 283 break; 284 case SND_SOC_DAIFMT_IB_NF: 285 /* Invert bit clock */ 286 val_cr2 ^= FSL_SAI_CR2_BCP; 287 break; 288 case SND_SOC_DAIFMT_NB_IF: 289 /* Invert frame clock */ 290 val_cr4 ^= FSL_SAI_CR4_FSP; 291 break; 292 case SND_SOC_DAIFMT_NB_NF: 293 /* Nothing to do for both normal cases */ 294 break; 295 default: 296 return -EINVAL; 297 } 298 299 /* DAI clock master masks */ 300 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 301 case SND_SOC_DAIFMT_CBS_CFS: 302 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 303 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 304 sai->is_slave_mode = false; 305 break; 306 case SND_SOC_DAIFMT_CBM_CFM: 307 sai->is_slave_mode = true; 308 break; 309 case SND_SOC_DAIFMT_CBS_CFM: 310 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 311 sai->is_slave_mode = false; 312 break; 313 case SND_SOC_DAIFMT_CBM_CFS: 314 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 315 sai->is_slave_mode = true; 316 break; 317 default: 318 return -EINVAL; 319 } 320 321 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 322 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 323 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 324 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 325 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 326 327 return 0; 328 } 329 330 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 331 { 332 int ret; 333 334 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER); 335 if (ret) { 336 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 337 return ret; 338 } 339 340 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER); 341 if (ret) 342 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 343 344 return ret; 345 } 346 347 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 348 { 349 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 350 unsigned int ofs = sai->soc_data->reg_offset; 351 unsigned long clk_rate; 352 u32 savediv = 0, ratio, savesub = freq; 353 int adir = tx ? RX : TX; 354 int dir = tx ? TX : RX; 355 u32 id; 356 int ret = 0; 357 358 /* Don't apply to slave mode */ 359 if (sai->is_slave_mode) 360 return 0; 361 362 /* 363 * There is no point in polling MCLK0 if it is identical to MCLK1. 364 * And given that MQS use case has to use MCLK1 though two clocks 365 * are the same, we simply skip MCLK0 and start to find from MCLK1. 366 */ 367 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 368 369 for (; id < FSL_SAI_MCLK_MAX; id++) { 370 clk_rate = clk_get_rate(sai->mclk_clk[id]); 371 if (!clk_rate) 372 continue; 373 374 ratio = clk_rate / freq; 375 376 ret = clk_rate - ratio * freq; 377 378 /* 379 * Drop the source that can not be 380 * divided into the required rate. 381 */ 382 if (ret != 0 && clk_rate / ret < 1000) 383 continue; 384 385 dev_dbg(dai->dev, 386 "ratio %d for freq %dHz based on clock %ldHz\n", 387 ratio, freq, clk_rate); 388 389 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512) 390 ratio /= 2; 391 else 392 continue; 393 394 if (ret < savesub) { 395 savediv = ratio; 396 sai->mclk_id[tx] = id; 397 savesub = ret; 398 } 399 400 if (ret == 0) 401 break; 402 } 403 404 if (savediv == 0) { 405 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 406 tx ? 'T' : 'R', freq); 407 return -EINVAL; 408 } 409 410 /* 411 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 412 * set TCR2 register for playback. 413 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 414 * and capture. 415 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 416 * and capture. 417 * 4) For Tx and Rx are both Synchronous with another SAI, we just 418 * ignore it. 419 */ 420 if (fsl_sai_dir_is_synced(sai, adir)) { 421 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs), 422 FSL_SAI_CR2_MSEL_MASK, 423 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 424 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs), 425 FSL_SAI_CR2_DIV_MASK, savediv - 1); 426 } else if (!sai->synchronous[dir]) { 427 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 428 FSL_SAI_CR2_MSEL_MASK, 429 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 430 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 431 FSL_SAI_CR2_DIV_MASK, savediv - 1); 432 } 433 434 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 435 sai->mclk_id[tx], savediv, savesub); 436 437 return 0; 438 } 439 440 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 441 struct snd_pcm_hw_params *params, 442 struct snd_soc_dai *cpu_dai) 443 { 444 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 445 unsigned int ofs = sai->soc_data->reg_offset; 446 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 447 unsigned int channels = params_channels(params); 448 u32 word_width = params_width(params); 449 u32 val_cr4 = 0, val_cr5 = 0; 450 u32 slots = (channels == 1) ? 2 : channels; 451 u32 slot_width = word_width; 452 int adir = tx ? RX : TX; 453 u32 pins; 454 int ret; 455 456 if (sai->slots) 457 slots = sai->slots; 458 459 if (sai->slot_width) 460 slot_width = sai->slot_width; 461 462 pins = DIV_ROUND_UP(channels, slots); 463 464 if (!sai->is_slave_mode) { 465 if (sai->bclk_ratio) 466 ret = fsl_sai_set_bclk(cpu_dai, tx, 467 sai->bclk_ratio * 468 params_rate(params)); 469 else 470 ret = fsl_sai_set_bclk(cpu_dai, tx, 471 slots * slot_width * 472 params_rate(params)); 473 if (ret) 474 return ret; 475 476 /* Do not enable the clock if it is already enabled */ 477 if (!(sai->mclk_streams & BIT(substream->stream))) { 478 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 479 if (ret) 480 return ret; 481 482 sai->mclk_streams |= BIT(substream->stream); 483 } 484 } 485 486 if (!sai->is_dsp_mode) 487 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 488 489 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 490 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 491 492 if (sai->is_lsb_first) 493 val_cr5 |= FSL_SAI_CR5_FBT(0); 494 else 495 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 496 497 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 498 499 /* Set to output mode to avoid tri-stated data pins */ 500 if (tx) 501 val_cr4 |= FSL_SAI_CR4_CHMOD; 502 503 /* 504 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 505 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 506 * RCR5(TCR5) for playback(capture), or there will be sync error. 507 */ 508 509 if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) { 510 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 511 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 512 FSL_SAI_CR4_CHMOD_MASK, 513 val_cr4); 514 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 515 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 516 FSL_SAI_CR5_FBT_MASK, val_cr5); 517 } 518 519 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 520 FSL_SAI_CR3_TRCE_MASK, 521 FSL_SAI_CR3_TRCE((1 << pins) - 1)); 522 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 523 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 524 FSL_SAI_CR4_CHMOD_MASK, 525 val_cr4); 526 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 527 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 528 FSL_SAI_CR5_FBT_MASK, val_cr5); 529 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 530 ~0UL - ((1 << min(channels, slots)) - 1)); 531 532 return 0; 533 } 534 535 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 536 struct snd_soc_dai *cpu_dai) 537 { 538 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 539 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 540 unsigned int ofs = sai->soc_data->reg_offset; 541 542 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 543 FSL_SAI_CR3_TRCE_MASK, 0); 544 545 if (!sai->is_slave_mode && 546 sai->mclk_streams & BIT(substream->stream)) { 547 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 548 sai->mclk_streams &= ~BIT(substream->stream); 549 } 550 551 return 0; 552 } 553 554 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 555 { 556 unsigned int ofs = sai->soc_data->reg_offset; 557 bool tx = dir == TX; 558 u32 xcsr, count = 100; 559 560 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 561 FSL_SAI_CSR_TERE, 0); 562 563 /* TERE will remain set till the end of current frame */ 564 do { 565 udelay(10); 566 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 567 } while (--count && xcsr & FSL_SAI_CSR_TERE); 568 569 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 570 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 571 572 /* 573 * For sai master mode, after several open/close sai, 574 * there will be no frame clock, and can't recover 575 * anymore. Add software reset to fix this issue. 576 * This is a hardware bug, and will be fix in the 577 * next sai version. 578 */ 579 if (!sai->is_slave_mode) { 580 /* Software Reset */ 581 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 582 /* Clear SR bit to finish the reset */ 583 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 584 } 585 } 586 587 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 588 struct snd_soc_dai *cpu_dai) 589 { 590 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 591 unsigned int ofs = sai->soc_data->reg_offset; 592 593 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 594 int adir = tx ? RX : TX; 595 int dir = tx ? TX : RX; 596 u32 xcsr; 597 598 /* 599 * Asynchronous mode: Clear SYNC for both Tx and Rx. 600 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 601 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 602 */ 603 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 604 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 605 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 606 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 607 608 /* 609 * It is recommended that the transmitter is the last enabled 610 * and the first disabled. 611 */ 612 switch (cmd) { 613 case SNDRV_PCM_TRIGGER_START: 614 case SNDRV_PCM_TRIGGER_RESUME: 615 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 616 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 617 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 618 619 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 620 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 621 /* 622 * Enable the opposite direction for synchronous mode 623 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 624 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 625 * 626 * RM recommends to enable RE after TE for case 1 and to enable 627 * TE after RE for case 2, but we here may not always guarantee 628 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 629 * TE after RE, which is against what RM recommends but should 630 * be safe to do, judging by years of testing results. 631 */ 632 if (fsl_sai_dir_is_synced(sai, adir)) 633 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 634 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 635 636 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 637 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 638 break; 639 case SNDRV_PCM_TRIGGER_STOP: 640 case SNDRV_PCM_TRIGGER_SUSPEND: 641 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 642 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 643 FSL_SAI_CSR_FRDE, 0); 644 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 645 FSL_SAI_CSR_xIE_MASK, 0); 646 647 /* Check if the opposite FRDE is also disabled */ 648 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 649 650 /* 651 * If opposite stream provides clocks for synchronous mode and 652 * it is inactive, disable it before disabling the current one 653 */ 654 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 655 fsl_sai_config_disable(sai, adir); 656 657 /* 658 * Disable current stream if either of: 659 * 1. current stream doesn't provide clocks for synchronous mode 660 * 2. current stream provides clocks for synchronous mode but no 661 * more stream is active. 662 */ 663 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 664 fsl_sai_config_disable(sai, dir); 665 666 break; 667 default: 668 return -EINVAL; 669 } 670 671 return 0; 672 } 673 674 static int fsl_sai_startup(struct snd_pcm_substream *substream, 675 struct snd_soc_dai *cpu_dai) 676 { 677 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 678 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 679 int ret; 680 681 /* 682 * EDMA controller needs period size to be a multiple of 683 * tx/rx maxburst 684 */ 685 if (sai->soc_data->use_edma) 686 snd_pcm_hw_constraint_step(substream->runtime, 0, 687 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 688 tx ? sai->dma_params_tx.maxburst : 689 sai->dma_params_rx.maxburst); 690 691 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 692 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 693 694 return ret; 695 } 696 697 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 698 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 699 .set_sysclk = fsl_sai_set_dai_sysclk, 700 .set_fmt = fsl_sai_set_dai_fmt, 701 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 702 .hw_params = fsl_sai_hw_params, 703 .hw_free = fsl_sai_hw_free, 704 .trigger = fsl_sai_trigger, 705 .startup = fsl_sai_startup, 706 }; 707 708 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 709 { 710 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 711 unsigned int ofs = sai->soc_data->reg_offset; 712 713 /* Software Reset for both Tx and Rx */ 714 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 715 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 716 /* Clear SR bit to finish the reset */ 717 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 718 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 719 720 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 721 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 722 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); 723 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 724 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 725 FSL_SAI_MAXBURST_RX - 1); 726 727 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 728 &sai->dma_params_rx); 729 730 snd_soc_dai_set_drvdata(cpu_dai, sai); 731 732 return 0; 733 } 734 735 static struct snd_soc_dai_driver fsl_sai_dai_template = { 736 .probe = fsl_sai_dai_probe, 737 .playback = { 738 .stream_name = "CPU-Playback", 739 .channels_min = 1, 740 .channels_max = 32, 741 .rate_min = 8000, 742 .rate_max = 192000, 743 .rates = SNDRV_PCM_RATE_KNOT, 744 .formats = FSL_SAI_FORMATS, 745 }, 746 .capture = { 747 .stream_name = "CPU-Capture", 748 .channels_min = 1, 749 .channels_max = 32, 750 .rate_min = 8000, 751 .rate_max = 192000, 752 .rates = SNDRV_PCM_RATE_KNOT, 753 .formats = FSL_SAI_FORMATS, 754 }, 755 .ops = &fsl_sai_pcm_dai_ops, 756 }; 757 758 static const struct snd_soc_component_driver fsl_component = { 759 .name = "fsl-sai", 760 }; 761 762 static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 763 {FSL_SAI_TCR1(0), 0}, 764 {FSL_SAI_TCR2(0), 0}, 765 {FSL_SAI_TCR3(0), 0}, 766 {FSL_SAI_TCR4(0), 0}, 767 {FSL_SAI_TCR5(0), 0}, 768 {FSL_SAI_TDR0, 0}, 769 {FSL_SAI_TDR1, 0}, 770 {FSL_SAI_TDR2, 0}, 771 {FSL_SAI_TDR3, 0}, 772 {FSL_SAI_TDR4, 0}, 773 {FSL_SAI_TDR5, 0}, 774 {FSL_SAI_TDR6, 0}, 775 {FSL_SAI_TDR7, 0}, 776 {FSL_SAI_TMR, 0}, 777 {FSL_SAI_RCR1(0), 0}, 778 {FSL_SAI_RCR2(0), 0}, 779 {FSL_SAI_RCR3(0), 0}, 780 {FSL_SAI_RCR4(0), 0}, 781 {FSL_SAI_RCR5(0), 0}, 782 {FSL_SAI_RMR, 0}, 783 }; 784 785 static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 786 {FSL_SAI_TCR1(8), 0}, 787 {FSL_SAI_TCR2(8), 0}, 788 {FSL_SAI_TCR3(8), 0}, 789 {FSL_SAI_TCR4(8), 0}, 790 {FSL_SAI_TCR5(8), 0}, 791 {FSL_SAI_TDR0, 0}, 792 {FSL_SAI_TDR1, 0}, 793 {FSL_SAI_TDR2, 0}, 794 {FSL_SAI_TDR3, 0}, 795 {FSL_SAI_TDR4, 0}, 796 {FSL_SAI_TDR5, 0}, 797 {FSL_SAI_TDR6, 0}, 798 {FSL_SAI_TDR7, 0}, 799 {FSL_SAI_TMR, 0}, 800 {FSL_SAI_RCR1(8), 0}, 801 {FSL_SAI_RCR2(8), 0}, 802 {FSL_SAI_RCR3(8), 0}, 803 {FSL_SAI_RCR4(8), 0}, 804 {FSL_SAI_RCR5(8), 0}, 805 {FSL_SAI_RMR, 0}, 806 {FSL_SAI_MCTL, 0}, 807 {FSL_SAI_MDIV, 0}, 808 }; 809 810 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 811 { 812 struct fsl_sai *sai = dev_get_drvdata(dev); 813 unsigned int ofs = sai->soc_data->reg_offset; 814 815 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 816 return true; 817 818 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 819 return true; 820 821 switch (reg) { 822 case FSL_SAI_TFR0: 823 case FSL_SAI_TFR1: 824 case FSL_SAI_TFR2: 825 case FSL_SAI_TFR3: 826 case FSL_SAI_TFR4: 827 case FSL_SAI_TFR5: 828 case FSL_SAI_TFR6: 829 case FSL_SAI_TFR7: 830 case FSL_SAI_TMR: 831 case FSL_SAI_RDR0: 832 case FSL_SAI_RDR1: 833 case FSL_SAI_RDR2: 834 case FSL_SAI_RDR3: 835 case FSL_SAI_RDR4: 836 case FSL_SAI_RDR5: 837 case FSL_SAI_RDR6: 838 case FSL_SAI_RDR7: 839 case FSL_SAI_RFR0: 840 case FSL_SAI_RFR1: 841 case FSL_SAI_RFR2: 842 case FSL_SAI_RFR3: 843 case FSL_SAI_RFR4: 844 case FSL_SAI_RFR5: 845 case FSL_SAI_RFR6: 846 case FSL_SAI_RFR7: 847 case FSL_SAI_RMR: 848 case FSL_SAI_MCTL: 849 case FSL_SAI_MDIV: 850 case FSL_SAI_VERID: 851 case FSL_SAI_PARAM: 852 case FSL_SAI_TTCTN: 853 case FSL_SAI_RTCTN: 854 case FSL_SAI_TTCTL: 855 case FSL_SAI_TBCTN: 856 case FSL_SAI_TTCAP: 857 case FSL_SAI_RTCTL: 858 case FSL_SAI_RBCTN: 859 case FSL_SAI_RTCAP: 860 return true; 861 default: 862 return false; 863 } 864 } 865 866 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 867 { 868 struct fsl_sai *sai = dev_get_drvdata(dev); 869 unsigned int ofs = sai->soc_data->reg_offset; 870 871 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 872 return true; 873 874 /* Set VERID and PARAM be volatile for reading value in probe */ 875 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 876 return true; 877 878 switch (reg) { 879 case FSL_SAI_TFR0: 880 case FSL_SAI_TFR1: 881 case FSL_SAI_TFR2: 882 case FSL_SAI_TFR3: 883 case FSL_SAI_TFR4: 884 case FSL_SAI_TFR5: 885 case FSL_SAI_TFR6: 886 case FSL_SAI_TFR7: 887 case FSL_SAI_RFR0: 888 case FSL_SAI_RFR1: 889 case FSL_SAI_RFR2: 890 case FSL_SAI_RFR3: 891 case FSL_SAI_RFR4: 892 case FSL_SAI_RFR5: 893 case FSL_SAI_RFR6: 894 case FSL_SAI_RFR7: 895 case FSL_SAI_RDR0: 896 case FSL_SAI_RDR1: 897 case FSL_SAI_RDR2: 898 case FSL_SAI_RDR3: 899 case FSL_SAI_RDR4: 900 case FSL_SAI_RDR5: 901 case FSL_SAI_RDR6: 902 case FSL_SAI_RDR7: 903 return true; 904 default: 905 return false; 906 } 907 } 908 909 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 910 { 911 struct fsl_sai *sai = dev_get_drvdata(dev); 912 unsigned int ofs = sai->soc_data->reg_offset; 913 914 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 915 return true; 916 917 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 918 return true; 919 920 switch (reg) { 921 case FSL_SAI_TDR0: 922 case FSL_SAI_TDR1: 923 case FSL_SAI_TDR2: 924 case FSL_SAI_TDR3: 925 case FSL_SAI_TDR4: 926 case FSL_SAI_TDR5: 927 case FSL_SAI_TDR6: 928 case FSL_SAI_TDR7: 929 case FSL_SAI_TMR: 930 case FSL_SAI_RMR: 931 case FSL_SAI_MCTL: 932 case FSL_SAI_MDIV: 933 case FSL_SAI_TTCTL: 934 case FSL_SAI_RTCTL: 935 return true; 936 default: 937 return false; 938 } 939 } 940 941 static struct regmap_config fsl_sai_regmap_config = { 942 .reg_bits = 32, 943 .reg_stride = 4, 944 .val_bits = 32, 945 .fast_io = true, 946 947 .max_register = FSL_SAI_RMR, 948 .reg_defaults = fsl_sai_reg_defaults_ofs0, 949 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 950 .readable_reg = fsl_sai_readable_reg, 951 .volatile_reg = fsl_sai_volatile_reg, 952 .writeable_reg = fsl_sai_writeable_reg, 953 .cache_type = REGCACHE_FLAT, 954 }; 955 956 static int fsl_sai_check_version(struct device *dev) 957 { 958 struct fsl_sai *sai = dev_get_drvdata(dev); 959 unsigned char ofs = sai->soc_data->reg_offset; 960 unsigned int val; 961 int ret; 962 963 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 964 return 0; 965 966 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 967 if (ret < 0) 968 return ret; 969 970 dev_dbg(dev, "VERID: 0x%016X\n", val); 971 972 sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >> 973 FSL_SAI_VERID_MAJOR_SHIFT; 974 sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >> 975 FSL_SAI_VERID_MINOR_SHIFT; 976 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 977 978 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 979 if (ret < 0) 980 return ret; 981 982 dev_dbg(dev, "PARAM: 0x%016X\n", val); 983 984 /* Max slots per frame, power of 2 */ 985 sai->param.slot_num = 1 << 986 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 987 988 /* Words per fifo, power of 2 */ 989 sai->param.fifo_depth = 1 << 990 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 991 992 /* Number of datalines implemented */ 993 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 994 995 return 0; 996 } 997 998 static int fsl_sai_probe(struct platform_device *pdev) 999 { 1000 struct device_node *np = pdev->dev.of_node; 1001 struct fsl_sai *sai; 1002 struct regmap *gpr; 1003 struct resource *res; 1004 void __iomem *base; 1005 char tmp[8]; 1006 int irq, ret, i; 1007 int index; 1008 1009 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1010 if (!sai) 1011 return -ENOMEM; 1012 1013 sai->pdev = pdev; 1014 sai->soc_data = of_device_get_match_data(&pdev->dev); 1015 1016 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1017 1018 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1019 base = devm_ioremap_resource(&pdev->dev, res); 1020 if (IS_ERR(base)) 1021 return PTR_ERR(base); 1022 1023 if (sai->soc_data->reg_offset == 8) { 1024 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1025 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1026 fsl_sai_regmap_config.num_reg_defaults = 1027 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1028 } 1029 1030 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 1031 "bus", base, &fsl_sai_regmap_config); 1032 1033 /* Compatible with old DTB cases */ 1034 if (IS_ERR(sai->regmap) && PTR_ERR(sai->regmap) != -EPROBE_DEFER) 1035 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 1036 "sai", base, &fsl_sai_regmap_config); 1037 if (IS_ERR(sai->regmap)) { 1038 dev_err(&pdev->dev, "regmap init failed\n"); 1039 return PTR_ERR(sai->regmap); 1040 } 1041 1042 /* No error out for old DTB cases but only mark the clock NULL */ 1043 sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); 1044 if (IS_ERR(sai->bus_clk)) { 1045 dev_err(&pdev->dev, "failed to get bus clock: %ld\n", 1046 PTR_ERR(sai->bus_clk)); 1047 sai->bus_clk = NULL; 1048 } 1049 1050 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1051 sprintf(tmp, "mclk%d", i); 1052 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); 1053 if (IS_ERR(sai->mclk_clk[i])) { 1054 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n", 1055 i + 1, PTR_ERR(sai->mclk_clk[i])); 1056 sai->mclk_clk[i] = NULL; 1057 } 1058 } 1059 1060 if (sai->soc_data->mclk0_is_mclk1) 1061 sai->mclk_clk[0] = sai->mclk_clk[1]; 1062 else 1063 sai->mclk_clk[0] = sai->bus_clk; 1064 1065 irq = platform_get_irq(pdev, 0); 1066 if (irq < 0) 1067 return irq; 1068 1069 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, IRQF_SHARED, 1070 np->name, sai); 1071 if (ret) { 1072 dev_err(&pdev->dev, "failed to claim irq %u\n", irq); 1073 return ret; 1074 } 1075 1076 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1077 sizeof(fsl_sai_dai_template)); 1078 1079 /* Sync Tx with Rx as default by following old DT binding */ 1080 sai->synchronous[RX] = true; 1081 sai->synchronous[TX] = false; 1082 sai->cpu_dai_drv.symmetric_rates = 1; 1083 sai->cpu_dai_drv.symmetric_channels = 1; 1084 sai->cpu_dai_drv.symmetric_samplebits = 1; 1085 1086 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && 1087 of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1088 /* error out if both synchronous and asynchronous are present */ 1089 dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); 1090 return -EINVAL; 1091 } 1092 1093 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { 1094 /* Sync Rx with Tx */ 1095 sai->synchronous[RX] = false; 1096 sai->synchronous[TX] = true; 1097 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1098 /* Discard all settings for asynchronous mode */ 1099 sai->synchronous[RX] = false; 1100 sai->synchronous[TX] = false; 1101 sai->cpu_dai_drv.symmetric_rates = 0; 1102 sai->cpu_dai_drv.symmetric_channels = 0; 1103 sai->cpu_dai_drv.symmetric_samplebits = 0; 1104 } 1105 1106 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1107 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1108 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1109 if (IS_ERR(gpr)) { 1110 dev_err(&pdev->dev, "cannot find iomuxc registers\n"); 1111 return PTR_ERR(gpr); 1112 } 1113 1114 index = of_alias_get_id(np, "sai"); 1115 if (index < 0) 1116 return index; 1117 1118 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1119 MCLK_DIR(index)); 1120 } 1121 1122 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0; 1123 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0; 1124 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; 1125 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; 1126 1127 platform_set_drvdata(pdev, sai); 1128 1129 /* Get sai version */ 1130 ret = fsl_sai_check_version(&pdev->dev); 1131 if (ret < 0) 1132 dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret); 1133 1134 /* Select MCLK direction */ 1135 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1136 sai->verid.major >= 3 && sai->verid.minor >= 1) { 1137 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1138 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1139 } 1140 1141 pm_runtime_enable(&pdev->dev); 1142 regcache_cache_only(sai->regmap, true); 1143 1144 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, 1145 &sai->cpu_dai_drv, 1); 1146 if (ret) 1147 goto err_pm_disable; 1148 1149 if (sai->soc_data->use_imx_pcm) { 1150 ret = imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE); 1151 if (ret) 1152 goto err_pm_disable; 1153 } else { 1154 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1155 if (ret) 1156 goto err_pm_disable; 1157 } 1158 1159 return ret; 1160 1161 err_pm_disable: 1162 pm_runtime_disable(&pdev->dev); 1163 1164 return ret; 1165 } 1166 1167 static int fsl_sai_remove(struct platform_device *pdev) 1168 { 1169 pm_runtime_disable(&pdev->dev); 1170 1171 return 0; 1172 } 1173 1174 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1175 .use_imx_pcm = false, 1176 .use_edma = false, 1177 .fifo_depth = 32, 1178 .reg_offset = 0, 1179 .mclk0_is_mclk1 = false, 1180 }; 1181 1182 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1183 .use_imx_pcm = true, 1184 .use_edma = false, 1185 .fifo_depth = 32, 1186 .reg_offset = 0, 1187 .mclk0_is_mclk1 = true, 1188 }; 1189 1190 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1191 .use_imx_pcm = true, 1192 .use_edma = false, 1193 .fifo_depth = 16, 1194 .reg_offset = 8, 1195 .mclk0_is_mclk1 = false, 1196 }; 1197 1198 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1199 .use_imx_pcm = true, 1200 .use_edma = false, 1201 .fifo_depth = 128, 1202 .reg_offset = 8, 1203 .mclk0_is_mclk1 = false, 1204 }; 1205 1206 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1207 .use_imx_pcm = true, 1208 .use_edma = true, 1209 .fifo_depth = 64, 1210 .reg_offset = 0, 1211 .mclk0_is_mclk1 = false, 1212 }; 1213 1214 static const struct of_device_id fsl_sai_ids[] = { 1215 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1216 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1217 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1218 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1219 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1220 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1221 { /* sentinel */ } 1222 }; 1223 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1224 1225 #ifdef CONFIG_PM 1226 static int fsl_sai_runtime_suspend(struct device *dev) 1227 { 1228 struct fsl_sai *sai = dev_get_drvdata(dev); 1229 1230 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1231 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1232 1233 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1234 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1235 1236 clk_disable_unprepare(sai->bus_clk); 1237 1238 regcache_cache_only(sai->regmap, true); 1239 1240 return 0; 1241 } 1242 1243 static int fsl_sai_runtime_resume(struct device *dev) 1244 { 1245 struct fsl_sai *sai = dev_get_drvdata(dev); 1246 unsigned int ofs = sai->soc_data->reg_offset; 1247 int ret; 1248 1249 ret = clk_prepare_enable(sai->bus_clk); 1250 if (ret) { 1251 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1252 return ret; 1253 } 1254 1255 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1256 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1257 if (ret) 1258 goto disable_bus_clk; 1259 } 1260 1261 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1262 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1263 if (ret) 1264 goto disable_tx_clk; 1265 } 1266 1267 regcache_cache_only(sai->regmap, false); 1268 regcache_mark_dirty(sai->regmap); 1269 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1270 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1271 usleep_range(1000, 2000); 1272 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1273 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1274 1275 ret = regcache_sync(sai->regmap); 1276 if (ret) 1277 goto disable_rx_clk; 1278 1279 return 0; 1280 1281 disable_rx_clk: 1282 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1283 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1284 disable_tx_clk: 1285 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1286 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1287 disable_bus_clk: 1288 clk_disable_unprepare(sai->bus_clk); 1289 1290 return ret; 1291 } 1292 #endif /* CONFIG_PM */ 1293 1294 static const struct dev_pm_ops fsl_sai_pm_ops = { 1295 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1296 fsl_sai_runtime_resume, NULL) 1297 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1298 pm_runtime_force_resume) 1299 }; 1300 1301 static struct platform_driver fsl_sai_driver = { 1302 .probe = fsl_sai_probe, 1303 .remove = fsl_sai_remove, 1304 .driver = { 1305 .name = "fsl-sai", 1306 .pm = &fsl_sai_pm_ops, 1307 .of_match_table = fsl_sai_ids, 1308 }, 1309 }; 1310 module_platform_driver(fsl_sai_driver); 1311 1312 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1313 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1314 MODULE_ALIAS("platform:fsl-sai"); 1315 MODULE_LICENSE("GPL"); 1316