1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/slab.h> 16 #include <linux/time.h> 17 #include <sound/core.h> 18 #include <sound/dmaengine_pcm.h> 19 #include <sound/pcm_params.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 22 23 #include "fsl_sai.h" 24 #include "imx-pcm.h" 25 26 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 27 FSL_SAI_CSR_FEIE) 28 29 static const unsigned int fsl_sai_rates[] = { 30 8000, 11025, 12000, 16000, 22050, 31 24000, 32000, 44100, 48000, 64000, 32 88200, 96000, 176400, 192000 33 }; 34 35 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 36 .count = ARRAY_SIZE(fsl_sai_rates), 37 .list = fsl_sai_rates, 38 }; 39 40 /** 41 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 42 * 43 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 44 * or Receiver's for both streams. This function is used to check if clocks of 45 * the stream's are synced by the opposite stream. 46 * 47 * @sai: SAI context 48 * @dir: stream direction 49 */ 50 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 51 { 52 int adir = (dir == TX) ? RX : TX; 53 54 /* current dir in async mode while opposite dir in sync mode */ 55 return !sai->synchronous[dir] && sai->synchronous[adir]; 56 } 57 58 static irqreturn_t fsl_sai_isr(int irq, void *devid) 59 { 60 struct fsl_sai *sai = (struct fsl_sai *)devid; 61 unsigned int ofs = sai->soc_data->reg_offset; 62 struct device *dev = &sai->pdev->dev; 63 u32 flags, xcsr, mask; 64 bool irq_none = true; 65 66 /* 67 * Both IRQ status bits and IRQ mask bits are in the xCSR but 68 * different shifts. And we here create a mask only for those 69 * IRQs that we activated. 70 */ 71 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 72 73 /* Tx IRQ */ 74 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 75 flags = xcsr & mask; 76 77 if (flags) 78 irq_none = false; 79 else 80 goto irq_rx; 81 82 if (flags & FSL_SAI_CSR_WSF) 83 dev_dbg(dev, "isr: Start of Tx word detected\n"); 84 85 if (flags & FSL_SAI_CSR_SEF) 86 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 87 88 if (flags & FSL_SAI_CSR_FEF) { 89 dev_dbg(dev, "isr: Transmit underrun detected\n"); 90 /* FIFO reset for safety */ 91 xcsr |= FSL_SAI_CSR_FR; 92 } 93 94 if (flags & FSL_SAI_CSR_FWF) 95 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 96 97 if (flags & FSL_SAI_CSR_FRF) 98 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 99 100 flags &= FSL_SAI_CSR_xF_W_MASK; 101 xcsr &= ~FSL_SAI_CSR_xF_MASK; 102 103 if (flags) 104 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 105 106 irq_rx: 107 /* Rx IRQ */ 108 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 109 flags = xcsr & mask; 110 111 if (flags) 112 irq_none = false; 113 else 114 goto out; 115 116 if (flags & FSL_SAI_CSR_WSF) 117 dev_dbg(dev, "isr: Start of Rx word detected\n"); 118 119 if (flags & FSL_SAI_CSR_SEF) 120 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 121 122 if (flags & FSL_SAI_CSR_FEF) { 123 dev_dbg(dev, "isr: Receive overflow detected\n"); 124 /* FIFO reset for safety */ 125 xcsr |= FSL_SAI_CSR_FR; 126 } 127 128 if (flags & FSL_SAI_CSR_FWF) 129 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 130 131 if (flags & FSL_SAI_CSR_FRF) 132 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 133 134 flags &= FSL_SAI_CSR_xF_W_MASK; 135 xcsr &= ~FSL_SAI_CSR_xF_MASK; 136 137 if (flags) 138 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 139 140 out: 141 if (irq_none) 142 return IRQ_NONE; 143 else 144 return IRQ_HANDLED; 145 } 146 147 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 148 u32 rx_mask, int slots, int slot_width) 149 { 150 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 151 152 sai->slots = slots; 153 sai->slot_width = slot_width; 154 155 return 0; 156 } 157 158 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 159 unsigned int ratio) 160 { 161 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 162 163 sai->bclk_ratio = ratio; 164 165 return 0; 166 } 167 168 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 169 int clk_id, unsigned int freq, int fsl_dir) 170 { 171 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 172 unsigned int ofs = sai->soc_data->reg_offset; 173 bool tx = fsl_dir == FSL_FMT_TRANSMITTER; 174 u32 val_cr2 = 0; 175 176 switch (clk_id) { 177 case FSL_SAI_CLK_BUS: 178 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 179 break; 180 case FSL_SAI_CLK_MAST1: 181 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 182 break; 183 case FSL_SAI_CLK_MAST2: 184 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 185 break; 186 case FSL_SAI_CLK_MAST3: 187 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 188 break; 189 default: 190 return -EINVAL; 191 } 192 193 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 194 FSL_SAI_CR2_MSEL_MASK, val_cr2); 195 196 return 0; 197 } 198 199 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 200 int clk_id, unsigned int freq, int dir) 201 { 202 int ret; 203 204 if (dir == SND_SOC_CLOCK_IN) 205 return 0; 206 207 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, 208 FSL_FMT_TRANSMITTER); 209 if (ret) { 210 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 211 return ret; 212 } 213 214 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, 215 FSL_FMT_RECEIVER); 216 if (ret) 217 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 218 219 return ret; 220 } 221 222 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 223 unsigned int fmt, int fsl_dir) 224 { 225 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 226 unsigned int ofs = sai->soc_data->reg_offset; 227 bool tx = fsl_dir == FSL_FMT_TRANSMITTER; 228 u32 val_cr2 = 0, val_cr4 = 0; 229 230 if (!sai->is_lsb_first) 231 val_cr4 |= FSL_SAI_CR4_MF; 232 233 /* DAI mode */ 234 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 235 case SND_SOC_DAIFMT_I2S: 236 /* 237 * Frame low, 1clk before data, one word length for frame sync, 238 * frame sync starts one serial clock cycle earlier, 239 * that is, together with the last bit of the previous 240 * data word. 241 */ 242 val_cr2 |= FSL_SAI_CR2_BCP; 243 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 244 break; 245 case SND_SOC_DAIFMT_LEFT_J: 246 /* 247 * Frame high, one word length for frame sync, 248 * frame sync asserts with the first bit of the frame. 249 */ 250 val_cr2 |= FSL_SAI_CR2_BCP; 251 break; 252 case SND_SOC_DAIFMT_DSP_A: 253 /* 254 * Frame high, 1clk before data, one bit for frame sync, 255 * frame sync starts one serial clock cycle earlier, 256 * that is, together with the last bit of the previous 257 * data word. 258 */ 259 val_cr2 |= FSL_SAI_CR2_BCP; 260 val_cr4 |= FSL_SAI_CR4_FSE; 261 sai->is_dsp_mode = true; 262 break; 263 case SND_SOC_DAIFMT_DSP_B: 264 /* 265 * Frame high, one bit for frame sync, 266 * frame sync asserts with the first bit of the frame. 267 */ 268 val_cr2 |= FSL_SAI_CR2_BCP; 269 sai->is_dsp_mode = true; 270 break; 271 case SND_SOC_DAIFMT_RIGHT_J: 272 /* To be done */ 273 default: 274 return -EINVAL; 275 } 276 277 /* DAI clock inversion */ 278 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 279 case SND_SOC_DAIFMT_IB_IF: 280 /* Invert both clocks */ 281 val_cr2 ^= FSL_SAI_CR2_BCP; 282 val_cr4 ^= FSL_SAI_CR4_FSP; 283 break; 284 case SND_SOC_DAIFMT_IB_NF: 285 /* Invert bit clock */ 286 val_cr2 ^= FSL_SAI_CR2_BCP; 287 break; 288 case SND_SOC_DAIFMT_NB_IF: 289 /* Invert frame clock */ 290 val_cr4 ^= FSL_SAI_CR4_FSP; 291 break; 292 case SND_SOC_DAIFMT_NB_NF: 293 /* Nothing to do for both normal cases */ 294 break; 295 default: 296 return -EINVAL; 297 } 298 299 /* DAI clock master masks */ 300 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 301 case SND_SOC_DAIFMT_CBS_CFS: 302 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 303 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 304 sai->is_slave_mode = false; 305 break; 306 case SND_SOC_DAIFMT_CBM_CFM: 307 sai->is_slave_mode = true; 308 break; 309 case SND_SOC_DAIFMT_CBS_CFM: 310 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 311 sai->is_slave_mode = false; 312 break; 313 case SND_SOC_DAIFMT_CBM_CFS: 314 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 315 sai->is_slave_mode = true; 316 break; 317 default: 318 return -EINVAL; 319 } 320 321 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 322 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 323 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 324 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 325 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 326 327 return 0; 328 } 329 330 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 331 { 332 int ret; 333 334 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER); 335 if (ret) { 336 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 337 return ret; 338 } 339 340 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER); 341 if (ret) 342 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 343 344 return ret; 345 } 346 347 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 348 { 349 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 350 unsigned int ofs = sai->soc_data->reg_offset; 351 unsigned long clk_rate; 352 u32 savediv = 0, ratio, savesub = freq; 353 int adir = tx ? RX : TX; 354 int dir = tx ? TX : RX; 355 u32 id; 356 int ret = 0; 357 358 /* Don't apply to slave mode */ 359 if (sai->is_slave_mode) 360 return 0; 361 362 for (id = 0; id < FSL_SAI_MCLK_MAX; id++) { 363 clk_rate = clk_get_rate(sai->mclk_clk[id]); 364 if (!clk_rate) 365 continue; 366 367 ratio = clk_rate / freq; 368 369 ret = clk_rate - ratio * freq; 370 371 /* 372 * Drop the source that can not be 373 * divided into the required rate. 374 */ 375 if (ret != 0 && clk_rate / ret < 1000) 376 continue; 377 378 dev_dbg(dai->dev, 379 "ratio %d for freq %dHz based on clock %ldHz\n", 380 ratio, freq, clk_rate); 381 382 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512) 383 ratio /= 2; 384 else 385 continue; 386 387 if (ret < savesub) { 388 savediv = ratio; 389 sai->mclk_id[tx] = id; 390 savesub = ret; 391 } 392 393 if (ret == 0) 394 break; 395 } 396 397 if (savediv == 0) { 398 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 399 tx ? 'T' : 'R', freq); 400 return -EINVAL; 401 } 402 403 /* 404 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 405 * set TCR2 register for playback. 406 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 407 * and capture. 408 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 409 * and capture. 410 * 4) For Tx and Rx are both Synchronous with another SAI, we just 411 * ignore it. 412 */ 413 if (fsl_sai_dir_is_synced(sai, adir)) { 414 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs), 415 FSL_SAI_CR2_MSEL_MASK, 416 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 417 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs), 418 FSL_SAI_CR2_DIV_MASK, savediv - 1); 419 } else if (!sai->synchronous[dir]) { 420 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 421 FSL_SAI_CR2_MSEL_MASK, 422 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 423 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 424 FSL_SAI_CR2_DIV_MASK, savediv - 1); 425 } 426 427 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 428 sai->mclk_id[tx], savediv, savesub); 429 430 return 0; 431 } 432 433 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 434 struct snd_pcm_hw_params *params, 435 struct snd_soc_dai *cpu_dai) 436 { 437 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 438 unsigned int ofs = sai->soc_data->reg_offset; 439 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 440 unsigned int channels = params_channels(params); 441 u32 word_width = params_width(params); 442 u32 val_cr4 = 0, val_cr5 = 0; 443 u32 slots = (channels == 1) ? 2 : channels; 444 u32 slot_width = word_width; 445 int adir = tx ? RX : TX; 446 u32 pins; 447 int ret; 448 449 if (sai->slots) 450 slots = sai->slots; 451 452 if (sai->slot_width) 453 slot_width = sai->slot_width; 454 455 pins = DIV_ROUND_UP(channels, slots); 456 457 if (!sai->is_slave_mode) { 458 if (sai->bclk_ratio) 459 ret = fsl_sai_set_bclk(cpu_dai, tx, 460 sai->bclk_ratio * 461 params_rate(params)); 462 else 463 ret = fsl_sai_set_bclk(cpu_dai, tx, 464 slots * slot_width * 465 params_rate(params)); 466 if (ret) 467 return ret; 468 469 /* Do not enable the clock if it is already enabled */ 470 if (!(sai->mclk_streams & BIT(substream->stream))) { 471 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 472 if (ret) 473 return ret; 474 475 sai->mclk_streams |= BIT(substream->stream); 476 } 477 } 478 479 if (!sai->is_dsp_mode) 480 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 481 482 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 483 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 484 485 if (sai->is_lsb_first) 486 val_cr5 |= FSL_SAI_CR5_FBT(0); 487 else 488 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 489 490 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 491 492 /* Set to output mode to avoid tri-stated data pins */ 493 if (tx) 494 val_cr4 |= FSL_SAI_CR4_CHMOD; 495 496 /* 497 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 498 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 499 * RCR5(TCR5) for playback(capture), or there will be sync error. 500 */ 501 502 if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) { 503 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 504 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 505 FSL_SAI_CR4_CHMOD_MASK, 506 val_cr4); 507 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 508 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 509 FSL_SAI_CR5_FBT_MASK, val_cr5); 510 } 511 512 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 513 FSL_SAI_CR3_TRCE_MASK, 514 FSL_SAI_CR3_TRCE((1 << pins) - 1)); 515 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 516 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 517 FSL_SAI_CR4_CHMOD_MASK, 518 val_cr4); 519 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 520 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 521 FSL_SAI_CR5_FBT_MASK, val_cr5); 522 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 523 ~0UL - ((1 << min(channels, slots)) - 1)); 524 525 return 0; 526 } 527 528 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 529 struct snd_soc_dai *cpu_dai) 530 { 531 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 532 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 533 unsigned int ofs = sai->soc_data->reg_offset; 534 535 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 536 FSL_SAI_CR3_TRCE_MASK, 0); 537 538 if (!sai->is_slave_mode && 539 sai->mclk_streams & BIT(substream->stream)) { 540 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 541 sai->mclk_streams &= ~BIT(substream->stream); 542 } 543 544 return 0; 545 } 546 547 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 548 { 549 unsigned int ofs = sai->soc_data->reg_offset; 550 bool tx = dir == TX; 551 u32 xcsr, count = 100; 552 553 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 554 FSL_SAI_CSR_TERE, 0); 555 556 /* TERE will remain set till the end of current frame */ 557 do { 558 udelay(10); 559 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 560 } while (--count && xcsr & FSL_SAI_CSR_TERE); 561 562 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 563 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 564 565 /* 566 * For sai master mode, after several open/close sai, 567 * there will be no frame clock, and can't recover 568 * anymore. Add software reset to fix this issue. 569 * This is a hardware bug, and will be fix in the 570 * next sai version. 571 */ 572 if (!sai->is_slave_mode) { 573 /* Software Reset */ 574 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 575 /* Clear SR bit to finish the reset */ 576 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 577 } 578 } 579 580 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 581 struct snd_soc_dai *cpu_dai) 582 { 583 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 584 unsigned int ofs = sai->soc_data->reg_offset; 585 586 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 587 int adir = tx ? RX : TX; 588 int dir = tx ? TX : RX; 589 u32 xcsr; 590 591 /* 592 * Asynchronous mode: Clear SYNC for both Tx and Rx. 593 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 594 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 595 */ 596 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 597 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 598 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 599 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 600 601 /* 602 * It is recommended that the transmitter is the last enabled 603 * and the first disabled. 604 */ 605 switch (cmd) { 606 case SNDRV_PCM_TRIGGER_START: 607 case SNDRV_PCM_TRIGGER_RESUME: 608 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 609 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 610 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 611 612 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 613 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 614 /* 615 * Enable the opposite direction for synchronous mode 616 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 617 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 618 * 619 * RM recommends to enable RE after TE for case 1 and to enable 620 * TE after RE for case 2, but we here may not always guarantee 621 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 622 * TE after RE, which is against what RM recommends but should 623 * be safe to do, judging by years of testing results. 624 */ 625 if (fsl_sai_dir_is_synced(sai, adir)) 626 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 627 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 628 629 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 630 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 631 break; 632 case SNDRV_PCM_TRIGGER_STOP: 633 case SNDRV_PCM_TRIGGER_SUSPEND: 634 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 635 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 636 FSL_SAI_CSR_FRDE, 0); 637 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 638 FSL_SAI_CSR_xIE_MASK, 0); 639 640 /* Check if the opposite FRDE is also disabled */ 641 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 642 643 /* 644 * If opposite stream provides clocks for synchronous mode and 645 * it is inactive, disable it before disabling the current one 646 */ 647 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 648 fsl_sai_config_disable(sai, adir); 649 650 /* 651 * Disable current stream if either of: 652 * 1. current stream doesn't provide clocks for synchronous mode 653 * 2. current stream provides clocks for synchronous mode but no 654 * more stream is active. 655 */ 656 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 657 fsl_sai_config_disable(sai, dir); 658 659 break; 660 default: 661 return -EINVAL; 662 } 663 664 return 0; 665 } 666 667 static int fsl_sai_startup(struct snd_pcm_substream *substream, 668 struct snd_soc_dai *cpu_dai) 669 { 670 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 671 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 672 int ret; 673 674 /* 675 * EDMA controller needs period size to be a multiple of 676 * tx/rx maxburst 677 */ 678 if (sai->soc_data->use_edma) 679 snd_pcm_hw_constraint_step(substream->runtime, 0, 680 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 681 tx ? sai->dma_params_tx.maxburst : 682 sai->dma_params_rx.maxburst); 683 684 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 685 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 686 687 return ret; 688 } 689 690 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 691 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 692 .set_sysclk = fsl_sai_set_dai_sysclk, 693 .set_fmt = fsl_sai_set_dai_fmt, 694 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 695 .hw_params = fsl_sai_hw_params, 696 .hw_free = fsl_sai_hw_free, 697 .trigger = fsl_sai_trigger, 698 .startup = fsl_sai_startup, 699 }; 700 701 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 702 { 703 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 704 unsigned int ofs = sai->soc_data->reg_offset; 705 706 /* Software Reset for both Tx and Rx */ 707 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 708 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 709 /* Clear SR bit to finish the reset */ 710 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 711 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 712 713 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 714 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 715 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); 716 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 717 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 718 FSL_SAI_MAXBURST_RX - 1); 719 720 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 721 &sai->dma_params_rx); 722 723 snd_soc_dai_set_drvdata(cpu_dai, sai); 724 725 return 0; 726 } 727 728 static struct snd_soc_dai_driver fsl_sai_dai_template = { 729 .probe = fsl_sai_dai_probe, 730 .playback = { 731 .stream_name = "CPU-Playback", 732 .channels_min = 1, 733 .channels_max = 32, 734 .rate_min = 8000, 735 .rate_max = 192000, 736 .rates = SNDRV_PCM_RATE_KNOT, 737 .formats = FSL_SAI_FORMATS, 738 }, 739 .capture = { 740 .stream_name = "CPU-Capture", 741 .channels_min = 1, 742 .channels_max = 32, 743 .rate_min = 8000, 744 .rate_max = 192000, 745 .rates = SNDRV_PCM_RATE_KNOT, 746 .formats = FSL_SAI_FORMATS, 747 }, 748 .ops = &fsl_sai_pcm_dai_ops, 749 }; 750 751 static const struct snd_soc_component_driver fsl_component = { 752 .name = "fsl-sai", 753 }; 754 755 static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 756 {FSL_SAI_TCR1(0), 0}, 757 {FSL_SAI_TCR2(0), 0}, 758 {FSL_SAI_TCR3(0), 0}, 759 {FSL_SAI_TCR4(0), 0}, 760 {FSL_SAI_TCR5(0), 0}, 761 {FSL_SAI_TDR0, 0}, 762 {FSL_SAI_TDR1, 0}, 763 {FSL_SAI_TDR2, 0}, 764 {FSL_SAI_TDR3, 0}, 765 {FSL_SAI_TDR4, 0}, 766 {FSL_SAI_TDR5, 0}, 767 {FSL_SAI_TDR6, 0}, 768 {FSL_SAI_TDR7, 0}, 769 {FSL_SAI_TMR, 0}, 770 {FSL_SAI_RCR1(0), 0}, 771 {FSL_SAI_RCR2(0), 0}, 772 {FSL_SAI_RCR3(0), 0}, 773 {FSL_SAI_RCR4(0), 0}, 774 {FSL_SAI_RCR5(0), 0}, 775 {FSL_SAI_RMR, 0}, 776 }; 777 778 static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 779 {FSL_SAI_TCR1(8), 0}, 780 {FSL_SAI_TCR2(8), 0}, 781 {FSL_SAI_TCR3(8), 0}, 782 {FSL_SAI_TCR4(8), 0}, 783 {FSL_SAI_TCR5(8), 0}, 784 {FSL_SAI_TDR0, 0}, 785 {FSL_SAI_TDR1, 0}, 786 {FSL_SAI_TDR2, 0}, 787 {FSL_SAI_TDR3, 0}, 788 {FSL_SAI_TDR4, 0}, 789 {FSL_SAI_TDR5, 0}, 790 {FSL_SAI_TDR6, 0}, 791 {FSL_SAI_TDR7, 0}, 792 {FSL_SAI_TMR, 0}, 793 {FSL_SAI_RCR1(8), 0}, 794 {FSL_SAI_RCR2(8), 0}, 795 {FSL_SAI_RCR3(8), 0}, 796 {FSL_SAI_RCR4(8), 0}, 797 {FSL_SAI_RCR5(8), 0}, 798 {FSL_SAI_RMR, 0}, 799 {FSL_SAI_MCTL, 0}, 800 {FSL_SAI_MDIV, 0}, 801 }; 802 803 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 804 { 805 struct fsl_sai *sai = dev_get_drvdata(dev); 806 unsigned int ofs = sai->soc_data->reg_offset; 807 808 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 809 return true; 810 811 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 812 return true; 813 814 switch (reg) { 815 case FSL_SAI_TFR0: 816 case FSL_SAI_TFR1: 817 case FSL_SAI_TFR2: 818 case FSL_SAI_TFR3: 819 case FSL_SAI_TFR4: 820 case FSL_SAI_TFR5: 821 case FSL_SAI_TFR6: 822 case FSL_SAI_TFR7: 823 case FSL_SAI_TMR: 824 case FSL_SAI_RDR0: 825 case FSL_SAI_RDR1: 826 case FSL_SAI_RDR2: 827 case FSL_SAI_RDR3: 828 case FSL_SAI_RDR4: 829 case FSL_SAI_RDR5: 830 case FSL_SAI_RDR6: 831 case FSL_SAI_RDR7: 832 case FSL_SAI_RFR0: 833 case FSL_SAI_RFR1: 834 case FSL_SAI_RFR2: 835 case FSL_SAI_RFR3: 836 case FSL_SAI_RFR4: 837 case FSL_SAI_RFR5: 838 case FSL_SAI_RFR6: 839 case FSL_SAI_RFR7: 840 case FSL_SAI_RMR: 841 case FSL_SAI_MCTL: 842 case FSL_SAI_MDIV: 843 case FSL_SAI_VERID: 844 case FSL_SAI_PARAM: 845 case FSL_SAI_TTCTN: 846 case FSL_SAI_RTCTN: 847 case FSL_SAI_TTCTL: 848 case FSL_SAI_TBCTN: 849 case FSL_SAI_TTCAP: 850 case FSL_SAI_RTCTL: 851 case FSL_SAI_RBCTN: 852 case FSL_SAI_RTCAP: 853 return true; 854 default: 855 return false; 856 } 857 } 858 859 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 860 { 861 struct fsl_sai *sai = dev_get_drvdata(dev); 862 unsigned int ofs = sai->soc_data->reg_offset; 863 864 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 865 return true; 866 867 /* Set VERID and PARAM be volatile for reading value in probe */ 868 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 869 return true; 870 871 switch (reg) { 872 case FSL_SAI_TFR0: 873 case FSL_SAI_TFR1: 874 case FSL_SAI_TFR2: 875 case FSL_SAI_TFR3: 876 case FSL_SAI_TFR4: 877 case FSL_SAI_TFR5: 878 case FSL_SAI_TFR6: 879 case FSL_SAI_TFR7: 880 case FSL_SAI_RFR0: 881 case FSL_SAI_RFR1: 882 case FSL_SAI_RFR2: 883 case FSL_SAI_RFR3: 884 case FSL_SAI_RFR4: 885 case FSL_SAI_RFR5: 886 case FSL_SAI_RFR6: 887 case FSL_SAI_RFR7: 888 case FSL_SAI_RDR0: 889 case FSL_SAI_RDR1: 890 case FSL_SAI_RDR2: 891 case FSL_SAI_RDR3: 892 case FSL_SAI_RDR4: 893 case FSL_SAI_RDR5: 894 case FSL_SAI_RDR6: 895 case FSL_SAI_RDR7: 896 return true; 897 default: 898 return false; 899 } 900 } 901 902 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 903 { 904 struct fsl_sai *sai = dev_get_drvdata(dev); 905 unsigned int ofs = sai->soc_data->reg_offset; 906 907 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 908 return true; 909 910 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 911 return true; 912 913 switch (reg) { 914 case FSL_SAI_TDR0: 915 case FSL_SAI_TDR1: 916 case FSL_SAI_TDR2: 917 case FSL_SAI_TDR3: 918 case FSL_SAI_TDR4: 919 case FSL_SAI_TDR5: 920 case FSL_SAI_TDR6: 921 case FSL_SAI_TDR7: 922 case FSL_SAI_TMR: 923 case FSL_SAI_RMR: 924 case FSL_SAI_MCTL: 925 case FSL_SAI_MDIV: 926 case FSL_SAI_TTCTL: 927 case FSL_SAI_RTCTL: 928 return true; 929 default: 930 return false; 931 } 932 } 933 934 static struct regmap_config fsl_sai_regmap_config = { 935 .reg_bits = 32, 936 .reg_stride = 4, 937 .val_bits = 32, 938 .fast_io = true, 939 940 .max_register = FSL_SAI_RMR, 941 .reg_defaults = fsl_sai_reg_defaults_ofs0, 942 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 943 .readable_reg = fsl_sai_readable_reg, 944 .volatile_reg = fsl_sai_volatile_reg, 945 .writeable_reg = fsl_sai_writeable_reg, 946 .cache_type = REGCACHE_FLAT, 947 }; 948 949 static int fsl_sai_check_version(struct device *dev) 950 { 951 struct fsl_sai *sai = dev_get_drvdata(dev); 952 unsigned char ofs = sai->soc_data->reg_offset; 953 unsigned int val; 954 int ret; 955 956 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 957 return 0; 958 959 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 960 if (ret < 0) 961 return ret; 962 963 dev_dbg(dev, "VERID: 0x%016X\n", val); 964 965 sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >> 966 FSL_SAI_VERID_MAJOR_SHIFT; 967 sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >> 968 FSL_SAI_VERID_MINOR_SHIFT; 969 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 970 971 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 972 if (ret < 0) 973 return ret; 974 975 dev_dbg(dev, "PARAM: 0x%016X\n", val); 976 977 /* Max slots per frame, power of 2 */ 978 sai->param.slot_num = 1 << 979 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 980 981 /* Words per fifo, power of 2 */ 982 sai->param.fifo_depth = 1 << 983 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 984 985 /* Number of datalines implemented */ 986 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 987 988 return 0; 989 } 990 991 static int fsl_sai_probe(struct platform_device *pdev) 992 { 993 struct device_node *np = pdev->dev.of_node; 994 struct fsl_sai *sai; 995 struct regmap *gpr; 996 struct resource *res; 997 void __iomem *base; 998 char tmp[8]; 999 int irq, ret, i; 1000 int index; 1001 1002 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1003 if (!sai) 1004 return -ENOMEM; 1005 1006 sai->pdev = pdev; 1007 sai->soc_data = of_device_get_match_data(&pdev->dev); 1008 1009 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1010 1011 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1012 base = devm_ioremap_resource(&pdev->dev, res); 1013 if (IS_ERR(base)) 1014 return PTR_ERR(base); 1015 1016 if (sai->soc_data->reg_offset == 8) { 1017 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1018 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1019 fsl_sai_regmap_config.num_reg_defaults = 1020 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1021 } 1022 1023 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 1024 "bus", base, &fsl_sai_regmap_config); 1025 1026 /* Compatible with old DTB cases */ 1027 if (IS_ERR(sai->regmap) && PTR_ERR(sai->regmap) != -EPROBE_DEFER) 1028 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 1029 "sai", base, &fsl_sai_regmap_config); 1030 if (IS_ERR(sai->regmap)) { 1031 dev_err(&pdev->dev, "regmap init failed\n"); 1032 return PTR_ERR(sai->regmap); 1033 } 1034 1035 /* No error out for old DTB cases but only mark the clock NULL */ 1036 sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); 1037 if (IS_ERR(sai->bus_clk)) { 1038 dev_err(&pdev->dev, "failed to get bus clock: %ld\n", 1039 PTR_ERR(sai->bus_clk)); 1040 sai->bus_clk = NULL; 1041 } 1042 1043 sai->mclk_clk[0] = sai->bus_clk; 1044 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1045 sprintf(tmp, "mclk%d", i); 1046 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); 1047 if (IS_ERR(sai->mclk_clk[i])) { 1048 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n", 1049 i + 1, PTR_ERR(sai->mclk_clk[i])); 1050 sai->mclk_clk[i] = NULL; 1051 } 1052 } 1053 1054 irq = platform_get_irq(pdev, 0); 1055 if (irq < 0) 1056 return irq; 1057 1058 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, IRQF_SHARED, 1059 np->name, sai); 1060 if (ret) { 1061 dev_err(&pdev->dev, "failed to claim irq %u\n", irq); 1062 return ret; 1063 } 1064 1065 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1066 sizeof(fsl_sai_dai_template)); 1067 1068 /* Sync Tx with Rx as default by following old DT binding */ 1069 sai->synchronous[RX] = true; 1070 sai->synchronous[TX] = false; 1071 sai->cpu_dai_drv.symmetric_rates = 1; 1072 sai->cpu_dai_drv.symmetric_channels = 1; 1073 sai->cpu_dai_drv.symmetric_samplebits = 1; 1074 1075 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && 1076 of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1077 /* error out if both synchronous and asynchronous are present */ 1078 dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); 1079 return -EINVAL; 1080 } 1081 1082 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { 1083 /* Sync Rx with Tx */ 1084 sai->synchronous[RX] = false; 1085 sai->synchronous[TX] = true; 1086 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1087 /* Discard all settings for asynchronous mode */ 1088 sai->synchronous[RX] = false; 1089 sai->synchronous[TX] = false; 1090 sai->cpu_dai_drv.symmetric_rates = 0; 1091 sai->cpu_dai_drv.symmetric_channels = 0; 1092 sai->cpu_dai_drv.symmetric_samplebits = 0; 1093 } 1094 1095 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1096 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1097 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1098 if (IS_ERR(gpr)) { 1099 dev_err(&pdev->dev, "cannot find iomuxc registers\n"); 1100 return PTR_ERR(gpr); 1101 } 1102 1103 index = of_alias_get_id(np, "sai"); 1104 if (index < 0) 1105 return index; 1106 1107 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1108 MCLK_DIR(index)); 1109 } 1110 1111 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0; 1112 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0; 1113 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; 1114 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; 1115 1116 platform_set_drvdata(pdev, sai); 1117 1118 /* Get sai version */ 1119 ret = fsl_sai_check_version(&pdev->dev); 1120 if (ret < 0) 1121 dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret); 1122 1123 /* Select MCLK direction */ 1124 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1125 sai->verid.major >= 3 && sai->verid.minor >= 1) { 1126 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1127 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1128 } 1129 1130 pm_runtime_enable(&pdev->dev); 1131 regcache_cache_only(sai->regmap, true); 1132 1133 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, 1134 &sai->cpu_dai_drv, 1); 1135 if (ret) 1136 goto err_pm_disable; 1137 1138 if (sai->soc_data->use_imx_pcm) { 1139 ret = imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE); 1140 if (ret) 1141 goto err_pm_disable; 1142 } else { 1143 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1144 if (ret) 1145 goto err_pm_disable; 1146 } 1147 1148 return ret; 1149 1150 err_pm_disable: 1151 pm_runtime_disable(&pdev->dev); 1152 1153 return ret; 1154 } 1155 1156 static int fsl_sai_remove(struct platform_device *pdev) 1157 { 1158 pm_runtime_disable(&pdev->dev); 1159 1160 return 0; 1161 } 1162 1163 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1164 .use_imx_pcm = false, 1165 .use_edma = false, 1166 .fifo_depth = 32, 1167 .reg_offset = 0, 1168 }; 1169 1170 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1171 .use_imx_pcm = true, 1172 .use_edma = false, 1173 .fifo_depth = 32, 1174 .reg_offset = 0, 1175 }; 1176 1177 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1178 .use_imx_pcm = true, 1179 .use_edma = false, 1180 .fifo_depth = 16, 1181 .reg_offset = 8, 1182 }; 1183 1184 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1185 .use_imx_pcm = true, 1186 .use_edma = false, 1187 .fifo_depth = 128, 1188 .reg_offset = 8, 1189 }; 1190 1191 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1192 .use_imx_pcm = true, 1193 .use_edma = true, 1194 .fifo_depth = 64, 1195 .reg_offset = 0, 1196 }; 1197 1198 static const struct of_device_id fsl_sai_ids[] = { 1199 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1200 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1201 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1202 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1203 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1204 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1205 { /* sentinel */ } 1206 }; 1207 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1208 1209 #ifdef CONFIG_PM 1210 static int fsl_sai_runtime_suspend(struct device *dev) 1211 { 1212 struct fsl_sai *sai = dev_get_drvdata(dev); 1213 1214 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1215 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1216 1217 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1218 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1219 1220 clk_disable_unprepare(sai->bus_clk); 1221 1222 regcache_cache_only(sai->regmap, true); 1223 1224 return 0; 1225 } 1226 1227 static int fsl_sai_runtime_resume(struct device *dev) 1228 { 1229 struct fsl_sai *sai = dev_get_drvdata(dev); 1230 unsigned int ofs = sai->soc_data->reg_offset; 1231 int ret; 1232 1233 ret = clk_prepare_enable(sai->bus_clk); 1234 if (ret) { 1235 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1236 return ret; 1237 } 1238 1239 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1240 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1241 if (ret) 1242 goto disable_bus_clk; 1243 } 1244 1245 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1246 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1247 if (ret) 1248 goto disable_tx_clk; 1249 } 1250 1251 regcache_cache_only(sai->regmap, false); 1252 regcache_mark_dirty(sai->regmap); 1253 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1254 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1255 usleep_range(1000, 2000); 1256 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1257 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1258 1259 ret = regcache_sync(sai->regmap); 1260 if (ret) 1261 goto disable_rx_clk; 1262 1263 return 0; 1264 1265 disable_rx_clk: 1266 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1267 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1268 disable_tx_clk: 1269 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1270 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1271 disable_bus_clk: 1272 clk_disable_unprepare(sai->bus_clk); 1273 1274 return ret; 1275 } 1276 #endif /* CONFIG_PM */ 1277 1278 static const struct dev_pm_ops fsl_sai_pm_ops = { 1279 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1280 fsl_sai_runtime_resume, NULL) 1281 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1282 pm_runtime_force_resume) 1283 }; 1284 1285 static struct platform_driver fsl_sai_driver = { 1286 .probe = fsl_sai_probe, 1287 .remove = fsl_sai_remove, 1288 .driver = { 1289 .name = "fsl-sai", 1290 .pm = &fsl_sai_pm_ops, 1291 .of_match_table = fsl_sai_ids, 1292 }, 1293 }; 1294 module_platform_driver(fsl_sai_driver); 1295 1296 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1297 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1298 MODULE_ALIAS("platform:fsl-sai"); 1299 MODULE_LICENSE("GPL"); 1300